CN1184564C - 计算机系统及在计算机系统中执行指令的方法 - Google Patents

计算机系统及在计算机系统中执行指令的方法 Download PDF

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Publication number
CN1184564C
CN1184564C CNB011179473A CN01117947A CN1184564C CN 1184564 C CN1184564 C CN 1184564C CN B011179473 A CNB011179473 A CN B011179473A CN 01117947 A CN01117947 A CN 01117947A CN 1184564 C CN1184564 C CN 1184564C
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China
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instruction
register
loading
around
storage
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Chinese (zh)
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CN1329304A (zh
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D·C·莫里斯
W·R·布里格
A·H·卡普
W·Y·陈
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
CNB011179473A 2000-04-27 2001-04-27 计算机系统及在计算机系统中执行指令的方法 Expired - Fee Related CN1184564C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/559,508 US6631460B1 (en) 2000-04-27 2000-04-27 Advanced load address table entry invalidation based on register address wraparound
US09/559508 2000-04-27

Publications (2)

Publication Number Publication Date
CN1329304A CN1329304A (zh) 2002-01-02
CN1184564C true CN1184564C (zh) 2005-01-12

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CNB011179473A Expired - Fee Related CN1184564C (zh) 2000-04-27 2001-04-27 计算机系统及在计算机系统中执行指令的方法

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US (1) US6631460B1 (enExample)
EP (1) EP1150202A3 (enExample)
JP (1) JP2001312405A (enExample)
CN (1) CN1184564C (enExample)

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US7149878B1 (en) 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US6970895B2 (en) * 2001-10-01 2005-11-29 Koninklijke Philips Electronics N.V. Programmable delay indexed data path register file for array processing
US6941449B2 (en) * 2002-03-04 2005-09-06 Hewlett-Packard Development Company, L.P. Method and apparatus for performing critical tasks using speculative operations
US20030177312A1 (en) * 2002-03-15 2003-09-18 Aravindh Baktha Controlling a store data forwarding mechanism during execution of a load operation
US20050166031A1 (en) * 2002-04-26 2005-07-28 Holmberg Anders P. Memory access register file
US7062636B2 (en) * 2002-09-19 2006-06-13 Intel Corporation Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation
US7080231B2 (en) * 2002-10-18 2006-07-18 Sun Microsystems, Inc. Processor with tagging buffer and methods for avoiding memory collisions
US7103880B1 (en) * 2003-04-30 2006-09-05 Hewlett-Packard Development Company, L.P. Floating-point data speculation across a procedure call using an advanced load address table
US7325228B1 (en) * 2003-04-30 2008-01-29 Hewlett-Packard Development Company, L.P. Data speculation across a procedure call using an advanced load address table
CN100390755C (zh) * 2003-10-14 2008-05-28 中国科学院计算技术研究所 含有显式高速缓冲存储器的计算机微体系结构
US7840949B2 (en) * 2003-11-03 2010-11-23 Ramal Acquisition Corp. System and method for data transformation using dataflow graphs
CN1306401C (zh) * 2004-03-19 2007-03-21 中国科学院计算技术研究所 一种支持有向有环图的微调度方法
US7366956B2 (en) * 2004-06-16 2008-04-29 Hewlett-Packard Development Company, L.P. Detecting data races in multithreaded computer programs
US7757237B2 (en) * 2004-06-16 2010-07-13 Hewlett-Packard Development Company, L.P. Synchronization of threads in a multithreaded computer program
US20050283770A1 (en) * 2004-06-18 2005-12-22 Karp Alan H Detecting memory address bounds violations
US7324106B1 (en) * 2004-07-27 2008-01-29 Nvidia Corporation Translation of register-combiner state into shader microcode
US20060242390A1 (en) * 2005-04-26 2006-10-26 Intel Corporation Advanced load address table buffer
US8266413B2 (en) 2006-03-14 2012-09-11 The Board Of Trustees Of The University Of Illinois Processor architecture for multipass processing of instructions downstream of a stalled instruction
US8127117B2 (en) 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor
JP5289688B2 (ja) * 2006-07-05 2013-09-11 ルネサスエレクトロニクス株式会社 プロセッサシステム及びプロセッサシステムを動作させるオペレーティングシステムプログラムの処理方法
US8417922B2 (en) * 2006-08-02 2013-04-09 Qualcomm Incorporated Method and system to combine multiple register units within a microprocessor
TWI646422B (zh) 2012-06-15 2019-01-01 英特爾股份有限公司 在處理器中之免消歧義失序載入／儲存佇列方法、微處理器、和非暫態性電腦可讀取儲存媒體
KR101826080B1 (ko) 2012-06-15 2018-02-06 인텔 코포레이션 통합된 구조를 갖는 동적 디스패치 윈도우를 가지는 가상 load store 큐
KR101825585B1 (ko) 2012-06-15 2018-02-05 인텔 코포레이션 명확화 없는 비순차 load store 큐를 갖는 재정렬된 투기적 명령어 시퀀스들
EP2862062B1 (en) 2012-06-15 2024-03-06 Intel Corporation A virtual load store queue having a dynamic dispatch window with a distributed structure
KR101993562B1 (ko) 2012-06-15 2019-09-30 인텔 코포레이션 Load store 재정렬 및 최적화를 구현하는 명령어 정의
WO2013188701A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. A method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
CN111723921B (zh) * 2019-03-22 2024-05-14 中科寒武纪科技股份有限公司 人工智能计算装置及相关产品
CN112052041B (zh) * 2020-10-10 2022-03-11 乐鑫信息科技（上海）股份有限公司 更新寄存器的方法
JP2023133850A (ja) * 2022-03-14 2023-09-27 富士通株式会社 演算処理装置および演算処理方法

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US5421022A (en) 1993-06-17 1995-05-30 Digital Equipment Corporation Apparatus and method for speculatively executing instructions in a computer system
US5634023A (en) 1994-07-01 1997-05-27 Digital Equipment Corporation Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions
US5799179A (en) 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US5625835A (en) 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
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US5903749A (en) 1996-07-02 1999-05-11 Institute For The Development Of Emerging Architecture, L.L.C. Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs
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US6487630B2 (en) * 1999-02-26 2002-11-26 Intel Corporation Processor with register stack engine that dynamically spills/fills physical registers to backing store

Also Published As

Publication number Publication date
CN1329304A (zh) 2002-01-02
JP2001312405A (ja) 2001-11-09
US6631460B1 (en) 2003-10-07
EP1150202A3 (en) 2003-02-05
EP1150202A2 (en) 2001-10-31

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