CN118431218A

CN118431218A - Package structure of semiconductor device and method for manufacturing the same

Info

Publication number: CN118431218A
Application number: CN202410644384.4A
Authority: CN
Inventors: 傅峻涛; 屠于梦; 张辉; 姜飞帆; 胡铁刚; 张学双
Original assignee: Hangzhou Silan Microelectronics Co Ltd; Xiamen Silan Advanced Compound Semiconductor Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd; Xiamen Silan Advanced Compound Semiconductor Co Ltd
Priority date: 2024-05-22
Filing date: 2024-05-22
Publication date: 2024-08-02

Abstract

The application discloses a packaging structure of a semiconductor device and a manufacturing method thereof, wherein the packaging structure comprises: the first surface of the substrate is provided with a groove, and the thickness of the edge of the substrate is larger than that of the center of the substrate; the control chip is positioned on the bottom surface of the groove of the substrate and is positioned in the cavity formed by the groove; the photoelectric chip is positioned on the control chip and covers part of the surface of the control chip; a bonding wire electrically connecting the control chip with the substrate; a protective layer or wavelength converter covering the optoelectronic chip; the packaging adhesive is positioned in the groove, fills a gap between the side wall of the groove and the control chip, and extends to cover one of the following top surfaces: (1) the encapsulation glue extends to cover part of the top surface of the control chip; (2) the encapsulation glue extends to cover part of the top surface of the protective layer; (3) The encapsulant extends over a portion of the top surface of the wavelength converter. The protection layer or the wavelength converter covers the photoelectric chip, and can protect the photoelectric chip.

Description

Package structure of semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device package structure and a method for manufacturing the same.

Background

The existing packaging structure of the photoelectric semiconductor device is generally composed of parts and elements made of various different materials, and depends on a die to carry out final packaging molding, so that the corresponding cost of the die is high, multiple sets of modules can be involved from the beginning of design to final shaping of the product, and the manufacturing cost of the product is high.

Further, since different materials have different coefficients of expansion, rigid materials can present risks of die droping and die tearing when wrapping the bond wires and die. The use of softer materials avoids such risks, but softer materials do not provide mechanical protection to the package, and the product can deform and damage the components, etc.

At present, the packaging structure of the photoelectric semiconductor device is manufactured by using a die, so that the cost is high, and the problem of product failure caused by shrinkage when the material is molded and cooled is also faced.

Therefore, there is a need for a semiconductor device package structure with higher reliability without depending on a die, so as to meet market demands.

Disclosure of Invention

In view of this, the present invention provides a semiconductor device package structure and a method for manufacturing the same, which avoid the dependence on a mold, reduce the package cost, and realize the requirements of low cost and high reliability.

To achieve the purpose, the invention adopts the following technical scheme:

According to an aspect of the present invention, there is provided a package structure of a semiconductor device, including: the first surface of the substrate is provided with a groove, and the thickness of the edge of the substrate is larger than that of the center of the substrate; the control chip is positioned on the bottom surface of the groove of the substrate and is positioned in the cavity formed by the groove; the photoelectric chip is positioned on the control chip and covers part of the surface of the control chip; a bonding wire electrically connecting the control chip and the substrate; a protective layer or wavelength converter covering the optoelectronic chip; the packaging adhesive is positioned in the groove, fills a gap between the side wall of the groove and the control chip, and extends to cover one of the following top surfaces: (1) The packaging adhesive extends to cover part of the top surface of the control chip; (2) The packaging adhesive extends to cover part of the top surface of the protective layer; (3) The encapsulation glue extends over a portion of the top surface of the wavelength converter.

Optionally, the substrate is a ceramic substrate.

Optionally, the substrate is an aluminum nitride ceramic substrate.

Optionally, the protective layer is a transparent layer.

Optionally, the wavelength converter is a phosphor layer.

Optionally, the thickness of the encapsulation glue is smaller than the depth of the groove, and the encapsulation glue completely encapsulates the bonding wire.

Optionally, the protective layer or the wavelength converter further extends to cover part or all of the surface of the control chip.

Optionally, the device further comprises a surrounding shield, wherein the surrounding shield is arranged around the light-emitting area of the photoelectric chip.

Optionally, when the encapsulation adhesive extends to cover a part of the top surface of the control chip, the enclosure is located on the surface of the control chip.

Optionally, when the encapsulation adhesive extends to cover a part of the top surface of the protective layer, the enclosure is located on the surface of the protective layer.

Optionally, the enclosure is located on a surface of the wavelength converter when the encapsulation glue extends over a portion of a top surface of the wavelength converter.

Optionally, the upper surface of the encapsulation glue is lower than the upper surface of the enclosure, and the encapsulation glue is located between the side wall of the groove and the enclosure.

Optionally, the substrate is further provided with a heat conducting block in a corresponding area of the control chip.

Optionally, the heat conducting block is a plurality of separate heat conducting blocks.

Optionally, the projection of the encapsulation adhesive to the substrate direction does not overlap with the projection of the optoelectronic chip to the substrate direction.

According to another aspect of the present invention, there is provided a method of manufacturing a package structure of a semiconductor device, including: providing a groove on a first surface of a substrate, wherein the groove is positioned in a central area of the substrate, and the thickness of the edge of the substrate is larger than that of the center of the substrate; a control chip is arranged in a groove of the substrate, and the control chip is positioned in a cavity formed by the groove; arranging a photoelectric chip on the control chip, wherein the photoelectric chip covers part of the surface of the control chip; electrically connecting the control chip with the substrate through a bonding wire; providing a protective layer or a wavelength converter, wherein the protective layer or the wavelength converter covers the optoelectronic chip; arranging packaging glue on the first surface of the substrate, wherein the packaging glue fills a gap between the side wall of the groove and the control chip and extends to cover one of the following top surfaces: (1) The packaging adhesive extends to cover part of the top surface of the control chip; (2) The packaging adhesive extends to cover part of the top surface of the protective layer; (3) The encapsulation glue extends over a portion of the top surface of the wavelength converter.

Optionally, the substrate is a ceramic substrate.

Optionally, the substrate is an aluminum nitride ceramic substrate.

Optionally, the protective layer is a transparent layer.

Optionally, the wavelength converter is a phosphor layer.

The beneficial technical effects of the invention are as follows: according to the packaging structure of the semiconductor device and the manufacturing method of the packaging structure, the protection layer or the wavelength converter covers the photoelectric chip, and the photoelectric chip can be protected. The protection layer is attached to the photoelectric chip, so that the reliability of the packaging structure is higher; the wavelength converter is attached to the photoelectric chip more easily to dissipate heat of the wavelength converter, and the better the heat dissipation is, the higher the conversion efficiency of the wavelength converter is.

Further, a groove is formed on the substrate, and packaging glue is filled in the groove to package the chip and the bonding wire in the groove, so that the processing of the packaging structure gets rid of the requirement on a die, and the cost can be effectively reduced while the flat packaging design is realized; the encapsulation glue can prevent the light from being emitted out of the photoelectric chip, and the encapsulation glue does not cover the light-emitting area of the photoelectric chip, so that the brightness of the photoelectric chip can be ensured.

Further, the packaging structure adopts the substrate with a certain thickness, so that a good external protection frame is provided for the chip, the risk of chip falling and bonding wire tearing is reduced due to soft packaging adhesive in the chip, and the substrate is of an integrated structure.

Further, the surrounding baffle can prevent the packaging adhesive from overflowing to the light-emitting area of the photoelectric chip, so that the brightness of the photoelectric chip is ensured.

Further, the through holes can be replaced by the conductive blocks in the substrate, so that the heat dissipation performance of the packaging structure of the semiconductor device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 is a schematic cross-sectional view of a package structure of a semiconductor device of a first embodiment of the present invention;

fig. 2 is a schematic top layout view of a package structure of a semiconductor device according to a first embodiment of the present invention;

fig. 3 is a schematic view showing the arrangement of through holes under a chip assembly in a package structure of a semiconductor device according to a first embodiment of the present invention;

Fig. 4 is a schematic cross-sectional view of a package structure of a semiconductor device according to a second embodiment of the present invention;

fig. 5 is a schematic top layout view of a package structure of a semiconductor device according to a second embodiment of the present invention;

fig. 6 is a schematic view showing a manufacturing flow of a package structure of a semiconductor device according to a second embodiment of the present invention;

fig. 7a to 7e are schematic cross-sectional views showing respective manufacturing steps of a package structure of a semiconductor device according to a second embodiment of the present invention;

Fig. 8 is a schematic cross-sectional view of a package structure of a semiconductor device according to a third embodiment of the present invention;

fig. 9 is a schematic cross-sectional view of a package structure of a semiconductor device of a fourth embodiment of the present invention;

Fig. 10 is a schematic layout view of a heat conducting block in a package structure of a semiconductor device according to a fourth embodiment of the present invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, and components have not been described in detail so as not to obscure the nature of the invention.

In the description of the present invention, it should be understood that the terms "upper," "lower," "left," "right," "inner," "outer," "transverse," "longitudinal," and the like are used for describing the form, position, and connection of the components of the present invention based on the orientation or position shown in the corresponding drawings, and are not intended to indicate or imply that the components must be located in a specific orientation or configuration in the whole, but are not to be construed as limiting the invention.

Fig. 1 is a schematic cross-sectional view of a package structure of a semiconductor device of a first embodiment of the present invention, the package structure 100 of the semiconductor device of the first embodiment including a substrate 1 and a chip 2 located in a recess 10 of the substrate 1; the recess 10 is located in a middle area of the substrate 1, the thickness of the edge of the substrate 1 is greater than the thickness of the center of the substrate 1, the chip 2 is located on a bottom 11 of the recess 10, the side wall of the recess 10 surrounds the chip 2 to form a cavity, the chip 2 includes a control chip 21 and a photoelectric chip 22, and the photoelectric chip 22 is electrically connected with the control chip 21. The control chip 21 is located on the first surface of the substrate 1, and specifically is located at the bottom surface of the recess 10 of the substrate 1, and the photo chip 22 is located on the control chip 21 and covers a part of the surface of the control chip 21.

The optoelectronic chip 22 is, for example, a light emitting diode chip or a laser diode chip, and the optoelectronic chip 22 has, for example, a plurality of light emitting regions that can be controlled independently of each other and can be arranged in a matrix form, for example, the optoelectronic chip 22 includes a matrix of 80×320 light emitting regions, but is not limited thereto, and is applicable to adaptive illumination in the automotive field. The control chip 21 is, for example, a chip for controlling the photo chip 22.

The second surface of the substrate 1 is disposed opposite to the first surface, the first surface and the second surface of the substrate 1 are both planar, and the first surface (upper surface) thereof is provided with a groove 10. Further, the substrate 1 may be a ceramic substrate, and preferably, the substrate 1 may be an aluminum nitride ceramic substrate. A plurality of conductive layers 12 are further disposed on the bottom surface 11 of the groove 10 of the substrate 1, and the upper surface of the control chip 21 is electrically connected with the corresponding conductive layers 12 on the substrate 1 through bonding wires 3. The second surface of the substrate 1, i.e. the side surface (substrate back surface) opposite to the bottom surface 11 of the recess 10, is further provided with pads 13, which pads 13 are electrically connected, for example, with the mounting and external of the package structure 100. The substrate 1 is further provided with a plurality of through holes 14 for communicating the bottom surface 11 of the recess 10 with the second surface, the through holes 14 comprise a plurality of through holes, and the conductive layer 12 or other conductive wiring structure can be connected with the bonding pads 13 on the second surface by filling conductive materials on the side walls of the through holes 14 or in the through holes 14 to realize electrical connection; further, referring to fig. 3, heat in the chip 2 can be timely conducted out through a plurality of through holes 14 arranged in an array, so that good heat dissipation capability is achieved.

The middle of the substrate 1 is provided with a window structure to form a groove 10, the shape, size and depth of the groove 10 are matched with those of the chip 2, of course, the substrate 1 is made of hard materials, various metal wiring layers can be arranged inside, and the structure outside the groove 10 can provide protection for the chip 2. Referring to fig. 2, the size of the control chip 21 is, for example, larger than that of the optoelectronic chip 22, and the edge region of the control chip 21 may be provided with pads for bonding or increasing the area to enhance heat dissipation, etc. A protective layer or wavelength converter 4 is provided on the optoelectronic chip 22, the protective layer or wavelength converter 4 covering at least the surface of the optoelectronic chip 22. In this embodiment, the protective layer or wavelength converter 4 covers the surface of the optoelectronic chip 22 and the exposed surface of the control chip 21. The protective layer or the wavelength converter 4 may be made of silicone, ceramic, glass, or the like. Optionally, the protective layer 4 is a transparent layer, and only protects the photo-electric chip 22 without changing the light color of the photo-electric chip 22, and the photo-electric chip 22 emits light of red, green, blue, or the like, for example. Alternatively, the wavelength converter 4 is a phosphor layer, and has a wavelength conversion function, so that the light emitted from the photo-electric chip 22 can be converted into white light. The packaging adhesive 5 is filled between the side wall of the groove 10 and the control chip 21, and covers the bonding wires 3 to protect the bonding wires 3. Further, the encapsulation glue 5 also extends over the edges of the protective layer or wavelength converter 4 to block moisture etc. in the external environment from entering from the interface between the protective layer or wavelength converter 4 and the control chip 21, affecting the reliability of the chip 2. The projection of the encapsulation adhesive 5 to the direction of the substrate 1 is not overlapped with the projection of the optoelectronic chip 22 to the direction of the substrate 1, so that the brightness of the optoelectronic chip 22 can be ensured. The protective layer or the wavelength converter 4 is generally arranged on the control chip 21 and the optoelectronic chip 22 before the encapsulation adhesive 5, after the arrangement of the bonding wires 3 and the protective layer or the wavelength converter 4 is completed, the encapsulation adhesive 5 is filled into the groove 10 so as to cover the exposed part surfaces of the groove 10, the bonding wires 3, the chip 2 and the edges of the protective layer or the wavelength converter 4, and the sealing protection of the chip 2 and the bonding wires 3 is realized through the encapsulation adhesive 5 and the protective layer or the wavelength converter 4. In order to reduce the influence on the bonding wire 3, the encapsulation glue 5 may be applied by, for example, dispensing or injection molding, and the encapsulation glue 5 may be made of, for example, a material with elasticity, such as silicone, silica gel, epoxy resin, etc., and has a hardness smaller than that of the substrate 1, so that the encapsulation glue 5 can realize sealing and waterproofing, and simultaneously reduce the mechanical load and stress of the bonding wire 3 and the chip 2, and avoid the risk of tearing the bonding wire 3 and falling the chip 2. Of course, in order to ensure that the function of the optoelectronic chip 22 is not affected, the encapsulation glue 5 only covers the edge area of the protection layer or the wavelength converter 4, and no encapsulation glue 5 is provided in the light emitting area of the optoelectronic chip 22, so as to ensure the light emitting brightness of the optoelectronic chip 22. In order to avoid overflow of the encapsulation compound 5, the depth of the recess 10 is for example not smaller than the combined height of the chip 2 and the protective layer or wavelength converter 4, i.e. the thickness of the encapsulation compound 5 is smaller than the depth of the recess 10.

Fig. 3 is a schematic view of the arrangement of through holes under a chip assembly in the package structure of the semiconductor device according to the first embodiment of the present invention, and as can be seen from fig. 3, in the package structure of the semiconductor device, the substrate 1 is provided with through holes 14 in a region corresponding to the control chip 21 in the chip 2, for example, the plurality of through holes 14 are arranged under the control chip 21 in an array manner, the inside or the side wall of the through holes 14 is filled with metal, the edge of the control chip 21 arranged in an array manner is larger than the edge of the control chip 21, and the heat conduction and dissipation capability of the chip 2 is enhanced through the through holes 14, so that the stability and reliability of the semiconductor device are improved.

Fig. 4 is a schematic cross-sectional view of a package structure of a semiconductor device according to a second embodiment of the present invention, and fig. 5 is a schematic top layout view of the package structure of the semiconductor device according to the second embodiment of the present invention; the semiconductor device of the second embodiment is similar to the first embodiment in its entirety, except that the edge area on the protective layer or the wavelength converter 4 is further provided with a surrounding shield 6, for example, the surrounding shield 6 surrounds the edge area of the protective layer or the wavelength converter 4 and is not disposed above the optoelectronic chip 22, as shown in fig. 4 and 5, when the encapsulation glue 5 is filled, the encapsulation glue 5 can be prevented from spreading to the light emitting area of the optoelectronic chip 22, which affects the brightness of the optoelectronic chip 22, that is, the projection of the encapsulation glue 5 in the direction of the substrate 1 and the projection of the optoelectronic chip 22 in the direction of the substrate 1 do not overlap, and the brightness of the optoelectronic chip 22 can be ensured. The enclosure 6 is arranged before the packaging glue 5, and the enclosure 6 also has a certain height, the enclosure 6 is made of the same material as the packaging glue 5, and the enclosure 6 is formed by a dispensing process; naturally, the enclosure 6 may also be formed of other materials. The enclosure 6 is made of a light-tight material, so that not only can the flow of the packaging adhesive 5 be blocked, but also unnecessary light scattering can be reduced, and the interference of stray light can be reduced.

The manufacturing flow of the package structure of the semiconductor device of the second embodiment is as shown in fig. 6, and includes:

Step S10, arranging a groove on a substrate; specifically, as shown in fig. 7a, a groove 10 having a certain depth is provided in a first surface of a central region of the substrate 1.

Step S20, arranging a chip in a groove of a substrate, and electrically connecting the chip with the substrate through a bonding wire; specifically, as shown in fig. 7b, a chip 2 is disposed on the bottom surface of the recess 10 of the substrate 1, the chip 2 includes a control chip 21 and a photo chip 22, the photo chip 22 is located above the control chip 21, and a bonding pad on the upper surface of the control chip 21 is electrically connected to the substrate 1 through a bonding wire 3.

Step S30, setting a protective layer or a wavelength converter; specifically, as shown in fig. 7c, a protective layer or wavelength converter 4 is provided on the control chip 21 to cover the exposed area of the control chip 21 and the optoelectronic chip 22.

S40, forming a fence; specifically, as shown in fig. 7d, on the protective layer or the wavelength converter 4, a shielding 6 is disposed around the light emitting area of the optoelectronic chip 22, and for example, the shielding 6 may be disposed through a dispensing process.

S50, forming packaging glue; specifically, as shown in fig. 7e, the packaging adhesive 5 is filled between the side wall of the groove 10 and the enclosure 6 to cover the exposed part of the surface of the substrate 1, the bonding wires 3, the chip 2 and the edge of the protection layer or the wavelength converter 4, and the sealing protection of the chip 2 and the bonding wires 3 is realized through the packaging adhesive 5 and the protection layer or the wavelength converter 4.

Fig. 8 is a schematic cross-sectional view of a package structure of a semiconductor device according to a third embodiment of the present invention; the whole package structure of the semiconductor device of the third embodiment is similar to that of the second embodiment, except that the protective layer or the wavelength converter 4 covers the surface of the optoelectronic chip 22 and extends to cover a part of the surface of the control chip 21, the enclosure 6 is located on the control chip 21, the encapsulation glue 5 covers the edge of the control chip 21, and a gap is formed between the protective layer or the wavelength converter 4 and the enclosure 6. In other embodiments, the protective layer or the wavelength converter 4 may cover only the surface of the optoelectronic chip 22 without extending over the surface of the control chip 21, or the protective layer or the wavelength converter 4 covers the surface of the optoelectronic chip 22 and extends over a part of the surface of the control chip 21, and the protective layer or the wavelength converter 4 extends to be in contact with the enclosure 6. The projection of the encapsulation adhesive 5 to the direction of the substrate 1 is not overlapped with the projection of the optoelectronic chip 22 to the direction of the substrate 1, so that the brightness of the optoelectronic chip 22 can be ensured.

Fig. 9 is a schematic cross-sectional view of a package structure of a semiconductor device of a fourth embodiment of the present invention; fig. 10 is a schematic layout view of a heat conducting block in a package structure of a semiconductor device according to a fourth embodiment of the present invention; the fourth embodiment is also similar to the first embodiment, except that the heat conduction of the chip 2 in the package structure of the semiconductor device of the fourth embodiment is not achieved by the through hole 14, in the fourth embodiment, the substrate 1 is provided with one or more heat conduction blocks 15 in a region corresponding to the chip 2, for example, referring to fig. 9 and 10, a plurality of heat conduction blocks 15 are arranged below the chip 2 in an array manner, and the edge of the heat conduction block 15 is larger than the edge of the chip 2, for example, so that the heat conduction and heat dissipation capability of the package structure of the semiconductor device is enhanced by the heat conduction blocks 15, thereby further improving the stability and reliability thereof.

Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.

At the same time, it should be understood that the example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope thereof to those skilled in the art. Numerous specific details are set forth, such as examples of specific components, devices, and methods, in order to provide a thorough understanding of the present disclosure. It will be apparent to one skilled in the art that the example embodiments may be embodied in many different forms without the use of specific details, and that the example embodiments should not be construed as limiting the scope of the disclosure. In some example embodiments, well-known device structures and well-known techniques have not been described in detail.

When an element or layer is referred to as being "on," "engaged to," "connected to" or "coupled to" another element or layer, it can be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a similar fashion (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.). As used herein, the term "and/or" includes any or all combinations of one or more of the associated listed items.

Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another element, region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A package structure of a semiconductor device, comprising:

The first surface of the substrate is provided with a groove, and the thickness of the edge of the substrate is larger than that of the center of the substrate;

the control chip is positioned on the bottom surface of the groove of the substrate and is positioned in the cavity formed by the groove;

The photoelectric chip is positioned on the control chip and covers part of the surface of the control chip;

A bonding wire electrically connecting the control chip and the substrate;

a protective layer or wavelength converter covering the optoelectronic chip;

The packaging adhesive is positioned in the groove, fills a gap between the side wall of the groove and the control chip, and extends to cover one of the following top surfaces:

(1) The packaging adhesive extends to cover part of the top surface of the control chip;

(2) The packaging adhesive extends to cover part of the top surface of the protective layer;

(3) The encapsulation glue extends over a portion of the top surface of the wavelength converter.

2. The package structure of claim 1, wherein the substrate is a ceramic substrate.

3. The package structure of claim 2, wherein the substrate is an aluminum nitride ceramic substrate.

4. The package structure of claim 1, wherein the protective layer is a transparent layer.

5. The package structure of claim 1, wherein the wavelength converter is a phosphor layer.

6. The package structure of claim 1, wherein a thickness of the encapsulation glue is less than a depth of the groove, the encapsulation glue completely encapsulating the bond wire.

7. The package structure according to claim 1, wherein the protective layer or the wavelength converter further extends to cover a part of or the entire surface of the control chip.

8. The package structure of claim 1 or 7, further comprising a dam disposed around the light emitting area of the optoelectronic chip.

9. The package structure of claim 8, wherein the enclosure is located on a surface of the control chip when the encapsulation glue extends over a portion of a top surface of the control chip.

10. The package structure of claim 8, wherein the enclosure is located on a surface of the protective layer when the encapsulation glue extends over a portion of a top surface of the protective layer.

11. The package structure of claim 8, wherein the enclosure is located on a surface of the wavelength converter when the encapsulant extends over a portion of a top surface of the wavelength converter.

12. The package structure of claim 8, wherein an upper surface of the encapsulation glue is lower than an upper surface of the enclosure, the encapsulation glue being located between a sidewall of the recess and the enclosure.

13. The package structure of claim 1, wherein the substrate is further provided with a heat conducting block in a corresponding region of the control chip.

14. The package structure of claim 13, wherein the thermally conductive block is a plurality of separate thermally conductive blocks.

15. The package structure of claim 1, wherein a projection of the encapsulation glue in the substrate direction does not overlap with a projection of the optoelectronic chip in the substrate direction.

16. A method of manufacturing a package structure of a semiconductor device, comprising:

Providing a groove on a first surface of a substrate, wherein the groove is positioned in a central area of the substrate, and the thickness of the edge of the substrate is larger than that of the center of the substrate;

A control chip is arranged in a groove of the substrate, and the control chip is positioned in a cavity formed by the groove;

Arranging a photoelectric chip on the control chip, wherein the photoelectric chip covers part of the surface of the control chip;

electrically connecting the control chip with the substrate through a bonding wire;

providing a protective layer or a wavelength converter, wherein the protective layer or the wavelength converter covers the optoelectronic chip;

Arranging packaging glue on the first surface of the substrate, wherein the packaging glue fills a gap between the side wall of the groove and the control chip and extends to cover one of the following top surfaces:

17. The method of manufacturing according to claim 16, wherein the substrate is a ceramic substrate.

18. The method of manufacturing according to claim 17, wherein the substrate is an aluminum nitride ceramic substrate.

19. The method of manufacturing according to claim 16, wherein the protective layer is a transparent layer.

20. The method of manufacturing according to claim 16, wherein the wavelength converter is a phosphor layer.

21. The method of manufacturing of claim 16, wherein the thickness of the encapsulation glue is less than the depth of the grooves, the encapsulation glue completely encapsulating the bond wires.

22. The method of manufacturing according to claim 16, wherein the protective layer or the wavelength converter further extends to cover a part of or the entire surface of the control chip.

23. The method of manufacturing of claim 16 or 22, further comprising a dam disposed around the light emitting area of the optoelectronic chip.

24. The method of manufacturing of claim 23, wherein the enclosure is located on a surface of the control chip when the encapsulation glue extends over a portion of the top surface of the control chip.

25. The method of manufacturing of claim 23, wherein the enclosure is located on a surface of the protective layer when the encapsulation glue extends over a portion of the top surface of the protective layer.

26. The method of manufacturing of claim 23, wherein the enclosure is located on a surface of the wavelength converter when the encapsulant extends over a portion of the top surface of the wavelength converter.

27. The method of manufacturing of claim 23, wherein the upper surface of the encapsulation glue is lower than the upper surface of the enclosure, the encapsulation glue being located between the sidewall of the recess and the enclosure.

28. The method of manufacturing of claim 16, wherein the substrate is further provided with a thermally conductive block in a corresponding region of the control chip.

29. The method of manufacturing of claim 28, wherein the thermally conductive block is a plurality of separate thermally conductive blocks.

30. The method of manufacturing according to claim 16, wherein the projection of the encapsulation compound to the substrate direction does not overlap with the projection of the optoelectronic chip to the substrate direction.