CN118411965B

CN118411965B - Display panel and electronic equipment

Info

Publication number: CN118411965B
Application number: CN202410874603.8A
Authority: CN
Inventors: 吴川; 徐培
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2024-07-02
Filing date: 2024-07-02
Publication date: 2024-09-06
Anticipated expiration: 2044-07-02
Also published as: CN118411965A

Abstract

The application provides a display panel and an electronic device. The display panel has a plurality of pixel areas arranged in an array, the display panel also comprises a bearing substrate, a public electrode wire positioned on the bearing substrate, a first sub-pixel electrode, a second sub-pixel electrode the first thin film transistor, the second thin film transistor, the first connecting section, the second connecting section and the second connecting section; the public electrode wire comprises a plurality of public body parts and public connection parts which are connected in sequence, and the public connection parts deviate from the bearing substrate compared with the public body parts; in two adjacent pixel areas in the same row: the first thin film transistor and the first sub-pixel electrode are positioned in one of the two pixel areas, and the source electrode of the first thin film transistor is electrically connected to the first sub-pixel electrode through the first connecting section; the second thin film transistor and the second sub-pixel electrode are positioned in the other one of the two pixel areas, and the source electrode of the second thin film transistor is electrically connected to the second sub-pixel electrode through a second connecting section, wherein the second connecting section and the common connecting part are arranged in a crossing mode to form parasitic capacitance.

Description

Display panel and electronic equipment

Technical Field

The application relates to the field of display, in particular to a display panel and electronic equipment.

Background

The liquid crystal display panel is popular with users because of its advantages of good viewing angle, low power consumption, long lifetime, etc. The display effect of the liquid crystal display panel when displaying a picture is receiving increasing attention from a user. However, the display quality of the liquid crystal display panel in the related art has room for improvement.

Disclosure of Invention

In a first aspect, an embodiment of the present application provides a display panel, where the display panel has a plurality of pixel areas arranged in an array, and the display panel further includes a carrier substrate and a pixel electrode disposed on the carrier substrate:

the public electrode wire comprises a plurality of public body parts and public connection parts which are connected in sequence, and the public connection parts deviate from the bearing substrate compared with the public body parts;

A first subpixel electrode;

a first thin film transistor;

the second sub-pixel electrode is arranged corresponding to the sub-pixels with different colors respectively with the first sub-pixel electrode;

A second thin film transistor;

A first connection section; and

A second connection section;

in two adjacent pixel areas in the same row: the first thin film transistor and the first sub-pixel electrode are positioned in one of the two pixel areas, and the source electrode of the first thin film transistor is electrically connected to the first sub-pixel electrode through the first connecting section; the second thin film transistor and the second sub-pixel electrode are located in the other one of the two pixel areas, and a source electrode of the second thin film transistor is electrically connected to the second sub-pixel electrode through the second connection section, wherein the second connection section and the common connection section are arranged in a crossing mode to form parasitic capacitance.

In a second aspect, an embodiment of the present application provides an electronic device, including the display panel according to the first aspect.

In the display panel provided by the embodiment of the application, the common connection part is far away from the bearing substrate compared with the common body part, so that the distance from the common connection part to the bearing substrate is relatively long. The source electrode of the second thin film transistor is electrically connected to the second sub-pixel electrode through the second connection section, wherein the second connection section and the common connection section are arranged in a crossing manner to form a parasitic capacitance. In the case that the distance from the second section to the carrier substrate is constant and the material of the medium between the carrier substrate and the second section is constant, the distance from the common connection portion to the carrier substrate is relatively long, and the distance from the common connection portion to the second section is also relatively long, so that the capacitance value of the parasitic capacitance is small. In other words, the parasitic capacitance formed by the second segment crossing the common electrode is relatively small. Therefore, the display panel provided by the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel displays.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a display panel according to an embodiment of the application;

FIG. 2 is a schematic representation of the display panel of FIG. 1 in an additional dimension;

FIG. 3 is a schematic view of a portion of the display panel shown in FIG. 1;

FIG. 4 is a schematic view of a portion of the display panel of FIG. 3;

FIG. 5 is a schematic diagram of the common electrode line and the second connection section in FIG. 4;

FIG. 6 is a schematic diagram of a second connection section provided in an embodiment in FIG. 5;

FIG. 7 is an exploded schematic view of the second connecting section shown in FIG. 6;

FIG. 8 is a schematic illustration of the dimensions of the portions of the second section of FIG. 7;

FIG. 9 is a schematic diagram of a dimensional identifier of a portion of the structure of FIG. 5;

FIG. 10 is a schematic structural view of a second section according to an embodiment;

FIG. 11 is a schematic diagram illustrating an included angle between a connection portion and a common connection portion in a display panel according to an embodiment;

FIG. 12 is a schematic view of a portion of the structure of FIG. 3;

FIG. 13 is a schematic view of FIG. 12 taken along line I-I;

FIG. 14 is an enlarged schematic view of FIG. 12 at II;

FIG. 15 is a schematic diagram of a display panel according to an embodiment of the application;

FIG. 16 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application;

FIG. 17 is a flowchart of another method for manufacturing a display panel according to the present application;

Fig. 18 is a schematic diagram of an electronic device according to an embodiment of the present application.

Reference numerals for main elements:

The electronic device 1, the display panel 10, the display area 10a, the non-display area 10b, the housing 30;

A carrier substrate 100, a data line 110, a scan line group 120, a first scan line 121, and a second scan line 122;

a pixel region 110a, a first sub-pixel region 110b, and a second sub-pixel region 110c;

A first subpixel electrode 130, a first thin film transistor Q1, a second thin film transistor Q2, a gate g, a source s, and a drain d;

the first connection section 140, the short-hand structure 140A, the second connection section 150, the long-hand structure 150A, the first section 151, the second section 152, the first pad 1521, the connection portion 1522, the second pad 1523, the first sub-conductive layer 152a, the second sub-conductive layer 152b;

A first insulating layer 160, a first via 161, an insulating planarization layer 170, a second via 171, a second insulating layer 180, a common electrode line 190, a common body portion 191, a common connection portion 192, a second sub-pixel electrode 210, a cof module 230, a cof unit 231, a circuit board 240, a gate insulating layer 260, a third via 261, a fourth via 172, a fifth via 181;

a first direction D1, a second direction D2.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" or "implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 2, fig. 3, fig. 4 and fig. 5, fig. 1 is a schematic diagram of a display panel according to an embodiment of the application; FIG. 2 is a schematic representation of the display panel of FIG. 1 in an additional dimension; FIG. 3 is a schematic view of a portion of the display panel shown in FIG. 1; FIG. 4 is a schematic view of a portion of the display panel of FIG. 3; fig. 5 is a schematic diagram of the common electrode line and the second connection section in fig. 4. The display panel 10 has a plurality of pixel regions 110a arranged in an array. The display panel 10 further includes a carrier substrate 100, a common electrode line 190, a first sub-pixel electrode 130, a first thin film transistor Q1, a second sub-pixel electrode 210, a second thin film transistor Q2, a first connection section 140 and a second connection section 150 disposed on the carrier substrate 100. The common electrode line 190 includes a plurality of common body portions 191 and common connection portions 192 connected in sequence. The common connection portion 192 faces away from the carrier substrate 100 compared to the common body portion 191. The second subpixel electrode 210 and the first subpixel electrode 130 are respectively disposed corresponding to the subpixels of different colors. In two adjacent pixel regions 110a in the same row: the first thin film transistor Q1 and the first sub-pixel electrode 130 are located in one of the two pixel regions 110a, and the source s of the first thin film transistor Q1 is electrically connected to the first sub-pixel electrode 130 through the first connection section 140; the second thin film transistor Q2 and the second sub-pixel electrode 210 are located in the other of the two pixel regions 110a, and the source s of the second thin film transistor Q2 is electrically connected to the second sub-pixel electrode 210 through the second connection section 150, wherein the second connection section 150 and the common connection section 192 are disposed to cross each other to form a parasitic capacitance.

In this embodiment, the display panel 10 includes a plurality of data lines 110 disposed at intervals and a plurality of scan line groups 120 disposed at intervals. The scan line set 120 includes a first scan line 121 and a second scan line 122 disposed at intervals. The plurality of scan line groups 120 are disposed to intersect and insulate the plurality of data lines 110. The two adjacent data lines 110 and the first scan line 121 and the second scan line 122 located in the same scan line group 120 together define a pixel region 110a.

For example, in the view angle of the present embodiment, the plurality of data lines 110 are arranged at intervals along the first direction D1, and the data lines 110 extend along the second direction D2. The plurality of scan line groups 120 are arranged at intervals along the second direction D2, and the scan line groups 120 extend along the first direction D1, and the scan line groups 120 include first scan lines 121 and second scan lines 122 arranged at intervals along the second direction D2. The first direction D1 is a transverse direction, and the second direction D2 is a longitudinal direction. It can be appreciated that the first direction D1 and the second direction D2 may also change according to the placement posture of the display panel 10. As long as the first direction D1 and the second direction D2 are different.

Two adjacent columns of data lines 110 and the first scan line 121 and the second scan line 122 of each scan line group 120 define a pixel region 110a, and thus the display panel 10 includes a plurality of pixel regions 110a arranged in an array.

For example, the mth column data line 110, the m+1th column data line 110, and the first scan line 121 and the second scan line 122 in the kth scan line set 120 together define a pixel region 110a, and the pixel region 110a may be named as an MK pixel region 110a. Accordingly, the mth column data line 110, the m+1th column data line 110, and the first scan line 121 and the second scan line 122 in the k+1th scan line group 120 collectively define a pixel region 110a, and the pixel region 110a may be named as an mth (k+1) pixel region 110a. Accordingly, the (m+1) -th column data line 110, and the first scan line 121 and the second scan line 122 in the kth row scan line group 120 collectively define a pixel region 110a, and the pixel region 110a may be named as an (m+1) -th K pixel region 110a.

In the schematic diagram of the present embodiment, referring to fig. 2, the kth line scan line group 120 is identified as 120 (K); the k+1th row scan line group 120 is identified as 120 (k+1); the mth column data line 110 is identified as 110 (M); column M+1 data line 110 is identified as 110 (M+1); the MK pixel region 110a is identified as 110a (MK); the Mth (K+1) pixel region 110a is identified as 110aM (K+1).

The first subpixel electrode 130 is configured to correspond to a first color subpixel, and the first color subpixel may be a red subpixel, a green subpixel, or a blue subpixel.

In two adjacent pixel regions 110a in the same row: the first thin film transistor Q1 and the first sub-pixel electrode 130 are located in one of the two pixel regions 110a, and the source s of the first thin film transistor Q1 is electrically connected to the first sub-pixel electrode 130 through the first connection section 140; the second thin film transistor Q2 and the second sub-pixel electrode 210 are located in the other of the two pixel regions 110a, and the source s of the second thin film transistor Q2 is electrically connected to the second sub-pixel electrode 210 through the second connection section 150, wherein the second connection section 150 and the common connection section 192 are disposed to cross each other to form a parasitic capacitance.

For example, two adjacent pixel regions 110a in the same row are respectively named as an MK-th pixel region 110a and an M (k+1) -th pixel region 110a. The first thin film transistor Q1 and the first sub-pixel electrode 130 are located in one of the two pixel regions 110a, and in the present embodiment, the first thin film transistor Q1 and the first sub-pixel electrode 130 are located in the mth (k+1) th pixel region 110a. The second thin film transistor Q2 and the second sub-pixel electrode 210 are located in the other of the two pixel regions 110a, and in this embodiment, the second thin film transistor Q2 and the second sub-pixel electrode 210 are located in the MK-th pixel region 110a. It is understood that, in other embodiments, the first thin film transistor Q1 and the first sub-pixel electrode 130 are located in the MK pixel region 110a; accordingly, the second thin film transistor Q2 and the second sub-pixel electrode 210 are located in the mth (k+1) th pixel region 110a.

Further, one of two adjacent pixel regions 110a located in the same column: the source s of the first thin film transistor Q1 is electrically connected to the first subpixel electrode 130 of the same pixel region 110a through the first connection section 140; another of the two adjacent pixel regions 110a located in the same column: the source s of the first thin film transistor Q1 is electrically connected to the first subpixel electrode 130 of the same pixel region 110a through the second connection segment 150.

In an embodiment, one of two adjacent first thin film transistors Q1 located in the same column is electrically connected to the mth column data line 110 through the first connection section 140; the source s of the other of the two first thin film transistors Q1 adjacent in the same column is electrically connected to the m+1th column data line 110 through the second connection section 150.

The second connection section 150 has a length greater than that of the first connection section 140, and the second connection section 150 has a resistance equal to that of the first connection section 140, and a specific case of the second connection section 150 will be described later. In this embodiment, the first connection section 140 is also referred to as a short-hand structure 140A, and the second connection section 150 is also referred to as a long-hand structure 150A.

The pixel region 110a includes a first sub-pixel region 110b and a second sub-pixel region 110c adjacent to each other and arranged along a first direction D1. The first sub-pixel electrode 130 is located in the first sub-pixel region 110b. The second subpixel electrode 210 is located in the second subpixel area 110c and is configured to be disposed corresponding to a second color subpixel, where the second color subpixel is different from the first color subpixel. The gate g of the second thin film transistor Q2 is electrically connected to the second scan line 122 corresponding to the pixel region 110a where the second thin film transistor Q2 is located; the drain d of the second thin film transistor Q2 is electrically connected to the data line 110 connected to the drain d of the first thin film transistor Q1 of the same pixel region 110 a; the source s of the second tft Q2 is electrically connected to the second subpixel electrode 210 in the same pixel area 110A through the long-hand structure 150A (i.e., another second connection segment 150).

In an embodiment, the source s of the second tft Q2 is electrically connected to the second sub-pixel electrode 210 located in the same pixel region 110A through the long-hand structure 150A (i.e. the second connection segment 150). The long-hand structure 150A to which the source s of the second thin film transistor Q2 is connected may be described with reference to any of the foregoing embodiments, and will not be described herein.

In the display panel 10 according to the embodiment of the present application, the common connection portion 192 faces away from the carrier substrate 100 compared to the common body portion 191, and therefore, the distance from the common connection portion 192 to the carrier substrate 100 is relatively longer. The source s of the second thin film transistor Q2 is electrically connected to the second subpixel electrode 210 through the second connection segment 150, wherein the second connection segment 150 is disposed to cross the common connection portion 192 to form a parasitic capacitance. In the case where the distance from the second section 152 to the carrier substrate 100 is constant and the material of the medium (specific medium will be described in detail later) between the carrier substrate 100 and the second section 152 is constant, the distance from the common connection 192 to the carrier substrate 100 is relatively long, and the distance from the common connection 192 to the second section 152 is also relatively long, so that the capacitance value of the parasitic capacitance is small. In other words, the parasitic capacitance formed by the second segment 152 crossing the common electrode is relatively small. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

Further, in an embodiment, the length of the second connection section 150 is greater than the length of the first connection section 140, and the resistance of the second connection section 150 is equal to the resistance of the first connection section 140. It should be noted that, the resistances of the second connection section 150 and the first connection section 140 are equal, and the case where the resistances of the second connection section 150 and the first connection section 140 are completely equal, or approximately equal, is included. Specifically, in one embodiment, the resistance of the first connection section 140 is named as a first resistance R1, and the resistance of the second connection section 150 is named as a second resistance R2, then 0.9R 2 is equal to or less than: r1 is less than or equal to 1.1. For example, R2: r1 may be, but is not limited to, 0.9, or 0.95, or 1.0, or 1.05, or 1.1. In this way, the resistance of the second connection segment 150 is equal or approximately equal to the resistance of the first connection segment 140. In the two adjacent pixel regions 110a located in the same row, the impedance between the first thin film transistor Q1 and the first sub-pixel electrode 130 is R, and the impedance between the second thin film transistor Q2 and the second sub-pixel electrode 210 is R'. The resistance of the second connection segment 150 is equal or approximately equal to the resistance of the first connection segment 140. When R2: when r1=1.0, R and R 'are generally equal, so that the problem of bright and dark lines caused by excessive impedance between R and R' can be reduced or even avoided. When R2 is more than or equal to 0.9: r1 is less than 1.0; or 1.0 < R2: when R1 is less than or equal to 1.1, the resistance of the second connection section 150 is considered to be approximately equal to the resistance of the first connection section 140. In this way, although the resistance of the second connection section 150 is different from the resistance of the first connection section 140, bright and dark lines that can be observed by human eyes are not easily generated when the display panel 10 displays.

It can be understood that, regardless of the length-size relationship between the first connection section 140 and the second connection section 150, and the resistance relationship between the first connection section 140 and the second connection section 150, only in the case that the length relationship between the first connection section 140 and the second connection section 150 is constant, and the resistance relationship between the first connection section 140 and the second connection section 150 is constant: the source s of the second thin film transistor Q2 is electrically connected to the second sub-pixel electrode 210 through the second segment 152, where the second connecting segment 150 and the common connecting portion 192 are disposed to form a parasitic capacitance, so that crosstalk caused by the larger parasitic capacitance when the display panel 10 displays can be improved.

Referring to fig. 6 and fig. 7 together, fig. 6 is a schematic diagram of a second connection section provided in the embodiment of fig. 5; fig. 7 is an exploded view of the second connecting section shown in fig. 6. The second connecting section 150 includes a first section 151 and a second section 152. The first segment 151 is connected to the source s of the second tft Q2 and is integrally formed with the source s. The second segment 152 is electrically connected to the first segment 151 and the second subpixel electrode 210, and the second segment 152 is adjacent to the carrier substrate 100 compared to the first segment 151.

The common connection 192 faces away from the carrier substrate 100 compared to the second connection section 150. The second section 152 and the first section 151 are disposed in different layers, and the second section 152 is closer to the carrier substrate 100 than the first section 151, so that the second section 152 is closer to the carrier substrate 100, and the distance between the second section 152 and the common connection portion 192 is increased as much as possible, and in the case that the material of the medium (specific medium will be described in detail later) between the carrier substrate 100 and the second section 152 is fixed, the distance between the common connection portion 192 and the second section 152 is relatively longer, and therefore, the capacitance value of the parasitic capacitance is smaller. In other words, the parasitic capacitance formed by the second segment 152 crossing the common electrode line 190 is relatively small. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

In addition, the first segment 151 is connected to and integrally constructed with the source s of the second thin film transistor Q2, and thus, the first segment 151 may be prepared in the same process as the source s of the second thin film transistor Q2 to save the process.

With continued reference to fig. 1 and 2, the display panel 10 further includes a scan line set 120. The scan line set 120 is adjacent to the carrier substrate 100 compared to the source s of the second tft Q2, wherein the second segment 152 is disposed on the same layer as the scan line set 120.

The scan line set 120 is described above, and will not be described herein. The scan line group 120 is adjacent to the carrier substrate 100 compared to the source s of the second thin film transistor Q2, and the second segment 152 is disposed in the same layer as the scan line group 120, so that the second segment 152 is adjacent to the carrier substrate 100 compared to the source s of the second thin film transistor Q2, and thus, the second segment 152 is relatively adjacent to the carrier substrate 100, and the distance between the second segment 152 and the common connection 192 is increased as much as possible, and in the case that the material of the medium (specific medium will be described in detail later) between the carrier substrate 100 and the second segment 152 is certain, the distance between the common connection 192 and the second segment 152 is relatively long, and thus, the capacitance value of the parasitic capacitance is small. In other words, the parasitic capacitance formed by the second segment 152 crossing the common electrode is relatively small. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

In addition, the second section 152 and the scan line group 120 are disposed in the same layer, and the second section 152 and the scan line group 120 can be manufactured in the same manufacturing process, so as to save the manufacturing process of the display panel 10. In one embodiment, the material of the second section 152 is the same as the material of the scan line set 120. The material of the second section 152 and the material of the scan line set 120 may be metal.

Referring to fig. 6, 7 and 8, fig. 8 is a schematic diagram illustrating the dimensions of the parts of the second section in fig. 7. The second section 152 includes a first pad portion 1521, a connecting portion 1522, and a second pad portion 1523 that are sequentially bent and connected. The first pad 1521 is configured to be electrically connected to the first segment 151, and a width W1 of the first pad 1521 is greater than a line width W0 of the connection portion 1522. The second pad 1523 is electrically connected to the second subpixel electrode 210, and the width W2 of the second pad 1523 is greater than the line width W0 of the connection portion 1522.

In this embodiment, the second section 152 includes a first pad 1521, a connecting portion 1522, and a second pad 1523 that are sequentially bent and connected. The first pad 1521 is configured to be electrically connected to the first segment 151, and the width of the first pad 1521 is greater than the line width of the connection portion 1522, so that the electrical connection performance of the first pad 1521 and the first segment 151 is better.

Further, the second pad 1523 is configured to be electrically connected to the second sub-pixel electrode 210, and the width of the second pad 1523 is greater than the line width of the connection portion 1522, so that the electrical connection performance of the second pad 1523 when electrically connected to the second sub-pixel electrode 210 is better.

Further, referring to fig. 8, the width W1 of the first pad 1521 satisfies: w1 is less than or equal to 2 mu m and less than or equal to 50 mu m. The width W2 of the second pad 1523 satisfies: w2 is more than or equal to 2 μm and less than or equal to 50 μm, and W2 is less than W1.

In an embodiment, the width W1 of the first pad 1521 may be, but is not limited to, 2 μm, or 5 μm, or 10 μm, or 15 μm, or 20 μm, or 25 μm, or 30 μm, or 35 μm, or 40 μm, or 45 μm, or 50 μm. The width W1 of the first pad 1521 satisfies: the size of the first pad 1521 is smaller than or equal to 2 μm and is smaller than or equal to 50 μm, so that the electrical connection performance of the first pad 1521 and the first segment 151 is better, and the size of the first pad 1521 is smaller, so that the display panel 10 has a higher aperture ratio.

The width W2 of the second pad 1523 may be, but is not limited to, 2 μm, or 5 μm, or 10 μm, or 15 μm, or 20 μm, or 25 μm, or 30 μm, or 35 μm, or 40 μm, or 45 μm, or 50 μm. The width W2 of the second pad 1523 satisfies: the size of the second pad 1523 may be relatively smaller, so that the display panel 10 may have a higher aperture ratio, on the one hand, the electrical connection performance of the second pad 1523 when electrically connected to the first subpixel electrode 130 may be better, and on the other hand, the size of the second pad 1523 may be smaller.

In addition, W2 < W1, the first pad 1521 may be designed to be larger in a limited space, so that the electrical connection performance of the first pad 1521 when electrically connected to the first segment 151 is better.

Further, referring to fig. 5 to 7, the common body 191 is disposed at the same level as the first section 151.

The common body 191 is disposed in the same layer as the first section 151, and thus, the common body 191 and the first section 151 may be manufactured in the same process to save the manufacturing process of the display panel 10.

Referring to fig. 5, 6 and 9, fig. 9 is a schematic diagram of a dimension identification of a portion of the structure in fig. 5. In an embodiment, the line width W0 of the connection portion 1522 of the second segment 152 satisfies: w0 is less than or equal to 2 mu m and less than or equal to 5 mu m, and the thickness d1 of the second section 152 meets the following conditions: d1 is more than or equal to 1000 and less than or equal to 8000 angstroms; the line width w2 of the common connection portion 192 satisfies: the thickness d2 of the common connection portion 192 is 3 μm or less and w2 is 100 μm or less, and the thickness d2 satisfies: d2 is 1000 angstrom or less and is less than or equal to 6000 angstroms.

The line width W0 of the connection portion 1522 of the second segment 152 may be, but is not limited to, 2 μm, or 3 μm, or 4 μm, or 5 μm. The thickness d1 of the second segment 152 may be, but is not limited to, 1000 angstroms, or 2000 angstroms, or 3000 angstroms, or 4000 angstroms, or 5000 angstroms, or 6000 angstroms, or 7000 angstroms, or 8000 angstroms. The line width w2 of the common connection portion 192 may be, but is not limited to, 3 μm, or 4 μm, or 5 μm, or 10 μm, or 20 μm, or 30 μm, or 40 μm, or 50 μm, or 60 μm, or 70 μm, or 80 μm, or 90 μm, or 100 μm. The thickness d2 of the common connection 192 may be, but is not limited to, 1000 angstroms, or 2000 angstroms, or 3000 angstroms, or 4000 angstroms, or 5000 angstroms, or 6000 angstroms.

The line width W0 of the connection portion 1522 of the second segment 152 satisfies: 2 μm.ltoreq.w1.ltoreq.5μm, the thickness d1 of the second section 152 satisfying: d1 is more than or equal to 1000 and less than or equal to 8000 angstroms; the line width w2 of the common connection portion 192 satisfies: the thickness d2 of the common connection portion 192 is 3 μm or less and w2 is 100 μm or less, and the thickness d2 satisfies: d2 is more than or equal to 1000 and less than or equal to 6000 angstroms, so that the capacitance value of the parasitic capacitance is smaller. In other words, the parasitic capacitance formed by the second segment 152 crossing the common electrode is relatively small. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a second section according to an embodiment. In another embodiment, the second segment 152 includes a first sub-conductive layer 152a and a second sub-conductive layer 152b that are stacked. Wherein the second sub-conductive layer 152b faces away from the carrier substrate 100 compared to the first sub-conductive layer 152 a. In one embodiment, the adhesion of the first sub-conductive layer 152a is greater than the adhesion of the second sub-conductive layer 152 b; the second sub-conductive layer 152b has a conductivity greater than the adhesion of the first sub-conductive layer 152 a. Thus, the second section 152 has not only good electrical conductivity but also good adhesion.

Further, in an embodiment, the thickness of the first sub-conductive layer 152a may be smaller than the thickness of the second sub-conductive layer 152 b. In this way, the second section 152 may be made further more conductive.

In an embodiment, referring to fig. 11, fig. 11 is a schematic diagram illustrating an included angle between a connection portion and a common connection portion in a display panel according to an embodiment. The angle a between the connection 1522 of the second segment 152 and the common connection 192 satisfies: a is more than or equal to 60 degrees and less than or equal to 90 degrees.

For example, the a may be, but is not limited to being 60 °, or 70 °, or 80 °, or 90 °. The angle a between the second section 152 and the common connection 192 satisfies: at 60 a-90, the facing area between the second section 152 and the common connection 192 is relatively small, thereby making the capacitance value of the parasitic capacitance small. In other words, the parasitic capacitance formed by the intersection of the second segment 152 and the common connection 192 is relatively small. Therefore, crosstalk due to a large parasitic capacitance when the display panel 10 displays can be improved.

Further, in an embodiment, the second section 152 includes one or more of copper (Cu), aluminum (Al), molybdenum (Mo), and the thickness d1 of the second section 152 satisfies: 1000 angstroms or less d1 or less 8000 angstroms can result in a lower resistance per unit length of the second segment 152. Even in the case that the second section 152 is long, it is still possible to satisfy that the sum of the resistance of the second section 152 and the resistance of the first section 151 (i.e., the sum of the resistances of the second connection sections 150) is equal to the resistance of the first connection sections 140. Therefore, the problem of bright and dark lines caused by excessively large impedance differences between two adjacent first thin film transistors Q1 and the corresponding first sub-pixel electrodes 130 in the same row can be reduced or even avoided. It can be seen that the display panel 10 provided by the embodiment of the application has higher display quality.

In the related art display panel 10, the second section 152 is typically a single layer of Indium Tin Oxide (ITO), and thus the second section 152 has a relatively large resistance. In this embodiment, the second section 152 is a metal conductive member, and under the same length, the resistance of the metal conductive member can be designed to be relatively small, so in the display panel 10 provided by the embodiment of the present application, the second section 152 is a metal conductive member, and therefore, although the length of the second connection section 150 is greater than that of the first connection section 140, the second section 152 may be a metal conductive member, and the second section 152 includes one or more of copper (Cu), aluminum (Al), and molybdenum (Mo), so that the sum of the resistance of the second section 152 and the resistance of the first section 151 (i.e., the sum of the resistances of the second connection section 150) is equal to the resistance of the first connection section 140.

The second section 152 comprises one or more of Cu, al, mo, for example, when the second section 152 comprises one of Cu, al, mo, the second section 152 is a Cu metal conductor; or the second section 152 is an Al metal conductor; or the second section 152 is a Mo metal conductor. When the second section 152 includes two of Cu, al, mo, the second section 152 is an alloy of Cu and Al; or the second section 152 is an alloy of Cu and Mo; or the second section 152 is an alloy of Al and Mo. The second section 152 comprises an alloy of Cu, al, mo.

Referring to fig. 12 and 13, fig. 12 is a schematic view of a portion of the structure in fig. 3; FIG. 13 is a schematic view of FIG. 12 taken along line I-I. The display panel 10 further includes a gate insulating layer (GI) 260, a first insulating layer (PV 1) 160, and an insulating planarization layer (PFA) 170. The gate insulating layer 260 is disposed on one side of the carrier substrate 100. Specifically, in one embodiment, the gate insulating layer 260 is disposed on the surface of the scan line set 120 and the second section 152 facing away from the carrier substrate 100. The common body 191 is disposed on the gate insulating layer 260. The first insulating layer 160 is disposed on a surface of the common body 191 facing away from the carrier substrate 100, and has two first through holes 161 disposed at intervals, where the first through holes 161 are used for exposing the common body 191. The insulating flat layer 170 is disposed on a surface of the first insulating layer 160 facing away from the carrier substrate 100, and has two second through holes 171 disposed at intervals, where each second through hole 171 is communicated with one first through hole 161. The common connection portion 192 is disposed on a surface of the insulating planarization layer 170 facing away from the carrier substrate 100, and is electrically connected to two adjacent common body portions 191 through the first through hole 161 and the second through hole 171.

In the present embodiment, the display panel 10 further includes a gate insulating layer 260, which is illustrated in the figure, and other structures are not illustrated. The gate insulating layer 260 is located at a side of the common body portion 191 close to the carrier substrate 100.

The common connection portion 192 is used to electrically connect two adjacent common body portions 191. The first insulating layer 160 has two first through holes 161 disposed at intervals, the first through holes 161 are used for exposing the common body 191, in other words, one of the two first through holes 161 is used for exposing one of the two common body 191, and the other of the two first through holes 161 is used for exposing the other of the two common body 191.

The surface of the insulating planarization layer 170 facing away from the carrier substrate 100 is planar or approximately planar. The insulating planarization layer 170 has two second through holes 171 disposed at intervals. One of the two second through holes 171 communicates with the one of the two first through holes 161, and the other of the two second through holes 171 communicates with the other of the two first through holes 161.

The common connection portion 192 is disposed on a surface of the insulating flat layer 170 facing away from the carrier substrate 100, and one end of the common connection portion 192 is electrically connected to the one of the two common body portions 191 through the one of the two second through holes 171 and the one of the two first through holes 161; the other end of the common connection portion 192 is electrically connected to the other of the two common body portions 191 through the other of the two second through holes 171 and the other of the two first through holes 161.

It can be seen that the medium between the second connection section 150 and the common connection portion 192 includes a gate insulating layer 260, a first insulating layer 160, and an insulating planarization layer 170. The calculation formula of the parasitic capacitance is. Wherein epsilon is the dielectric constant of the medium; k is a constant; d is the thickness between the capacitive electrode plates, in embodiments between the second section 152 of the second connection section 150 and the common connection 192; s is the capacitive area, i.e. the area facing between the second segment 152 and the common connection 192.

In the related art, the common electrode line 190 is generally in an integral structure, and the position of the common electrode line 190 is the same as that of the common body 191 in the display panel 10 provided in the embodiment of the present application, so that the distance between the common electrode line 190 and the second section 152 of the second connection section 150 in the related art is relatively short, and thus, the parasitic capacitance formed by the common electrode line 190 and the second section 152 of the second connection section 150 is relatively large. In the display panel 10 according to the embodiment of the present application, the common connection portion 192 is away from the carrier substrate 100 compared to the common body portion 191, so that a distance between the common connection portion 192 and the second section 152 of the second connection section 150 is greater, and therefore, a capacitance value of the parasitic capacitance formed by the second connection section 150 crossing the common connection portion 192 is smaller. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

Further, the thickness of the gate insulating layer 260 is D _g, the thickness of the first insulating layer 160 is D _pv1, and the thickness of the insulating planarization layer 170 is D _PFA, wherein D _g＜D_pv1+D_PFA. In addition, the common body 191 and the second section 152 are staggered (i.e., not directly opposite) so that parasitic capacitance between the common body 191 and the second section 152 is small. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

In an embodiment, the gate insulating layer 260 includes a silicon nitride (SiNx) monolayer, or a silicon oxide (SiO 2) monolayer, or a stack of silicon nitride (SiNx) and silicon oxide (SiO 2), wherein the thickness D _g of the gate insulating layer 260 satisfies: d _g a to 8000 a. The first insulating layer 160 includes a silicon nitride monolayer, or a silicon oxide monolayer, or a stack of silicon nitride and silicon oxide, wherein the thickness D _pv1 of the first insulating layer 160 satisfies: d _PV1 a to 8000 a. The insulating planarization layer 170 is an organic insulating layer, and the thickness D _PFA of the insulating planarization layer 170 satisfies: d _PFA of 5000 angstroms or less less than or equal to 30000 angstroms.

1 Angstrom is equal to 0.1 nanometers (nm). In one embodiment, when the gate insulating layer 260 includes a stack of silicon nitride (SiNx) and silicon oxide (SiO 2), in other words, the gate insulating layer 260 includes a stack of a silicon nitride (SiNx) layer and a silicon oxide (SiO 2) layer. The silicon oxide (SiO 2) layer in the gate insulating layer 260 is closer to the active layer of the thin film transistor (e.g., the first thin film transistor Q1, the second thin film transistor Q2) than the silicon nitride (SiNx) layer in the gate insulating layer 260.

In one embodiment, when the first insulating layer 160 includes a stack of silicon nitride (SiNx) and silicon oxide (SiO 2), in other words, the first insulating layer 160 includes a stack of a silicon nitride (SiNx) layer and a silicon oxide (SiO 2) layer. The silicon oxide (SiO 2) layer in the first insulating layer 160 is closer to the active layer of the thin film transistor (e.g., the first thin film transistor Q1, the second thin film transistor Q2) than the silicon nitride (SiNx) layer in the first insulating layer 160.

The gate insulating layer 260 includes a silicon nitride (SiNx) single layer, or a silicon oxide (SiO 2) single layer, or a stack of silicon nitride (SiNx) and silicon oxide (SiO 2), wherein a thickness D _g of the gate insulating layer 260 satisfies: d _g -8000 angstroms; the first insulating layer 160 includes a silicon nitride monolayer, or a silicon oxide monolayer, or a stack of silicon nitride and silicon oxide, wherein the thickness D _pv1 of the first insulating layer 160 satisfies: d _PV1 -8000 angstroms; the insulating planarization layer 170 is an organic insulating layer, and the thickness D _PFA of the insulating planarization layer 170 satisfies: and D _PFA is less than or equal to 5000 angstroms and less than or equal to 30000 angstroms, so that the capacitance value of the parasitic capacitance is smaller. In other words, the parasitic capacitance formed by the second segment 152 crossing the common electrode is relatively small. Therefore, the display panel 10 provided in the embodiment of the application can improve crosstalk caused by larger parasitic capacitance when the display panel 10 displays.

Further, the display panel 10 further includes a second insulation layer (PV 2) 180. The second insulating layer 180 is disposed on a surface of the common connection portion 192 facing away from the carrier substrate 100. The second insulating layer 180 is used to protect the common connection portion 192, prevent the common connection portion 192 from being oxidized or damaged, etc.

In one embodiment, when the second insulating layer 180 includes a stack of silicon nitride (SiNx) and silicon oxide (SiO 2), in other words, the second insulating layer 180 includes a stack of a silicon nitride (SiNx) layer and a silicon oxide (SiO 2) layer. The silicon oxide (SiO 2) layer in the second insulating layer 180 is closer to the active layer of the thin film transistor (e.g., the first thin film transistor Q1, the second thin film transistor Q2) than the silicon nitride (SiNx) layer in the second insulating layer 180. In one embodiment, the thickness D _PV2 of the second insulating layer 180 satisfies: d _PV2 of 1000 angstrom or less and 7000 angstroms or less.

Referring to fig. 14, fig. 14 is an enlarged schematic view of fig. 12 at II. In this embodiment, the second segment 152 of the second connection segment 150 is electrically connected to the second subpixel electrode 210 through each through hole. Specifically, the gate insulating layer 260 has a third through hole 261, the insulating planarization layer 170 has a fourth through hole 172, and the second insulating layer 180 has a fifth through hole 181. The second subpixel electrode 210 is electrically connected to the second segment 152 through the third through hole 261, the fourth through hole 172, and the fifth through hole 181.

Referring to fig. 1 to 3 and fig. 12, a common connection portion 192 is disposed across the second connection sections 150 (specifically, the second sections 152 of the second connection sections 150) of the two adjacent pixel regions 110a, and forms parasitic capacitances respectively.

In this way, one common connection portion 192 may be disposed to cross the second connection sections 150 of the adjacent two pixel regions 110a, respectively, to form parasitic capacitances, and thus, the number of common connection portions 192 in the display panel 10 may be reduced, thereby simplifying the manufacturing process of the display panel 10.

Referring to fig. 1, fig. 2 and fig. 15 together, fig. 15 is a schematic diagram of a display panel according to an embodiment of the application. The display panel 10 has a display region 10a and a non-display region 10b. The display area 10a is an area that can be displayed in the display panel 10. The non-display area 10b is provided at the periphery of the display area 10a, and the non-display area 10b cannot display. The plurality of data lines 110, the plurality of scan line groups 120, the first sub-pixel electrode 130, the first thin film transistor Q1, the first connection section 140, and the second connection section 150 are disposed in the display area 10a.

When the display panel 10 further includes a common electrode line 190 (refer to fig. 3 and 15), the common electrode line 190 is disposed in the display area 10a. In addition, the common electrode line 190 is located between two adjacent data lines 110. The common electrode line 190 is not illustrated in fig. 15.

When the display panel 10 further includes a second sub-pixel electrode 210 and a second thin film transistor Q2, the second sub-pixel electrode 210 and the second thin film transistor Q2 are disposed in the display region 10a.

When the display panel 10 is driven, the driving may be performed in a column inversion manner. For example, the polarities of adjacent two data lines 110 are opposite. For example, the polarity of the mth column data line 110 is a first polarity, and then the polarity of the m+1th column data line 110 is a second polarity; accordingly, the polarity of the m+2th column data line 110 is the first polarity, and the polarity of the m+3rd column data line 110 is the second polarity. In one embodiment, the first polarity is positive and, correspondingly, the second polarity is negative. In another embodiment, the first polarity is negative and, correspondingly, the second polarity is positive.

As can be seen from the foregoing description of the data lines 110 and the scan line groups 120 of the display panel 10, the display panel 10 according to the embodiment of the application is a Dual gate (Dual gate) driving mode. Whereby fewer data lines 110 may be used. Therefore, the number of Chip On Film (COF) units electrically connected to the data lines 110 can be reduced. The flip chip film unit is simply referred to as COF unit 231. Specifically, referring to fig. 15, the display panel 10 further includes a circuit board 240 and a COF module 230. The COF module 230 is electrically connected to the circuit board 240 and the plurality of data lines 110. The COF module 230 includes a plurality of COF units 231 disposed at intervals. The COF unit 231 is electrically connected to the circuit board 240 and to a portion (may be plural) of the plurality of data lines 110, and different COF units 231 are electrically connected to different data lines 110.

In addition, in the related art, the drain electrodes d of the first thin film transistors Q1 located in the same column are all electrically connected to the same data line 110, so that when the column inversion driving is performed, due to the presence of a Feed through (Feed through) voltage, brightness of sub-pixels corresponding to the positive and negative electrodes cannot be completely uniform, and when the human eyes shake at a certain frequency, brightness difference of sub-pixels corresponding to the positive and negative electrodes captured by the human eyes occurs, so that the user can perceive that the display panel 10 has a shaking pattern.

In the embodiment of the present application, two adjacent first thin film transistors Q1 located in the same column are electrically connected to different data lines 110, specifically, one of two adjacent first thin film transistors Q1 located in the same column: the drain d is electrically connected to the mth column data line 110; the other of the two first thin film transistors Q1 adjacent in the same column: the drain d is electrically connected to the m+1th column data line 110. Therefore, compared with the display panel 10 in the prior art, the display panel 10 provided in the embodiment of the application disturbs the polarity arrangement of the sub-pixels located in the same column. Specifically, when the display panel 10 is driven, the driving may be performed in a column inversion manner. For example, the polarities of adjacent two data lines 110 are opposite. For example, the polarity of the Mth column data line 110 is a first polarity, and then the polarity of the M+1th column data line 110 is a second polarity. Therefore, the shaking marks due to the presence of a Feed-through voltage of the coupling capacitance of the first sub-pixel electrode 130 may be reduced or even avoided. Furthermore, the design of the first connection section 140 and the second connection section 150 of the display panel 10 according to the embodiment of the present application makes the resistances of two adjacent first tfts Q1 in the same column equal when connected to the corresponding data line 110, so that the problem of bright and dark lines caused by excessive impedance difference between the adjacent first tfts Q1 in the same column and the corresponding first sub-pixel electrodes 130 can be reduced or even avoided. Therefore, the display panel 10 provided by the embodiment of the application has better display effect.

The application also provides a preparation method of the display panel 10. The method for manufacturing the display panel 10 according to the embodiment of the present application can manufacture the display panel 10 according to the previous embodiment. Accordingly, the display panel 10 described above may be manufactured by the manufacturing method of the display panel 10 according to the embodiment of the present application. Next, a method for manufacturing the display panel 10 according to an embodiment of the present application will be described.

Referring to fig. 16, fig. 16 is a flowchart of a method for manufacturing a display panel according to an embodiment of the application. The manufacturing method of the display panel 10 includes S10a, S20a, S30a, S40a, S50a, S60a, S70a, S80a and S90a. S10a, S20a, S30a, S40a, S50a, S60a, S70a, S80a, and S90a are described in detail below.

S10a, forming a first metal layer.

Specifically, forming the first metal layer includes depositing the first metal layer (M1 Depo), patterning the first metal layer (M1 PHT), etching (WET), and stripping (M1 Strip). The stripping is to strip the photoresist layer covered on the corresponding film layer, for example, in this embodiment, the stripping is to strip the photoresist layer on the first metal layer. In an embodiment, after S10a, a gate electrode, a scan line group, etc. in the display panel may be formed.

And S20a, sequentially forming a gate insulating layer and an active layer.

Specifically, the gate insulating layer may be formed by deposition, for example, by depositing the gate insulating layer. The gate insulation layer may be deposited simply referred to as GI Depo. The active layer may be formed using an active layer deposition and Bake (Depo/Bake), active layer Patterning (PHT), and active layer etching process. The active layer is also referred to as a channel layer.

And S30a, forming a gate insulating layer.

Specifically, the gate insulating layer may be formed by patterning (Photo) the gate insulating layer, drying (GI Dry) the gate insulating layer, and stripping (GI strip) the gate insulating layer.

S40a, forming a source-drain electrode layer.

Specifically, forming the source-drain layer may include source-drain metal layer deposition (SD Depo), source-drain patterning (SD PHT), source-drain etching (SD WET), and stripping (SD Strip).

S50a, pre-forming a first insulating layer and an insulating flat layer.

Specifically, pre-forming the first insulating layer may include first insulating layer deposition (PV 1 Depo) and insulating planarization layer deposition (PFA Depo), insulating planarization layer patterning (PFA PHT), and insulating planarization layer development (i.e., PFA development).

S60a, forming a first insulating layer.

Specifically, forming the first insulating layer includes patterning and drying the first insulating layer. The first insulating layer patterning may be abbreviated as PV1 PHT, and the first insulating layer drying may be abbreviated as (PV 1 Dry).

And S70a, forming a first indium tin oxide layer.

Specifically, forming the first layer of indium tin oxide includes depositing (1-ITO Depo), patterning (1-ITO PHP), etching (1-ITO WET), and stripping (1-ITO Strip). Through S70a, the first indium tin oxide layer may form a common electrode.

S80a, forming a second insulating layer.

Specifically, forming the second insulating layer includes second insulating layer deposition (PV 2 Depo), patterning (PV 2 PHT), etching (PV 2 Dry), and stripping (PV 2 Strip).

And S90a, forming a second indium tin oxide layer.

Specifically, forming the second indium tin oxide layer includes depositing (2-ITO Depo), patterning (2-ITO PHP), etching (2-ITO WET), and stripping (2-ITO Strip). Through S70a, each pixel electrode (e.g., the first sub-pixel electrode 130 and the second sub-pixel electrode 210) is formed.

It can be appreciated that, in one embodiment, the gate g, the scan line group 120 and the second section 152 of the second connection section 150 are the first layer metal (M1) in the display panel; the source s, the drain d, the first segment 151 of the second connection segment 150, and the common body 191 of the common electrode line 190 are the second metal layer (M2) in the display panel; the common connection portion 192 of the common electrode line 190 is a third metal layer (M3) in the display panel 10.

Referring to fig. 17, fig. 17 is a flowchart of another method for manufacturing a display panel according to the present application. The preparation method of the display panel comprises S10b, S20b, S30b, S40b, S50b, S60b, S70b and S80b. S10b, S20b, S30b, S40b, S50b, S60b, S70b and S80b are described in detail below.

S10b, forming a first metal layer.

Specifically, forming the first metal layer includes depositing the first metal layer (M1 Depo), patterning the first metal layer (M1 PHT), etching (WET), and stripping (M1 Strip). The stripping is to strip the photoresist layer covered on the corresponding film layer, for example, in this embodiment, the stripping is to strip the photoresist layer on the first metal layer. In an embodiment, after S10b, a gate electrode, a scan line group, etc. in the display panel may be formed.

And S20b, sequentially forming a gate insulating layer and an active layer.

Specifically, the gate insulating layer may be formed by deposition, for example, by depositing the gate insulating layer. The gate insulation layer may be deposited simply referred to as GI Depo. The active layer may be formed using an active layer deposition and bake (Depo/Bbke), active layer Patterning (PHT), and active layer etching processes.

And S30b, forming a gate insulating layer.

S40b, forming a source drain electrode layer.

S50b, forming a first insulating layer and an insulating flat layer.

Specifically, forming the first insulating layer and the insulating planarization layer may include first insulating layer deposition (PV 1 Depo) and insulating planarization layer deposition (PFA Depo), insulating planarization layer patterning (PFA PHT), insulating planarization layer development (i.e., PFA development), and first insulating layer drying (PV 1 Dry).

And S60b, forming a first indium tin oxide layer.

Specifically, forming the first layer of indium tin oxide includes depositing (1-ITO Depo), patterning (1-ITO PHP), etching (1-ITO WET), and stripping (1-ITO Strip). Through S70b, the first indium tin oxide layer may form a common electrode.

And S70b, forming a second insulating layer.

And S80b, forming a second indium tin oxide layer.

Specifically, forming the second indium tin oxide layer includes depositing (2-ITO Depo), patterning (2-ITO PHP), etching (2-ITO WET), and stripping (2-ITO Strip). Through S70b, the second indium tin oxide layer may form a second segment of the first main connection segment, and each pixel electrode (e.g., the first sub-pixel electrode and the second sub-pixel electrode 210).

Referring to fig. 18, fig. 18 is a schematic diagram of an electronic device according to an embodiment of the application. The electronic device 1 may be, but is not limited to, a device with a display panel 10, such as a mobile phone, a tablet computer, etc. The electronic device 1 comprises a display panel 10. The display panel 10 is used for realizing the display function of the electronic device 1. The display panel 10 is described with reference to any one of the foregoing embodiments, and will not be described herein.

In an embodiment, the electronic device 1 further comprises a housing 30, and the housing 30 is configured to carry the display panel 10. It will be appreciated that in other embodiments, the electronic device 1 may not include the housing 30. The embodiment of the present application does not limit whether the electronic device 1 includes the housing 30.

It should be noted that the foregoing examples and descriptions of the types of the electronic device 1 are merely an introduction of one application scenario of the display panel 10, and should not be construed as limiting the display panel 10 provided in the embodiments of the present application.

While embodiments of the present application have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and alternatives to the above embodiments may be made by those skilled in the art within the scope of the application, which is also to be regarded as being within the scope of the application.

Claims

1. The display panel is characterized by comprising a plurality of pixel areas arranged in an array, and further comprises a bearing substrate and a plurality of pixel areas arranged in the array, wherein the bearing substrate is positioned on the display panel:

A first subpixel electrode;

a first thin film transistor;

A second thin film transistor;

A first connection section; and

A second connection section;

2. The display panel of claim 1, wherein the second connection section comprises:

The first section is connected with the source electrode of the second thin film transistor and is of an integral structure with the source electrode; and

And a second segment electrically connected to the first segment and the second subpixel electrode, the second segment being adjacent to the carrier substrate as compared to the first segment.

3. The display panel of claim 2, wherein the display panel further comprises:

And the scanning line group is adjacent to the bearing substrate compared with the source electrode of the second thin film transistor, wherein the second section and the scanning line group are arranged on the same layer.

4. The display panel of claim 2, wherein the second segment comprises a first pad, a connecting portion and a second pad that are sequentially bent and connected;

The first pad part is used for being electrically connected with the first section, and the width of the first pad part is larger than the line width of the connecting part;

The second pad is used for being electrically connected with the second sub-pixel electrode, and the width of the second pad is larger than the line width of the connecting part.

5. The display panel of claim 2, wherein the common body portion is co-layer with the first segment.

6. The display panel of claim 2, wherein the display panel further comprises:

The grid insulation layer is arranged on the surface of the bearing substrate, and the public body part is arranged on the grid insulation layer;

the first insulating layer is arranged on one side of the public body part, which is away from the bearing substrate, and is provided with two first through holes which are arranged at intervals, wherein the first through holes are used for exposing the public body part;

The insulation flat layer is arranged on the surface of the first insulation layer, which is away from the bearing substrate, and is provided with two second through holes which are arranged at intervals, and each second through hole is communicated with one first through hole;

The common connecting part is arranged on the surface of the insulating flat layer, which is away from the bearing substrate, and is electrically connected with the two adjacent common body parts through the first through hole and the second through hole.

7. The display panel of claim 6, wherein the gate insulating layer comprises a silicon nitride monolayer, or a silicon oxide monolayer, or a stack of silicon nitride and silicon oxide, wherein a thickness D _g of the gate insulating layer satisfies: d _g -8000 angstroms;

The first insulating layer comprises a silicon nitride single layer, a silicon oxide single layer or a lamination of silicon nitride and silicon oxide, wherein the thickness D _pv1 of the first insulating layer meets the following conditions: d _PV1 -8000 angstroms;

the insulating flat layer is an organic insulating layer, and the thickness D _PFA of the insulating flat layer meets the following conditions: d _PFA of 5000 angstroms or less less than or equal to 30000 angstroms.

8. The display panel of claim 7, further comprising a second insulating layer disposed on a surface of the common connection portion facing away from the carrier substrate.

9. The display panel of claim 1, wherein one common connection portion is disposed to cross the second connection sections of the adjacent two pixel regions, and parasitic capacitances are respectively formed.

10. An electronic device comprising the display panel according to any one of claims 1-9.