CN118399899A - Millimeter wave frequency band double-circuit synthesized bidirectional amplifier, chip and electronic equipment - Google Patents
Millimeter wave frequency band double-circuit synthesized bidirectional amplifier, chip and electronic equipment Download PDFInfo
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Abstract
The invention discloses a millimeter wave frequency band double-path synthesis bidirectional amplifier, a chip and electronic equipment, and belongs to the field of communication or radars. The two-way synthesis bidirectional amplifier comprises two bidirectional amplifying paths Path1 and Path2 which are connected in parallel and at least two stages, and the two bidirectional amplifying paths adopt the noise elimination technology of the low-noise amplifier and the parallel power synthesis technology of the power amplifier at the same time, so that the noise performance of the low-noise amplifier and the saturated output power performance of the power amplifier are improved; the 1 st-stage common gate amplifier of the Path1 low noise amplifier adopts a cross-over lifting technology to improve gain performance, and meanwhile, other stages of amplifiers of the low noise amplifier and each stage of amplifier of the power amplifier adopt a common source differential amplifier with a neutralization capacitor to offset a gate leakage parasitic capacitor C gd, so that performance is improved. The invention can realize the low noise coefficient of the low noise amplifier and the high saturated output power of the power amplifier at the same time, and reduce the chip area.
Description
Technical Field
The invention relates to the field of communication or radar, in particular to a millimeter wave frequency band double-path synthesis bidirectional amplifier, a chip and electronic equipment.
Background
The rapid growth of wireless communications has changed the way people produce and live, but traditional low-band spectrum resources have failed to meet the needs of people for higher data rates and higher standard transmission quality, and integrated circuits face new challenges due to the explosive growth trend of various communication applications in both variety and number, causing channels to become very crowded. One approach to this problem is to find new channels at higher frequencies, and scientists turn the focus to the millimeter wave or even terahertz band, which is a rich and undeveloped spectrum resource, with bands ranging from 30-300GHz and 100 GHz-10 THz, respectively, and wavelengths between the microwave and far infrared.
The transmitter and the receiver of the traditional transceiver are independently designed, are not mutually influenced, have high isolation, but occupy a large amount of chip area, and are unfavorable for the miniaturization of devices and the requirement of low cost. Therefore, researchers propose to simplify the architecture of the transceiver system, i.e., the bidirectional transceiver structure, so that the system is miniaturized, low-power-consumption and low-cost without greatly reducing the performance. The bidirectional amplifier is a key part of the bidirectional transceiver, plays a decisive role in the performance of the transceiver, can be switched into working states of a Power Amplifier (PA) and a low noise amplifier (Low noise amplifier, LNA) in transmitting and receiving modes, has the advantages of simple structure, small area, low cost and the like, and has good application prospects in the aspects of millimeter wave vehicle radar, a multiple-input multiple-output system, a phased array system and the like. The current mainstream technology is that the direction switching of the bidirectional amplifier is realized by switching the bias condition of the transistor, and the bidirectional amplifier can be divided into input-output matching multiplexing and full-level multiplexing according to the multiplexing degree, and the higher the multiplexing degree is, the higher the design difficulty is, and the smaller the area is; and as the frequency increases, the loss becomes larger, the performance of the bidirectional amplifier becomes worse, and designing a bidirectional amplifier with high performance and high multiplexing degree at high frequency becomes a design difficulty.
Disclosure of Invention
In order to solve at least one of the technical problems existing in the prior art to a certain extent, the invention aims to provide a millimeter wave frequency band two-way synthesis bidirectional amplifier, a chip and electronic equipment.
The first technical scheme adopted by the invention is as follows:
A millimeter wave band two-way composite bi-directional amplifier comprising two bi-directional amplification paths comprising at least two stages, the bi-directional amplification paths comprising:
The low-noise amplifier is used for amplifying signals received by the antenna and comprises a first input matching network, a first inter-stage matching network and a first output matching network;
the power amplifier is used for amplifying signals to be transmitted through the antenna and comprises a second input matching network, a second interstage matching network and a second output matching network;
the first input matching network and the second output matching network are coupled and multiplexed, and the first output matching network and the second input matching network are coupled and multiplexed.
Further, the low noise amplifier and the power amplifier both adopt differential circuit structures;
the two bidirectional amplifying paths are called a first amplifying Path Path1 and a second amplifying Path Path2;
the first amplifying path comprises a common gate path of the low noise amplifier and a1 st path of the power amplifier;
the second amplifying path comprises a common source path of the low noise amplifier and a 2 nd path of the power amplifier;
The first amplifying path comprises a first input end and a first output end, and the second amplifying path comprises a second input end and a second output end;
the first input end and the second input end are connected in parallel to form an input end of the two-way synthetic bidirectional amplifier;
The first output end and the second output end are connected in parallel to form an output end of the two-way synthetic bidirectional amplifier.
Further, the common-gate path of the low-noise amplifier comprises a common-gate differential amplifier M L1 adopting a transconductance boosting technology and N-1 common-source differential amplifiers M L2、...、MLN adopting a capacitance neutralization technology, and the 1 st path of the power amplifier comprises N common-source differential amplifiers M P1、...、MPN adopting the capacitance neutralization technology;
The common source path of the low noise amplifier comprises N common source differential amplifiers M L1_、...、MLN_ adopting a capacitance neutralization technology, and the 2 nd path of the power amplifier comprises N common source differential amplifiers M P1_、...、MPN_ adopting the capacitance neutralization technology;
Where N represents the number of stages of the amplifier.
Further, the matching network between the two-way composite bidirectional amplifiers comprises an asymmetric parallel input transformer, at least one symmetric interstage matching transformer and a symmetric parallel output transformer;
The asymmetric parallel input transformer comprises an input/output matching network T 1io1 of a first amplification Path Path1 and an input/output matching network T 2io1 of a second amplification Path Path 2; the symmetrical interstage matching transformer comprises N-1 interstage matching networks T 1mid1、...、T1midN-1 for a first amplification Path Path1 and N-1 interstage matching networks T 2mid1、...、T2midN-1 for a second amplification Path Path 2; the symmetrical parallel output transformer comprises an input/output matching network T 1io2 of a first amplification Path Path1 and an input/output matching network T 2io2 of a second amplification Path Path 2;
Where N represents the number of stages of the amplifier.
Further, the low noise amplifier and the interstage matching network of the power amplifier are independently designed and share the same chip area by adopting a coplanar decoupling transformer.
Further, the low noise amplifier and the power amplifier are both three-stage amplifiers;
The input/output matching networks T 1io1、T1io2、T2io1 and T 2io2 are three-coil transformers comprising three inductors, and any two of the three inductors are magnetically coupled;
The first end inductor L a1 of the input/output matching network T 1io1 is connected with an antenna, one inductor L a2 of the second end is connected with the source stage of the transistor M L1 of the low-noise amplifier and the drain electrode of the transistor M P1 of the power amplifier, and the other inductor L a3 is connected with the grid electrode of the transistor M L1 in a cross mode and used for transconductance improvement of a common gate amplifier;
The first end inductor L a1_ of the input/output matching network T 2io1 is connected with an antenna, one inductor L a2_ of the second end is connected with the drain electrode of the transistor M P1_ of the power amplifier, and the other inductor L a3_ is connected with the grid electrode of the transistor M L1_ of the low-noise amplifier;
The first inductor L b1/Lb1_ of the input/output matching network T 1io2/T2io2 is connected to the mixer, one inductor L b2/Lb2_ of the second end is connected to the drain of the transistor M L3/ML3_ of the low noise amplifier, and the other inductor L b3/Lb3_ is connected to the gate of the transistor M P3/MP3_ of the power amplifier.
Further, the millimeter wave frequency band two-way synthesis bidirectional amplifier comprises four inter-stage matching networks T 1mid1、T1mid2、T2mid1 and T 2mid2, and the inter-stage matching networks adopt a transformer area coplanar decoupling structure;
The interstage matching networks T 1mid1、T1mid2、T2mid1 and T 2mid2 are four-coil transformers, and the four-coil transformers are realized as a superposition of a common single-coil transformer and an 8-shaped transformer in the layout; two inductive magnetic couplings forming the common single-turn transformer and two inductive magnetic couplings forming the 8-shaped transformer so that the magnetic coupling coefficient between the single-turn transformer and the 8-shaped transformer is close to zero;
The 8-shaped inductor L c1/Lc1_ at the first end of the inter-stage matching network T 1mid1/T2mid1 is connected with the grid electrode of the transistor M P1/MP1_, the single-turn inductor L c2/Lc2_ is connected with the drain electrode of the transistor M L1/ML1_, the 8-shaped inductor L c3/Lc3_ at the second end is connected with the drain electrode of the transistor M P2/MP2_, and the single-turn inductor L c4/Lc4_ is connected with the grid electrode of the transistor M L2/ML2_ for matching between the 1 st stage and the 2 nd stage of the two-way bidirectional amplifier;
The 8-shaped inductor L d1/Ld1_ at the first end of the inter-stage matching network T 1mid2/T2mid2 is connected with the grid electrode of the transistor M P2/MP2_, the single-loop inductor L d2/Ld2_ is connected with the drain electrode of the transistor M L2/ML2_, the 8-shaped inductor L d3/Ld3_ at the second end is connected with the drain electrode of the transistor M P3/MP3_, and the single-loop inductor L d4/Ld4_ is connected with the grid electrode of the transistor M L3/ML3_ for matching between the 2 nd stage and the 3 rd stage of the two-way bidirectional amplifier.
Further, the millimeter wave frequency band two-way synthesis bidirectional amplifier is controlled by the following means:
The center tap of the inductor L a2 is connected with a control voltage V ctrl; the center tap of the inductor L a3、Lc4、Ld4、La3_、Lc4_、Ld4_ is connected with the bias voltage V gLNA, and the center tap of the inductor L c1、Ld1、Lb3、Lc1_、Ld1_、Lb3_ is connected with the bias voltage V gPA; the control voltage V ctrl needs a large-sized switch to control, and the on/off of the switch and the magnitudes of the bias voltages V gLNA and V gPA are controlled through a serial peripheral interface to control the bidirectional amplifier to operate in a low noise amplifier mode or a power amplifier mode.
Further, the grid electrode of the low noise amplifier/power amplifier is connected with the drain electrode of the power amplifier/low noise amplifier, and when the power amplifier/low noise amplifier works, the transistor in the off state of the low noise amplifier/power amplifier is used as a neutralization capacitor, and the interstage matching network is multiplexed.
Further, the low noise amplifier and the power amplifier are both three-stage amplifiers;
The input/output matching network T 1io1 is a three-coil transformer, and any two of the three inductors are magnetically coupled; the input/output matching networks T 1io2、T2io1 and T 2io2 are two-coil transformers;
The first end inductor L a1 of the transformer T 1io1 is connected with an antenna, one inductor L a2 of the second end is connected with the source electrode of the transistor M L1 of the low-noise amplifier, and the other inductor L a3 is connected with the grid electrode of the transistor M L1 and the drain electrode of the transistor M P1 of the power amplifier;
The first end inductor L a1_ of the transformer T 2io1 is connected with an antenna, and the second end inductor L a2_ is connected with the grid electrode of the transistor M L1_ of the low-noise amplifier and the drain electrode of the transistor M P1_ of the power amplifier;
the second end inductor L b1/Lb1_ of the transformer T 1io2/T2io2 is connected to the mixer, and the first end inductor L b2/Lb2_ is connected to the drain of the transistor M L3/ML3_ of the low noise amplifier and the gate of the transistor M P3/MP3_ of the power amplifier.
Further, the inter-stage matching networks of the power amplifier and the low noise amplifier are shared, and the inter-stage matching networks T 1mid1、T1mid2、T2mid1 and T 2mid2 are two-coil transformers;
The first end inductor L c1/Lc1_ of the transformer T 1mid1/T2mid1 is connected with the drain electrode of the transistor M L1/ML1_ and the grid electrode of the transistor M P1/MP1_, and the second end inductor L c2/Lc2_ is connected with the grid electrode of the transistor M L2/ML2_ and the drain electrode of the transistor M P2/MP2_ for matching between the 1 st stage and the 2 nd stage of the bidirectional amplifier;
the first end inductor L d1/Ld1_ of the transformer T 1mid2/T2mid2 is connected to the drain of the transistor M L2/ML2_ and the gate of the transistor M P2/MP2_, and the second end inductor L d2/Ld2_ is connected to the gate of the transistor M L3/ML3_ and the drain of the transistor M P3/MP3_, for matching between the 2 nd and 3 rd stages of the bidirectional amplifier.
Further, when the transistors of the low noise amplifier and the power amplifier are both NMOS transistors, the center tap of the inductor L a2 is connected to the control voltage V ctrl, the gate of the tail current source transistor of the low noise amplifier is connected to the bias voltage V gLNA, and the gate of the tail current source transistor of the power amplifier is connected to the bias voltage V gPA; the control voltage V ctrl needs a large-sized switch to control, and the on/off of the switch and the magnitudes of the bias voltages V gLNA and V gPA are controlled through a serial peripheral interface to control the bidirectional amplifier to operate in a low noise amplifier mode or a power amplifier mode.
Further, when the transistor of the low noise amplifier and the transistor of the power amplifier are cross-connected with each other as an NMOS transistor and a PMOS transistor, a tail current source is not required; the source electrode of the NMOS transistor is grounded, the source electrode of the PMOS transistor is grounded, the center tap of the matching network inductor L a2 is grounded, the center tap of the matching network inductor L a3、Lc2、Ld2、La2_、Lc2_、Ld2_ is connected with the control voltage V ctrl1, and the center tap of the inductor L c1、Ld1、Lb2、Lc1_、Ld1_、Lb2_ is connected with the control voltage V ctrl2; the control voltages V ctrl1 and V ctrl2 require a large-sized switch to control, and the switch is turned on and off by a serial peripheral interface to control the bi-directional amplifier to operate in a low noise amplifier mode or a power amplifier mode.
The second technical scheme adopted by the invention is as follows:
A chip comprises the millimeter wave frequency band two-way synthesis bidirectional amplifier.
The third technical scheme adopted by the invention is as follows:
An electronic device comprising a millimeter wave band two-way composite bi-directional amplifier as described above, or a chip as described above.
The beneficial effects of the invention include:
(1) The present invention provides a double-path bidirectional amplifier, mainly comprising a single-path LNA and a single-path PA, wherein the LNA adopts a noise cancellation technology, the PA adopts a double-path power synthesis technology, each path of LNA and PA form a single bidirectional amplifier, the LNA and the PA form the double-path bidirectional amplifier together, the noise coefficient of the LNA is reduced, the saturated output power of the PA is increased, and the system sensitivity and transmission range are increased.
(2) The invention applies three-inductance coupling technology, transformer area sharing decoupling technology or inductance multiplexing technology, and can reduce the chip area to about half of the unidirectional amplifier.
(3) The prior bidirectional amplifier is mainly concentrated in a low frequency band, and mostly has about 28GHz, so that researches on the bidirectional amplifier in a high frequency band are carried out.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made with reference to the accompanying drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and other drawings may be obtained according to these drawings without the need of inventive labor for those skilled in the art.
Fig. 1 is a schematic block diagram of a millimeter wave band two-way synthesis bi-directional amplifier according to embodiment 1 of the present invention;
Fig. 2 is a circuit diagram of a millimeter wave band two-way composite bidirectional amplifier of embodiment 1 of the present invention;
FIG. 3 is a circuit diagram of the control V ctrl switch in example 1 of the present invention;
fig. 4 is a schematic diagram of a coplanar decoupling structure of a transformer in embodiment 1 of the present invention;
fig. 5 is a diagram showing simulation results of coupling coefficients between inductance coils of a coplanar decoupling structure of a transformer in embodiment 1 of the present invention;
FIG. 6 is a diagram showing simulation results of the S-parameter of LNA mode in embodiment 1 of the invention;
FIG. 7 is a graph showing simulation results of S 21 Gain and Phase of the CG and CS paths in LNA mode in example 1 of the invention;
FIG. 8 is a diagram showing simulation results of LNA mode noise figure NF in embodiment 1 of the present invention;
FIG. 9 is a graph showing simulation results of the S-parameter of the PA mode in example 1 of the present invention;
fig. 10 is the output power, gain and power added efficiency performance of PA mode of embodiment 1 of the present invention: pout, gain, and PAE;
Fig. 11 is a circuit diagram of a millimeter wave band two-way composite bidirectional amplifier of embodiment 2 of the present invention;
fig. 12 is a circuit diagram of a millimeter wave band two-way composite bidirectional amplifier of embodiment 3 of the present invention;
Fig. 13 is a circuit diagram of a millimeter wave band two-way composite bi-directional amplifier of embodiment 4 of the present invention;
fig. 14 is a circuit diagram of a millimeter wave band two-way composite bidirectional amplifier of embodiment 5 of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a plurality means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated. Furthermore, "and/or" describes an association relationship of the association object, and the representation may have three relationships, for example, a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
Example 1
As shown in fig. 1, this embodiment provides a millimeter wave frequency band dual-Path synthesized bidirectional amplifier based on an inter-stage matching network transformer coplanar decoupling technology, which includes a first amplifying Path1 and a second amplifying Path2:
The first amplifying Path1 comprises an input/output matching network T 1io1 connected to the first input end and an input/output matching network T 1io2 connected to the first output end, a1 st, 2 nd stage LNAPA differential amplifier and inter-stage decoupling matching networks T 1mid1 and T 1mid2;
The second amplification Path2 includes an input-output matching network T 2io1 connected to the second input terminal and an input-output matching network T 2io2 connected to the second output terminal, 1 st, 2 nd stage LNAPA differential amplifier and inter-stage decoupling matching networks T 2mid1 and T 2mid2.
In the embodiment, two bidirectional amplifying paths of the two-way synthesized bidirectional amplifier simultaneously adopt a noise elimination technology of the low-noise amplifier and a parallel power synthesis technology of the power amplifier, so that the noise performance of the low-noise amplifier and the saturated output power performance of the power amplifier are improved; the 1 st-stage common gate amplifier of the Path1 low noise amplifier adopts a cross-over lifting technology to improve gain performance, and meanwhile, other stages of amplifiers of the low noise amplifier and each stage of amplifier of the power amplifier adopt a common source differential amplifier with a neutralization capacitor to offset a gate leakage parasitic capacitor C gd, so that performance is improved; in addition, the chip area can be reduced to about half of the unidirectional amplifier by using a three-inductance coupling technology, a transformer area sharing decoupling technology or an inductance multiplexing technology. The invention can realize the low noise coefficient of the low noise amplifier and the high saturated output power of the power amplifier at the same time, and reduce the chip area.
It should be noted that, in the present embodiment, the bidirectional amplifying path is in a 3-stage structure, but is not limited to a 3-stage structure, and other stages (such as 2-stage, 4-stage or more stages) are also applicable to the technical solution of the present application, so that the bidirectional amplifying paths of other stages are also within the protection scope of the present application.
The circuit structure and the working mode of the millimeter wave frequency band two-way synthesis bidirectional amplifier are explained in detail below with reference to the accompanying drawings. Description of the reference numerals: because the circuit structure of the amplifier mainly adopts a differential symmetrical structure, that is, the circuit structure comprises two side circuits with the same circuit structure, the circuit structure comprises symmetrical identical components (the connection relation of the components is also the same), the last letter in the subscript is adopted to distinguish the components, such as an LNA transistor M L1a and an LNA transistor M L1a, the two transistors are symmetrical transistors and are respectively positioned at two sides of the circuit, and the last letter in the subscript can be omitted for the sake of simplicity of representation, for example, the transistor M L1a and/or the transistor M L1b can be represented as M L1.
(1) Description of the Circuit Structure
As shown in fig. 2, fig. 2 is a circuit diagram of a millimeter wave band two-way synthesis bidirectional amplifier, and the specific circuit structure includes:
The first part is a first amplification Path1, including input/output matching networks T 1io1 and T 1io2, interstage decoupling matching networks T 1mid1 and T 1mid2, and 1 st, 2 nd, and 3 rd stage LNAPA differential amplifiers, each of which is described below.
The input-output matching network T 1io1 includes an inductance L a1、La2、La3 that serves as an input of the LNA and an output match of the PA for the first amplification Path 1. In T 1io1, one end of the inductor L a1 is used to connect to one end of the differential antenna, and the other end is grounded; Two ends of the inductor L a2 are connected with the drain end of the Path 1-level PA common-source differential amplifier M P1 and the source end of the LNA common-gate differential amplifier M L1, and the center tap is connected with the control voltage V ctrl; The two ends of the inductor L a3 are used to connect to the gate terminal of the Path1 stage 1 LNA common-gate differential amplifier M L1, where a cross connection is required, and the center tap is connected to the bias voltage V gLNA. The inductor L a1 is coupled with the inductor L a3, and the coupling coefficient is k a1; The inductor L a1 is coupled with the inductor L a2, and the coupling coefficient is k a2; inductance L a2 is coupled to inductance L a3 with a coupling coefficient of k a3. the control voltage V ctrl needs to be switched between VDD and ground and a large current is needed, and thus a switch is needed for switching, and a switching circuit diagram is shown in fig. 3, which includes a PMOS transistor M1 and NMOS transistors M2, M1 and M2 with their gate terminals connected together to a resistor R1, the source terminal VDD of the control voltage V SW connected through R1, The source terminal of M2 is grounded, the drain terminals of M1 and M2 are connected together to be connected with a decoupling capacitor C1, and the control voltage V ctrl is output.
The input-output matching network T 1io2 includes an inductance L b1、Lb2、Lb3 that serves as an output of the Path1LNA to match the input of the PA. In T 1io2, one end of the inductor L b1 is used to connect to one end of the differential mixer, and the other end is grounded; two ends of the inductor L b2 are used for being connected with a drain end of the Path 13 rd-stage LNA common-source differential amplifier M L3, and a center tap is connected with VDD; the two ends of the inductor L b3 are used for being connected with the gate end of the Path 13 rd-stage PA common-source differential amplifier M P3, and the center tap is connected with the bias voltage V gPA. The inductor L b1 is coupled with the inductor L b3, and the coupling coefficient is k b1; the inductor L b1 is coupled with the inductor L b2, and the coupling coefficient is k b2; inductance L b2 is coupled to inductance L b3 with a coupling coefficient of k b3.
The interstage matching transformer T 1mid1 includes an inductance L c1、Lc2、Lc3、Lc4 for interstage matching of the 1 st and 2 nd stages of the LNA and/or PA. Two ends of the inductor L c1 are used for being connected with a gate end of the Path1 level 1 PA common source differential amplifier M P1, and a center tap is connected with bias voltage V gPA; Two ends of the inductor L c2 are used for being connected with a drain end of the Path1 level 1 LNA common-gate differential amplifier M L1, and a center tap is connected with VDD; two ends of the inductor L c3 are connected with the drain end of the Path1 level 2 PA common source differential amplifier M P2, and a center tap is connected with VDD; The two ends of the inductor L c4 are used for being connected with the gate end of the Path1 level 2 LNA common source differential M L2 amplifier, and the center tap is connected with the bias voltage V gLNA. The inductor L c1 and the inductor L c3 are mutually coupled, the coupling coefficient is k c1, and the inductor is realized as an 8-shaped transformer in a layout and is used for the interstage matching of the PA; The inductor L c2 and the inductor L c4 are mutually coupled, the coupling coefficient is k c2, and the common single-turn transformer is realized in the layout and is used for the interstage matching of the LNA; The 8-shaped transformer can self-offset the magnetic coupling with other transformers, and the coupling coefficients between the inductance L c1 and the inductance L c3 and the inductance L c2 and the inductance L c4 are close to zero.
The interstage matching transformer T 1mid2 includes an inductance L d1、Ld2、Ld3、Ld4 for interstage matching of the 2 nd and 3 rd stages of the LNA and/or PA. Two ends of the inductor L d1 are used for being connected with a gate end of the Path1 level 2 PA common source differential amplifier M P2, and a center tap is connected with bias voltage V gPA; Two ends of the inductor L d2 are used for being connected with a drain end of the Path1 level 2 LNA common-gate differential amplifier M L2, and a center tap is connected with VDD; two ends of the inductor L d3 are connected with the drain end of the Path 13 rd-stage PA common-source differential amplifier M P3, and a center tap is connected with VDD; The two ends of the inductor L c4 are used for being connected with the gate end of the Path 13 rd-stage LNA common-source differential M L3 amplifier, and the center tap is connected with the bias voltage V gLNA. The inductor L d1 and the inductor L d3 are mutually coupled, the coupling coefficient is k d1, and the inductor is realized as an 8-shaped transformer in a layout and is used for the interstage matching of the PA; The inductor L d2 and the inductor L d4 are mutually coupled, the coupling coefficient is k d2, and the common single-turn transformer is realized in the layout and is used for the interstage matching of the LNA; the 8-shaped transformer can self-offset the magnetic coupling with other transformers, and the coupling coefficients between the inductance L d1 and the inductance L d3 and the inductance L d2 and the inductance L d4 are close to zero.
The layout implementation form of the interstage matching transformer T 1mid1 is illustrated by way of example, as shown in FIG. 4, the interface order is ①②③④⑤⑥⑦⑧ in turn, The corresponding connection mode is as follows: ①② Inductance L c1;③④ inductance L c2;⑤⑥ inductance L c3;⑦⑧ inductance L c4. the inductance L c1 and the inductance L c3 are 8-shaped inductances, the coupling coefficient is k c1, and an 8-shaped transformer is formed, the inductance L c2, The inductance L c3 is a single-turn square inductance, the coupling coefficient is k c2, the common single-turn transformer is formed, and the input and output of the 8-shaped transformer and the common single-turn transformer face the same direction. the 8-shaped transformer and the common single-turn transformer are subjected to coplanar stacking design in the same position space, and occupy the same area, namely, the coplanar design. Because the 8-shaped transformer can self-offset the magnetic coupling with other transformers, the coupling coefficients between the inductance L c1 and the inductance L c3 and the inductance L c2 and the inductance L c4 are close to zero, and a coplanar decoupling structure of the transformer is integrally formed.
The stage 1 LNAPA differential amplifier includes a differential cascode structure (acting as an LNA) with transconductance boosting and a differential cascode structure (acting as a PA) with neutralization capacitance, LNA transistor M L1 for amplifying the LNA signal and PA transistor M P1 for amplifying the PA signal. The source end of the LNA transistor M L1 is connected with the inductor L a2 of the input/output matching network T 1io1, the gate end is in cross connection with the transconductance enhancement inductor L a3 so as to improve gain, and the drain end is connected with the inductor L c2 of the interstage matching transformer T 1mid1; the drain terminal of the PA transistor M P1 is connected to the inductor L a2 of the input/output matching network T 1io1, the gate terminal is connected to the inductor L c1 of the inter-stage matching transformer T 1mid1, the source terminal is grounded, and a gate-drain neutralization capacitor C N1 exists between the gate and the drain of the differential transistor to reduce parasitism.
The 2 nd stage LNAPA differential amplifiers all adopt differential common source structures with neutralization capacitors, the grid electrode of the LNA transistor M L2 is connected with the inductance L c4 of the interstage matching transformer T 1mid1, the drain end is connected with the inductance L d2 of the interstage matching transformer T 1mid2, the source electrode is grounded, and a grid-drain neutralization capacitor C N2 exists between the grid and the drain of the differential transistor so as to reduce parasitism; the drain terminal of the PA transistor M P2 is connected to the inductance L c3 of the inter-stage matching transformer T 1mid1, the gate terminal is connected to the inductance L d1 of the inter-stage matching transformer T 1mid2, the source terminal is grounded, and a gate-drain neutralization capacitance C N3 exists between the gate and the drain of the differential transistor to reduce parasitics.
The 3 rd stage LNAPA differential amplifier adopts a differential common source structure with a neutralization capacitor, the gate end of the LNA transistor M L3 is connected with the inductor L d4 of the interstage matching transformer T 1mid2, the drain end is connected with the inductor L b2 of the input/output matching network T 1io2, the source electrode is grounded, and a gate-drain neutralization capacitor C N4 exists between the gate and the drain of the differential transistor so as to reduce parasitism; the drain end of the PA transistor M P3 is connected to the inductor L d3 of the interstage matching transformer T 1mid2, the gate end is connected to the inductor L b3 of the input/output matching network T 1io2, the source is grounded, and a gate-drain neutralization capacitor C N5 exists between the gate and the drain of the differential transistor to reduce parasitism.
In LNA mode, the input signal of LNA enters the inductance L a1 of the input-output matching network T 1io1 from the antenna end, after being coupled by the multi-coil transformer, the signal flows into the 1 st stage LNAPA differential amplifier through L a2, Into the source of transistor M L1 and out of the drain of M L1, where the gate of M L1 is connected to L a3 of T 1io1 for transconductance enhancement, The center tap of L a3 is connected with V gLNA and used for controlling the on and off of M L1; The signal is output from the drain terminal of M L1, flows into the inductor L c2 of the interstage matching transformer T 1mid1, and after being coupled with the inductor L c4 through the inductor L c2, Flows into the 2 nd stage LNAPA differential amplifier, enters the gate terminal of the transistor M L2 and is output from the drain terminal of M L2, Wherein the gate end of M L2 is connected to the L c4,Lc4 center tap V gLNA of T 1mid1 for controlling the on and off of M L2; The signal is output from the drain terminal of M L2, flows into the inductor L d2 of the interstage matching transformer T 1mid2, and after being coupled with the inductor L d4 through the inductor L d2, Flows into the 3 rd stage LNAPA differential amplifier, enters the gate terminal of transistor M L3 and is output from the drain terminal of M L3, Wherein the gate end of M L3 is connected to the L d4,Ld4 center tap V gLNA of T 1mid2 for controlling the on and off of M L3; The signal flows into the inductance L b2 of the input-output matching network T 1io2 after being output from the drain end of the M L3, and finally flows out through the L b1 after being coupled by the multi-coil transformer.
In the PA mode, the input signal of the PA enters the inductance L b1 of the input-output matching network T 1io2 from the mixer end, after being coupled by the multi-coil transformer, the signal flows into the 3 rd stage LNAPA differential amplifier through L b3, Into the gate terminal of transistor M P3 and out of the drain terminal of M P3, Wherein the gate end of M P3 is connected to the L b3,Lb3 center tap V gPA of T 1io2 for controlling the on and off of M P3; The signal is output from the drain terminal of M P3, flows into the inductor L d3 of the interstage matching transformer T 1mid2, and after being coupled with the inductor L d1 through the inductor L d3, Flows into the 2 nd stage LNAPA differential amplifier, enters the gate terminal of the transistor M P2 and is output from the drain terminal of M P2, wherein the gate end of M P2 is connected to the L d1,Ld1 center tap V gPA of T 1mid2 for controlling the on and off of M P2; The signal is output from the drain terminal of M P2, flows into the inductor L c3 of the interstage matching transformer T 1mid1, and after being coupled with the inductor L c1 through the inductor L c3, Flows into the 1 st stage LNAPA differential amplifier, enters the gate terminal of the transistor M P1 and is output from the drain terminal of M P1, Wherein the gate end of M P1 is connected to the L c1,Lc1 center tap V gPA of T 1mid1 for controlling the on and off of M P1; the signal flows into the inductance L a2 of the input-output matching network T 1io1 after being output from the drain end of the M P3, and finally flows out through the L a1 after being coupled by the multi-coil transformer.
The second part is Path2, which includes input/output matching networks T 2io1 and T 2io2, interstage decoupling matching networks T 2mid1 and T 2mid2, and 1 st, 2 nd, and 3 rd stage LNAPA differential amplifiers, each of which is described below.
The input-output matching network T 2io1 includes an inductance L a1_、La2_、La3_ that serves as an input for the Path2LNA and an output match for the PA. In T 2io1, one end of the inductor L a1_ is used to connect to one end of the differential antenna, and the other end is grounded; two ends of the inductor L a2_ are connected with the drain end of the Path2 level 1 PA common source differential amplifier M P1_, and a center tap is connected with VDD; two ends of the inductor L a3_ are used for being connected with a gate end of the Path 21 st-stage LNA common-source differential amplifier M L1_, and a center tap is connected with the bias voltage V gLNA. The inductor L a1_ is coupled with the inductor L a3_, and the coupling coefficient is k a1_; the inductor L a1_ is coupled with the inductor L a2_, and the coupling coefficient is k a2_; inductance L a2_ is coupled to inductance L a3_ with a coupling coefficient of k a3_.
The input-output matching network T 2io2 includes an inductance L b1_、Lb2_、Lb3_ that serves as an output of the Path2LNA to match the input of the PA. In T 2io2, one end of the inductor L b1_ is used to connect to one end of the differential mixer, and the other end is grounded; two ends of the inductor L b2_ are used for being connected with a drain end of the Path 23 rd-stage LNA common-source differential amplifier M L3_, and a center tap is connected with VDD; the two ends of the inductor L b3_ are used for being connected with the gate end of the Path 23 rd-stage PA common-source differential amplifier M P3_, and the center tap is connected with the bias voltage V gPA. The inductor L b1_ is coupled with the inductor L b3_, and the coupling coefficient is k b1_; the inductor L b1_ is coupled with the inductor L b2_, and the coupling coefficient is k b2_; inductance L b2_ is coupled to inductance L b3_ with a coupling coefficient of k b3_.
The interstage matching transformer T 2mid1 includes an inductance L c1_、Lc2_、Lc3_、Lc4_ for interstage matching of the 1 st and 2 nd stages of the LNA and/or PA. Two ends of the inductor L c1_ are used for being connected with a gate end of the Path 21 st-stage PA common-source differential amplifier M P1_, and a center tap is connected with bias voltage V gPA; Two ends of the inductor L c2_ are used for being connected with a drain end of the Path 21 st-stage LNA common-gate differential amplifier M L1_, and a center tap is connected with VDD; two ends of the inductor L c3_ are connected with the drain end of the Path2 level 2 PA common source differential amplifier M P2_, and a center tap is connected with VDD; The two ends of the inductor L c4_ are used for being connected with the gate end of the Path2 level 2 LNA common source differential M L2_ amplifier, and the center tap is connected with the bias voltage V gLNA. The inductor L c1_ and the inductor L c3_ are mutually coupled, the coupling coefficient is k c1_, and the inductor is realized as an 8-shaped transformer in a layout and is used for the interstage matching of the PA; The inductor L c2_ and the inductor L c4_ are mutually coupled, the coupling coefficient is k c2, and the common single-turn transformer is realized in the layout and is used for the interstage matching of the LNA; The 8-shaped transformer can self-offset the magnetic coupling with other transformers, and the coupling coefficients between the inductance L c1_ and the inductance L c_3 and the inductance L c2_ and the inductance L c4_ are close to zero.
The interstage matching transformer T 2mid2 includes an inductance L d1_、Ld2_、Ld3_、Ld4_ for interstage matching of the 2 nd and 3 rd stages of the LNA and/or PA. Two ends of the inductor L d1_ are used for being connected with a gate end of the Path 2-level PA common-source differential amplifier M P2_, and a center tap is connected with bias voltage V gPA; Two ends of the inductor L d2_ are used for being connected with a drain end of the Path2 level 2 LNA common-gate differential amplifier M L2_, and a center tap is connected with VDD; two ends of the inductor L d3_ are connected with the drain end of the Path 23 rd-stage PA common-source differential amplifier M P3_, and a center tap is connected with VDD; The two ends of the inductor L c4_ are used for being connected with the gate end of the Path 23 rd-stage LNA common-source differential M L3_ amplifier, and the center tap is connected with the bias voltage V gLNA. The inductor L d1_ and the inductor L d3_ are mutually coupled, the coupling coefficient is k d1_, and the inductor is realized as an 8-shaped transformer in a layout and is used for the interstage matching of the PA; The inductor L d2_ and the inductor L d4_ are mutually coupled, the coupling coefficient is k d2_, and the common single-turn transformer is realized in the layout and is used for the interstage matching of the LNA; The 8-shaped transformer can self-offset the magnetic coupling with other transformers, and the coupling coefficients between the inductance L d1_ and the inductance L d3_ and the inductance L d2_ and the inductance L d4_ are close to zero.
The 1 st-stage LNA and PA differential amplifier adopt differential common source structures with neutralization capacitors, the gate end of an LNA transistor M L1_ is connected with the inductor L a3_ of an input/output matching network T 2io1, the drain end of the LNA transistor M L1_ is connected with the inductor L c2_ of an interstage matching transformer T 2mid1, the source electrode of the LNA and the PA differential amplifier is grounded, and a gate-drain neutralization capacitor C N6 exists between the gate and the drain of the differential transistor so as to reduce parasitism; the drain terminal of the PA transistor M P1_ is connected to the inductor L a2_ of the input/output matching network T 2io1, the gate terminal is connected to the inductor L c1_ of the inter-stage matching transformer T 2mid1, the source terminal is grounded, and a gate-drain neutralization capacitor C N7 exists between the gate and the drain of the differential transistor to reduce parasitism.
The 2 nd-stage LNA and PA differential amplifier adopt differential common source structures with neutralization capacitors, the gate end of the LNA transistor M L2_ is connected with the inductance L c4_ of the interstage matching transformer T 2mid1, the drain end is connected with the inductance L d2_ of the interstage matching transformer T 2mid2, the source electrode is grounded, and a gate-drain neutralization capacitor C N8 exists between the gate and the drain of the differential transistor so as to reduce parasitism; the drain terminal of the PA transistor M P2_ is connected to the inductance L c3_ of the inter-stage matching transformer T 2mid1, the gate terminal is connected to the inductance L d1_ of the inter-stage matching transformer T 2mid2, the source terminal is grounded, and a gate-drain neutralization capacitance C N9 exists between the gate and the drain of the differential transistor to reduce parasitics.
The 3 rd-stage LNA and the PA differential amplifier both adopt differential common source structures with neutralization capacitors, the gate end of the LNA transistor M L3_ is connected with the inductance L d4_ of the interstage matching transformer T 2mid2, the drain end is connected with the inductance L b2_ of the input/output matching network T 2io2, the source electrode is grounded, and a gate-drain neutralization capacitor C N10 exists between the gate and the drain of the differential transistor so as to reduce parasitism; the drain end of the PA transistor M P3_ is connected to the inductor L d3_ of the interstage matching transformer T 2mid2, the gate end is connected to the inductor L b3_ of the input/output matching network T 2io2, the source is grounded, and a gate-drain neutralization capacitor C N11 exists between the gate and the drain of the differential transistor to reduce parasitism.
In LNA mode, the input signal of LNA enters the inductance L a1_ of the input-output matching network T 2io1 from the antenna end, after being coupled by the multi-coil transformer, the signal flows into the 1 st stage LNAPA differential amplifier through L a3_, Into the gate terminal of transistor M L1_ and out of the drain terminal of M L1_, Wherein the gate end of M L1 is connected to the L a3_,La3_ center tap V gLNA of T 2io1 for controlling the on and off of M L1_; The signal is output from the drain terminal of M L1_, flows into the inductor L c2_ of the interstage matching transformer T 2mid1, and after being coupled with the inductor L c4_ through the inductor L c2_, Flows into the 2 nd stage LNAPA differential amplifier, enters the gate terminal of the transistor M L2_ and is output from the drain terminal of M L2_, Wherein the gate end of M L2_ is connected to the L c4_,Lc4_ center tap V gLNA of T 2mid1 for controlling the on and off of M L2_; The signal is output from the drain terminal of M L2_, flows into the inductor L d2_ of the interstage matching transformer T 2mid2, and after being coupled with the inductor L d4_ through the inductor L d2_, Flows into the 3 rd stage LNAPA differential amplifier, enters the gate terminal of transistor M L3_ and is output from the drain terminal of M L3_, Wherein the gate end of M L3_ is connected to the L d4_,Ld4_ center tap V gLNA of T 2mid2 for controlling the on and off of M L3_; the signal flows into the inductance L b2_ of the input-output matching network T 2io2 after being output from the drain end of the M L3_, and finally flows out through the L b1_ after being coupled by the multi-coil transformer.
In the PA mode, the input signal of the PA enters the inductance L b1_ of the input-output matching network T 2io2 from the mixer end, after being coupled by the multi-coil transformer, the signal flows into the 3 rd stage LNAPA differential amplifier through L b3_, Into the gate terminal of transistor M P3_ and out of the drain terminal of M P3_, Wherein the gate end of M P3_ is connected to the L b3_,Lb3_ center tap V gPA of T 2io2 for controlling the on and off of M P3_; The signal is output from the drain terminal of M P3_, flows into the inductor L d3_ of the interstage matching transformer T 2mid2, and after being coupled with the inductor L d1_ through the inductor L d3_, Flows into the 2 nd stage LNAPA differential amplifier, enters the gate terminal of the transistor M P2_ and is output from the drain terminal of M P2_, Wherein the gate end of M P2_ is connected to the L d1_,Ld1_ center tap V gPA of T 2mid2 for controlling the on and off of M P2_; The signal is output from the drain terminal of M P2_, flows into the inductor L c3_ of the interstage matching transformer T 2mid1, and after being coupled with the inductor L c1_ through the inductor L c3_, Flows into the 1 st stage LNAPA differential amplifier, enters the gate terminal of the transistor M P1_ and is output from the drain terminal of M P1_, Wherein the gate end of M P1_ is connected to the L c1_,Lc1_ center tap V gPA of T 2mid1 for controlling the on and off of M P1_; The signal flows into the inductance L a2_ of the input-output matching network T 2io1 after being output from the drain end of the M P3_, and finally flows out through the L a1_ after being coupled by the multi-coil transformer.
The first amplifying Path Path1 and the second amplifying Path Path2 are connected together at the input/output matching network through the ground to form a millimeter wave frequency band double-Path synthesis bidirectional amplifier with differential input and differential output.
(2) Description of the principle of operation of the Circuit
The millimeter wave frequency band double-path synthesis bidirectional amplifier based on the inter-stage matching network transformer coplanar decoupling technology in the embodiment is as follows:
The two-way amplifier comprises a first amplifying Path Path1 and a second amplifying Path Path2, each Path is of a single two-way amplifier circuit structure, and the single two-way amplifier is formed by cascading an input/output matching network, a 3-stage differential amplifier and a decoupling interstage matching network.
The LNA is realized by adopting a noise cancellation technology and comprises two paths, and the common grid is low in millimeter wave frequency band gain and the noise coefficient NF is mainly related to a 1 st-stage amplifier, so that the common grid-common source (CG-CS) noise cancellation technology is only adopted at the 1 st stage. The 1 st route of LNA is formed by 3-level differential amplifier cascade connection, the 1 st level adopts a differential common gate structure with enhanced transconductance, and the 2 nd and 3 rd levels adopt differential common source structures with neutralization capacitors; the 2 nd paths of 1,2 and 3 rd-stage amplifiers of the LNA all adopt differential common-source structures with neutralization capacitors. CG-CS noise cancellation techniques are based on a common-gate (CG) path and a common-source (CS) path that together cancel the thermal noise of a common-gate amplifier, where the CG path and the CS path need to have 180 ° opposite directions and have identical gains in order to better cancel the noise. Since the gain of the common gate amplifier is smaller than that of the common source amplifier at high frequency, the gain of the CG path is improved by adopting a transconductance enhancement technology at the common gate amplifier, and the reverse of the two paths can be realized by depending on the phase offset of the transformer.
The PA adopts two-path parallel power synthesis technology to improve the saturated output power of the PA. The 1 st circuit and the 2 nd circuit of the PA have the same structure, are composed of three stages of differential common source amplifiers with neutralization capacitors, are synthesized at an output matching network, and finally are realized into two paths of differential input and differential output high-performance PA.
The CG Path of the LNA and the 1 st Path of the PA form the Path1 of the two-way composite bi-directional amplifier, the CS Path of the LNA and the 2 nd Path of the PA form the Path2 of the two-way composite bi-directional amplifier, and the Path1 and the Path2 are cascaded to form the two-way composite bi-directional amplifier.
For the first amplifying Path1, the input/output matching network T 1io1 is used for the input matching of the LNA of Path1 and the output matching of the PA, the transconductance-boosted three-coil transformer is composed of an inductor L a1、La2、La3, the input stage of the LNA is based on a common-gate topology, the impedance is lower (1/g m), near the optimal impedance of the PA so that the same matching network can be shared. Inductor L a3 serves as a transconductance boosting inductor to compensate for the gain of the common-gate amplifier, inductor L a2 connects the input stage of the LNA (the source of LNA transistor M L1) and the output stage of the PA (the drain of PA transistor M P1) simultaneously, one end of the inductor L a1 is used for being connected with one end of the differential antenna, and the other end of the inductor L a1 is grounded. the three inductors are coupled to each other, so that the multiplexing of the values of the parameters of the input-output matching network T 1io1,T1io1 needs to consider the compromise of the performance of the LNA and the PA. The input/output matching network T 1io2 is used for the output matching of the Path1LNA and the input matching of the PA, and consists of an inductor L b1、Lb2、Lb3, an inductor L b2 is connected with the output stage of the LNA (the drain terminal of the LNA transistor M L3), An inductor L b3 is connected to the input stage of the PA (the gate terminal of the PA transistor M P3), and one end of the inductor L b1 is connected to one end of the mixer, and the other end is grounded. The three inductors are coupled to each other, so that the multiplexing of the values of the parameters of the input-output matching network T 1io2,T1io2 needs to consider the compromise of the performance of the LNA and the PA.
Further as an alternative implementation, in order to ensure the performance of the LNA and the PA and share the area of the bidirectional amplifier, the present invention proposes a transformer coplanar decoupling technology, and in the interstage decoupling matching network T 1mid1、T1mid2, the interstage matching networks of the LNA and the PA are separately designed. Taking a four-coil transformer T 1mid1 as an example, the overall layout is as shown in fig. 4, the LNA matching network adopts a single-coil transformer design, and according to the current flow direction, the current direction of a primary coil (③④) is clockwise, and the current direction of a secondary coil (⑦⑧) is anticlockwise, so that reverse coupling is formed. The PA matching network is designed by a figure 8 transformer, and the primary coil (①②) and the secondary coil (⑤⑥) have opposite equal amounts of magnetic flux in the regions a and b according to the current flow direction, and the two are reversely coupled. Because the 8-shaped PA transformer area a and the area b have opposite equal amounts of magnetic fluxes, the current generated by the PA transformer and the current of the LNA transformer can be mutually offset, and the mutual influence between the two transformers is eliminated. The decoupling simulation results between the inductive coils ①②, ⑤⑥ and ③④, ⑦⑧ are shown in fig. 5, where the coupling coefficients between the decoupling inductive coils are all less than 0.1, and the decoupling inductive coils are in a weak coupling state or even no coupling state. The transformer coplanar decoupling technology realizes the separation design of the LNA and/or the PA interstage matching network, greatly reduces the area of a chip, and improves the performances of the LNA and the PA such as gain. The specific connection mode of T 1mid1、T1mid2 is described with reference to the circuit structure.
For the second amplification Path2, the input-output matching network T 2io1 is used for the input matching of the LNA and the output matching of the PA of Path2, a three-coil transformer is composed of an inductance L a1_、La2_、La3_, the inductance L a3_ is connected to the input stage of the LNA (the gate terminal of the LNA transistor M L1_), The inductor L a2_ is connected to the output stage of the PA (drain terminal of the PA transistor M P1_), and one end of the inductor L a1_ is connected to one end of the differential antenna, and the other end is grounded. The three inductors are coupled to each other, so that the multiplexing of the values of the parameters of the input-output matching network T 2io1,T2io1 needs to consider the compromise of the performance of the LNA and the PA. The input/output matching network T 2io2 is used for the output matching of the Path2LNA and the input matching of the PA, and consists of an inductor L b1_、Lb2_、Lb3_, an inductor L b2_ is connected with the output stage of the LNA (the drain terminal of the LNA transistor M L3_), An inductor L b3_ is connected to the input stage of the PA (the gate terminal of the PA transistor M P3_), and one end of the inductor L b1_ is connected to one end of the mixer, and the other end is grounded. The three inductors are coupled to each other, so that the multiplexing of the values of the parameters of the input-output matching network T 2io2,T2io2 needs to consider the compromise of the performance of the LNA and the PA.
Further as an alternative implementation manner, in order to ensure the performance of the LNA and the PA and share the area of the bidirectional amplifier, as in Path1, the inter-stage decoupling matching network T 2mid1、T2mid2 also applies the transformer area coplanar decoupling technology, separates the inter-stage matching networks of the LNA and the PA, adopts a single-turn transformer for the LNA, adopts an 8-shaped transformer for the PA, and then stacks the two transformers together to realize the reduction of the chip area. The specific connection mode of T 2mid1、T2mid2 is described with reference to the circuit structure.
In addition, in the design of the millimeter wave frequency band two-way synthesis bidirectional amplifier, 11 differential common source amplifier structures are used, and in the amplifiers, a neutralization capacitor C N1～11 is adopted to be connected to the grid-drain terminal of a differential transistor in a cross mode. The parasitic capacitance C gd of the differential transistor can be effectively counteracted, so that the stability of the differential common source amplifier is improved.
Based on the millimeter wave frequency band two-way synthesis bidirectional amplifier, the embodiment also provides a control method, which comprises the following steps:
The middle tap of the inductor Lc2、Lc3、Ld2、Ld3、Lb2、La2_、Lc2_、Lc3_、Ld2_、Ld3_、Lb2_ is connected with VDD; the middle tap of the inductor L a3、Lc4、Ld4、La3_、Lc4_、Ld4_ is connected with the bias voltage V gLNA; the middle tap of the inductor L c1、Ld1、Lb3、Lc1_、Ld1_、Lb3_ is connected with the bias voltage V gPA; the center tap of the inductor L a2 is connected to the control voltage V ctrl.
Controlling the bias voltage V gLNA to bias at a preset non-zero voltage, controlling the bias voltage V ctrl to be zero and controlling the bias voltage V gPA to bias to be zero so as to enable the millimeter wave frequency band two-way synthesis bidirectional amplifier to work in an LNA mode;
And controlling the bias voltage V gPA to bias at a preset non-zero voltage, controlling the bias voltage V ctrl to be VDD and controlling the bias voltage V gLNA to bias to be zero so as to enable the millimeter wave frequency band two-way synthesis bidirectional amplifier to work in a PA mode.
In LNA mode, LNA transistor M L1、ML2、ML3、ML1_、ML2_、ML3_ is on and PA transistor M P1、MP2、MP3、MP1_、MP2_、MP3_ is off.
In PA mode, PA transistor M P1、MP2、MP3、MP1_、MP2_、MP3_ is on and LNA transistor M L1、ML2、ML3、ML1_、ML2_、ML3_ is off.
The bias voltage V gLNA and the bias voltage V gPA only need extremely small current, and the magnitude of the bias voltage is changed through SPI; the control voltage V ctrl is connected to the source or drain of the transistor, and needs to be switched between VDD and ground, and a large current is required, so that a switch is required to switch the control voltage V ctrl. As shown in fig. 3, the schematic circuit diagram of the switch can control the magnitude of the bias voltage V SW through the SPI, when V SW =1, the NMOS transistor M2 is turned on, the PMOS transistor M1 is turned off, and the value of the control voltage V ctrl is equal to zero, which is equivalent to the ground; when V SW =0, the NMOS transistor M2 is turned off, the PMOS transistor M1 is turned on, and the value of the control voltage V ctrl is approximately equal to VDD.
(3) Experimental results
The millimeter wave frequency band two-way synthesis bidirectional amplifier adopting the coplanar decoupling transformer in the embodiment 1 of the invention is used for the front end of the D frequency band bidirectional transceiver. In LNA mode, S parameter simulation results are shown in FIG. 6, the bandwidth of 3dB gain (S 21) is 130-146GHz, the highest gain is 17.421dB@137GHz, the input is matched with S 11 < -7dB, and the output is matched with S 22 < -14dB. To verify the effect of the noise cancellation technique of the LNA, the gain and phase of the CG and CS paths of the LNA are simulated, as shown in fig. 7, it can be seen that at 140GHz, the gain of the CG path is smaller than that of the CS path, the phase of the CG path is about 224 ° different from that of the CS path, and is deviated from 180 °, but the matching network needs to compromise the performance of the PA and the LNA, which is acceptable. The CG-CS noise cancellation effect exists, and finally the LNA in-band noise figure NF is 5.974-7.195dB, as shown in fig. 8. The input 1dB compression point IP1dB of the LNA is-18.12 dBm. The total power consumption of the LNA was 69.7mW.
In the PA mode, the simulation result of the S parameter is shown in FIG. 9, the bandwidth of the 3dB gain (S 21) is 136-148GHz, the highest gain is 21.147dB@144GHz, the input is matched with S 11 < -9dB, and the output is matched with S 22 < -18.8dB. As shown in fig. 10, the Gain, output Power P out, and Power added efficiency (Power-ADDED EFFICIENCY, PAE) of PA at 140GHz as a function of input Power P in are shown in fig. 10, saturated output Power P sat is 11.65dBm, maximum PAE is 7.82%, and PA mode total Power consumption is 119.7mW.
Example 2
As shown in fig. 11, the circuit configuration of the present embodiment is the same as that in embodiment 1, and the main difference from embodiment 1 is that: based on embodiment 1, the PA first stage differential amplifier transistor M P1 of the Path1 of the millimeter wave band two-way synthesis bi-directional amplifier is changed from an NMOS transistor to a PMOS transistor, the source terminal is VDD-terminated, the drain terminal is LNA transistor M L1, and then connected to both ends of the inductor L a1.
In embodiment 1, the center tap of the inductor L a1 is connected to the control voltage V ctrl and needs a large switch to switch, and in embodiment 2, the center tap of the inductor L a1 is connected to ground. The circuit structure can be simplified and the chip area can be reduced, but the performance of the amplifier is slightly reduced due to the smaller transconductance g m of the PMOS transistor, etc.
Example 3
As shown in fig. 12, the circuit configuration of the present embodiment is the same as that in embodiment 1, and the main difference from embodiment 1 is that: based on embodiment 1, the internal circuits of Path1 and Path2 of the millimeter wave frequency band two-way synthesis bidirectional amplifier adopt the concept that transistors in an off state can be used as a neutralization capacitor, the gate end of the LNA/PA amplifier transistor is connected with the drain end of the PA/LNA amplifier transistor, when the PA/LNA works, the transistors in the LNA/PA off state can be used as the neutralization capacitor, the interstage matching network is multiplexed, and the multiplexing degree is extremely high. The center tap of the matching network inductor L a2 is connected with control voltage V ctrl, the center tap of the matching network inductor La3、Lc1、Lc2、Ld1、Ld2、Lb2、La2_、Lc1_、Lc2_、Ld1_、Ld2_、Lb2_ is connected with VDD, the grid electrode of the LNA tail current source transistor M LT2、MLT3、MLT1_、MLT2_、MLT3_ is connected with bias voltage V gLNA, and the grid electrode of the PA tail current source transistor M PT1、MPT2、MPT3、MPT1_、MPT2_、MPT3_ is connected with bias voltage V gPA; the bias voltage V gLNA is controlled to be biased at a preset non-zero voltage and the bias voltage V gPA is controlled to be biased to be zero through SPI, and the switch control voltage V ctrl is controlled to be zero, so that the two-way synthesis bidirectional amplifier works in an LNA mode; the bias voltage V gLNA is controlled to be biased to zero through SPI and the bias voltage V gPA is controlled to be biased to be at a preset non-zero voltage, and the switch control voltage V ctrl is controlled to be VDD, so that the two-way synthetic bidirectional amplifier works in a PA mode.
However, this method requires increasing the tail current source to switch the direction, and increases the chip area; and the matching networks are shared, so that the performance of the LNA and the PA is required to be compromised; meanwhile, the method is not available at high frequency, because the parasitic effect of the transistor is enhanced at high frequency, the capacitance Q value of the transistor is low, the passive loss is increased, and the turned-off transistor acts as an active load to cause performance degradation of an output 1dB compression point OP1dB, PAE and the like.
Example 4
As shown in fig. 13, the circuit configuration of this embodiment is the same as that in embodiment 3, and the main difference from embodiment 3 is that: based on embodiment 3, the LNA adopts an NMOS transistor, the PA adopts a PMOS transistor, no tail current source is required, the NMOS transistor source is grounded, the PMOS transistor source is grounded, the center tap of the matching network inductor L a2 is grounded, the center tap of the matching network inductor L a3、Lc2、Ld2、La2_、Lc2_、Ld2_ is grounded to the control voltage V ctrl1, and the center tap of the matching network inductor L c1、Ld1、Lb2、Lc1_、Ld1_、Lb2_ is grounded to the control voltage V ctrl2; the switch control voltage V ctrl1 is a preset non-zero voltage and V ctrl2 is VDD, so that the two-way synthesis bidirectional amplifier works in an LNA amplifier mode; the bidirectional amplifier can be controlled to work in a low noise amplifier mode or a power amplifier mode; the two-way composite bi-directional amplifier is operated in PA mode by switching control voltage V ctrl1 to ground and V ctrl2 to a preset non-zero voltage. The tail current source transistor is optimized by the method, but the performance of the PA is obviously deteriorated due to the smaller transconductance g m value of the PMOS transistor; the switching of the circuit direction requires a large-size switch to switch the values of V ctrl1 and V ctrl2, and still occupies the chip area; at the same time, the LNA/PA performance tradeoff mentioned in example 3 and the performance degradation problem caused by the low transistor capacitance Q remain.
Example 5
As shown in fig. 14, the circuit configuration of the present embodiment is the same as that in embodiment 4, and the main difference from embodiment 4 is that: based on embodiment 4, the LNA adopts a PMOS transistor, the PA adopts an NMOS transistor, no tail current source is required, the PMOS transistor source is connected to VDD, the NMOS transistor source is grounded, the center tap of the matching network inductor L a2 is connected to VDD, the center tap of the matching network inductor L a3、Lc2、Ld2、La2_、Lc2_、Ld2_ is connected to the control voltage V ctrl1, and the center tap of the matching network inductor L c1、Ld1、Lb2、Lc1_、Ld1_、Lb2_ is connected to the control voltage V ctrl2; the switch control voltage V ctrl1 is a preset non-zero voltage and V ctrl2 is ground, so that the two-way synthesis bidirectional amplifier works in an LNA amplifier mode; the two-way composite bi-directional amplifier is operated in PA mode by switching control voltages V ctrl1 to VDD and V ctrl2 to a preset non-zero voltage. Because the PA has a high transconductance and the LNA has a low transconductance, the overall performance of the bi-directional amplifier is slightly better than that of example 4, with NMOS as the PA's transistor and PMOS as the LNA's transistor.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (14)
1. The millimeter wave frequency band two-way synthesis bidirectional amplifier is characterized by comprising two bidirectional amplification paths at least comprising two stages, wherein the bidirectional amplification paths comprise:
The low-noise amplifier is used for amplifying signals received by the antenna and comprises a first input matching network, a first inter-stage matching network and a first output matching network;
the power amplifier is used for amplifying signals to be transmitted through the antenna and comprises a second input matching network, a second interstage matching network and a second output matching network;
the first input matching network and the second output matching network are coupled and multiplexed, and the first output matching network and the second input matching network are coupled and multiplexed.
2. The millimeter wave frequency band two-way synthesis bidirectional amplifier according to claim 1, wherein the low noise amplifier and the power amplifier both adopt differential circuit structures;
The two bidirectional amplifying paths are called a first amplifying path and a second amplifying path;
the first amplifying path comprises a common gate path of the low noise amplifier and a1 st path of the power amplifier;
the second amplifying path comprises a common source path of the low noise amplifier and a 2 nd path of the power amplifier;
The first amplifying path comprises a first input end and a first output end, and the second amplifying path comprises a second input end and a second output end;
the first input end and the second input end are connected in parallel to form an input end of the two-way synthetic bidirectional amplifier;
The first output end and the second output end are connected in parallel to form an output end of the two-way synthetic bidirectional amplifier.
3. The millimeter wave frequency band two-way synthesis bidirectional amplifier according to claim 2, wherein the common gate path of the low noise amplifier comprises a common gate differential amplifier adopting a transconductance boosting technology and N-1 common source differential amplifiers adopting a capacitance neutralization technology, and the 1 st path of the power amplifier comprises N common source differential amplifiers adopting a capacitance neutralization technology;
The 2 nd path of the power amplifier comprises N common-source differential amplifiers adopting a capacitance neutralization technology;
Where N represents the number of stages of the amplifier.
4. The millimeter wave band two-way composite bi-directional amplifier according to claim 2, wherein the matching network between the two-way composite bi-directional amplifiers comprises an asymmetric parallel input transformer, at least one symmetric interstage matching transformer, and a symmetric parallel output transformer;
The asymmetric parallel input transformer comprises an input/output matching network T 1io1 of a first amplifying path and an input/output matching network T 2io1 of a second amplifying path; the symmetrical interstage matching transformer comprises N-1 interstage matching networks T 1mid1、...、T1midN-1 for a first amplification path and N-1 interstage matching networks T 2mid1、...、T2midN-1 for a second amplification path; the symmetrical parallel output transformer comprises an input/output matching network T 1io2 of a first amplifying path and an input/output matching network T 2io2 of a second amplifying path;
Where N represents the number of stages of the amplifier.
5. A millimeter wave band two-way composite bi-directional amplifier according to any of claims 1-4, wherein said low noise amplifier and said inter-stage matching network of said power amplifier are independently designed and share the same chip area using coplanar decoupling transformers.
6. The millimeter wave band two-way composite bidirectional amplifier according to claim 5, wherein the low noise amplifier and the power amplifier are three-stage amplifiers;
The input/output matching networks T 1io1、T1io2、T2io1 and T 2io2 are three-coil transformers comprising three inductors, and any two of the three inductors are magnetically coupled;
The first end inductor L a1 of the input/output matching network T 1io1 is connected with an antenna, one inductor L a2 of the second end is connected with the source stage of the transistor M L1 of the low-noise amplifier and the drain electrode of the transistor M P1 of the power amplifier, and the other inductor L a3 is connected with the grid electrode of the transistor M L1 in a cross mode and used for transconductance improvement of a common gate amplifier;
The first end inductor L a1_ of the input/output matching network T 2io1 is connected with an antenna, one inductor L a2_ of the second end is connected with the drain electrode of the transistor M P1_ of the power amplifier, and the other inductor L a3_ is connected with the grid electrode of the transistor M L1_ of the low-noise amplifier;
The first inductor L b1/Lb1_ of the input/output matching network T 1io2/T2io2 is connected to the mixer, one inductor L b2/Lb2_ of the second end is connected to the drain of the transistor M L3/ML3_ of the low noise amplifier, and the other inductor L b3/Lb3_ is connected to the gate of the transistor M P3/MP3_ of the power amplifier.
7. The millimeter wave band two-way composite bi-directional amplifier according to claim 6, wherein the millimeter wave band two-way composite bi-directional amplifier comprises four inter-stage matching networks T 1mid1、T1mid2、T2mid1 and T 2mid2, and the inter-stage matching networks adopt a transformer area coplanar decoupling structure;
The interstage matching networks T 1mid1、T1mid2、T2mid1 and T 2mid2 are four-coil transformers, and the four-coil transformers are realized as a superposition of a common single-coil transformer and an 8-shaped transformer in the layout; two inductive magnetic couplings forming the common single-turn transformer and two inductive magnetic couplings forming the 8-shaped transformer;
The 8-shaped inductor L c1/Lc1_ at the first end of the inter-stage matching network T 1mid1/T2mid1 is connected with the grid electrode of the transistor M P1/MP1_, the single-turn inductor L c2/Lc2_ is connected with the drain electrode of the transistor M L1/ML1_, the 8-shaped inductor L c3/Lc3_ at the second end is connected with the drain electrode of the transistor M P2/MP2_, and the single-turn inductor L c4/Lc4_ is connected with the grid electrode of the transistor M L2/ML2_ for matching between the 1 st stage and the 2 nd stage of the two-way bidirectional amplifier;
The 8-shaped inductor L d1/Ld1_ at the first end of the inter-stage matching network T 1mid2/T2mid2 is connected with the grid electrode of the transistor M P2/MP2_, the single-loop inductor L d2/Ld2_ is connected with the drain electrode of the transistor M L2/ML2_, the 8-shaped inductor L d3/Ld3_ at the second end is connected with the drain electrode of the transistor M P3/MP3_, and the single-loop inductor L d4/Ld4_ is connected with the grid electrode of the transistor M L3/ML3_ for matching between the 2 nd stage and the 3 rd stage of the two-way bidirectional amplifier.
8. A millimeter wave band two-way composite bi-directional amplifier according to any one of claims 6 or 7, characterized in that the millimeter wave band two-way composite bi-directional amplifier is controlled by:
The center tap of the inductor L a2 is connected with a control voltage V ctrl; the center tap of the inductor L a3、Lc4、Ld4、La3_、Lc4_、Ld4_ is connected with the bias voltage V gLNA, and the center tap of the inductor L c1、Ld1、Lb3、Lc1_、Ld1_、Lb3_ is connected with the bias voltage V gPA; the control voltage V ctrl needs a large-sized switch to control, and the on/off of the switch and the magnitudes of the bias voltages V gLNA and V gPA are controlled through a serial peripheral interface to control the bidirectional amplifier to operate in a low noise amplifier mode or a power amplifier mode.
9. The millimeter wave band two-way composite bi-directional amplifier according to any one of claims 1 to 4, wherein a gate of the low noise amplifier/power amplifier is connected to a drain of the power amplifier/low noise amplifier, and when the power amplifier/low noise amplifier is operated, a transistor in an off state of the low noise amplifier/power amplifier is used as a neutralization capacitor, and an inter-stage matching network is multiplexed.
10. The millimeter wave band two-way composite bidirectional amplifier according to claim 9, wherein the low noise amplifier and the power amplifier are three-stage amplifiers;
The input/output matching network T 1io1 is a three-coil transformer, and any two of the three inductors are magnetically coupled; the input/output matching networks T 1io2、T2io1 and T 2io2 are two-coil transformers;
The first end inductor L a1 of the transformer T 1io1 is connected with an antenna, one inductor L a2 of the second end is connected with the source electrode of the transistor M L1 of the low-noise amplifier, and the other inductor L a3 is connected with the grid electrode of the transistor M L1 and the drain electrode of the transistor M P1 of the power amplifier;
The first end inductor L a1_ of the transformer T 2io1 is connected with an antenna, and the second end inductor L a2_ is connected with the grid electrode of the transistor M L1_ of the low-noise amplifier and the drain electrode of the transistor M P1_ of the power amplifier;
the second end inductor L b1/Lb1_ of the transformer T 1io2/T2io2 is connected to the mixer, and the first end inductor L b2/Lb2_ is connected to the drain of the transistor M L3/ML3_ of the low noise amplifier and the gate of the transistor M P3/MP3_ of the power amplifier.
11. The millimeter wave band two-way composite bidirectional amplifier according to claim 10, wherein an inter-stage matching network of the power amplifier and the low noise amplifier is shared, and the inter-stage matching networks T 1mid1、T1mid2、T2mid1 and T 2mid2 are two-coil transformers;
The first end inductor L c1/Lc1_ of the transformer T 1mid1/T2mid1 is connected with the drain electrode of the transistor M L1/ML1_ and the grid electrode of the transistor M P1/MP1_, and the second end inductor L c2/Lc2_ is connected with the grid electrode of the transistor M L2/ML2_ and the drain electrode of the transistor M P2/MP2_ for matching between the 1 st stage and the 2 nd stage of the bidirectional amplifier;
the first end inductor L d1/Ld1_ of the transformer T 1mid2/T2mid2 is connected to the drain of the transistor M L2/ML2_ and the gate of the transistor M P2/MP2_, and the second end inductor L d2/Ld2_ is connected to the gate of the transistor M L3/ML3_ and the drain of the transistor M P3/MP3_, for matching between the 2 nd and 3 rd stages of the bidirectional amplifier.
12. The millimeter wave band two-way composite bi-directional amplifier according to claim 1, 10 or 11, wherein when the transistors of the low noise amplifier and the power amplifier are both NMOS transistors, the center tap of the inductor L a2 is connected to the control voltage V ctrl, the gate of the tail current source transistor of the low noise amplifier is connected to the bias voltage V gLNA, The grid electrode of the tail current source transistor of the power amplifier is connected with bias voltage V gPA; The control voltage V ctrl needs a large-size switch to control, and the on-off of the switch and the magnitudes of the bias voltages V gLNA and V gPA are controlled through a serial peripheral interface so as to control the bidirectional amplifier to work in a low-noise amplifier mode or a power amplifier mode; When the transistor of the low noise amplifier and the transistor of the power amplifier are in cross connection with an NMOS transistor and a PMOS transistor, a tail current source is not needed; The source electrode of the NMOS transistor is grounded, the source electrode of the PMOS transistor is grounded, the center tap of the matching network inductor L a2 is grounded, the center tap of the matching network inductor L a3、Lc2、Ld2、La2_、Lc2_、Ld2_ is connected with the control voltage V ctrl1, and the center tap of the inductor L c1、Ld1、Lb2、Lc1_、Ld1_、Lb2_ is connected with the control voltage V ctrl2; The control voltages V ctrl1 and V ctrl2 require a large-sized switch to control, and the switch is turned on and off by a serial peripheral interface to control the bi-directional amplifier to operate in a low noise amplifier mode or a power amplifier mode.
13. A chip comprising a millimeter wave band two-way composite bi-directional amplifier as claimed in any one of claims 1 to 12.
14. An electronic device comprising a millimeter wave band two-way composite bi-directional amplifier as claimed in any one of claims 1 to 12, or a chip as claimed in claim 13.
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