CN118380411A - Groove type power device structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a trench type power device structure and a manufacturing method thereof, wherein a first trench and a second trench extending downwards from the bottom of the first trench are formed in a semiconductor substrate, the first trench is used for filling a gate, the second trench is used for filling a dielectric layer, the first trench comprises a necking section, the width of the necking section from the top to the bottom is gradually reduced, and therefore the area of an emitter region formed by ion implantation between adjacent gate trenches is increased, and the problem that the normal opening of threshold voltage is influenced due to the fact that the area of the emitter region is too small in the prior art can be solved.

Description

Groove type power device structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a groove type power device structure and a manufacturing method thereof.

Background

Conventional Trench-type power device structures, such as IGBTs (Insulated Gate Bipolar Transistor, insulated gate bipolar transistors), trench MOSFETs (Trench metal oxide transistors), and the like, require strict control of alignment accuracy between the contact hole and the gate Trench due to design rules and device physical model limitations during fabrication of the contact hole, and generally have a photolithography capability of about 50-100 nm.

As the device size is continuously reduced, the device cell pitch is also reduced, as shown in fig. 1, when the device cell pitch (CELL PITCH) d is reduced to about 1um, the natural pitch between the contact hole 200 and the trench 100 is already less than 200nm, the alignment accuracy is required to be limited to be within 50nm, and obviously, the alignment accuracy cannot be ensured by a common photoetching machine, so that the contact hole can deviate. Impurity ions injected into the bottom of the contact hole 200 are laterally spread to both sides at a certain activation temperature, and the contact hole 200 is deviated to cause different ion concentrations at both sides, so that the contact hole 200 cannot be simultaneously opened. In addition, in the prior art, after the etching of the contact hole 200 is completed, the area of the emitter region 300 located between adjacent trenches is greatly reduced, and there is a problem in that it is difficult to normally turn on the threshold voltage.

Disclosure of Invention

The present invention is directed to a trench power device structure and a method of fabricating the same that address one or more of the problems of the prior art.

In order to solve the above problems, the present invention provides a trench power device structure, including:

A semiconductor substrate having a gate trench comprising a first trench and a second trench extending downward from a bottom of the first trench, the first trench comprising a reduced section that gradually decreases in width from top to bottom opening;

a gate formed within the second trench;

the dielectric layer fills the first groove and covers the grid electrode; and

And the metal plug is formed in the region of the semiconductor substrate between two adjacent gate trenches.

Optionally, in the trench type power device structure, the second trench extends downward from a bottom of the necking section, a side wall of the necking section forms an angle with the surface of the semiconductor substrate, a side wall of the second trench forms an angle with the surface of the semiconductor substrate, and the first angle is smaller than the second angle.

Optionally, in the trench type power device structure, the necking section extends from a top to a bottom of the first trench.

Optionally, in the trench power device structure, a difference between the second angle and the first angle is 6 ° to 7 °.

Optionally, in the trench type power device structure, a difference between a top opening width and a bottom opening width of the first trench is 0.3 μm to 0.32 μm.

Optionally, in the trench type power device structure, a difference between a top opening width and a bottom opening width of the second trench is 0.20 μm to 0.28 μm.

Optionally, in the trench type power device structure, the first trench and the second trench are connected to a reference plane, and an upper surface of the gate is coincident with the reference plane, or an upper surface of the gate is lower than the reference plane.

Optionally, in the trench type power device structure, a distance between the upper surface of the gate and the top opening of the gate trench is 0.4 μm to 0.5 μm.

Optionally, in the trench power device structure, the semiconductor substrate has a body region and an emitter region in a region between two adjacent gate trenches, the emitter region covers the body region, the metal plug penetrates the emitter region and extends into the body region, and a bottom surface of the emitter region is lower than a top surface of the gate.

The invention also provides a manufacturing method of the groove type power device structure, which comprises the following steps:

Providing a semiconductor substrate, and etching the semiconductor substrate to form a gate trench, wherein the gate trench comprises a first trench and a second trench extending downwards from the bottom of the first trench, the first trench comprises a necking section, and the width of the necking section from the top to the bottom is gradually reduced;

Forming a gate in the second trench;

Filling a dielectric layer in the first groove, wherein the dielectric layer covers the grid electrode; and

And etching the region of the semiconductor substrate between two adjacent gate trenches by taking the dielectric layer as a mask to form a contact hole, and forming a metal plug in the contact hole.

Optionally, in the method for manufacturing a trench type power device structure, the second trench extends downward from the bottom of the necking section, a side wall of the necking section forms an angle with the surface of the semiconductor substrate, a side wall of the second trench forms an angle with the surface of the semiconductor substrate, and the first angle is smaller than the second angle.

Optionally, in the method for manufacturing a trench power device structure, the step of forming a gate in the second trench includes:

And filling a gate material in the gate trench, and etching back the gate material to stop at a reference surface formed by connecting the first trench and the second trench or to stop below the reference surface.

Optionally, in the method for manufacturing a trench power device structure, the method further includes:

And forming a body region and an emitter region on the semiconductor substrate, wherein the body region and the emitter region are formed in a region between two adjacent first trenches through ion implantation, the emitter region covers the body region, the metal plug penetrates through the emitter region and extends into the body region, and the bottom surface of the emitter region is lower than the top surface of the grid electrode.

In summary, the trench type power device structure and the manufacturing method thereof provided by the invention have the following advantages compared with the prior art:

(1) Forming a first groove and a second groove extending downwards from the bottom of the first groove in the semiconductor substrate, wherein the first groove is used for filling a grid electrode, the second groove is used for filling a dielectric layer, and subsequently, when etching the area between adjacent grid electrode grooves to form a contact hole, the dielectric layer filled in the first groove plays a role of a mask, so that the contact hole can be etched without the assistance of a photomask mask, a photomask mask can be omitted, the production cost is reduced, and the alignment precision can be improved;

(2) The first groove comprises a necking section, and the width of the necking section from the top to the bottom is gradually reduced, so that the area of an emitter region formed by ion implantation between adjacent gate grooves is increased, and the problem that the normal opening of threshold voltage is influenced due to the fact that the area of the emitter region is too small in the prior art can be solved;

(3) Further, the side wall of the necking section forms a first angle with the surface of the semiconductor substrate, the side wall of the second groove forms a second angle with the surface of the semiconductor substrate, the first angle is smaller than the second angle, different inclination angles are designed to enable the boundary of the first groove and the second groove to have obvious corners, and when the grid electrode is formed through back etching of the grid electrode material, the corners can play a role in indicating the back etching depth, the back etching precision is improved, and the grid electrode is prevented from protruding out of the second groove to have sharp corners.

Drawings

Fig. 1 is a schematic structural diagram of a trench type power device in the prior art;

fig. 2 is a flowchart of a method for manufacturing a trench power device according to an embodiment of the present invention;

fig. 3 to fig. 12 are schematic views of device structures corresponding to steps of a method for manufacturing a trench type power device according to an embodiment of the present invention;

Wherein, each reference sign is explained as follows:

100-grooves; 200-contact holes, 300-emitter regions;

10-a semiconductor substrate; 21-body region; 22-emitter regions; 30-gate trenches; 31-a first trench; 32-a second trench; 40-gate material; 41-grid electrode; 50-a dielectric layer; 60-contact holes; a 70-inversion barrier layer; 80-a metallic material; 81-a metal plug; 23-metal electrode layer.

Detailed Description

The trench type power device and the manufacturing method thereof provided by the invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments. It will be appreciated that relative terms such as "above," "below," "top," "bottom," "above," and "below" as illustrated in the figures may be used to describe various element relationships to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element. It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.

As shown in fig. 2, an embodiment of the present invention provides a method for manufacturing a trench power device, including the following steps:

s1, providing a semiconductor substrate, and etching the semiconductor substrate to form a gate trench, wherein the gate trench comprises a first trench and a second trench extending downwards from the bottom of the first trench, the first trench comprises a necking section, and the width of the necking section from the top to the bottom is gradually reduced;

s2, forming a grid electrode in the second groove;

s3, filling a dielectric layer in the first groove, wherein the dielectric layer covers the grid electrode;

and S4, etching the region of the semiconductor substrate between two adjacent grid grooves by taking the dielectric layer as a mask to form a contact hole, and forming a metal plug in the contact hole.

Accordingly, referring to fig. 12 in combination with fig. 3, an embodiment of the present invention further provides a trench type power device structure, including:

A semiconductor substrate 10, the semiconductor substrate 10 having a gate trench 30, the gate trench 30 comprising a first trench 31 and a second trench 32 extending downward from a bottom of the first trench 31, the first trench 31 comprising a reduced section, the reduced section decreasing in width from top to bottom opening;

a gate 41, the gate 41 being formed within the second trench 32;

a dielectric layer 50, wherein the dielectric layer 50 fills the first trench 31 and covers the gate 41; and

A metal plug 81, wherein the metal plug 81 is formed in a region of the semiconductor substrate 10 between two adjacent gate trenches 30.

The trench type power device structure provided by the embodiment of the invention can be obtained by utilizing the manufacturing method provided by the embodiment of the invention. The trench type power device structure and the manufacturing method thereof according to the embodiment of the invention are described in further detail below with reference to fig. 3 to 12.

First, step S1 is performed, referring to fig. 3, a semiconductor substrate 10 is provided, and the semiconductor substrate 10 is etched to form a gate trench 30. The semiconductor substrate 10 may be any suitable substrate known to those skilled in the art, such as a bulk silicon substrate, a germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a substrate composed of a base and a monocrystalline silicon layer epitaxial thereon, a fused silicon substrate, and the like.

Two gate trenches 30 are shown in fig. 3, but it should be understood that the number of gate trenches 30 in the semiconductor substrate 10 is not limited to the present invention, and in other embodiments of the present invention, one or more gate trenches 30 may be formed at the same time according to device requirements, and when there are two or more gate trenches 30, the width of each gate trench 30 may be the same, or different, the depth of each gate trench 30 may be the same, or different, and the spacing between the gate trenches 30 may be the same, or different.

Specifically, the gate trench 30 includes a first trench 31 and a second trench 32 extending downward from the bottom of the first trench 31. The second trench 32 is used for forming a gate, the first trench 31 is used for filling a dielectric layer, the dielectric layer filled in the first trench 31 has an electrical isolation function, for example, the gate and a source-drain electrode formed subsequently are kept insulated, and the dielectric layer also has a mask function when etching the semiconductor substrate 10 between adjacent gate trenches 30 to form a contact hole, so that when the contact hole is formed by etching, a self-aligned contact hole etching process is substantially adopted, the problem of contact hole alignment deviation caused by process fluctuation is basically avoided, and therefore, the alignment precision can be improved.

When the first trench 31 and the second trench 32 are formed by etching, the semiconductor substrate 10 may be etched according to a first target width to form an initial trench, and then the initial trench is reprocessed to a certain depth according to a second target width having a width greater than the first target width, wherein a portion of the initial trench that is not reprocessed is the second trench 32, and a portion that is reprocessed is the first trench 31. The first trench 31 has a bottom opening width equal to a top opening width of the second trench 32, and the first trench 31 has a top opening width equal to the second target width.

In both the etching to form the initial trench and the re-processing to form the final gate trench 30, a photolithography process may be performed on the hard mask layer at the first target width and the second target width to define a trench top opening width, respectively, and then a dry etching process may be used to etch the semiconductor substrate 10 to form the initial trench and process the initial trench to form the gate trench 30. The gate trench generally formed by the dry etching process may have a top opening width equal to or greater than a bottom opening width, so that the second trench 32 has a constant or slightly reduced opening width from top to bottom, and the gate trench of the present application has relatively no significant change in its entirety, and the gate trench is formed by performing a secondary processing process such that the first trench 31 has a top opening width significantly greater than a bottom opening width, thereby forming the gate trench 30 integrally formed by the first trench 31 and the second trench 32 in a funnel shape.

Compared with the prior art, the gate trench 30 in this embodiment has a constant top opening width, and thus the area of the semiconductor substrate occupied by the entire semiconductor substrate is reduced, so that the area of the semiconductor substrate 10 between adjacent gate trenches 30 is increased, i.e., the area of the emitter region formed by ion implantation between adjacent gate trenches 30 is increased, and thus the problem in the prior art that the threshold voltage is normally opened due to the too small area of the emitter region can be solved.

In a preferred embodiment, as shown in fig. 3, the reduced section extends from the top of the first groove 31 to the bottom thereof, i.e. the entire first groove 31 gradually decreases in width from the top to the bottom.

The area of the emitter region may be maximized when the reduced section extends from the top to the bottom of the first trench 31, but the present application does not limit that the first trench 31 can only adopt the structure as shown in fig. 3, and in other embodiments, the first trench 31 may further include a straight section or an approximately straight section above the reduced section, that is, the first trench 31 is gradually reduced in width to extend a section after the width of the opening from the top to the bottom is maintained constant; or the necked-down section is located below the straight section, etc. The structural design of the first trench 21 with reduced semiconductor substrate area is within the scope of the present application as long as it is compared to the prior art.

The sidewalls of the reduced section are angled to the semiconductor substrate surface at a first angle and the sidewalls of the second trench are angled to the semiconductor substrate surface at a second angle, preferably the first angle is smaller than the second angle, i.e. the sidewalls of the reduced section and the sidewalls of the first trench 31 have different angles of inclination, so that the junction of the first trench 31 and the second trench 32 does not transition smoothly, but has a sharp corner. Further, preferably, the difference between the second angle and the first angle is 6 ° to 7 °, for example, the first angle may be 82 °, and the second angle may be 89 °. Further preferably, the difference between the top opening width and the bottom opening width of the first trench 31 is 0.3 μm to 0.32 μm, for example, the top opening width of the first trench 31 is 8 μm, the bottom opening width is 0.5 μm, the difference between the top opening width and the bottom opening width of the second trench 32 is 0.20 μm to 0.28 μm, for example, the top opening width of the second trench 32 is 0.5 μm, and the bottom opening width is 0.23 μm.

Next, step S2 is performed, as shown in fig. 6, a gate 41 is formed in the second trench 32, and when forming the gate 41, the gate trench 30 may be filled with a gate material, and then a back etching process is performed, so that the gate 41 is formed only in the second trench 32.

The specific process can be as follows: forming a gate dielectric layer (not shown) on the side walls and the bottom wall of the gate trench 30 by using a thermal oxidation process or a chemical vapor deposition process, wherein the material of the gate dielectric layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride and a high-K gate dielectric layer, and the gate dielectric layer may have a single-layer structure or a stacked structure, for example, an ONO stacked structure (i.e., a silicon oxide-silicon nitride-silicon oxide stacked structure); then, as shown in fig. 4 and 5, a silicon-containing material such as silane or chlorosilane is used as a reaction gas source, and polysilicon is further deposited by a low pressure chemical vapor deposition (LP-CVD) process to fill the gate trench 30, so that at least the deposited polysilicon fills the gate trench 30; thereafter, a Chemical Mechanical Planarization (CMP) process or a wet etching process may be used to planarize the top surface of the polysilicon layer to the top surface of the hard mask layer, so that the gate material 40 only fills the gate trench 30, wherein, when the Chemical Mechanical Planarization (CMP) process is used, the gate dielectric layer on the top surface of the hard mask layer may also be removed together; next, the gate material 40 may be etched back and forth using a dry etching process, a wet etching process, or a process of combining dry etching and wet etching, and stopped at a reference surface formed by the first trench 31 and the second trench 32, or stopped under the reference surface, thereby obtaining the gate 41.

In the prior art, the etch back depth is controlled by controlling the etching amount or monitored by an on-line scanning electron microscope device. In the manufacturing method provided by the embodiment of the invention, the joint of the first groove 31 and the second groove 32 has obvious corners, and the corners play a role in guiding the back etching of the gate material 40, so that the accurate control of the back etching depth is facilitated.

When the back etching gate material 40 stops on the reference surface formed by the connection of the first trench 31 and the second trench 32, the upper surface of the gate 41 is overlapped with the reference surface; the upper surface of the gate 41 is formed below the reference surface when the back-etched gate material 40 stops below the reference surface. That is, the upper surface of the gate electrode 41 is formed so as not to protrude beyond the reference plane, so that it is ensured that the gate electrode 41 does not have sharp corners due to the top being positioned in the first trench 31 having a larger width, and thus, an unexpected tip discharge can be prevented from being generated.

Although the gate 41 may not completely fill the second trench 32, it is preferable that the upper surface of the gate 41 is only slightly lower than the reference surface to ensure that the depth of ion implantation ensures that the bottom surface of the emitter region is lower than the top surface of the gate 41 when the emitter region is formed by ion implantation adjacent to the gate trench 30. Since the typical emitter ion implantation junction depth is 0.5 μm to 0.6 μm, it is preferable to design the distance between the upper surface of the gate electrode and the top opening of the gate trench 30 to be 0.4 μm to 0.5 μm, that is, the depth of the back etching when the back etching process is performed after the gate trench 30 is filled with the gate material is 0.4 μm to 0.5 μm, so that the bottom surface of the emitter region formed by ion implantation of the semiconductor substrate 10 between the adjacent gate trenches 30 is ensured to be lower than the top surface of the gate electrode 41.

Next, step S3 is performed, as shown in fig. 8, the first trench 31 is filled with a dielectric layer 50, and the dielectric layer 50 covers the gate 41. In this step, it is not limited that the dielectric layer 50 only fills the first trench 31, and it is also possible that the dielectric layer 50 fills part of the second trench 32. Specifically, when the gate 41 fills the second trench 32, the dielectric layer 50 only fills the first trench 31, and when the gate 41 does not completely fill the second trench 32, the dielectric layer 50 fills the remaining space of the second trench 32 while filling the first trench 31, so as to ensure that the dielectric layer 50 can always cover the gate 41. In summary, after the gate 41 is formed in the gate trench 30, the dielectric layer 50 fills the remaining space of the gate trench 30, which may include only the first trench 31 or may include a portion of the second trench 32 in addition to the first trench 31.

After the gate 41 is formed in the second trench 32, a Chemical Vapor Deposition (CVD) or spin-on deposition process may be used to fill the first trench 31 with a flowable dielectric material at a preset temperature (e.g., 800-1200 ℃) to avoid filling gaps by using the flowability of the flowable dielectric material, and form the dielectric layer 50 that fills the first trench 31 after cooling, where the remaining space of the second trench 32 is also filled with the dielectric material when the second trench 32 is not filled with the gate 41. The flowable dielectric material may be any material capable of flowing at a temperature and capable of functioning as an insulating medium in the art, including, for example, at least one of silicate glass, tetraethyl orthosilicate, spin-on glass (SOG), and a polymeric material, wherein the silicate glass may include at least one of phosphosilicate glass (PSG), borosilicate glass (BSG), and borophosphosilicate glass (BPSG).

Finally, step S4 is performed, as shown in fig. 9, using the dielectric layer 50 as a mask, etching the region of the semiconductor substrate 10 between two adjacent gate trenches 30 to form a contact hole 60, and forming a metal plug 81 in the contact hole 60, as shown in fig. 11.

The specific process of forming the metal plug 81 may be as follows:

Firstly, a metal barrier layer (not shown) is covered on the side wall of the contact hole 60 through the processes of sputtering deposition and the like, wherein the material of the metal barrier layer comprises at least one of titanium Ti, titanium nitride TiN, tantalum Ta and tantalum nitride TaN, and the metal barrier layer can be of a single-layer structure or a laminated structure, and plays a role in isolation and leakage prevention; then, as shown in fig. 10, a metal material 80 such as tungsten or copper is deposited by a sputtering deposition process or the like to fill the contact hole 60, and the excessive metal material 80 above the top surface of the dielectric layer 50 is removed by a CMP process or an etching back process to obtain the metal plug 81.

In addition, referring to fig. 3 and fig. 7, the manufacturing method provided by the embodiment of the invention may further include: a body region 21 and an emitter region 22 are formed by ion implantation for a region of the semiconductor substrate 10 located between two adjacent first trenches 31, the emitter region 22 covering the body region 21, and as shown in fig. 11, the metal plug 81 penetrates the emitter region 22 and extends into the body region 21, and a bottom surface of the emitter region 22 is lower than a top surface of the gate 41.

The body region 21 is also called a base region, and is a body layer for forming a channel, the conductivity type of the body region 21 is opposite to that of the semiconductor substrate 10, the conductivity type of the emitter region 22 is the same as that of the semiconductor substrate 10, and as an example, the semiconductor substrate 10 is an N-type semiconductor substrate, the body region 21 is a P-type doped region, and the emitter region 22 is an n+ emitter region.

The steps of forming the body region 21 and the emitter region 22 may be performed between the step S3 and the step S4, or the step of forming the body region 21 may be performed before the step S1 or between the step S1 and the step S2, and the step of forming the emitter region 22 may be performed between the step S3 and the step S4, so that the present application is not particularly limited, and it is only necessary to ensure that the step of forming the body region 21 and the emitter region 22 is completed before etching the semiconductor substrate 10 to form the contact hole 60. As shown in fig. 3 and 7, the step of forming the body region 21 is performed before the step S1, and the step of forming the emitter region 22 is performed between the step S3 and the step S4.

In addition, as shown in fig. 9, after the contact hole 60 is formed, an inversion ion implantation may be performed at the bottom of the contact hole 60, and a low temperature annealing (i.e., annealing performed at a temperature lower than a preset temperature at which the dielectric layer 50 can flow) may be performed, so that after the implanted heavily doped ions are diffused, an inversion barrier layer 70 is formed at the bottom of the contact hole 60, the inversion barrier layer 70 has the same conductivity type as the body region 21, and the ion doping concentration of the inversion barrier layer 70 is greater than that of the body region 21, so as to reduce the contact resistance of a contact plug formed in the contact hole 60.

Further optionally, as shown in fig. 12, the manufacturing method provided by the embodiment of the present invention may further include: the metal electrode layer 23 is deposited on the surfaces of the metal plug 81, the metal barrier layer and the dielectric layer 50 by sputtering deposition or the like by using aluminum, aluminum-silicon alloy, aluminum-silicon-copper alloy or the like as a target material, and a passivation layer (not shown) is formed on the metal electrode layer 23 by chemical vapor deposition or the like for improving the reliability of the device.

In summary, in the trench type power device structure and the manufacturing method thereof provided in the embodiments of the present invention, a first trench and a second trench extending downward from the bottom of the first trench are formed in a semiconductor substrate, the first trench is used for filling a gate, the second trench is used for filling a dielectric layer, and subsequently, when etching a region between adjacent gate trenches to form a contact hole, the dielectric layer filled in the first trench plays a role of a mask, so that the contact hole can be etched without assistance of a photomask, and then a photomask can be omitted, thereby reducing production cost and improving alignment accuracy; in addition, the first groove comprises a necking section, the width of the necking section from the top to the bottom is gradually reduced, so that the area of an emitter region formed by ion implantation between adjacent gate grooves is increased, and the problem that the normal opening of threshold voltage is influenced due to the fact that the area of the emitter region is too small in the prior art can be solved; further, the side wall of the necking section forms a first angle with the surface of the semiconductor substrate, the side wall of the second groove forms a second angle with the surface of the semiconductor substrate, the first angle is smaller than the second angle, different inclination angles are designed to enable the boundary of the first groove and the second groove to have obvious corners, and when the grid electrode is formed through back etching of the grid electrode material, the corners can play a role in indicating the back etching depth, the back etching precision is improved, and the grid electrode is prevented from protruding out of the second groove to have sharp corners.

It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (13)

1. A trench power device structure comprising:

A semiconductor substrate having a gate trench comprising a first trench and a second trench extending downward from a bottom of the first trench, the first trench comprising a reduced section that gradually decreases in width from top to bottom opening;

a gate formed within the second trench;

the dielectric layer fills the first groove and covers the grid electrode; and

And the metal plug is formed in the region of the semiconductor substrate between two adjacent gate trenches.

2. The trench power device structure of claim 1 wherein the second trench extends downward from a bottom of the reduced section, a sidewall of the reduced section forming an angle with the semiconductor substrate surface of a first angle, a sidewall of the second trench forming an angle with the semiconductor substrate surface of a second angle, the first angle being less than the second angle.

3. The trench power device structure of claim 2 wherein the reduced mouth section extends from a top to a bottom of the first trench.

4. A trench power device structure as claimed in claim 2 or claim 3 wherein the difference between the second angle and the first angle is 6 ° to 7 °.

5. The trench power device structure of claim 4 wherein a difference between a top opening width and a bottom opening width of the first trench is 0.3 μm to 0.32 μm.

6. The trench power device structure of claim 5 wherein a difference between a top opening width and a bottom opening width of the second trench is 0.20 μm to 0.28 μm.

7. The trench power device structure of claim 1 wherein said first trench and said second trench meet at a reference plane, an upper surface of said gate electrode coinciding with said reference plane or an upper surface of said gate electrode being lower than said reference plane.

8. The trench power device structure of claim 1 or 7 wherein a distance between said gate upper surface and said gate trench top opening is 0.4 μm to 0.5 μm.

9. The trench power device structure of claim 1 wherein said semiconductor substrate has a body region and an emitter region in a region between adjacent two of said gate trenches, said emitter region overlying said body region, said metal plug extending through said emitter region and into said body region, a bottom surface of said emitter region being lower than a top surface of said gate.

10. A method of fabricating a trench power device structure, comprising:

Providing a semiconductor substrate, and etching the semiconductor substrate to form a gate trench, wherein the gate trench comprises a first trench and a second trench extending downwards from the bottom of the first trench, the first trench comprises a necking section, and the width of the necking section from the top to the bottom is gradually reduced;

Forming a gate in the second trench;

Filling a dielectric layer in the first groove, wherein the dielectric layer covers the grid electrode; and

And etching the region of the semiconductor substrate between two adjacent gate trenches by taking the dielectric layer as a mask to form a contact hole, and forming a metal plug in the contact hole.

11. The method of claim 10, wherein the second trench extends downward from a bottom of the reduced section, a sidewall of the reduced section forms a first angle with the semiconductor substrate surface, a sidewall of the second trench forms a second angle with the semiconductor substrate surface, and the first angle is less than the second angle.

12. The method of fabricating a trench power device structure of claim 10 wherein the step of forming a gate in said second trench comprises:

And filling a gate material in the gate trench, and etching back the gate material to stop at a reference surface formed by connecting the first trench and the second trench or to stop below the reference surface.

13. The method of manufacturing a trench power device structure of claim 10, further comprising:

And forming a body region and an emitter region on the semiconductor substrate, wherein the body region and the emitter region are formed in a region between two adjacent first trenches through ion implantation, the emitter region covers the body region, the metal plug penetrates through the emitter region and extends into the body region, and the bottom surface of the emitter region is lower than the top surface of the grid electrode.