CN118380336B - Fan-out type semiconductor packaging component and forming method thereof - Google Patents
Fan-out type semiconductor packaging component and forming method thereof Download PDFInfo
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- CN118380336B CN118380336B CN202410808052.5A CN202410808052A CN118380336B CN 118380336 B CN118380336 B CN 118380336B CN 202410808052 A CN202410808052 A CN 202410808052A CN 118380336 B CN118380336 B CN 118380336B
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 97
- 239000002070 nanowire Substances 0.000 claims abstract description 33
- 239000002131 composite material Substances 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 238000000608 laser ablation Methods 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 8
- 238000012545 processing Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 129
- 238000005538 encapsulation Methods 0.000 claims description 22
- 238000002513 implantation Methods 0.000 claims description 20
- -1 oxygen ions Chemical class 0.000 claims description 20
- 239000004033 plastic Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005507 spraying Methods 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000004528 spin coating Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 238000002207 thermal evaporation Methods 0.000 claims description 7
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000001721 transfer moulding Methods 0.000 claims description 5
- 238000000748 compression moulding Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000011282 treatment Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims 1
- 230000006378 damage Effects 0.000 abstract description 3
- 238000011900 installation process Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000002042 Silver nanowire Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a fan-out semiconductor packaging member and a forming method thereof, which relate to the technical field of semiconductors, in the forming method of the fan-out semiconductor packaging member, two inclined side surfaces are formed by processing two side surfaces of a packaging layer, thereby forming a metal nanowire layer/metal layer composite shielding structure, and an ion implantation process is carried out on the peripheral edge area of a chip packaging body, the metal burrs are nitrided or oxidized, the metal burrs can be effectively nitrided or oxidized by controlling the direction of ion implantation, the metal nanowire layer/metal layer composite shielding structure cannot be damaged, and then the burrs can be conveniently removed cleanly when the metal nitride burrs or the metal oxide burrs are removed through a laser ablation process, so that the damage to the circuit of the printed circuit board in the subsequent installation process can be effectively avoided, and the short circuit phenomenon is effectively avoided.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a fan-out semiconductor package and a method for forming the same.
Background
In the packaging process of semiconductor chips, the wafer from the wafer front process is cut into small wafers (semiconductor chips) through a dicing process, then the cut wafers are attached to corresponding positions of corresponding carrier boards through bonding materials, packaging treatment is carried out on packaging substrates, finished product testing is carried out after packaging is completed, and therefore qualified semiconductor packaging components are obtained, and then the qualified semiconductor packaging components are attached to a printed circuit board. In the process of manufacturing the semiconductor packaging member, in order to eliminate electromagnetic interference, a metal shielding layer is generally required to be disposed outside the packaging layer, so that metal burrs are easily generated at the peripheral edges of the semiconductor packaging member when the semiconductor packaging member is removed from the carrier, and then the metal burrs are easily dropped to cause short circuit when the semiconductor packaging member is mounted, and further the metal burrs are required to be removed.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies of the prior art and providing a fan-out type semiconductor package and a method of forming the same.
In order to achieve the above object, the present invention provides a method of forming a fan-out type semiconductor package member, the method of forming a fan-out type semiconductor package member including the steps of: providing a carrier plate, and placing a semiconductor chip on the carrier plate; forming an encapsulation layer on the carrier plate, wherein the encapsulation layer wraps the semiconductor chip; processing two sides of the encapsulation layer to form two inclined sides; then spraying an organic adhesive layer on the packaging layer; then forming a metal nanowire layer/metal layer composite shielding structure on the organic adhesive layer to form a chip package; when the chip packaging body is stripped from the carrier plate, metal burrs are generated at the peripheral edges of the chip packaging body; then, carrying out an ion implantation process on the peripheral edge area of the chip packaging body to enable the metal burrs to be nitrided or oxidized, and then removing the metal nitride burrs or the metal oxide burrs through a laser ablation process to obtain a chip packaging unit; providing a circuit substrate, and arranging a plurality of chip packaging units and conductive columns on the circuit substrate; forming a plastic layer, wherein the plastic layer wraps the chip packaging unit and the conductive column; forming a plurality of grooves on the surface of the plastic layer, arranging the additional chip packaging units in the grooves, and then forming a redistribution layer on the plastic layer.
Preferably, the encapsulation layer is formed by a transfer molding, compression molding, lamination, spin coating or spray coating process.
Preferably, the two sides of the encapsulation layer are subjected to a mechanical cutting process, a chemical mechanical polishing process or a laser ablation process to form two inclined sides.
Preferably, the metal nanowire layer is formed through a spin coating process or a spray coating process, and the metal layer is formed through thermal evaporation, magnetron sputtering, electron beam evaporation or chemical vapor deposition.
Preferably, the metal nanowire layer and the metal layer are alternately formed to obtain a multi-layered stacked composite shielding structure, wherein the alternating times are 2-4 times.
Preferably, the ion implantation process is performed by implanting oxygen ions or nitrogen ions at an implantation dose of 2×10 11-3×1013cm-2 and an implantation energy of 10-60: 60 kev.
Preferably, the circuit substrate is electrically connected to the chip packaging unit.
The invention also provides a fan-out type semiconductor packaging component, which is prepared by adopting the forming method.
Compared with the prior art, the fan-out type semiconductor packaging component and the forming method thereof have the following beneficial effects: in the invention, the two sides of the packaging layer are processed to form two inclined sides, so that the metal nanowire layer/metal layer composite shielding structure is formed. The bonding stability of the metal nanowire layer/metal layer composite shielding structure and the packaging layer is effectively improved, and the metal burrs are nitrided or oxidized through the ion implantation process on the peripheral edge area of the chip packaging body. Through controlling the direction of ion implantation, can effectively make the metal burr by nitridation or oxidation, and can not harm metal nanowire layer/metal layer composite shielding structure, then when removing metal nitride burr or metal oxide burr through laser ablation technology, can make things convenient for the burr to get rid of cleanly, and then can effectively avoid follow-up installation damage printed circuit board's circuit, effectively avoid the short circuit phenomenon.
Drawings
Fig. 1 is a schematic structural view of two inclined sides formed by processing two sides of a package layer in a method for forming a fan-out type semiconductor package member according to the present invention.
Fig. 2 is a schematic structural diagram of a metal nanowire layer/metal layer composite shielding structure formed in the method for forming a fan-out semiconductor package member of the present invention.
Fig. 3 is a schematic structural diagram of a method for forming a fan-out semiconductor package according to the present invention, in which the chip package is peeled from a carrier.
Fig. 4 is a schematic structural diagram of a plurality of chip package units, conductive pillars and a plastic layer disposed on a circuit substrate in the method for forming a fan-out semiconductor package structure of the present invention.
Fig. 5 is a schematic structural diagram of a redistribution layer formed on a plastic layer in a method for forming a fan-out type semiconductor package according to the present invention.
Reference numerals: 100. carrier plate, 101, semiconductor chip, 200, packaging layer, 201, metal nanowire layer/metal layer composite shielding structure, 300, chip package, 2010, metal burrs, 300', chip package unit, 400, circuit substrate, 401, conductive pillars 401, 500, plastic layer, 600, redistribution layer, 601, conductive solder balls.
Detailed Description
For a better understanding of the technical solution of the present invention, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 5, the present embodiment provides a method for forming a fan-out semiconductor package member, the method for forming a fan-out semiconductor package member including the steps of:
as shown in fig. 1, a carrier 100 is provided, and a semiconductor chip 101 is disposed on the carrier 100.
In a specific embodiment, the carrier 100 may be one of a glass carrier, a resin carrier, a metal carrier, or a ceramic carrier, and the semiconductor chip 101 is bonded to the carrier 100 by a temporary bonding material.
As shown in fig. 1, an encapsulation layer 200 is formed on the carrier 100, and the encapsulation layer 200 encapsulates the semiconductor chip 101.
In particular embodiments, the encapsulation layer 200 is formed by a transfer molding, compression molding, lamination, spin coating, or spray coating process. In a specific embodiment, the material of the encapsulation layer 200 is epoxy, and in particular, the encapsulation layer 200 is formed by a transfer molding process.
As shown in fig. 1, both sides of the encapsulation layer 200 are processed to form two inclined sides.
In a specific embodiment, the two sides of the encapsulation layer 200 are subjected to a mechanical cutting process, a chemical mechanical polishing process, or a laser ablation process to form two inclined sides, more specifically, by a laser ablation process to form the inclined sides.
As shown in fig. 2, an organic glue layer is then sprayed on the encapsulation layer 200, and then a metal nanowire layer/metal layer composite shielding structure 201 is formed on the organic glue layer to form a chip package 300.
In a specific embodiment, the metal nanowire layer is formed through a spin coating process or a spray coating process, and the metal layer is formed through thermal evaporation, magnetron sputtering, electron beam evaporation or chemical vapor deposition. In a specific embodiment, the metal nanowire layer and the metal layer are alternately formed to obtain a multi-layer stacked metal nanowire layer/metal layer composite shielding structure, wherein the alternating times are 2-4 times.
In a specific embodiment, the specific process of forming the metal nanowire layer through a spin coating process or a spray coating process is as follows: and spraying a suspension containing metal nanowires, wherein the metal nanowires are silver nanowires or copper nanowires, and the metal nanowires in the metal nanowire layers are mutually interwoven together to form a metal nanowire grid.
In a specific embodiment, in the step of forming the metal layer by thermal evaporation, magnetron sputtering, electron beam evaporation or chemical vapor deposition, the metal layer is made of one or more of copper, aluminum and silver, in a more specific embodiment, a metal shielding layer is formed by thermal evaporation copper plating, and in the process of thermal evaporation copper, the copper layer is attached to the metal nanowire layer, and the metal nanowire layer and the metal layer are formed by alternating 3 times, so as to obtain the metal nanowire layer/metal layer composite shielding structure 201 which is alternately stacked.
As shown in fig. 3, when the chip package 300 is peeled from the carrier 100, metal burrs 2010 are generated at the peripheral edges of the chip package 300.
As shown in fig. 3, an ion implantation process is then performed on the peripheral edge region of the chip package 300 such that the metal burr 2010 is nitrided or oxidized, and then the metal nitride burr or the metal oxide burr is removed by a laser ablation process to obtain a chip package unit 300'.
In a specific embodiment, the implantation ions of the ion implantation process are oxygen ions or nitrogen ions, the implantation dosage of the implantation ions is 2×10 11-3×1013cm-2, and the implantation energy of the oxygen ions is 10-60 kev.
In a specific embodiment, the ion implantation process is adjusted to have an ion implantation dose of 2×1011cm-2、3×1011cm-2、5×1011cm-2、8×1011cm-2、2×1012cm-2、6×1012cm-2、9×1012cm-2、1×1013cm-2 or 3×10 13cm-2, an ion implantation energy of 10kev, 20kev, 30kev, 40kev, 50kev or 60 kev, the implantation ions are oxygen ions or nitrogen ions, and an ion implantation direction is adjusted so that the metal burr 2010 is oxidized or nitrided, and the main structure of the metal nanowire layer/metal layer composite shielding structure 201 is not damaged during the ion implantation process, for example, the implantation ions are oxygen ions, the implantation dose of the oxygen ions is 2×10 12cm-2, the implantation energy of the oxygen ions is 30kev, and thus the metal burr 2010 is completely oxidized, or the implantation ions are for example, the implantation ions are nitrogen ions, the implantation dose of the nitrogen ions is 8×10 11cm-2, and the implantation energy of the nitrogen ions is 20kev, and thus the metal burr 2010 is completely nitrided.
In a specific embodiment, the metal nitride burr or the metal oxide burr is removed by a laser ablation process to obtain the chip packaging unit 300', and the laser ablation process can remove the burr well after the metal burr is nitrided or oxidized.
As shown in fig. 4, a circuit substrate 400 is provided, a plurality of the chip package units 300 'and the conductive pillars 401 are disposed on the circuit substrate 400, and then a plastic layer 500 is formed, and the plastic layer 500 encapsulates the chip package units 300' and the conductive pillars 401.
In a specific embodiment, the chip packaging unit 300' and the conductive pillars 401 are electrically connected to the circuit substrate, and more specifically, the conductive pillars 401 are metal copper pillars, and are formed by an electroplating process.
In a specific embodiment, the plastic layer 500 is then formed by an injection molding process, and the plastic layer 500 may be an epoxy resin.
As shown in fig. 5, a plurality of grooves are formed on the surface of the molding layer 500, additional chip packaging units 300' are disposed in the grooves, and then a redistribution layer 600 is formed on the molding layer 500.
In a specific embodiment, the plurality of grooves are formed by a mechanical cutting or laser ablation process, so that the additional chip packaging units 300 'are disposed, and then a redistribution layer 600 is formed on the molding layer 500, wherein the redistribution layer 600 includes an insulating dielectric layer and a metal wiring layer disposed in the insulating dielectric layer, and the metal wiring layer is electrically connected to the additional chip packaging units 300' and the conductive pillars 401, and further, conductive solder balls 601 are formed on the redistribution layer 600.
As shown in fig. 5, the present invention also proposes a fan-out type semiconductor package member, which is prepared and formed by the above-mentioned forming method.
In other embodiments, the method for forming a fan-out semiconductor package member according to the present invention includes the following steps: a carrier is provided, and a semiconductor chip is placed on the carrier. And forming an encapsulation layer on the carrier plate, wherein the encapsulation layer wraps the semiconductor chip. The two sides of the encapsulation layer are processed to form two sloped sides. And then spraying an organic adhesive layer on the packaging layer. And then forming a metal nanowire layer/metal layer composite shielding structure on the organic adhesive layer to form the chip packaging body. When the chip package is peeled off from the carrier plate, metal burrs are generated at the peripheral edges of the chip package. And then performing an ion implantation process on the peripheral edge area of the chip packaging body to enable the metal burrs to be nitrided or oxidized, and removing the metal nitride burrs or the metal oxide burrs through a laser ablation process to obtain the chip packaging unit. Providing a circuit substrate, and arranging a plurality of chip packaging units and conductive columns on the circuit substrate. And forming a plastic layer, wherein the plastic layer wraps the chip packaging unit and the conductive column. Forming a plurality of grooves on the surface of the plastic layer, arranging the additional chip packaging units in the grooves, and then forming a redistribution layer on the plastic layer.
According to one embodiment of the invention, the encapsulation layer is formed by a transfer molding, compression molding, lamination, spin coating or spray coating process.
According to one embodiment of the invention, the two sides of the encapsulation layer are subjected to a mechanical cutting process, a chemical mechanical polishing process or a laser ablation process to form two inclined sides.
According to one embodiment of the invention, the metal nanowire layer is formed by a spin coating process or a spray coating process, and the metal layer is formed by thermal evaporation, magnetron sputtering, electron beam evaporation or chemical vapor deposition.
According to one embodiment of the invention, the metal nanowire layers and the metal layers are alternately formed to obtain a multi-layer stacked composite shielding structure, wherein the alternating times are 2-4 times.
According to one embodiment of the invention, the implanted ions of the ion implantation process are oxygen ions or nitrogen ions, the implantation dosage of the implanted ions is 2×10 11-3×1013cm-2, and the implantation energy of the oxygen ions is 10-60: 60 kev.
According to an embodiment of the present invention, the circuit substrate is electrically connected to the chip packaging unit.
According to an embodiment of the present invention, the present invention also proposes a fan-out type semiconductor package member, which is prepared and formed by the above-mentioned forming method.
According to the invention, the two sides of the packaging layer are processed to form two inclined sides, so that the metal nanowire layer/metal layer composite shielding structure is formed, the combination stability of the metal nanowire layer/metal layer composite shielding structure and the packaging layer is effectively improved, the metal burrs are nitrided or oxidized through an ion implantation process on the peripheral edge area of the chip packaging body, the metal burrs can be effectively nitrided or oxidized through controlling the ion implantation direction, the metal nanowire layer/metal layer composite shielding structure is not damaged, then the burrs can be conveniently removed cleanly when the metal nitride burrs or metal oxide burrs are removed through a laser ablation process, further, the circuit of a printed circuit board can be effectively prevented from being damaged in the subsequent mounting process, and the short circuit phenomenon is effectively avoided.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A method of forming a fan-out semiconductor package, comprising: the method for forming the fan-out type semiconductor packaging component comprises the following steps:
Providing a carrier plate, and placing a semiconductor chip on the carrier plate;
forming an encapsulation layer on the carrier plate, wherein the encapsulation layer wraps the semiconductor chip;
processing two sides of the encapsulation layer to form two inclined sides;
then spraying an organic adhesive layer on the packaging layer;
then forming a metal nanowire layer/metal layer composite shielding structure on the organic adhesive layer to form a chip package;
when the chip packaging body is stripped from the carrier plate, metal burrs are generated at the peripheral edges of the chip packaging body;
then, carrying out an ion implantation process on the peripheral edge area of the chip packaging body to enable the metal burrs to be nitrided or oxidized, and then removing the metal nitride burrs or the metal oxide burrs through a laser ablation process to obtain a chip packaging unit;
providing a circuit substrate, and arranging a plurality of chip packaging units and conductive columns on the circuit substrate;
forming a plastic layer, wherein the plastic layer wraps the chip packaging unit and the conductive column;
forming a plurality of grooves on the surface of the plastic layer, arranging the additional chip packaging units in the grooves, and then forming a redistribution layer on the plastic layer.
2. The method of forming a fan-out semiconductor package member according to claim 1, wherein: the encapsulation layer is formed by a transfer molding, compression molding, lamination, spin coating, or spray coating process.
3. The method of forming a fan-out semiconductor package member according to claim 1, wherein:
And performing mechanical cutting treatment, chemical mechanical polishing treatment or laser ablation treatment on two side surfaces of the packaging layer to form two inclined side surfaces.
4. The method of forming a fan-out semiconductor package member according to claim 1, wherein: the metal nanowire layer is formed through a spin coating process or a spray coating process, and the metal layer is formed through thermal evaporation, magnetron sputtering, electron beam evaporation or chemical vapor deposition.
5. The method of forming a fan-out semiconductor package member according to claim 4, wherein: and alternately forming the metal nanowire layers and the metal layers to obtain a multi-layer stacked composite shielding structure, wherein the number of the alternation times is 2-4.
6. The method of forming a fan-out semiconductor package member according to claim 1, wherein: the implantation ions of the ion implantation process are oxygen ions or nitrogen ions, the implantation dosage of the implantation ions is 2 multiplied by 10 11-3×1013cm-2, and the implantation energy of the oxygen ions is 10-60 kev.
7. The method of forming a fan-out semiconductor package member according to claim 1, wherein: the circuit substrate is electrically connected with the chip packaging unit.
8. A fan-out semiconductor package, characterized by: the fan-out semiconductor package member formed using the forming method of any one of claims 1 to 7.
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| CN202410808052.5A CN118380336B (en) | 2024-06-21 | 2024-06-21 | Fan-out type semiconductor packaging component and forming method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0471179A1 (en) * | 1990-08-11 | 1992-02-19 | Audi Ag | Process for deburring metal workpiece edges |
| CN108735668A (en) * | 2017-04-21 | 2018-11-02 | 株式会社迪思科 | The manufacturing method of semiconductor packages |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111211079B (en) * | 2019-01-23 | 2020-12-25 | 苏州日月新半导体有限公司 | Method for manufacturing integrated circuit package |
| CN109950159A (en) * | 2019-03-11 | 2019-06-28 | 嘉盛半导体(苏州)有限公司 | A kind of method for packaging semiconductor |
| CN114792634B (en) * | 2022-06-27 | 2022-08-26 | 威海市泓淋电力技术股份有限公司 | Flexible packaging structure and manufacturing method thereof |
| CN118136525B (en) * | 2024-05-08 | 2024-07-23 | 日月新半导体(威海)有限公司 | Semiconductor packaging structure and preparation method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0471179A1 (en) * | 1990-08-11 | 1992-02-19 | Audi Ag | Process for deburring metal workpiece edges |
| CN108735668A (en) * | 2017-04-21 | 2018-11-02 | 株式会社迪思科 | The manufacturing method of semiconductor packages |
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