CN118366934A

CN118366934A - Electronic package and method for manufacturing the same

Info

Publication number: CN118366934A
Application number: CN202310066327.8A
Authority: CN
Inventors: 陈盈儒; 陈敏尧; 张垂弘
Original assignee: Xinai Technology Nanjing Co ltd
Current assignee: Xinai Technology Nanjing Co ltd
Priority date: 2023-01-10
Filing date: 2023-01-19
Publication date: 2024-07-19
Also published as: TW202429658A; TWI832667B

Abstract

The invention provides an electronic package and a manufacturing method thereof. The electronic package comprises an insulating layer on one side of the circuit structure, an ABF is adopted, the electronic element and the functional component are arranged on the ABF of the circuit structure to be electrically connected with the circuit structure, and the electronic element and the functional component are covered by the covering layer to be configured on the covering layer and electrically connected with the circuit structure, so that the utilization rate of the using space of the circuit structure and the number of the element configurations are increased by configuring the functional component and the electronic element, and the integration level of the electronic package is improved.

Description

Electronic package and method for manufacturing the same

Technical Field

The present invention relates to semiconductor packaging technology, and more particularly, to an electronic package capable of preventing warpage during packaging and a method for manufacturing the same.

Background

With the vigorous development of the electronic industry, electronic products tend to be thin, light, short and small in shape, and functional in the development direction of high performance, high function and high speed. Therefore, in order to meet the demands of high Integration and miniaturization (Miniaturization) of semiconductor devices, a package substrate having high-density and fine-pitch circuits is often used in the packaging process.

As shown in fig. 1, a conventional coreless (coreless) package substrate 1 includes a plurality of stacked dielectric layers 11 and a wiring layer 12 provided on each of the dielectric layers 11.

As the functional requirements increase, the number of the circuit layers 12 increases, so that the overall planar package area of the package substrate 1 increases,

However, in the conventional package substrate 1, the semiconductor chip 10 is disposed on the surface, so that the protection of the semiconductor chip 10 is poor, and the semiconductor chip 10 occupies the space on the surface of the package substrate 1, so that it is difficult to reduce the volume of the package substrate 1, and the miniaturization requirement cannot be met.

Furthermore, since the semiconductor chip 10 occupies the space on the surface of the package substrate 1, other devices cannot be disposed on the surface of the package substrate 1, thereby affecting the performance of the electronic product.

Therefore, how to overcome the above problems of the prior art has been an urgent problem.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an electronic package and a method for manufacturing the same, which at least partially solve the problems of the prior art.

The electronic package of the present invention includes: the circuit structure is defined with a first side and a second side which are opposite, and comprises a plurality of insulating layers and a plurality of circuit layers formed on each insulating layer, so that at least one insulating layer corresponding to the first side is defined as a first insulating layer, at least one insulating layer corresponding to the second side is defined as a second insulating layer, the circuit layer combined with the first insulating layer is defined as a first circuit layer, and the circuit layer combined with the second insulating layer is defined as a second circuit layer, wherein the material for forming the first insulating layer is a taste enhancement film (Ajinomoto build-up film) which is different from the material for forming the second insulating layer; an electronic element arranged on the first side of the circuit structure and electrically connected with the first circuit layer; the functional component is arranged on the first side of the circuit structure and is electrically connected with the first circuit layer; the coating layer is arranged on the first side of the circuit structure to coat the electronic element and the functional component, wherein the material for forming the coating layer is different from the material for forming the first insulating layer; and the wiring structure is arranged on the coating layer and is electrically connected with the first circuit layer.

The invention also provides a method for manufacturing the electronic package, which comprises the following steps: providing a carrier having a first surface and a second surface opposite to each other; forming a circuit structure on the first surface and the second surface of the carrier, wherein each circuit structure is defined with a first side and a second side which are opposite, and comprises a plurality of insulating layers and a plurality of circuit layers formed on each insulating layer, so that at least one insulating layer corresponding to the first side is defined as a first insulating layer, at least one insulating layer corresponding to the second side is defined as a second insulating layer, the circuit layer combined with the first insulating layer is defined as a first circuit layer, and the circuit layer combined with the second insulating layer is defined as a second circuit layer, wherein the material for forming the first insulating layer is an Ajinomoto build-up film (Ajinomoto build-up film) which is different from the material for forming the second insulating layer; removing the carrier to make each circuit structure as a coreless layer type packaging substrate; arranging an electronic element and a functional component on a first side of the circuit structure, and respectively electrically connecting the electronic element and the functional component with the first circuit layer; forming a coating layer on the first side of the circuit structure so that the electronic element and the functional component are coated by the coating layer, wherein the material for forming the coating layer is different from the material for forming the first insulating layer; and forming a wiring structure on the coating layer, wherein the wiring structure is electrically connected with the first circuit layer.

In the foregoing electronic package and the method for manufacturing the same, the thermal expansion coefficient of the cladding layer is the largest, and the thermal expansion coefficient of the second insulating layer is the smallest among the cladding layer, the first insulating layer and the second insulating layer.

In the foregoing electronic package and the method for manufacturing the same, the functional component includes a plurality of passive components stacked on each other.

In the foregoing electronic package and the method for manufacturing the same, a height of the functional component relative to the first side is greater than a height of the electronic component relative to the first side.

In the foregoing electronic package and the method for manufacturing the same, the first circuit layer is embedded in the first insulating layer, and the first insulating layer and the first circuit layer are coplanar on the first side.

Therefore, the electronic package and the manufacturing method thereof of the invention not only enable the electronic element to have better protection property by embedding the electronic element in the coating layer, but also save the use space on the surface of the coating layer, so that compared with the prior art, the invention can reduce the volume of the electronic package so as to meet the miniaturization requirement.

Furthermore, the functional component is formed in a stacking manner without dispersing a plurality of passive elements on the surface of the circuit structure, so that the utilization rate of the use space of the first side of the circuit structure and the number of the element arrangement are increased, and the electronic package has better energy storage exchange performance and is further beneficial to improving the integration level of the electronic package.

In addition, the circuit structure is formed on two opposite sides of the bearing piece at the same time, so that warping generated by stress in each insulating layer is offset, and the insulating layer at the outermost side of the circuit structure is kept in a flat state, therefore, in the subsequent process of configuring the electronic element and the functional component, the electronic element and the functional component can be ensured to be effectively aligned and connected with the first circuit layer, and the yield of the electronic package piece is improved.

In addition, the second insulating layer, the first insulating layer and the coating layer are configured in a way of small CTE from small to large on the basis of the direction of the second side of the circuit structure towards the first side, so that the electronic package can be effectively prevented from deforming and warping after the electronic package is subjected to a plurality of environmental temperature change processes.

Drawings

Fig. 1 is a cross-sectional view of a conventional package substrate.

Fig. 2A to 2E are schematic cross-sectional views illustrating a manufacturing method of the electronic package of the present invention.

Fig. 2C-1 is a schematic cross-sectional view of a portion of the process of fig. 2C.

Fig. 2F is a schematic cross-sectional view of the subsequent process of fig. 2E.

The reference numerals are as follows:

1 packaging substrate

10 Semiconductor chip

11 Dielectric layer

12 Line layer

2 Electronic package

21 Line structure

21A first side

21B second side

210 First insulating layer

211 First circuit layer

212 Second insulating layer

213 Second circuit layer

23 Wiring structure

230 Wiring layer

231 Conductive post

24 Solder ball

25 Coating layer

25A,4a surface

26,28 Insulating protective layer

260,280:

27 conductive element

29 Electronic device

30 Electronic component

30A action surface

30B inactive face

300 Electrode pad

31,41 Conductive bump

4 Functional component

40 Passive element

400 Contact point

42 Dielectric layer

8 Bearing plate

80 Adhesive tape

9 Bearing part

9A first surface

9B second surface

90 Plate body

91 Metal layer

92 Stripping layer

D, t, thickness

H1, h2 height

Detailed Description

Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the present disclosure, as illustrated by the following specific examples.

It should be understood that the structures, proportions, sizes, etc. shown in the drawings attached hereto are for the purpose of understanding and reading only and are not intended to limit the scope of the invention, which is defined by the appended claims, but rather by the appended claims. Also, the terms "upper", "first", "second", "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the invention, as such changes or modifications in the relative relationship may be made without materially altering the technical context.

Fig. 2A to 2E are schematic cross-sectional views illustrating a manufacturing method of the electronic package 2 according to the present invention.

As shown in fig. 2A, a carrier 9 is provided, which has a first surface 9a and a second surface 9b opposite to each other, so that the circuit structure 21 is symmetrically formed on the first surface 9a and the second surface 9b of the carrier 9.

In this embodiment, the carrier 9 is a temporary carrier, which may be a plate having metal layers on opposite sides, such as a copper foil substrate, and the first surface 9a and the second surface 9b of the plate 90 are sequentially formed with a release layer 92 and a metal layer 91, so that the circuit structure 21 is formed on the metal layer 91.

Furthermore, each of the circuit structures 21 defines a first side 21a and a second side 21b opposite to each other, and includes a plurality of insulating layers and a plurality of circuit layers formed on each of the insulating layers, so that a portion of the circuit layers of the circuit structures 21 are exposed from the insulating layers of the second side 21 b. For example, the insulating layer is a dielectric layer such as Ajinomoto build-up film (ABF), poly-p-diazole benzene (Polybenzoxazole PBO), polyimide (PI), prepreg with glass fiber (Prepreg PP) or other dielectric materials.

Further, the insulating layers may be made of different materials, such that at least one ABF layer corresponding to the first side 21a is defined as a first insulating layer 210, and at least one (three layers as shown) PP layer corresponding to the second side 21b is defined as a second insulating layer 212, such that a line layer combined with the first insulating layer 210 is defined as a first line layer 211, and a line layer combined with the second insulating layer 212 is defined as a second line layer 213.

In addition, build-up process is used to form the circuit layer by electroplating metal (e.g., copper) or other means. It should be understood that, by using the build-up method, multiple insulating layers can be added to the multiple circuit structures 21 as required to fabricate multiple circuit layers.

Therefore, by using the via material without glass fiber as the first insulating layer 210 (e.g., ABF), it is advantageous to form finer laser blind vias (vertical lines) or smaller fine line/fine pitch (L/S) wirings (e.g., the first line layer 211 embedded in the first insulating layer 210) due to no glass fiber limitation, so as to increase the wiring density.

As shown in fig. 2B, the plate body 90 and the metal layer 91 are separated by the peeling layer 92, and the metal layer 91 is removed by etching to obtain a plurality of circuit structures 21, so that each circuit structure 21 is used as a coreless package substrate.

In this embodiment, after the metal layer 91 is removed, the first circuit layer 211 on the first side 21a of the circuit structure 21 is exposed from the first insulating layer 210. For example, the first insulating layer 210 and the first circuit layer 211 are coplanar on the first side 21 a.

Furthermore, the circuit structure 21 is fabricated on the carrier 9, and after the carrier 9 is removed, the circuit structure 21 is in a warped (warpage) state according to uneven force distribution, such as in a warped direction with left and right sides warped upward or bent downward, so that the circuit structure 21 is smiling or crying. Therefore, the first insulating layer 210 and the second insulating layer 212 are made of different materials, so as to disperse stress and avoid stress concentration, and thus the warpage of the circuit structure 21 can be greatly reduced after the carrier 9 is removed.

As shown in fig. 2C, at least one electronic component 30 and at least one functional device 4 are separately disposed on the first sides 21a of the plurality of circuit structures 21, such that the electronic component 30 and the functional device 4 are electrically connected to the first circuit layer 211.

In the present embodiment, the electronic component 30 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. For example, if the electronic device 30 is a semiconductor chip, it has an opposite active surface 30a and a non-active surface 30b, the active surface 30a has a plurality of electrode pads 300, which are electrically connected to the first circuit layer 211 by a plurality of conductive bumps 31 in a manner that the active surface 30a faces downward (e.g. flip-chip manner); or the electronic device 30 may be electrically connected to the first circuit layer 211 by a plurality of bonding wires (not shown); alternatively, the electronic device 30 may directly contact the first circuit layer 211. However, the manner of electrically connecting the electronic device 30 to the first circuit layer 211 is not limited to the above.

Furthermore, the functional device 4 is an electronic module, which is electrically connected to the first circuit layer 211 through a plurality of conductive bumps 41. For example, the functional component 4 includes a plurality of electronic components, such as passive components 40 (also active chips like electronic components 30) shown in fig. 2C-1, which are stacked on each other with contacts 400 via conductive bumps 41, so that a height h1 of the functional component 4 relative to the first side 21a is greater than a height h2 of the electronic components 30 relative to the first side 21 a. It should be understood that the height h1 of the functional component 4 relative to the first side 21a may also be equal to or smaller than the height h2 of the electronic component 30 relative to the first side 21 a.

In addition, the process of the functional component 4 is to attach at least one passive component 40 to the carrier plate 8 by using an adhesive tape 80, wherein the thickness d of the passive component is about 125-200 micrometers (um), such as a Multi-LAYER CERAMIC Capacitor (MLCC) as shown in fig. 2C-1, then coat the passive component 40 with a dielectric layer 42 such as ABF, and expose the contact 400 to the dielectric layer 42 (such as a laser opening) to form a conductive bump 41 in the opening, stack another passive component 40 through the conductive bump 41, and coat the other passive component 40 with another dielectric layer 42 such as ABF. Finally, the carrier plate 8 and the adhesive tape 80 are removed. It should be understood that the number of stacks of the passive components 40 can be designed according to the requirement, and the thickness t of the dielectric layer 42 and the thickness d of the passive components 40 are not particularly limited, for example, if the specifications of 0.25 mm long, 0.125 mm wide and 0.125 mm thick of the passive components 40 are adopted, ABF with a thickness t of 150 μm is selected as the dielectric layer 42.

In addition, before the electronic component 30 and the functional component 4 are disposed, an insulating protection layer 26 such as a solder mask layer may be formed on the first side 21a of the circuit structure 21, and a plurality of openings 260 exposing the first circuit layer 211 are formed on the insulating protection layer 26 for aligning and combining the plurality of conductive bumps 31,41.

As shown in fig. 2D, a coating layer 25 is formed on the first side 21a of each circuit structure 21, so that the electronic component 30 and the functional device 4 are embedded in the coating layer 25.

In the present embodiment, the coating layer 25 contacts the first side 21a of the circuit structure 21 or the insulating protection layer 26, and covers the periphery of the electronic component 30, and also surrounds and covers the functional device 4.

Furthermore, the material forming the cladding layer 25 is an insulating material, such as Polyimide (PI), dry film (dry film), epoxy molding compound (epoxy molding compound, abbreviated as EMC) or other packaging material, which may be formed on the first side 21a of the circuit structure 21 by pressing (lamination) or molding (molding).

The material forming the clad layer 25 is EMC, the Coefficient of Thermal Expansion (CTE) thereof is 10 to 25ppm/°c, the material forming the first insulating layer 210 is ABF, the CTE thereof is 10 to 17ppm/°c, and the material forming the second insulating layer 212 is prepreg (PP), the CTE thereof is 10ppm/°c, so that the CTE of the clad layer 25 is the largest and the CTE of the second insulating layer 212 is the smallest among the three.

In addition, the functional component 4 or the electronic component 30 may be exposed on the surface 25a of the coating layer 25. For example, a part of the material of the cover layer 25, or even a part of the material of the functional element 4 (or the electronic element 30), such as a part of the material of the dielectric layer 42, may be removed by a leveling process, such as polishing, so that the surface 25a of the cover layer 25 is flush with the surface 4a of the functional element 4 (or the inactive surface 30b of the electronic element 30), so that the functional element 4 (or the electronic element 30) is exposed on the surface 25a of the cover layer 25.

As shown in fig. 2E, a wiring structure 23 electrically connected to the first circuit layer 211 is formed on the cladding layer 25 to obtain an electronic package 2.

In this embodiment, the wiring structure 23 includes a wiring layer 230 formed on the cladding layer 25 and at least one conductive pillar 231 formed in the cladding layer 25 to electrically connect the wiring layer 230 and the first wiring layer 211. For example, a via may be formed in the cladding layer 25, and then a metal material may be electroplated or deposited in the via to form the conductive pillar 231. It should be understood that the wiring structure 23 can be formed with multiple insulating layers and wiring layers combined with the insulating layers on the surface 25a of the cladding layer 25 by build-up method according to need, and is not limited to the single-layer wiring layer 230 in the figure.

Furthermore, the wiring layer 230 may contact the surface 4a of the functional component 4 to facilitate heat dissipation of the functional component 4.

In addition, an insulating protection layer 28 such as a solder mask layer may be formed on the cladding layer 25, and a plurality of openings 280 exposing the outermost wiring layer 230 may be formed on the insulating protection layer 28.

In addition, another insulating protection layer 28, such as a solder mask, may be formed on the second side 21b of the circuit structure 21, and a plurality of openings 280 exposing the second circuit layer 213 may be formed on the insulating protection layer 28.

Therefore, the electronic device 30 is embedded in the coating layer 25, so that the electronic device 30 has better protection and the space on the surface 25a of the coating layer 25 is saved, and compared with the prior art, the volume of the electronic package 2 is reduced, so as to meet the miniaturization requirement.

Furthermore, the functional components 4 are formed in a stacked manner without dispersing a plurality of passive components 40 on the surface of the circuit structure 21, so as to increase the utilization rate of the usage space of the first side 21a of the circuit structure 21 and the number of components, thereby having better energy storage exchange performance and further being beneficial to improving the integration level of the electronic package 2.

In addition, the circuit structures 21 are formed on opposite sides of the carrier 9 at the same time to offset the warpage generated by the stress in each insulating layer, so that the outermost insulating layer of the circuit structures 21 is kept in a flat state, and therefore, in the subsequent process of disposing the electronic component 30 and the functional component 4, the electronic component 30 and the functional component 4 can be ensured to be effectively aligned and connected with the first circuit layer 211, so as to improve the yield of the electronic package 2.

Further, after the carrier 9 is removed, the circuit structure 21 uses the PP layer (the second insulating layer 212) with relatively high rigidity as a carrier substrate, so as to provide stress support for the cladding layer 25 and the first insulating layer 210 when forming the cladding layer 25, thereby avoiding warpage, deformation or other adverse phenomena.

In addition, the second insulating layer 212, the first insulating layer 210 and the cladding layer 25 are disposed in a manner of CTE from small to large in the direction of the second side 21b of the circuit structure 21 toward the first side 21a, so as to effectively avoid deformation and warpage of the electronic package 2 after the electronic package 2 is subjected to multiple environmental temperature variation processes.

As shown in fig. 2F, an electronic device 29, such as an antenna element, a chip package module or other electronic structure, is attached to the wiring layer 230 in the opening 280 via a plurality of conductive elements 27, such as solder material.

In this embodiment, a circuit board (not shown) may be disposed on the second circuit layer 213 in the opening 280 through a plurality of solder balls 24.

Therefore, since the electronic device 30 such as a semiconductor chip is not required to be disposed in the space on the surface 25a of the cladding layer 25, a larger area of the antenna device (such as the electronic device 29) can be used to provide better signal receiving and transmitting performance, so that the signal strength of the electronic device 30 is better.

The present invention also provides an electronic package 2, comprising: a circuit structure 21, at least one electronic component 30 and at least one functional component 4 arranged on the circuit structure 21, a coating layer 25 and a wiring structure 23.

The circuit structure 21 defines a first side 21a and a second side 21b opposite to each other, and includes a plurality of insulating layers and a plurality of circuit layers formed on each insulating layer, such that at least one insulating layer corresponding to the first side 21a is defined as a first insulating layer 210, at least one insulating layer corresponding to the second side 21b is defined as a second insulating layer 212, the circuit layer combined with the first insulating layer 210 is defined as a first circuit layer 211, and the circuit layer combined with the second insulating layer 212 is defined as a second circuit layer 213, wherein the material forming the first insulating layer 210 is a flavored pixel build-up film (Ajinomoto build-up film) different from the material forming the second insulating layer 212.

The electronic component 30 is disposed on the first side 21a of the circuit structure 21 and electrically connected to the first circuit layer 211.

The functional component 4 is disposed on the first side 21a of the circuit structure 21 and electrically connected to the first circuit layer 211.

The coating layer 25 is disposed on the first side 21a of the circuit structure 21 to coat the electronic component 30 and the functional component 4, wherein a material of the coating layer 25 is different from a material of the first insulating layer 210.

The wiring structure 23 is disposed on the cladding layer 25 and electrically connected to the first circuit layer 211.

In one embodiment, among the cladding layer 25, the first insulating layer 210 and the second insulating layer 212, the thermal expansion coefficient of the cladding layer 25 is the largest, and the thermal expansion coefficient of the second insulating layer 212 is the smallest.

In one embodiment, the functional element 4 comprises a plurality of passive elements 40 stacked on top of each other.

In one embodiment, the height h1 of the functional element 4 relative to the first side 20a is greater than the height h2 of the electronic component 30 relative to the first side 20 a.

In one embodiment, the first circuit layer 211 is embedded in the first insulating layer 210, and the first insulating layer 210 and the first circuit layer 211 are coplanar on the first side 20 a.

In summary, the electronic package and the manufacturing method thereof of the present invention not only enable the electronic component to have better protection, but also save the space on the surface of the coating by embedding the electronic component in the coating, so the present invention can reduce the volume of the electronic package to meet the miniaturization requirement.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications to the above would be obvious to those of ordinary skill in the art, without departing from the spirit and scope of the present invention. The scope of the invention is therefore intended to be indicated by the appended claims.

Claims

1. An electronic package, comprising:

the circuit structure is defined with a first side and a second side which are opposite, and comprises a plurality of insulating layers and a plurality of circuit layers formed on each insulating layer, at least one insulating layer corresponding to the first side is defined as a first insulating layer, at least one insulating layer corresponding to the second side is defined as a second insulating layer, the circuit layer combined with the first insulating layer is defined as a first circuit layer, the circuit layer combined with the second insulating layer is defined as a second circuit layer, wherein the material for forming the first insulating layer is a taste-enhancing film, and the material for forming the second insulating layer is different from the material for forming the second insulating layer;

An electronic element arranged on the first side of the circuit structure and electrically connected with the first circuit layer;

the functional component is arranged on the first side of the circuit structure and is electrically connected with the first circuit layer;

The coating layer is arranged on the first side of the circuit structure to coat the electronic element and the functional component, wherein the material for forming the coating layer is different from the material for forming the first insulating layer; and

The wiring structure is arranged on the coating layer and is electrically connected with the first circuit layer.

2. The electronic package of claim 1, wherein the thermal expansion coefficient of the cladding layer is the largest and the thermal expansion coefficient of the second insulating layer is the smallest among the cladding layer, the first insulating layer and the second insulating layer.

3. The electronic package of claim 1, wherein the functional component comprises a plurality of passive components stacked on top of each other.

4. The electronic package of claim 1, wherein the height of the functional component relative to the first side is greater than the height of the electronic component relative to the first side.

5. The electronic package of claim 1, wherein the first circuit layer is embedded in the first insulating layer, and the first insulating layer and the first circuit layer are coplanar on the first side.

6. A method of manufacturing an electronic package, comprising:

providing a carrier having a first surface and a second surface opposite to each other;

Forming a circuit structure on the first surface and the second surface of the carrier, wherein the circuit structure is defined with a first side and a second side which are opposite, and comprises a plurality of insulating layers and a plurality of circuit layers formed on each insulating layer, at least one insulating layer corresponding to the first side is defined as a first insulating layer, at least one insulating layer corresponding to the second side is defined as a second insulating layer, so that the circuit layer combined with the first insulating layer is defined as a first circuit layer, and the circuit layer combined with the second insulating layer is defined as a second circuit layer, wherein the material for forming the first insulating layer is a material of a taste enhancement film which is different from the material for forming the second insulating layer;

Removing the carrier to make each circuit structure as a coreless layer type packaging substrate;

Arranging an electronic element and a functional component on a first side of the circuit structure, and enabling the electronic element and the functional component to be respectively and electrically connected with the first circuit layer;

Forming a coating layer on the first side of the circuit structure so that the electronic element and the functional component are coated by the coating layer, wherein the material for forming the coating layer is different from the material for forming the first insulating layer; and

Forming a wiring structure on the cladding layer, and electrically connecting the wiring structure to the first circuit layer.

7. The method of claim 6, wherein the thermal expansion coefficient of the cladding layer is the largest and the thermal expansion coefficient of the second insulating layer is the smallest among the cladding layer, the first insulating layer and the second insulating layer.

8. The method of claim 6, wherein the functional component comprises a plurality of passive components stacked on top of each other.

9. The method of claim 6, wherein the functional element has a height relative to the first side that is greater than a height of the electronic component relative to the first side.

10. The method of claim 6, wherein the first circuit layer is embedded in the first insulating layer and the first circuit layer are coplanar on the first side.