CN117766413A

CN117766413A - Manufacturing method of electronic package and bearing structure thereof

Info

Publication number: CN117766413A
Application number: CN202211258290.0A
Authority: CN
Inventors: 张垂弘; 陈敏尧; 林松焜
Original assignee: Xinai Technology Nanjing Co ltd
Current assignee: Xinai Technology Nanjing Co ltd
Priority date: 2022-09-19
Filing date: 2022-10-13
Publication date: 2024-03-26
Also published as: TWI830388B

Abstract

The invention provides a manufacturing method of an electronic package and a bearing structure thereof. The bearing structure comprises a bearing plate and a circuit layer, wherein the bearing plate comprises a plate body, and a first metal layer, a second metal layer and a third metal layer which are sequentially combined on the plate body, so that the circuit layer is combined on the third metal layer, and the bearing structure does not need to use a solder mask layer, so that the related process for manufacturing the solder mask layer is not needed, and the manufacturing cost is effectively reduced.

Description

Manufacturing method of electronic package and bearing structure thereof

Technical Field

The present invention relates to semiconductor packaging technology, and more particularly, to a method for manufacturing an electronic package and a carrier structure thereof.

Background

The conventional semiconductor package using the lead frame as the chip carrier has various types and kinds, such as the conventional quadrilateral planar package structure (Quad Flat package, QFP for short), and along with the vigorous development of the electronic industry, the electronic products also gradually move toward the trend of multiple functions and high performance, and also move toward the development of miniaturization (miniaturization). Therefore, a new Quad Flat Non-leaded (QFN) package structure has been developed.

Fig. 1A is a schematic cross-sectional view of a conventional QFN semiconductor package 1. As shown in fig. 1A, a metal layer is formed on a carrier (not shown), and then etched to form a circuit layer 10, and a surface treatment layer 100 is formed on the circuit layer 10.

Next, the semiconductor chip 11 is disposed on the die pad 10b of the circuit layer 10 through the adhesive 12, and the semiconductor chip 11 is electrically connected to the electrical contact pad 10a of the circuit layer 10 through a plurality of bonding wires 110.

Then, forming a molding compound 13 on the circuit layer 10 to cover the semiconductor chip 11 and the bonding wires 110; finally, the carrier plate is removed to expose the circuit layer 10.

However, in the conventional semiconductor package 1, the circuit layer 10 is exposed from the encapsulant 13, so that the copper material on the side surface of the circuit layer 10 is not protected, and is easily oxidized, resulting in poor electrical surface and power consumption between the semiconductor chip 11 and the circuit layer 10.

Furthermore, although the solder mask layer 14 can be formed around the circuit layer 10, as shown in fig. 1B, to prevent the oxidation of the circuit layer 10, related processes, such as coating solder mask material, pre-baking, developing, baking, ultraviolet (UV) curing, etc. are required, which results in complicated process steps, thus greatly increasing the manufacturing cost, and failing to meet the requirements of light weight and thinness due to the increased weight of the solder mask layer 14.

In addition, since the circuit layer 10 is formed by etching a metal layer, only the circuit layer 10 having a line width/line spacing of 50/50 micrometers (um) can be manufactured, and thus the conventional QFN semiconductor package 1 is difficult to meet the requirements of fine circuits, and thus cannot be provided with more circuits, resulting in no improvement of functions.

Therefore, how to overcome the above-mentioned problems in the prior art has become a major challenge in the industry.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing an electronic package and a carrier structure thereof, which at least partially solve the problems of the prior art.

The bearing structure of the invention comprises: the bearing plate comprises a plate body, a first metal layer combined on one side of the plate body, a second metal layer combined on the first metal layer and a third metal layer combined on the second metal layer; and a circuit layer bonded to the third metal layer.

In the foregoing bearing structure, the first metal layer is further bonded to the other side of the board, so that the first metal layer is bonded to both opposite sides of the board.

In the foregoing carrier structure, the first metal layer is a copper layer.

In the foregoing carrier structure, the second metal layer is a copper layer.

In the foregoing carrier structure, the third metal layer is a copper layer.

The foregoing carrier structure further includes a surface treatment layer formed on the circuit layer.

The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: providing at least one bearing structure; arranging an electronic element on the circuit layer so that the electronic element is electrically connected with the circuit layer; forming a packaging layer on the third metal layer so that the packaging layer covers the electronic element; and removing the bearing plate to expose the circuit layer outside the packaging layer.

In the foregoing manufacturing method, the circuit layer has a die pad and a plurality of electrical contact pads, so that the electronic device is disposed on the die pad and electrically connected to the plurality of electrical contact pads.

In the foregoing manufacturing method, the electronic device is electrically connected to the circuit layer by a wire bonding method.

In the foregoing manufacturing method, the electronic component is further disposed on the circuit layer on two opposite sides of the carrier by overlapping the two carrier plates with each other in a manner that the plate bodies thereof face each other to form a carrier, and the opposite sides of the carrier are the third metal layers.

Therefore, in the manufacturing method of the electronic package and the carrying structure thereof, the carrying structure is mainly used without using a solder mask layer, so that the related process for manufacturing the solder mask layer is not needed, and compared with the prior art, the carrying structure of the invention can shorten the process steps by nearly 50%, thereby effectively reducing the manufacturing cost, and can greatly reduce the weight so as to meet the requirements of lightness, thinness and shortness.

Furthermore, the third metal layer is used as a seed crystal layer of the bearing structure, so that the circuit layer with the wire width/wire distance of 10/10 micrometers (um) can be manufactured, and the circuit layer of the bearing structure can meet the requirement of fine circuits compared with the mode of etching the metal layer in the prior art.

In addition, the manufacturing method of the electronic packaging piece of the invention enables the packaging layer to effectively protect the side copper material of the circuit layer by embedding the circuit layer in the packaging layer without protruding the packaging layer so as to prevent the circuit layer from oxidation, so that compared with the prior art, the electronic packaging piece of the invention can lead the electronic component and the circuit layer to generate better electrical performance and power consumption.

Drawings

Fig. 1A and 1B are schematic cross-sectional views of different QFN semiconductor packages in the prior art.

Fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing a carrier structure according to the present invention.

Fig. 3A to 3C are schematic cross-sectional views illustrating a manufacturing method of the electronic package of the present invention.

The reference numerals are as follows:

1. semiconductor package

10,20 Circuit layer

10a,201 electrical contact pad

10b,200 die pad

100,21 surface treatment layer

11. Semiconductor chip

110. Bonding wire

12. Adhesive glue

13. Packaging colloid

14. Solder mask layer

2. Bearing structure

3. Electronic package

31. Electronic component

31a working face

31b non-active surface

310. Conducting wire

32. Bonding layer

33. Encapsulation layer

33a first surface

33b second surface

34. Conductive element

81. First resistive layer

810. An opening

82. Second resist layer

9. Bearing piece

9a first side

9b second side

90. Bearing plate

900. Board body

901. A first metal layer

902. Second metal layer

903. Third metal layer

t, d thickness

Detailed Description

Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the present disclosure, as illustrated by the following specific examples.

It should be understood that the structures, proportions, sizes, etc. shown in the drawings attached hereto are for the purpose of understanding and reading only and are not intended to limit the scope of the invention, which is defined by the appended claims, but rather by the appended claims. Also, the terms "upper", "first", "second", "third", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the invention as embodied in any manner or by any combination of relative terms.

Fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing the carrier structure 2 according to the present invention.

As shown in fig. 2A, a carrier 9 having opposite first and second sides 9a and 9b is provided, which includes two carrier plates 90 stacked on each other, wherein the carrier plates 90 include a plate body 900, a first metal layer 901 bonded on one side of the plate body 900, a second metal layer 902 bonded on the first metal layer 901, and a third metal layer 903 bonded on the second metal layer 902, such that the plurality of carrier plates 90 are bonded to each other with the plate bodies 900 facing each other, and the first and second sides 9a and 9b of the carrier 9 are the third metal layers 903.

In this embodiment, the carrier 90 is a temporary carrier, and the board body 900 may be an organic polymeric board or a copper foil substrate such as bismaleimide/triazazine (Bismaleimide triazine, BT for short). For example, another first metal layer 901 is bonded on the other side of the board body 900, so that the plurality of first metal layers 901 on the opposite sides of the board body 900 can be used as a copper foil substrate, i.e. the first metal layer 901 is a copper layer (or copper foil). Further, the plurality of carrier plates 90 are bonded to each other with the first metal layer 901 thereof.

Furthermore, the second metal layer 902 may also be a copper layer, and the third metal layer 903 may be a seed layer, which may be made by sputtering copper.

As shown in fig. 2B, a first resist layer 81 having a plurality of openings 810 is formed on the first side 9a and the second side 9B of the carrier 9 by a patterning process, so as to expose a portion of the surface of the third metal layer 903.

As shown in fig. 2C, a circuit layer 20 is formed on the third metal layer 903 in the opening 810, and the circuit layer 20 has at least one die pad 200 and a plurality of electrical contact pads 201.

In this embodiment, the die pad 200 and the plurality of electrical contact pads 201 are separated from each other, and the material forming the circuit layer 20 is copper. For example, the circuit layer 20 may be fabricated by sputtering (sputtering), vapor deposition (vapor deposition), electroplating, electroless plating, chemical plating, or film deposition (patterning), but the invention is not limited thereto.

As shown in fig. 2D, a second resist layer 82 is formed on the die pad 200 to form a surface treatment layer 21 on other surfaces of the circuit layer 20 (e.g., the electrical contact pad 201).

In this embodiment, the material forming the surface treatment layer 21 includes electroplated nickel/gold, electroless nickel/gold, nickel-plated Immersion gold (ENIG), nickel-plated palladium Immersion gold (ENEPIG), electroless Tin plating (im, tin) or organic solder resist (Organic Solderability Preservative, OSP for short). Preferably, the surface treatment layer 21 is a gold layer.

As shown in fig. 2E, the first resist layer 81 and the second resist layer 82 are removed to expose the die pad 200.

As shown in fig. 2F, the two carrier plates 90 of the carrier 9 are separated from each other to obtain a plurality of carrier structures 2.

In this embodiment, the carrier structure 2 includes a carrier 90 (which includes a board body 900, a first metal layer 901, a second metal layer 902 and a third metal layer 903 sequentially disposed on one side of the board body), and a circuit layer 20 disposed on the third metal layer 903.

Furthermore, another first metal layer 901 may be disposed on the other side of the board 900, and the surface treatment layer 21 is formed on a portion of the surface of the circuit layer (such as the electrical contact pad 201).

Therefore, the carrier structure 2 of the present invention does not need to use a solder mask layer, or even a dielectric material such as pre-preg (PP) or Ajinomoto build-up film (ABF), and thus related processes such as coating the solder mask material, pre-baking, developing, baking, and Ultraviolet (UV) curing are not needed, so that compared with the prior art, the carrier structure 2 of the present invention can shorten the process steps by about 50%, so as to effectively reduce the manufacturing cost, and can greatly reduce the weight, so as to meet the requirements of light weight and shortness.

Furthermore, the carrier structure 2 is used as a seed layer to electroplate the line layer 20 with a line width/line spacing of 10/10 micrometers (um) in the opening 810 of the patterned first resist layer 81 by using the third metal layer 903, so that the carrier structure 2 can make the line layer 20 meet the requirements of thin line specifications compared with the prior art manner of etching metal layers.

In addition, by overlapping the bearing plates 90 to form the sandwich-shaped bearing piece 9, the bearing piece 9 can produce two groups of bearing structures 2 at a time in the mass production process, so the manufacturing method of the bearing structure 2 can improve the production benefit by 40 to 50 percent.

Fig. 3A to 3C are schematic cross-sectional views illustrating a manufacturing method of the electronic package 3 according to the present invention. In the present embodiment, the carrier structure 2 shown in fig. 2F is used.

As shown in fig. 3A, a carrier structure 2 is provided to dispose an electronic device 31 on the die pad 200, and the electronic device 31 is electrically connected to the electrical contact pad 201.

In the present embodiment, the electronic component 31 is an active component, a passive component or a combination of the two components, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic device 31 is a semiconductor chip, which has an active surface 31a and a non-active surface 31b opposite to each other, the electronic device 31 is adhered to the die pad 200 by a bonding layer 32, such as a glue, on the non-active surface 31b, and the active surface 31a has a plurality of electrode pads (not shown) electrically connected to the plurality of electrical contact pads 201 by a plurality of wires 310 in a wire bonding manner.

As shown in fig. 3B, an encapsulation layer 33 is formed on the third metal layer 903 of the carrier 2, so that the encapsulation layer 33 encapsulates the electronic component 31 and the conductive wires 310.

In this embodiment, the encapsulation layer 33 defines a first surface 33a and a second surface 33b opposite to each other, so that the encapsulation layer 33 is bonded to the third metal layer 903 with the first surface 33a.

Furthermore, the encapsulation layer 33 is an encapsulant such as Polyimide (PI), dry film (dry film), epoxy (epoxy) or molding compound (molding compound), and can be formed on the carrier structure 2 by lamination or molding, but is not limited to the above materials.

As shown in fig. 3C, the carrier 90 is removed, so that the circuit layer 20 is exposed on the first surface 33a of the encapsulation layer 33.

In this embodiment, the carrier plate is removed by sequentially removing the plate body 900, the first metal layer 901, the second metal layer 902 and the third metal layer 903. For example, the third metal layer 903 is removed by etching, the circuit layer 20 is slightly etched, so that the exposed surface of the circuit layer 20 is slightly recessed into the first surface 33a of the encapsulation layer 33; alternatively, the third metal layer 903 is removed by polishing, and a leveling operation may be performed, so that the exposed surface of the circuit layer 20 is flush with the first surface 33a of the encapsulation layer 33.

In a subsequent process, conductive elements 34 such as solder balls may be formed on the exposed surface of the circuit layer 20 for the electronic package 3 to be mounted on a circuit board.

Therefore, in the manufacturing method of the electronic package 3 of the present invention, the circuit layer 20 is embedded in the packaging layer 33 without protruding the first surface 33a of the packaging layer 33, so that the packaging layer 33 effectively protects the side copper material of the circuit layer 20 to avoid oxidation of the circuit layer 20, and compared with the prior art, the electronic package 3 of the present invention can generate better electrical performance (electrical performance) and power consumption (power dissipation) between the electronic component 31 and the circuit layer 20 due to the embedding of the circuit layer 20 in the packaging layer 33.

Furthermore, the thickness t of the carrier 90 is extremely thin (0.02 mm) so as to facilitate reducing the thickness d (about 0.65 mm) of the encapsulation layer 33, so that the electronic package 3 can meet the requirements of light weight, thinness and shortness.

The present invention also provides a load-bearing structure 2 comprising: a carrier 90, and a circuit layer 20.

The carrier plate 90 comprises a plate body 900, a first metal layer 901 bonded to the plate body 900, a second metal layer 902 bonded to the first metal layer 901, and a third metal layer 903 bonded to the second metal layer 902.

The wiring layer 20 is bonded to the third metal layer 903.

In one embodiment, the first metal layer 901 is further bonded to the other side of the board 900, such that the first metal layer 901 is bonded to both opposite sides of the board 900.

In one embodiment, the first metal layer 901 is a copper layer.

In one embodiment, the second metal layer 902 is a copper layer.

In one embodiment, the third metal layer 903 is a copper layer.

In one embodiment, the carrier structure 2 further includes a surface treatment layer 21 formed on the circuit layer 20.

In summary, in the manufacturing method of the electronic package and the carrying structure thereof, the carrying structure is mainly used without using the solder mask layer, so that the related process of manufacturing the solder mask layer is not needed, and the carrying structure of the invention can shorten the process steps by about 50%, thereby effectively reducing the manufacturing cost, and greatly reducing the weight, so as to meet the requirements of lightness, thinness and shortness.

Furthermore, the carrier structure can be used as a seed crystal layer by using the third metal layer, so that the circuit layer of the carrier structure can meet the requirement of fine circuits, and the wire width/wire distance of the circuit layer is 10/10 micrometers (um).

In addition, the manufacturing method of the electronic packaging piece of the invention enables the packaging layer to effectively protect the side copper material of the circuit layer by embedding the circuit layer in the packaging layer without protruding the packaging layer so as to prevent the circuit layer from oxidation, so that the electronic packaging piece of the invention can lead the electronic element and the circuit layer to generate better electrical performance and power consumption.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications to the above would be obvious to those of ordinary skill in the art, without departing from the spirit and scope of the present invention. The scope of the invention is therefore intended to be indicated by the appended claims.

Claims

1. A load bearing structure comprising:

the bearing plate comprises a plate body, a first metal layer combined on one side of the plate body, a second metal layer combined on the first metal layer and a third metal layer combined on the second metal layer; and

and the circuit layer is combined on the third metal layer.

2. The carrier structure of claim 1 wherein the first metal layer is further bonded to the other side of the plate such that the first metal layer is bonded to both opposite sides of the plate.

3. The carrier structure of claim 1, wherein the first metal layer is a copper layer.

4. The carrier structure of claim 1 wherein the second metal layer is a copper layer.

5. The carrier structure of claim 1 wherein the third metal layer is a copper layer.

6. The carrier structure of claim 1, further comprising a surface treatment layer formed on the wiring layer.

7. A method of manufacturing an electronic package, comprising:

providing at least one load bearing structure according to any one of claims 1 to 6;

arranging an electronic element on the circuit layer so that the electronic element is electrically connected with the circuit layer;

forming a packaging layer on the third metal layer so that the packaging layer covers the electronic element; and

removing the carrier plate to expose the circuit layer outside the packaging layer.

8. The method of claim 7, wherein the circuit layer has a die pad and a plurality of electrical contact pads, such that the electronic device is disposed on the die pad and electrically connected to the plurality of electrical contact pads.

9. The method of claim 7, wherein the electronic device is electrically connected to the circuit layer by wire bonding.

10. The method of claim 7 further comprising laminating two carrier plates with their plate bodies facing each other to form a carrier, wherein the third metal layers are disposed on the opposite sides of the carrier, and the electronic components are disposed on the circuit layers on the opposite sides of the carrier.