CN118350325A

CN118350325A - Method for optimizing digital logic circuit, computer device and storage medium

Info

Publication number: CN118350325A
Application number: CN202410784757.8A
Authority: CN
Inventors: 邢自然
Original assignee: Xinxingji Technology Co ltd
Current assignee: Xinxingji Technology Co ltd
Priority date: 2024-06-18
Filing date: 2024-06-18
Publication date: 2024-07-16
Anticipated expiration: 2044-06-18
Also published as: CN118350325B

Abstract

The application provides a method, a computer device and a storage medium for optimizing a digital logic circuit. According to the method, a first node with increased arrival time in a dynamic forest is determined through the dynamic forest corresponding to the Boolean logic network, a first dynamic tree taking the first node as a root node is determined in the dynamic forest according to the first node, a second node in the Boolean logic network is determined according to a leaf node of the first dynamic tree and the transmission delay of an output edge of the leaf node, a corresponding third node exists in the dynamic forest in response to the second node, a timing margin is obtained according to the third node, and the digital logic circuit is optimized based on the timing margin. According to the method, the nodes with the affected arrival time in the Boolean logic network are represented through the dynamic tree in the dynamic forest, the problem that the Boolean logic network needs to be repeatedly traversed after the nodes in the Boolean logic network are changed is avoided, and further the time for analyzing and optimizing the circuit by the EDA tool can be greatly shortened.

Description

Method for optimizing digital logic circuit, computer device and storage medium

Technical Field

The present application relates to the field of digital logic circuits, and in particular, to a method, a computer device, and a storage medium for optimizing a digital logic circuit.

Background

With the increasing scale of modern digital logic circuits and the increasing complexity of functions, users have higher and higher requirements on the timing, power consumption or area (Performance Power Area, PPA) of the circuits, chip designers are pressing to require Electronic Design Automation (EDA) tools for digital circuits that can efficiently accomplish global level optimization of the circuits. Therefore, how to analyze and optimize circuits efficiently becomes an integral part of modern EDA tools.

Disclosure of Invention

The present application is directed to a method, a computer device and a storage medium for optimizing a digital logic circuit, which solve or partially solve the above-mentioned problems.

Based on the above object, the present application provides in a first aspect a method for optimizing a digital logic circuit, comprising:

Acquiring a Boolean logic network corresponding to the digital logic circuit;

acquiring a dynamic forest corresponding to the Boolean logic network, wherein the dynamic forest comprises a plurality of dynamic trees;

determining a first node of the dynamic forest, wherein the first node is a node with increased arrival time;

Determining a first dynamic tree taking the first node as a root node in the dynamic forest according to the first node;

Acquiring leaf nodes of the first dynamic tree;

determining a second node in the boolean logic network according to the transmission delays of the leaf node and the first node;

And responding to the existence of a corresponding third node in the dynamic forest of the second node, obtaining a timing margin according to the third node, and optimizing the digital logic circuit based on the timing margin.

In a second aspect of the present application, there is provided a computer device comprising:

one or more processors, memory; and

One or more programs;

Wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of the first aspect.

In a third aspect of the application, there is provided a non-transitory computer readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method according to the first aspect.

From the foregoing, it can be seen that the present application provides a method, computer device and storage medium for optimizing digital logic circuits. According to the method, a first node with increased arrival time in a dynamic forest is determined through the dynamic forest corresponding to the Boolean logic network, a first dynamic tree taking the first node as a root node is determined in the dynamic forest according to the first node, a second node in the Boolean logic network is determined according to a leaf node of the first dynamic tree and the transmission delay of an output edge of the leaf node, a corresponding third node exists in the dynamic forest in response to the second node, a timing margin is obtained according to the third node, and the digital logic circuit is optimized based on the timing margin. According to the method, the nodes with the affected arrival time in the Boolean logic network are represented through the dynamic tree in the dynamic forest, the problem that the Boolean logic network needs to be repeatedly traversed after the nodes in the Boolean logic network are changed is avoided, and further the time for analyzing and optimizing the digital logic circuit by an EDA tool can be greatly shortened.

Drawings

In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 shows a schematic diagram of an exemplary boolean logic network according to an embodiment of the present application.

Fig. 2A shows a schematic diagram of a boolean logic network according to an embodiment of the present application.

FIG. 2B shows a schematic diagram of an exemplary dynamic tree 210, according to an embodiment of the application.

Fig. 2C shows a schematic structural diagram of an exemplary dynamic tree 220, according to an embodiment of the present application.

Fig. 3A shows a schematic structural diagram of an exemplary dynamic tree 300 according to an embodiment of the present application.

FIG. 3B shows a schematic diagram of an exemplary dynamic tree 310, according to an embodiment of the present application.

Fig. 3C shows a schematic structural diagram of an exemplary dynamic tree 320, according to an embodiment of the present application.

Fig. 4A shows a schematic diagram of an exemplary boolean logic network according to an embodiment of the present application.

Fig. 4B shows a schematic structural diagram of an exemplary dynamic tree 410, according to an embodiment of the present application.

Fig. 4C shows a schematic structural diagram of an exemplary dynamic forest according to an embodiment of the present application.

Fig. 4D shows a schematic structural diagram of yet another exemplary dynamic forest according to an embodiment of the present application.

Fig. 4E shows a schematic structural diagram of an exemplary further dynamic forest according to an embodiment of the present application.

Fig. 4F shows a schematic structural diagram of an exemplary dynamic tree 428, according to an embodiment of the application.

Fig. 5 shows a flow diagram of an exemplary method for optimizing a digital logic circuit according to an embodiment of the application.

Fig. 6 shows a schematic structural diagram of an exemplary computer device according to an embodiment of the present application.

Detailed Description

The present application will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

It will be appreciated that before using the technical solutions of the embodiments of the present application, the user is informed of the type, the range of use, the use scenario, etc. of the related personal information in an appropriate manner, and the authorization of the user is obtained.

For example, in response to receiving an active request from a user, a prompt is sent to the user to explicitly prompt the user that the operation it is requesting to perform will require personal information to be obtained and used with the user. Therefore, the user can select whether to provide personal information to the software or hardware such as the electronic equipment, the application program, the server or the storage medium for executing the operation of the technical scheme according to the prompt information.

As an alternative but non-limiting implementation, in response to receiving an active request from a user, the manner in which the prompt information is sent to the user may be, for example, a popup, in which the prompt information may be presented in a text manner. In addition, a selection control for the user to select to provide personal information to the electronic device in a 'consent' or 'disagreement' manner can be carried in the popup window.

It will be appreciated that the above-described notification and user authorization acquisition process is merely illustrative, and not limiting of the implementation of the present application, and that other ways of satisfying relevant legal regulations may be applied to the implementation of the present application.

To aid understanding, some concepts related to embodiments of the application are described below.

1. Boolean logic Network (Boolean Network): a directed acyclic graph (DIRECTED ACYCLIC GRAPH, DAG). The graph is composed of a set of nodesAnd directed edge setThe composition is formed. Wherein:

1) The directed edge represents the direction of signal propagation. For directed edges, the starting node is defined as the tail node, and the pointing node (or ending node) is defined as the head node.

2) Input edge: for any nodeAll head nodes areAre all referred to as the nodeIs a part of the input edge of the display.

3) Output edge: for any nodeAll tail nodes areAre all referred to as the nodeIs provided. In the boolean logic network of the embodiment of the present application, all output edges correspond to the same logic signal, which is also referred to as a nodeIs provided.

4) Direct preamble node and direct successor node: for any nodeIf (if)Is thatA direct preamble node of (c) existsAs a tail node of the pipeline,An edge that is a head node; if it isIs thatIs the direct preamble node of (1)Is thatIs a direct successor node of (c).

5) Input signal set: for any nodeIts input signal set represents the set of signals carried by its input edge.

6) The nodes of each boolean logic network correspond to a certain logic function describing the relationship of the output signal to the set of input signals.

7) Input interface node): One or more ofThe nodes in the set have no input edges.

8) Output interface node): One or more ofThe nodes in the set have no output edges.

9) Topological ordering: there must be a topological ordering of the directed acyclic graph. Topology ordering is a set of nodesA process of integer association is performed. For one nodeAssigning integer setsThe numbers assigned to any two nodes are not the same and the order of the assigned numbers is the same as the topological order between the nodes. In particular, byAs an integerThe corresponding node is, for any integerAnd is also provided withIf there is a slave on the Boolean logic networkTo the point ofPath of (2)。

Due to the use of integersCan uniquely and certainly represent nodesWithout affecting understanding, the following text appliesTo represent。

2. Path (path): a sequence of nodes in which a directed edge exists between any two adjacent nodes such that the two nodes are the tail and head nodes of the edge, respectively.

1) The first node in the sequence is the starting node of the path.

2) The last node in the sequence is the termination node of the path.

3. Transfer input logic cone: a special subnetwork (TRANSITIVE FAN-in cone, TFI) is a node-specific oneAnd satisfies the following: any node in the setTo the nodePaths exist; any from PI toIs passed through a node in a TFI set.

4. Transfer output logic cone: a special subnetwork (TRANSITIVE FAN-out cone, TFO) is a node-specific oneAnd satisfies the following: any node in the setTo the nodePaths exist; any slaveThe paths to the POs all pass through at least one node in one TFI set.

5. Delay (delay): each edge of the directed acyclic graph can bind a positive number representing signal propagation delay in the physical world. Is provided withFor one edge in the directed acyclic graph, thenRepresenting the delay of this edge.

6. Arrival time (ARRIVAL TIME): the maximum time (max) that a signal can travel from any PI to a node. Definition of the definitionTransmission of representative signals from arbitrary PI to nodeIs formally defined as follows:

，

Wherein, when the node When it belongs to PIWhen (when)When it does not belong to PIWith its predecessor nodesDelay ofAnd (5) recursively calculating.

7. Time required (required time): the time of arrival of a signal request (typically the shortest arrival time (min)), typically defined on a set of PO nodes, isThe required time for a representative node is formally defined as follows:

，

wherein, if the node Belonging to PO, the required time is derived from user constraints. The time required by other nodes is determined by the following nodesDelay ofRecursive computation results, for example, for nodes not belonging to POCan be defined by the nodeSubsequent node of (a)Delay ofAnd (5) calculating to obtain the product. In generalRepresenting one clock cycle, the timing constraint of the digital circuit is that the signals complete and are written into the register through the combinational logic gate operation in one clock cycle.

8. Timing margin (slot): for one nodeThe timing margin is. When (when)Less than zero, representing a nodeThere is a timing violation.

Fig. 1 shows a schematic diagram of an exemplary boolean logic network 100 according to an embodiment of the present application.

As shown in FIG. 1, nodes 0 through 9 may be included in the Boolean logic network 100, where nodes {0,1,2} are PI and nodes {7,8,9} are PO. Assuming that the delay of each edge is 1, the arrival time of the node 7 is 4.

As described in the background, as modern digital logic circuits become larger and more complex in functionality, users have increased their requirements for timing, power consumption, or area (Performance Power Area, PPA) of the circuits, and chip designers are pressing the need for Electronic Design Automation (EDA) tools for digital circuits that can efficiently perform global level optimization of the circuits. Therefore, how to analyze and optimize circuits efficiently becomes an integral part of modern EDA tools.

With the increasing pursuit of the performance, power consumption and area of the digital circuits, the scale of the digital circuits is larger and larger, and further the analysis and optimization problems of the digital circuit design are more and more complex. Most analysis and optimization problems are NP-Hard problems, which refer to all NP problems (non-deterministic polynomials (non-DETERMINISTIC POLYNOMIAL, NP)), where in theory the EDA tool cannot ensure the obtained optimization result as an optimal solution within an acceptable turn-around time (TAT) from the time of application to the time of obtaining the result, the user typically invests in expert manual tuning, i.e. user-independent Editing (ECO) and opens multiple rounds of automatic optimization based on heuristic algorithms.

Whether ECO or heuristic based automatic optimization, the core operation is to alter the circuit part, then observe whether the PPA of the circuit is improved, and based on this, decide whether to apply the alteration. However, these two steps may take up a significant portion of the design flow time. Among these, ECO corresponds to a real-time interaction of the user with the EDA tool, which is a huge expenditure of manual effort. Heuristic optimization is a greedy way of optimizing, also requiring the EDA tool to calculate quickly for each optimization change.

In summary, the core requirement of the above-mentioned practical application on EDA tools is to effectively evaluate after a circuit change and quickly return whether the current change will affect PPA. The user or heuristic makes the next decision based on this feedback. Therefore, a fast evaluation algorithm can greatly improve TAT.

The basic flow of the conventional analysis optimization is to abstract a target digital logic circuit into a Boolean logic network, and obtain the time sequence state of the circuit by analyzing the path and the constraint of the Boolean logic network. The editing of the circuit may correspond to changes to the boolean logic network, such as changing the implementation of the logic gates (changing standard logic gate cells), moving the positions of the logic gates (re-layout), changing the connection implementation of the logic gates (re-winding), overwriting the logic, etc.

In editing a boolean logic network, a user can quickly and relatively accurately estimate the power consumption and area change per change, but it is difficult to simultaneously quickly and accurately estimate the timing. The reason for this is that the evaluation of power consumption and area often depends only on the variation itself, whereas the evaluation of timing needs to pass the effect of local changes to the global, thereby deriving the correct timing information. And there is also a mutual influence between the local changes, which results in a more complex estimation of global timing variations.

In some embodiments, the method of evaluating timing can be divided into two types: first, a run-time oriented algorithm propagates the effects of changes to a limited extent when changes occur. For example, one simple evaluation method is the current nodeChanges in arrival time caused by changes in (a) are reflected only in the small range effects of the neighboring nodes of the previous and subsequent stages of the node. Thus, since the number of nodes involved in each evaluation is small, its runtime is small. However, since the evaluation range is small at each time, the evaluation cannot guarantee the accuracy. Therefore, the accuracy of the evaluation is reduced by adopting the evaluation method, and the ECO and the heuristic optimization algorithm can make wrong decisions according to the evaluation result with lower accuracy, so that PPA is reduced. To repair the erroneous decisions made, the user has to optimize the turn by further adding ECO and heuristic algorithms, which can lead to an increase in TAT.

And secondly, an algorithm for evaluating precision guidance. This algorithm applies its changes to the global at each change. When a node changes its own arrival time according to the operation formula of arrival time, the node which is possibly affected globally is. In the worst caseThe aggregate size is equal to the number of nodes in the overall directed acyclic graph. In modern large-scale digital circuit designs, the number of nodes may be tens of millions, and the number of changes may be millions. Therefore, the run time required for such an algorithm is large. Users experience significant churning and delays in making ECO's in large-scale digital circuit designs, and therefore take a long time to automatically optimize with heuristic algorithms.

Fig. 2A shows a schematic diagram of a boolean logic network 200 according to an embodiment of the present application.

As shown in fig. 2A, in the related art, when the node u is modified, in order to obtain an evaluation result with higher accuracy, the change of the node u needs to be applied to the global, that is, all nodes in the boolean logic network 200 need to be traversed once. When a change is made to node v, all nodes in the boolean logic network 200 need to be traversed again. Thus, in the boolean logic network 200, a problem arises in that some nodes 202 are repeatedly traversed multiple times. For large scale digital circuit designs, tens of millions of nodes are altered, or millions of node alterations result in a large number of nodes being repeatedly traversed. Such large-scale repeated traversals result in a larger run time required by the algorithm, thereby reducing the evaluation and optimization efficiency of the digital logic circuit.

In view of this, the present application provides a method, computer device and storage medium for optimizing digital logic circuits. According to the method, a first node with increased arrival time in a dynamic forest is determined through the dynamic forest corresponding to the Boolean logic network, a first dynamic tree taking the first node as a root node is determined in the dynamic forest according to the first node, a second node in the Boolean logic network is determined according to a leaf node of the first dynamic tree and the transmission delay of an output edge of the leaf node, a corresponding third node exists in the dynamic forest in response to the second node, a timing margin is obtained according to the third node, and the digital logic circuit is optimized based on the timing margin. According to the method, the nodes with the affected arrival time in the Boolean logic network are represented through the dynamic tree in the dynamic forest, the problem that the Boolean logic network needs to be repeatedly traversed after the nodes in the Boolean logic network are changed is avoided, and further the time for analyzing and optimizing the circuit by the EDA tool can be greatly shortened on the premise that the evaluation accuracy is not affected.

A dynamic Tree (LCT) is a Tree-shaped data structure, and a plurality of dynamic trees may form a dynamic forest. FIG. 2B shows a schematic diagram of an exemplary dynamic tree 210, according to an embodiment of the application.

As shown in FIG. 2B, some operations may be performed on the dynamic tree 210 with the invocation of a function. In some exemplary application scenarios, a parent node of a dynamic tree where a node on the dynamic tree is currently located may be obtained through a parent function; the root function can be used for acquiring the tree root node (root node) of the dynamic tree where the node on the dynamic tree is currently located; the link between the node and the parent node of the current tree can be disconnected through the cut function, and the node is used as the root node of the new dynamic tree; the root node of one dynamic tree may be linked to the leaf node of another dynamic tree by a link function. The operation has the running time of。

In some embodiments, after the call cut function performs a cut operation on the dynamic tree 210 for the edge 206 between node p and node n, node n is taken as the root node of the new dynamic tree (dynamic tree 220), and the link of node n with the parent node p of the dynamic tree 210 is broken, as shown in FIG. 2B. In dynamic tree 220, node n is then the root node of subtree 204. Wherein the subtree 204 may include a plurality of nodes, the number of nodes of the subtree 204 in fig. 2C is merely exemplary, and the present application is not limited thereto.

Fig. 3A shows a schematic structural diagram of an exemplary dynamic tree 300 according to an embodiment of the present application. FIG. 3B shows a schematic diagram of an exemplary dynamic tree 310, according to an embodiment of the present application.

As shown in fig. 3A and 3B, in some embodiments, link functions may be invoked to perform linking operations on dynamic tree 300 and dynamic tree 310. Node n is the root node of dynamic tree 310 and node l is the leaf node of dynamic tree 300.

As shown in FIG. 3C, after the link function is invoked to perform a linking operation on the dynamic tree 300 and the dynamic tree 310, node n is linked under node l by edge 302.

Note that the circles in fig. 2A to 3C represent nodes in the dynamic tree. Meanwhile, the number of nodes of the dynamic tree in fig. 2A to 3C is merely exemplary, and the present application is not limited thereto.

Fig. 4A shows a schematic diagram of an exemplary boolean logic network 400 according to an embodiment of the present application.

As shown in fig. 4A, in some embodiments, the boolean logic network 400 may be derived from digital logic circuits. User editing of digital logic may correspond to modification of boolean logic network 400. When a first modification is made to the boolean logic network 400, a dynamic forest corresponding to the boolean logic network 400 may be generated.

It should be noted that the number of nodes in the boolean logic network 400 is only exemplary, and the present application is not limited thereto.

In conjunction with fig. 4A and 4B, in some embodiments, a dynamic forest corresponding to boolean logic network 400 may be constructed through a lookup table that may support nodes in any given boolean logic network to return to nodes in the corresponding dynamic forest. When a change is made to node u in the boolean logic network 400, the change to node u results in an increase in the arrival time of node u. If nodes u, v and w have no change in arrival time before the change to node u, i.e., the change to node u is the first change to boolean logic network 400, then there is no dynamic forest corresponding to boolean logic network 400, i.e., there are no nodes in the dynamic forest corresponding to nodes in boolean logic network 400 in the lookup table.

When a first change is made to the boolean logic network 400, as shown in fig. 4A, in some embodiments, the change to node u results in an increased arrival time for node u that can be propagated to the successor nodes v and w of node u. At this time, since the arrival time of the node v is affected by the modification of the node u, the arrival time of the node v increases. Thus, node v, which is affected by the modification of node u, may be added to the lookup table, as shown in FIG. 4B, to construct node v' in the dynamic tree 410, which corresponds to node v. Meanwhile, when the node u is changed, a node u' corresponding to the node u may also be constructed in the dynamic tree 410. In the boolean logic network 400, if the modification of node u does not affect the arrival time of node w, then it is not necessary to construct a node corresponding to node w in the dynamic tree 410 to save space in the lookup table.

Fig. 4C shows a schematic structural diagram of an exemplary dynamic forest 420, according to an embodiment of the present application.

As shown in fig. 4C, in some embodiments, dynamic forest 420 may be comprised of nodes in boolean logic network 400 that are affected by the modification of node u. Dynamic forest 420 may include a plurality of dynamic trees, for example, a dynamic tree with node u 'as the root node and node v' as the root node.

Because the construction of the dynamic forest 420 has traversed the node that was previously changed by the node u to cause the arrival time to change, when the user changes other nodes in the boolean logic network 400, expansion can be performed based on the dynamic forest 420, and further analysis and evaluation of the time sequence can be performed, without traversing the corresponding node of the dynamic forest 420 in the boolean logic network 400 again.

Fig. 4D shows a schematic structural diagram of yet another exemplary dynamic forest 420 in accordance with an embodiment of the present application.

As shown in fig. 4D, when other nodes in the boolean logic network 400 cause the arrival time of node v (e.g., the first node) to be affected again to increase, in some embodiments, node v and the first delay delta of node v may be determined. Taking the example that the change to the node v causes the arrival time of the node v to be affected again to increase, in some embodiments, a first root node (e.g., node u ') of the dynamic tree in which the node v is currently located in the dynamic forest corresponding to the node v' and a second delay increment of the first root node may be obtained. Wherein the second delay delta may be obtained by invoking a first function (e.g., delta function) that may be used to return an arrival time delta caused by a modification of a predecessor node of a node in the boolean logic network corresponding to the root node on the dynamic tree.

It can be determined whether the node v 'is affected by the node u' by the first delay increment and the second delay increment. In some embodiments, when the first delay delta is greater than the second delay delta, it may be determined that the arrival time of node v' has further increased beyond the arrival time increased by the modification of node u. As shown in FIG. 4D, in some embodiments, the links of node v 'and node u' may be broken by a cut function, resulting in a first dynamic tree 424 rooted at node v 'and a dynamic tree 422 rooted at node u'. As an alternative embodiment, when the node u 'and the node v' are the same node, the first dynamic tree 424 may be obtained according to the node v ', without calling a cut function to disconnect the node v' from the root node. By comparing the first delay increment with the second delay increment, whether the arrival time of the first node is still influenced by the first root node or not can be determined, and whether the first node and the current dynamic tree are required to be disconnected or not is determined.

When the call cut function disconnects first dynamic tree 424 from dynamic tree 422, leaf nodes in the dynamic tree may be assigned in some embodiments. As shown in fig. 4C, in the dynamic tree with node u' as the first root node, a first set of leaf nodes of the dynamic tree where the first root node is currently located in the dynamic forest 420 may be obtained. Wherein a second function (e.g., leafs functions) may be invoked to obtain the leaf nodes of the dynamic tree, and the second function may return the set of leaf nodes in the same dynamic tree as the target node.

As shown in fig. 4C, in some embodiments, the first set of leaf nodes may include node 1, node 2, and node 3. After the link between the node v 'and the node u' is disconnected, as shown in fig. 4D, the dynamic tree to which the leaf node belongs may be determined according to the root node of the dynamic tree to which the leaf node in the first leaf node set belongs. In some embodiments, when the root node of the dynamic tree where the node 2 and the node 3 (e.g., the fourth node) in the first leaf node set are currently located is the node v', the node 2 and the node 3 may be added to the leaf node set of the first dynamic tree 424, thereby obtaining the first dynamic tree 424, and implementing reassignment of dynamic leaf child nodes after the link is broken.

Fig. 4E shows a schematic structural diagram of an exemplary further dynamic forest 420 according to an embodiment of the present application.

As an alternative embodiment, as shown in FIG. 4E, if the further increase in arrival time of node v 'is due to a modification of node x', after the first dynamic tree 424 is obtained, a link function may be invoked to link node v 'under node x', thereby obtaining dynamic tree 426. This may indicate that the source node of the current arrival time variation of node v 'is node x'.

As described above, when a user changes other nodes in the boolean logic network 400, expansion may be performed based on the dynamic forest 420, so as to perform analysis and evaluation of the time sequence.

Fig. 4F shows a schematic structural diagram of an exemplary dynamic tree 428, according to an embodiment of the application. The dynamic tree 428 may be a second dynamic tree.

As shown in fig. 4F, after the first dynamic tree 424 is obtained, the first dynamic tree 424 may be extended from the leaf node of the first dynamic tree 424 based on the arrival time of the further increase of the node v ', so that the node between the leaf node of the first dynamic tree 424 and the node v' does not need to be traversed again, thereby saving the running time of the EDA tool. In some embodiments, leaf nodes of the first dynamic tree 424 may be obtained.

As shown in fig. 4F, in some embodiments, the leaf nodes of the acquired first dynamic tree 424 may include node 2 and node 3. From node 2 and node 3 in the dynamic forest, the corresponding nodes of node 2 and node 3 in the boolean logic network can be determined. Wherein a third function (e.g., dag _vertex function) may be invoked to determine the node in the dynamic forest that corresponds to the node in the boolean logic network.

The second node in the boolean logic network may be determined according to the transmission delays of the corresponding nodes of the nodes 2 and 3 in the boolean logic network and the output edges of the nodes. And expanding the dynamic tree according to whether the second node exists a corresponding third node in the dynamic forest.

Taking the example of the third node corresponding to the second node in the dynamic forest as node 4 and node 5, as shown in fig. 4F, in some embodiments, it may be determined whether the second root node of the current dynamic tree in which node 4 and node 5 are located in the dynamic forest is node v', to determine whether node 4 and node 5 belong to the same dynamic tree as node 2 and node 3. If the second root node of the dynamic tree where node 4 and node 5 are located is node v', in some embodiments, a timing margin for evaluating and optimizing the digital logic circuit may be derived from node 4 and node 5. In determining the timing margin, in some embodiments, the timing margin may be determined from the clock period of the digital logic circuit and the difference in arrival times of node 4 and node 5. The second node influenced by the arrival time of the change of the node can be determined through the corresponding node of the leaf node of the dynamic tree in the Boolean logic network and the transmission delay of the output edge of the node, and then a corresponding third node can be found in the dynamic forest according to the second node. In this way, the corresponding node affected by the change of the arrival time is determined based on the leaf node of the dynamic tree, and the node between the leaf node and the root node in the dynamic tree does not need to be traversed again, so that the time for analyzing and optimizing the digital logic circuit by the EDA tool can be greatly shortened.

As an alternative embodiment, if the second root node of the dynamic tree where the node 4 and the node 5 are located is not the node v', it is determined whether the links of the node 4 and the node 5 to the second root node need to be disconnected according to the arrival time of the node 4 and the node 5, so as to link the node 4 and the node 5 under the node 2 and the node 3, thereby expanding the first dynamic tree 424.

In some embodiments, a fourth function (e.g., aTree function) may be invoked to return the arrival times of node 4 and node 5. The arrival time of the node 4 and the node 5 may be the sum of arrival time of corresponding nodes of the node 4 and the node 5 in the boolean logic network and the arrival time increment caused by the modification of the preamble node of the corresponding node of the node 4 and the node 5 in the boolean logic network. Wherein a fifth function (e.g., delta_source function) may be invoked to return the source node of the arrival time variation of the node.

When the arrival times of the node 4 and the node 5 are smaller than the sum of the arrival times of the node 2 and the node 3 and the transmission delays of the nodes corresponding to the node 2 and the node 3 in the boolean logic network, it can be determined that the arrival times of the node 4 and the node 5 are affected by the node 2 and the node 3. Since the dynamic tree in which node 4 and node 5 are located is not the first dynamic tree 424, in some embodiments, the links of node 4 and node 5 with the second root node may be broken, resulting in a second dynamic tree having node 4 and node 5 as root nodes, respectively. After the link is broken, a link function may be invoked to link the second dynamic tree under node 2 and node 3, resulting in dynamic tree 428.

It should be noted that, in some embodiments, if the second node does not have a corresponding third node in the dynamic forest, a node (for example, a fifth node) corresponding to the second node needs to be created in the dynamic forest, that is, a node corresponding to the second node is added in the lookup table, and the node is used as the third node to perform subsequent expansion of the dynamic tree.

It should be noted that the number of nodes shown in the above-mentioned figures is exemplary, and the present application is not limited thereto.

Fig. 5 shows a flow diagram of an exemplary method 500 for optimizing a digital logic circuit according to an embodiment of the application. The method 500 may include the following steps.

At step 502, a boolean logic network (e.g., boolean logic network 400 in fig. 4A) corresponding to the digital logic circuit is obtained.

At step 504, a dynamic forest (e.g., dynamic forest 420 in fig. 4C) corresponding to the boolean logic network is obtained, the dynamic forest including a plurality of dynamic trees (e.g., dynamic trees 422, 424 in fig. 4D).

At step 506, a first node (e.g., node v' in fig. 4C) of the dynamic forest is determined, the first node being a node of increased arrival time.

At step 508, a first dynamic tree (e.g., dynamic tree 424 in fig. 4D) having the first node as a root node is determined in the dynamic forest based on the first node.

In some embodiments, the determining, according to the first node, a first dynamic tree in the dynamic forest having the first node as a root node further comprises: acquiring a first delay increment of the first node; acquiring a first root node of a dynamic tree where the first node is currently located in the dynamic forest; determining a second delay delta for the first root node; and responding to the first delay increment being larger than the second delay increment, wherein the first node and the first root node are the same node, and obtaining the first dynamic tree according to the first node. By comparing the first delay delta with the second delay delta, it can be determined whether the arrival time of the first node is still affected by the first root node.

In some embodiments, determining, in the dynamic forest, a first dynamic tree having the first node as a root node according to the first node further comprises: in response to the first delay delta being greater than the second delay delta and the first node and the first root node (e.g., node u' in fig. 4D) not being the same node, the first node and the first root node are disconnected to obtain the first dynamic tree. By comparing the first delay increment with the second delay increment, whether the arrival time of the first node is still influenced by the first root node or not can be determined, and whether the first node and the current dynamic tree are required to be disconnected or not is determined.

In some embodiments, said disconnecting said first node and said first root node to obtain said first dynamic tree further comprises: acquiring a first leaf node set (for example, a leaf node set formed by node 1, node 2 and node 3 in fig. 4C) of a dynamic tree where the first root node is currently located in the dynamic forest; disconnecting the first node from the first root node; in response to a root node of a dynamic tree in which a fourth node (e.g., node 2 and node 3 in fig. 4C) in the first set of leaf nodes is currently located being the first node, the fourth node is added to the first set of leaf nodes of the first dynamic tree to obtain the first dynamic tree. The method realizes the reassignment of the dynamic leaf child nodes after the link is disconnected, thereby obtaining a first dynamic tree.

At step 510, leaf nodes of the first dynamic tree (e.g., node 2 and node 3 in FIG. 4D) are obtained.

In step 512, a second node in the boolean logic network is determined based on the propagation delays of the leaf node and the corresponding output edges of the leaf node in the boolean logic network.

In step 514, in response to the second node having a corresponding third node (e.g., node 4 and node 5 of FIG. 4F) in the dynamic forest, a timing margin is derived from the third node and the digital logic circuit is optimized based on the timing margin.

In some embodiments, the obtaining a timing margin from the third node in response to the second node having a corresponding third node in the dynamic forest further comprises: determining whether a second root node of a dynamic tree where the third node is currently located in the dynamic forest is the first node or not in response to the existence of a corresponding third node in the dynamic forest by the second node; and responding to the second root node being the first node, and obtaining the timing margin according to the third node. Whether the third node and the leaf node of the first dynamic tree belong to the same dynamic tree can be determined by judging whether the second root node is the first node.

In some embodiments, the method further comprises: and in response to the second node not having a corresponding third node in the dynamic forest, creating a fifth node in the dynamic forest, and taking the fifth node as the third node. When there are nodes that are not affected by the first modification of a node that are not created as nodes in the dynamic forest, then the corresponding nodes need to be created in the dynamic forest.

In some embodiments, the method further comprises: in response to the second root node not being the first node and the arrival time of the third node being less than the sum of the arrival time of the leaf node and the transmission delay, disconnecting the third node from the second root node to obtain a second dynamic tree, the root node of the second dynamic tree being the third node; and linking the second dynamic tree below the leaf node, and obtaining the timing margin according to the third node. Thus, the node between the leaf node and the root node of the dynamic tree does not need to be traversed, and the expansion of the dynamic tree is realized by linking the third node to the position below the leaf node.

In some embodiments, deriving a timing margin from the third node and optimizing the digital logic circuit based on the timing margin further comprises: acquiring the arrival time of the third node; obtaining the timing margin according to the difference between the clock period of the digital logic circuit and the arrival time of the third node; the digital logic circuit is optimized based on the timing margin.

The application provides a method, computer equipment and storage medium for optimizing a digital logic circuit. According to the method, a first node with increased arrival time in a dynamic forest is determined through the dynamic forest corresponding to the Boolean logic network, a first dynamic tree taking the first node as a root node is determined in the dynamic forest according to the first node, a second node in the Boolean logic network is determined according to a leaf node of the first dynamic tree and the transmission delay of an output edge of the leaf node, a corresponding third node exists in the dynamic forest in response to the second node, a timing margin is obtained according to the third node, and the digital logic circuit is optimized based on the timing margin. According to the method, the nodes with the affected arrival time in the Boolean logic network are represented through the dynamic tree in the dynamic forest, the problem that the Boolean logic network needs to be repeatedly traversed after the nodes in the Boolean logic network are changed is avoided, and further the time for analyzing and optimizing the digital logic circuit by the EDA tool can be greatly shortened on the premise that the evaluation accuracy is not affected.

It should be noted that, the method of the embodiment of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of an embodiment of the present application, the devices interacting with each other to accomplish the method.

It should be noted that the foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Fig. 6 shows a schematic structural diagram of an exemplary computer device 600 according to an embodiment of the present application. The computer device 600 may include: processor 602, memory 604, network interface 606, peripheral interface 608, and bus 610. Wherein the processor 602, the memory 604, the network interface 606, and the peripheral interface 608 enable communication connections within the device between each other via a bus 610.

The processor 602 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application SPECIFIC INTEGRATED Circuit (ASIC), or one or more integrated circuits. The processor 602 may be used to perform functions related to the techniques described herein. In some embodiments, the processor 602 may also include multiple processors integrated as a single logical component. As shown in fig. 6, the processor 602 may include a plurality of processors 602a, 602b, and 602c.

The memory 604 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in fig. 6, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) as well as data to be processed. The processor 602 may also access stored program instructions and data and execute the program instructions to perform operations on the data to be processed. Memory 604 may include volatile memory or nonvolatile memory. In some embodiments, memory 604 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.

The network interface 606 may be configured to provide communications with other external devices to the computer device 600 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 606 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.

Peripheral interface 608 may be configured to connect computer apparatus 600 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.

Bus 610 may be configured to transfer information between the various components of computer device 600 (e.g., processor 602, memory 604, network interface 606, and peripheral interface 608), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.

It should be noted that although the above-described device only shows the processor 602, the memory 604, the network interface 606, the peripheral interface 608, and the bus 610, in a specific implementation, the device may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary for implementing the embodiments of the present application, and not all the components shown in the drawings.

The computer device of the foregoing embodiments is configured to implement the corresponding method 500 in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described herein.

Based on the same technical concept, the present application also provides a non-transitory computer readable storage medium corresponding to the method of any embodiment described above, where the non-transitory computer readable storage medium stores computer instructions for causing the computer to perform the method 500 of any embodiment described above.

The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be any method or technology for information storage. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

The storage medium of the foregoing embodiments stores computer instructions for causing the computer to perform the method 500 described in any of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.

Based on the same inventive concept, the present application also provides a computer program product, corresponding to any of the embodiment methods 500 described above, comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the described method 500. Corresponding to the execution bodies to which the steps in the embodiments of the method 500 correspond, the processor that executes the corresponding step may belong to the corresponding execution body.

The computer program product of the above embodiment is configured to cause a processor to perform the method 500 of any of the above embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.

Claims

1. A method for optimizing a digital logic circuit, comprising:

Acquiring a Boolean logic network corresponding to the digital logic circuit;

Acquiring leaf nodes of the first dynamic tree;

determining a second node in the Boolean logic network according to the transmission delay of the leaf node and the corresponding output edge of the leaf node in the Boolean logic network;

2. The method of claim 1, wherein the determining, from the first node, a first dynamic tree in the dynamic forest having the first node as a root node further comprises:

Acquiring a first delay increment of the first node;

Acquiring a first root node of a dynamic tree where the first node is currently located in the dynamic forest;

Determining a second delay delta for the first root node;

And responding to the first delay increment being larger than the second delay increment, wherein the first node and the first root node are the same node, and obtaining the first dynamic tree according to the first node.

3. The method of claim 2, wherein the determining, from the first node, a first dynamic tree in the dynamic forest having the first node as a root node further comprises:

And in response to the first delay delta being greater than the second delay delta and the first node and the first root node not being the same node, disconnecting the first node and the first root node to obtain the first dynamic tree.

4. The method of claim 1, wherein the deriving a timing margin from the third node in response to the second node having a corresponding third node in the dynamic forest further comprises:

determining whether a second root node of a dynamic tree where the third node is currently located in the dynamic forest is the first node or not in response to the existence of a corresponding third node in the dynamic forest by the second node;

and responding to the second root node being the first node, and obtaining the timing margin according to the third node.

5. The method of claim 4, wherein the method further comprises:

in response to the second root node not being the first node and the arrival time of the third node being less than the sum of the arrival time of the leaf node and the transmission delay, disconnecting the third node from the second root node to obtain a second dynamic tree, the root node of the second dynamic tree being the third node;

and linking the second dynamic tree below the leaf node, and obtaining the timing margin according to the third node.

6. The method of claim 3, wherein the disconnecting the first node and the first root node to obtain the first dynamic tree further comprises:

Acquiring a first leaf node set of a dynamic tree where the first root node is currently located in the dynamic forest;

disconnecting the first node from the first root node;

and in response to the root node of the dynamic tree where the fourth node in the first leaf node set is currently located being the first node, adding the fourth node into the leaf node set of the first dynamic tree to obtain the first dynamic tree.

7. The method of claim 1, wherein the deriving a timing margin from the third node and optimizing the digital logic circuit based on the timing margin further comprises:

acquiring the arrival time of the third node;

Obtaining the timing margin according to the difference between the clock period of the digital logic circuit and the arrival time of the third node;

The digital logic circuit is optimized based on the timing margin.

8. The method of claim 4, wherein the method further comprises:

And in response to the second node not having a corresponding third node in the dynamic forest, creating a fifth node in the dynamic forest, and taking the fifth node as the third node.

9. A computer device, comprising:

one or more processors, memory; and

One or more programs;

Wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of any of claims 1-8.

10. A non-transitory computer readable storage medium containing a computer program, which when executed by one or more processors causes the processors to perform the method of any of claims 1-8.