CN118338654A

CN118338654A - Semiconductor structure, forming method thereof and memory

Info

Publication number: CN118338654A
Application number: CN202310004781.0A
Authority: CN
Inventors: 周刘涛; 潘烁; 张启强
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-03
Filing date: 2023-01-03
Publication date: 2024-07-12
Also published as: WO2024146039A9; WO2024146039A1

Abstract

The disclosure relates to the technical field of semiconductors, and relates to a semiconductor structure, a forming method thereof and a memory. The forming method of the present disclosure includes: providing an initial semiconductor structure comprising a substrate and an initial bit line structure, wherein the substrate comprises a first doped region and a second doped region, the initial bit line structure comprises a bit line conductive structure and an initial bit line isolation structure, the bit line conductive structure is electrically connected with the first doped region, and the initial bit line isolation structure covers the bit line conductive structure; forming a sacrificial layer; etching the sacrificial layer to form an opening exposing the top of the initial bit line isolation structure; forming a protective layer in the opening, wherein the protective layer and the initial bit line isolation structure and the bit line conductive structure form an intermediate bit line structure; removing the sacrificial layer to form a first contact window on at least one side of the intermediate bit line structure; and forming a conductive contact structure in the first contact window, wherein the conductive contact structure is electrically connected with the second doped region. The forming method can reduce short circuit risk and improve product yield.

Description

Semiconductor structure, forming method thereof and memory

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a forming method thereof and a memory.

Background

The memory has the advantages of small volume, high integration degree, high transmission speed and the like, and is widely applied to mobile equipment such as mobile phones, tablet computers and the like.

The storage node contact plug is one of important parts of the memory, the isolation layer on the surface of the bit line structure is easy to damage in the process of manufacturing the storage node contact plug, structural defects are caused, short circuits are easy to occur between the storage node contact piece and the bit line structure and between adjacent storage node contact pieces, and the product yield is low.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, the present disclosure provides a semiconductor structure, a method for forming the same, and a memory, which can reduce the risk of short circuit and improve the yield of products.

According to one aspect of the present disclosure, there is provided a method for forming a semiconductor structure, including:

Providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate and an initial bit line structure positioned on the substrate, the substrate comprises an active region, the active region comprises a first doping region and a second doping region, the initial bit line structure comprises a bit line conductive structure and an initial bit line isolation structure, the bit line conductive structure is electrically connected with the first doping region, and the initial bit line isolation structure covers the top and the side wall of the bit line conductive structure;

forming a sacrificial layer covering the initial semiconductor structure;

Etching the sacrificial layer to form an opening exposing the top of the initial bit line isolation structure;

Forming a protective layer in the opening, wherein the protective layer and the initial bit line isolation structure form an intermediate bit line isolation structure, and the intermediate bit line isolation structure and the bit line conductive structure form an intermediate bit line structure;

Removing the sacrificial layer to form a first contact window on at least one side of the intermediate bit line structure;

and forming a conductive contact structure in the first contact window, wherein the conductive contact structure is electrically connected with the second doped region.

In one exemplary embodiment of the present disclosure, the orthographic projection of the initial bit line isolation structure on the substrate is located within the orthographic projection of the protective layer on the substrate.

In an exemplary embodiment of the present disclosure, before removing the sacrificial layer, the forming method further includes:

Etching the sacrificial layer to form an insulating window on at least one side of the intermediate bit line structure, the second doped region being located between the insulating window and the intermediate bit line structure;

And filling an insulating material in the insulating window to form an insulating layer.

In one exemplary embodiment of the present disclosure, forming the initial bit line structure includes:

Forming a first conductive material layer, a second conductive material layer, a third conductive material layer and an insulating material layer which are sequentially stacked and distributed along the direction perpendicular to the substrate on the surface of the substrate;

etching the first conductive material layer, the second conductive material layer, the third conductive material layer and the insulating material layer to form a bit line conductive structure and an insulating cover layer covering the top of the bit line conductive structure;

Forming a first isolation layer attached to the side wall of the structure formed by the bit line conductive structure and the insulating cover layer in a conformal manner;

forming a second isolation layer on the surface of the first isolation layer;

And forming a third isolation layer on the surface of the structure formed by the first isolation layer, the second isolation layer and the insulating cover layer, wherein the insulating cover layer, the first isolation layer, the second isolation layer and the third isolation layer form an initial bit line isolation structure.

In an exemplary embodiment of the present disclosure, the first contact window exposes a surface of the second doped region, and a conductive contact structure is formed in the first contact window, including:

Filling a contact plug material layer in the first contact windows, wherein the contact plug material layer is in contact with the surface of the second doped region and fills each first contact window;

selectively etching the contact plug material layer to enable the top of the contact plug material layer to be lower than the surface, close to the substrate, of the protection layer;

Etching the rest of the contact plug material layer and the middle bit line isolation structure to form a contact plug, a target bit line isolation structure and a second contact window, wherein the tops of the rest of the first isolation layer, the second isolation layer and the third isolation layer in the target bit line isolation structure are higher than the tops of the bit line conductive structure and the rest of the contact plug material layer, and the target bit line isolation structure and the bit line conductive structure form a target bit line structure;

A conductive contact structure is formed within the second contact window, the conductive contact structure extending from the second contact window to a top of the target bit line structure on one side thereof.

In one exemplary embodiment of the present disclosure, forming the conductive contact structure within the second contact window includes:

forming a diffusion barrier layer attached to the surface of the structure formed by the insulating layer, the target bit line isolation structure and the contact plug in a conformal manner;

Forming a conductive layer on the surface of the diffusion barrier layer, wherein the conductive layer fills the second contact window;

And etching the conductive layer and the diffusion barrier layer to disconnect the conductive layers corresponding to the adjacent second contact windows from each other and disconnect the diffusion barrier layers corresponding to the adjacent second contact windows from each other.

In one exemplary embodiment of the present disclosure, the material of the first isolation layer is the same as the material of the third isolation layer, which is different from the material of the second isolation layer.

In an exemplary embodiment of the disclosure, the active region includes two second doped regions, the first doped region is located between the two second doped regions, each of the second doped regions respectively corresponds to form one first contact window, and two first contact windows corresponding to the two second doped regions are respectively located at two sides of the intermediate bit line structure.

In one exemplary embodiment of the present disclosure, etching the sacrificial layer to form an opening exposing a top of the initial bit line isolation structure includes:

Forming a first mask layer on the surface of the sacrificial layer;

forming a first photoresist layer on the surface of the first mask layer;

exposing and developing the first photoresist layer to form a first development area;

etching the first mask layer in the first development area to form a first mask pattern;

and etching the sacrificial layer by taking the first mask layer with the first mask pattern as a mask to form an opening exposing the top of the initial bit line isolation structure.

In one exemplary embodiment of the present disclosure, forming a protective layer in the opening includes:

forming an insulating protection material layer on the surface of the sacrificial layer, wherein the opening is filled with the insulating protection material layer;

Flattening the surface of the insulating protection material layer far away from the substrate;

and removing the insulating protection material layer positioned on the surface of the sacrificial layer, and enabling the top of the insulating protection material layer positioned in the opening to be flush with the surface of the sacrificial layer.

According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

a substrate comprising an active region, the active region comprising a first doped region and a second doped region;

A target bit line structure on the substrate, the target bit line structure comprising a bit line conductive structure and a target bit line isolation structure, the bit line conductive structure being electrically connected with the first doped region, the target bit line isolation structure covering the top and sidewalls of the bit line conductive structure, the target bit line isolation structure comprising a first portion and a second portion in sequence from top to bottom, an orthographic projection of the second portion on the substrate being located within an orthographic projection of the first portion on the substrate;

and the conductive contact structure is at least positioned on one side of the target bit line structure and is electrically connected with the second doped region.

In one exemplary embodiment of the present disclosure, the first and second portions of the target bit line isolation structure are T-shaped in cross-section in a direction perpendicular to the substrate.

In one exemplary embodiment of the present disclosure, the conductive contact structure extends from one side of the target bit line structure to the top of the target bit line structure.

In an exemplary embodiment of the present disclosure, the target bit line isolation structure includes an insulating cover layer, a first isolation layer, a second isolation layer, a third isolation layer, and a protection layer, where the insulating cover layer is located on top of the bit line conductive structure, the protection layer is located on top of the insulating cover layer, the first isolation layer is attached to a sidewall of a structure formed by the bit line conductive structure and the insulating cover layer, the second isolation layer is located on a surface of the first isolation layer, the third isolation layer is located on a surface of the structure formed by the first isolation layer, the second isolation layer, and the insulating cover layer, and the protection layer is used as the first portion, and the second portion includes at least the insulating cover layer.

In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

The insulation layer is at least positioned on one side of the target bit line structure, and an area surrounded by the insulation layer and the target bit line structure is a first contact window;

The conductive contact structure is at least partially located within the first contact window.

In an exemplary embodiment of the present disclosure, the first contact window exposes a surface of the second doped region, and the semiconductor structure further includes:

the contact plug is positioned at the bottom of the first contact window and is in contact connection with the surface of the second doping region, and the tops of the first isolation layer, the second isolation layer and the third isolation layer are higher than the tops of the bit line conductive structure and the contact plug;

the part of the first contact window which is not filled by the contact plug is a second contact window, and the conductive contact structure is positioned in the second contact window and extends to the top of the target bit line structure at one side of the second contact window.

In one exemplary embodiment of the present disclosure, the conductive contact structure includes:

a diffusion barrier layer attached to the bottom and the side wall of the second contact window and extending from the second contact window to the top of the target bit line structure at one side of the second contact window;

and the conductive layer is positioned on the surface of the barrier layer.

In an exemplary embodiment of the disclosure, the active region includes two second doped regions, the first doped region is located between the two second doped regions, each of the second doped regions respectively corresponds to form one conductive contact structure, and the two conductive contact structures corresponding to the two second doped regions are respectively located at two sides of the target bit line structure.

According to one aspect of the present disclosure, there is provided a memory comprising a semiconductor structure as claimed in any one of the above.

According to the method for forming the semiconductor structure, before the conductive contact structure is formed, the protective layer can be formed at the top of the initial bit line isolation structure, in the process of forming the conductive contact structure, the surface of the initial bit line isolation structure can be protected through the protective layer, even if part of the film layer at the top of the bit line conductive structure is damaged in the process of processing by adopting a grinding or etching process in the process of subsequently forming the conductive contact structure, the damage of the protective layer is also the protective layer, the top of the initial bit line isolation structure is not damaged, the insulating isolation effect of the initial bit line isolation structure is guaranteed, the risk of short circuit between the conductive contact structure and the bit line conductive structure which are formed subsequently is reduced, and the product yield is improved.

According to the semiconductor structure and the memory, the bit line conducting structure can be insulated and protected through the target bit line isolation structure, the risk of short circuit or coupling between the bit line conducting structure and other surrounding structures is reduced, and the product yield is improved. Meanwhile, since the orthographic projection of the second part of the target bit line isolation structure on the substrate is positioned in the orthographic projection of the first part on the substrate, namely, the width of the first part is larger than that of the second part, the thickness of the insulating structure between the conductive contact structures formed subsequently can be increased through the design of the first part, the risk of short circuit between the adjacent conductive contact structures can be reduced, and the product yield can be further improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

FIG. 1 is a schematic diagram of a semiconductor structure in the related art;

Fig. 2 is a flow chart of a semiconductor structure in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an initial semiconductor structure in an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a second mask layer and a second photoresist layer according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram after step S220 is completed in the embodiment of the disclosure;

FIG. 6 is a schematic diagram of an initial bit line isolation structure in an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram after step S250 is completed in an embodiment of the disclosure;

fig. 8 is a schematic structural diagram after step S120 is completed in an embodiment of the disclosure;

fig. 9 is a schematic structural diagram after step S130 is completed in the embodiment of the disclosure;

fig. 10 is a schematic structural diagram after step S330 is completed in the embodiment of the disclosure;

fig. 11 is a schematic structural diagram after step S140 is completed in the embodiment of the disclosure;

fig. 12 is a schematic structural diagram after step S410 is completed in the embodiment of the disclosure;

fig. 13 is a schematic structural diagram after step S420 is completed in an embodiment of the disclosure;

FIG. 14 is a schematic diagram of a third mask layer and a third photoresist layer according to an embodiment of the disclosure;

fig. 15 is a schematic structural diagram after step S170 is completed in the embodiment of the disclosure;

FIG. 16 is a schematic view of an insulating material in an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram after step S180 is completed in the embodiment of the present disclosure;

fig. 18 is a schematic structural diagram after step S150 is completed in the embodiment of the present disclosure;

FIG. 19 is a schematic view of a first contact window in an embodiment of the present disclosure;

fig. 20 is a schematic structural diagram after step S160 is completed in the embodiment of the disclosure;

fig. 21 is a schematic structural diagram after step S510 is completed in the embodiment of the present disclosure;

Fig. 22 is a schematic structural diagram after step S520 is completed in the embodiment of the disclosure;

fig. 23 is a schematic structural diagram after step S530 is completed in the embodiment of the present disclosure;

fig. 24 is a schematic structural diagram after step S540 is completed in the embodiment of the present disclosure;

Fig. 25 is a top view of a semiconductor structure in an embodiment of the disclosure.

Reference numerals illustrate:

100. An insulating isolation layer; 110. silicon oxide; 120. silicon nitride; 101. a notch; 1. an initial semiconductor structure; 11. a substrate; 111. shallow trench isolation structures; 112. a word line structure; 12. an initial bit line structure; 121. a bit line conductive structure; 1211. a first conductive material layer; 1212. a second conductive material layer; 1213. a third conductive material layer; 1214. an insulating material layer; 122. an initial bit line isolation structure; 1221. an insulating cover layer; 1222. a first isolation layer; 1223. a second isolation layer; 1224. a third isolation layer; 13. a protective layer; 130. an insulating protective material layer; 20. an intermediate bit line isolation structure; 200. an intermediate bit line structure; 2. a sacrificial layer; 201. an opening; 202. an insulating window; 203. a first contact window; 2031. a second contact window; 3. a conductive contact structure; 310. a contact plug material layer; 31. a diffusion barrier layer; 32. a conductive layer; 4. an insulating layer; 5. a contact plug; 6. a target bit line structure; 410. an insulating material; 400. a first mask layer; 401. a first photoresist layer; 4011. a first development zone; 500. a second mask layer; 501. a second photoresist layer; 5011. a second development region; 600. a third mask layer; 601. a third photoresist layer; 6011. a third development zone; 700. an insulating dielectric layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

With the continuous development of mobile devices, mobile devices with battery power, such as mobile phones, tablet computers, wearable devices and the like, are increasingly applied to life, a memory is used as an indispensable element in the mobile devices, and great demands are put forward by people on the small size and integration of the memory.

As the integration of memory increases, the distance between the storage node contact plug and the bit line structure becomes smaller due to the increasing number of circuits in a unit area, the storage node contact plug and the bit line structure are generally required to be insulated by the insulating isolation layer 100, and in this process, if the thickness of the insulating isolation layer 100 is not enough, the risk of short circuit between the storage node contact plug and the bit line structure is also easily caused. The insulating spacer 100 covers the top and sidewalls of the bit line structure, and the insulating spacer 100 generally comprises a sandwich structure of silicon nitride 120-silicon oxide 110-silicon nitride 120; in the process of forming the storage node contact plug, multiple etching and grinding processes are generally required, in this process, the top of the insulating isolation layer 100 is easily damaged, a notch 101 appears, so that the top of the oxide layer is exposed, in the subsequent wet etching process, the oxide layer is easily completely etched, the insulating isolation layer 100 is damaged, a short circuit is easily generated between the bit line structure and the storage node contact plug formed subsequently, and the product yield is lower.

Based on this, the embodiment of the present disclosure provides a method for forming a semiconductor structure, fig. 2 shows a flowchart of the method for forming a semiconductor structure of the present disclosure, and referring to fig. 2, the method for forming includes steps S110 to S160, where:

Step S110, providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate and an initial bit line structure positioned on the substrate, the substrate comprises an active area, the active area comprises a first doping area and a second doping area, the initial bit line structure comprises a bit line conductive structure and an initial bit line isolation structure, the bit line conductive structure is electrically connected with the first doping area, and the initial bit line isolation structure covers the top and the side wall of the bit line conductive structure;

step S120, forming a sacrificial layer covering the initial semiconductor structure;

Step S130, etching the sacrificial layer to form an opening exposing the top of the initial bit line isolation structure;

Step S140, forming a protective layer in the opening, wherein the protective layer and the initial bit line isolation structure form an intermediate bit line isolation structure, and the intermediate bit line isolation structure and the bit line conductive structure form an intermediate bit line structure;

Step S150, removing the sacrificial layer to form a first contact window on at least one side of the intermediate bit line structure;

and step S160, forming a conductive contact structure in the first contact window, where the conductive contact structure is electrically connected with the second doped region.

The steps of the method for forming a semiconductor structure of the present disclosure and their specific details are described in detail below:

As shown in fig. 2, in step S110, an initial semiconductor structure is provided, the initial semiconductor structure including a substrate and an initial bit line structure on the substrate, the substrate including an active region, the active region including a first doped region and a second doped region, the initial bit line structure including a bit line conductive structure and an initial bit line isolation structure, the bit line conductive structure being electrically connected to the first doped region, the initial bit line isolation structure covering a top and a sidewall of the bit line conductive structure.

As shown in fig. 3, the initial semiconductor structure 1 may include a substrate 11 and an initial bit line structure 12, wherein:

The substrate 11 may have a flat plate structure, which may be rectangular, circular, elliptical, polygonal, or irregular, and may be made of a semiconductor material, for example, silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 11 are not particularly limited.

In some embodiments of the present disclosure, the substrate 11 may be a silicon substrate having a shallow trench isolation structure 111 formed therein, and the shallow trench isolation structure 111 may be formed by filling an isolation material layer in the trench after forming the trench in the substrate 11. The material of the shallow trench isolation structure 111 may include silicon nitride or silicon oxide, and is not limited herein. The shallow trench isolation structure 111 can separate a plurality of active regions on the substrate 11, where the active regions may include first doped regions and second doped regions that are spaced apart, and the number of the second doped regions may be two, and the first doped region may be located between the two second doped regions. A plurality of word line structures 112 may be further formed in the substrate 11, and the word line structures 112 may be spaced apart, each word line structure 112 may pass through a plurality of active regions, and a first doped region and a second doped region in each active region through which it passes may be located at two sides of the word line structure 112, respectively.

An initial bit line structure 12 may be formed on top of the substrate 11, the initial bit line structure 12 may include a bit line conductive structure 121 and an initial bit line isolation structure 122, wherein:

The bit line conductive structure 121 may be in contact with the first doped region, and the bit line conductive structure 121 may include a first conductive material layer 1211, a second conductive material layer 1212, and a third conductive material layer 1213 sequentially stacked in a direction perpendicular to the substrate 11, and the first conductive material layer 1211, the second conductive material layer 1212, and the third conductive material layer 1213 may be aligned at both ends in a direction parallel to the substrate 11. In some embodiments of the present disclosure, the material of the first conductive material layer 1211 may be polysilicon, and the polysilicon in the first conductive material layer 1211 may be doped, thereby improving the conductivity of the first conductive material layer 1211; the material of the second conductive material layer 1212 may be titanium nitride, and the material of the third conductive material layer 1213 may be tungsten, and the diffusion of tungsten into the polysilicon and the substrate 11 may be prevented by the titanium nitride, so as to ensure the stability of the bit line conductive structure 121.

The initial bit line isolation structure 122 may include an insulating cap layer 1221, a first isolation layer 1222, a second isolation layer 1223, and a third isolation layer 1224, where the insulating cap layer 1221 is located on top of the bit line conductive structure 121, the first isolation layer 1222 is attached to a sidewall of the structure formed by the bit line conductive structure 121 and the insulating cap layer 1221, and the thickness of the first isolation layer 1222 may be 2nm to 4nm, for example, it may be 2nm, 3nm, or 4 nm; the second isolation layer 1223 covers the surface of the first isolation layer 1222, and may have a thickness of 1nm to 3nm, for example, 1nm, 2nm, 3nm, or the like; the third isolation layer 1224 covers the surface of the structure formed by the first isolation layer 1222, the second isolation layer 1223, and the insulating cover layer 1221, and may have a thickness of 4nm to 6nm, for example, 4nm, 5nm, or 6 nm. Of course, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may have other thicknesses, and the thicknesses of the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 are not particularly limited.

In an exemplary embodiment of the present disclosure, the material of the first isolation layer 1222 is the same as the material of the second isolation layer 1223, and the material of the third isolation layer 1224 is different from the material of the second isolation layer 1223. For example, the materials of the first isolation layer 1222 and the third isolation layer 1224 may be silicon nitride, the materials of the second isolation layer 1223 may be silicon oxide, and the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may be a "sandwich" structure formed by silicon nitride-silicon oxide-silicon nitride.

In some embodiments of the present disclosure, the surface of the substrate 11 may also be formed with an insulating dielectric layer 700, and the orthographic projection of the insulating dielectric layer 700 on the substrate 11 does not overlap with the orthographic projection of the initial bit line structure 12 on the substrate 11. For example, the insulating dielectric layer 700 may cover the surface of the substrate 11 and may have an opening exposing the substrate 11, and the initial bit line structure 12 may be in contact with the surface of the substrate 11 through the opening in the insulating dielectric layer 700.

In one exemplary embodiment of the present disclosure, forming the initial bit line structure 12 may include step S210-step S250, wherein:

in step S210, a first conductive material layer 1211, a second conductive material layer 1212, a third conductive material layer 1213, and an insulating material layer 1214 are formed on the surface of the substrate 11, which are stacked in order along a direction perpendicular to the substrate 11.

As shown in fig. 4, the first conductive material layer 1211 may be formed on the surface of the substrate 11 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, thermal evaporation, or the like, and when the insulating dielectric layer 700 is formed on the surface of the substrate 11, the first conductive material layer 1211 may cover both the insulating dielectric layer 700 and the surface of the substrate 11 not covered by the insulating dielectric layer 700. The material of the first conductive material layer 1211 may be polysilicon, and a portion of the first conductive material layer 1211 located in the opening region of the insulating dielectric layer 700 may be doped so as to improve the conductive ability of the first conductive material layer 1211 located in the opening region of the insulating dielectric layer 700.

The second conductive material layer 1212 may be formed on the surface of the first conductive material layer 1211 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, thermal evaporation, or the like, and the material of the second conductive material layer 1212 may be titanium nitride.

The third conductive material layer 1213 may be formed on the surface of the second conductive material layer 1212 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, thermal evaporation, or the like, and the material of the third conductive material layer 1213 may be tungsten.

The insulating material layer 1214 may be formed on the surface of the third conductive material layer 1213 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or the like, and the material of the insulating material layer 1214 may be silicon nitride.

In step S220, the first conductive material layer 1211, the second conductive material layer 1212, the third conductive material layer 1213 and the insulating material layer 1214 are etched to form a bit line conductive structure 121, and an insulating cap layer 1221 covering the top of the bit line conductive structure 121.

As shown in fig. 5, the first conductive material layer 1211, the second conductive material layer 1212, the third conductive material layer 1213, and the insulating material layer 1214 may be etched by a non-isotropic etching process, thereby forming a bit line conductive structure 121 on top of the substrate 11, and simultaneously forming an insulating cap layer 1221 on the surface of the bit line conductive structure 121.

For example, as shown in fig. 4, a second mask layer 500 may be formed on the surface of the insulating material layer 1214, where the second mask layer 500 may be a single layer or a multi-layer film, and the material may be at least one of carbide, siO ₂, siN, polysilicon, and SiON, and of course, may be other materials, which are not listed herein.

In some embodiments, the second mask layer 500 may be a multi-layer, which may include a carbide layer and a SiON layer, wherein the carbide layer may be formed on a surface of the insulating material layer 1214, and the SiON layer may be located on a surface of the carbide layer. A carbide layer may be formed on the surface of the insulating material layer 1214 by a chemical vapor deposition process, and a SiON layer may be formed on the surface of the carbide layer by an atomic layer deposition process.

With continued reference to fig. 4, a second photoresist layer 501 may be formed on a surface of the second mask layer 500 facing away from the substrate 11 by spin coating or other methods, and a material of the second photoresist layer 501 may be a positive photoresist or a negative photoresist, which is not particularly limited herein.

The second photoresist layer 501 may be exposed using a reticle whose pattern may be matched to the pattern desired for the bit line conductive structure 121. Subsequently, the exposed second photoresist layer 501 may be developed, thereby forming a second development region 5011, and the second development region 5011 may expose the surface of the second mask layer 500.

The second mask layer 500 may be etched in the second developing region 5011 by a non-isotropic etching process, the etched region may expose the insulating material layer 1214, thereby forming a second mask pattern on the second mask layer 500, the second mask pattern may have a stripe shape, and an orthographic projection of the second mask pattern on the insulating material layer 1214 may be located in an opening region of the insulating dielectric layer 700.

It should be noted that, when the second mask layer 500 has a single-layer structure, a single etching process may be used to form the second mask pattern, and when the second mask layer 500 has a multi-layer structure, each of the film layers may be subjected to layered etching, that is: one layer may be etched by one etching process, and the second mask layer 500 may be etched through by a plurality of etching processes to form a second mask pattern.

After the etching process is completed, the second photoresist layer 501 may be removed by cleaning with a cleaning solution or by ashing, so that the second mask layer 500 having the second mask pattern is not covered by the second photoresist layer 501.

The second mask layer 500 having the second mask pattern is used as a mask to perform anisotropic etching on the first conductive material layer 1211, the second conductive material layer 1212, the third conductive material layer 1213, and the insulating material layer 1214, so as to form the bit line conductive structure 121 and the insulating cap layer 1221 covering the bit line conductive structure 121. In the embodiment of the present disclosure, the structure after step S220 is completed is shown in fig. 5.

In some embodiments of the present disclosure, forming the first, second, and third isolation layers 1222, 1223, 1224 may include:

in step S230, a first isolation layer 1222 is formed to be attached to a sidewall of the structure formed by the bit line conductive structure 121 and the insulating cap 1221.

As shown in fig. 6, the first isolation layer 1222 may be formed on the surface of the structure formed by the substrate 11, the insulating dielectric layer 700, the bit line conductive structure 121 and the insulating cover layer 1221 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, thermal evaporation, or the like, however, the first isolation layer 1222 may be formed by other methods, and the forming method of the first isolation layer 1222 is not limited in particular. Subsequently, the first isolation layer 1222 located outside the sidewalls of the structure in which the bit line conductive structure 121 and the insulating cap layer 1221 are formed together may be removed, and only the first isolation layer 1222 located on the sidewalls of the structure in which the bit line conductive structure 121 and the insulating cap layer 1221 are formed together remains.

In step S240, a second isolation layer 1223 is formed on the surface of the first isolation layer 1222.

The second isolation layer 1223 may be formed on the surface of the structure formed by the first isolation layer 1222 and the insulating cover layer 1221 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, thermal evaporation, or the like, however, the second isolation layer 1223 may be formed by other methods, and the forming method of the second isolation layer 1223 is not limited specifically. Subsequently, the second isolation layer 1223 located outside the sidewalls of the first isolation layer 1222 may be removed, leaving only the second isolation layer 1223 located on the sidewalls of the first isolation layer 1222.

In step S250, a third isolation layer 1224 is formed on the surface of the structure formed by the first isolation layer 1222, the second isolation layer 1223 and the insulating cover layer 1221, where the insulating cover layer 1221, the first isolation layer 1222, the second isolation layer 1223 and the third isolation layer 1224 together form the initial bit line isolation structure 122.

The third isolation layer 1224 may be formed on the surface of the structure formed by the first isolation layer 1222, the second isolation layer 1223, and the insulating cover layer 1221 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation, or other methods, however, the forming method of the third isolation layer 1224 is not limited in particular. In the embodiment of the present disclosure, the structure after step S250 is completed is shown in fig. 6.

In other embodiments of the present disclosure, as shown in fig. 7, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may be sequentially formed on the surface of the structure formed by the bit line conductive structure 121, the insulating cover layer 1221, and the substrate 11 (or the insulating dielectric layer 700), and after the third isolation layer 1224 is formed, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 on the surface of the substrate 11 (or the insulating dielectric layer 700) may be removed, only the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 on the sidewalls of the bit line conductive structure 121 and the sidewalls of the insulating cover layer 1221 remain, and in some embodiments, the same material as that of the third isolation layer 1224 may be deposited on the surfaces of the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 at the same time, and the top of the first isolation layer 1223 may be capped by the material, so as to prevent the top of the second isolation layer 1223 from being exposed, and the remaining first isolation layer 1222, the second isolation layer 1223, the third isolation layer 1224 may be formed on the top of the first isolation layer 1223, and the third isolation layer 1224 may be formed on the top of the first isolation layer 1223 and the top of the insulating cover layer 1221. For example, a wet etching process may be used to remove the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 on the surface of the insulating dielectric layer 700.

In some embodiments of the present disclosure, the number of the initial bit line structures 12 may be plural, the plural initial bit line structures 12 may be spaced apart on the substrate 11, and the initial bit line structures 12 are disposed with insulation therebetween.

As shown in fig. 2, in step S120, a sacrificial layer is formed overlying the initial semiconductor structure.

For example, the sacrificial layer 2 may be formed on the side of the substrate 11 near the initial bit line structure 12 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, thermal oxidation, or the like, and of course, the sacrificial layer 2 may be formed by other methods, which are not further described herein. The sacrificial layer 2 may cover the surface of the structure formed by the initial bit line isolation structures 122 and the substrate 11, and may fill the gaps between the initial bit line isolation structures 122 of each initial bit line structure 12 when the number of the initial bit line structures 12 is plural. In the embodiment of the present disclosure, the structure after step S120 is completed is shown in fig. 8.

In an exemplary embodiment of the present disclosure, the material of the sacrificial layer 2 may be an insulating material, for example, silicon oxide, and of course, the material of the sacrificial layer 2 may be other materials, which is not particularly limited herein. It should be noted that the material of the sacrificial layer 2 is different from the exposed material of the surface of the initial bit line isolation structure 122.

As shown in fig. 2, in step S130, the sacrificial layer is etched to form an opening exposing the top of the initial bit line isolation structure.

A dry etching process may be used to selectively etch a portion of the area in the sacrificial layer 2, thereby forming an opening 201 in the sacrificial layer 2, and the opening 201 may expose the top of the initial bit line isolation structure 122. When the number of the initial bit line structures 12 is plural, the number of the openings 201 may be plural, and each opening 201 may expose the top of the initial bit line isolation structure 122 of each initial bit line structure 12. In the embodiment of the present disclosure, the structure after step S130 is completed is shown in fig. 9.

In an embodiment of the present disclosure, etching the sacrificial layer 2 to form the opening 201 exposing the top of the initial bit line isolation structure 122 (i.e., step S130) may include steps S310-S350, wherein:

in step S310, a first mask layer 400 is formed on the surface of the sacrificial layer 2.

As shown in fig. 10, a first mask layer 400 may be formed on the surface of the sacrificial layer 2, where the first mask layer 400 may be a single layer film or a multi-layer film, and the material may be at least one of carbide, siO ₂, siN, polysilicon, and SiON, and of course, may be other materials, which are not listed here.

In some embodiments, the structure of the first mask layer 400 may be the same as that of the second mask layer 500, and specific details of the first mask layer may refer to the second mask layer 500, so that details are not repeated herein.

In step S320, a first photoresist layer 401 is formed on the surface of the first mask layer 400.

The first photoresist layer 401 may be formed on the surface of the first mask layer 400 facing away from the substrate 11 by spin coating or other methods, and the material of the first photoresist layer 401 may be a positive photoresist or a negative photoresist, which is not particularly limited herein.

In step S330, the first photoresist layer 401 is exposed and developed to form a first developing region 4011.

The first photoresist layer 401 may be exposed using a reticle whose pattern may be matched to the pattern required for the opening 201. Subsequently, the exposed first photoresist layer 401 may be developed, thereby forming a first development region 4011, and the first development region 4011 may expose a surface of the first mask layer 400. In the embodiment of the present disclosure, the structure after step S330 is completed is shown in fig. 10.

In step S340, the first mask layer 400 is etched in the first developing region 4011 to form a first mask pattern.

The first mask layer 400 may be etched in the first developing region 4011 by a non-isotropic etching process, and the etched region may expose the sacrificial layer 2, thereby forming a first mask pattern on the first mask layer 400, the first mask pattern may be in a stripe shape, and an orthographic projection of the initial bit line isolation structure 122 on the substrate 11 is within an orthographic projection of the first mask pattern on the substrate 11.

After the etching process is completed, the first photoresist layer 401 may be removed by cleaning with a cleaning solution or by ashing, so that the first mask layer 400 having the first mask pattern is not covered by the first photoresist layer 401.

In step S350, the sacrificial layer 2 is etched with the first mask layer 400 having the first mask pattern as a mask to form an opening 201 exposing the top of the initial bit line isolation structure 122.

The sacrificial layer 2 is anisotropically etched using the first mask layer 400 having the first mask pattern as a mask and the initial bit line structure 12 as an etch stop layer to form an opening 201 exposing the top of the initial bit line structure 12.

As shown in fig. 2, in step S140, a protective layer is formed in the opening, the protective layer and the initial bit line isolation structure constitute an intermediate bit line isolation structure, and the intermediate bit line isolation structure and the bit line conductive structure constitute an intermediate bit line structure.

The protective layer 13 may be formed in the opening 201 in the sacrificial layer 2 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or the like, and of course, the protective layer 13 may be formed by other methods, and the forming method of the protective layer 13 is not particularly limited.

The protection layer 13 is attached to the top of the initial bit line isolation structure 122, in the subsequent process of forming the conductive contact structure, the surface of the initial bit line isolation structure 122 can be protected by the protection layer 13, even if part of the film layer at the top of the bit line conductive structure 121 is damaged in the process of adopting grinding or etching technology for processing in the subsequent process of forming the conductive contact structure, the damaged protection layer 13 does not damage the top of the initial bit line isolation structure 122, the top of the second isolation layer 1223 is not exposed, and in the subsequent wet etching process, the second isolation layer 1223 is not etched away, thereby being beneficial to ensuring the insulation isolation effect of the initial bit line isolation structure 122, reducing the risk of short circuit between the conductive contact structure formed subsequently and the bit line conductive structure 121, and further improving the product yield. In the embodiment of the present disclosure, the structure after step S140 is completed is shown in fig. 11.

The material of the protective layer 13 may be an insulating acid-resistant material in order to reduce consumption of the protective layer 13 during subsequent wet etching. For example, the material of the protection layer 13 may be silicon nitride.

In some embodiments of the present disclosure, the orthographic projection of the initial bit line isolation structure 122 onto the substrate 11 is located within the orthographic projection of the protective layer 13 onto the substrate 11, and the protective layer 13 and the initial bit line isolation structure 122 may together constitute the intermediate bit line isolation structure 20 in a "T-shape". The design of the "T-shaped" intermediate bit line isolation structure 20 may help to increase the thickness of the insulating structure between subsequently formed conductive contact structures, which may reduce the risk of shorting between adjacent conductive contact structures.

In one exemplary embodiment of the present disclosure, forming the protective layer 13 in the opening 201 may include steps S410 to S430, wherein:

in step S410, an insulating protective material layer 130 is formed on the surface of the sacrificial layer 2, and the opening 201 is filled with the insulating protective material layer 130.

The insulating protective material layer 130 may be formed on the surface of the sacrificial layer 2 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or the like, however, the insulating protective material layer 130 may be formed by other methods, and the forming method of the insulating protective material layer 130 is not limited in particular. The insulating protective material layer 130 may at least fill the opening 201, i.e. deposition may be stopped after the insulating protective material layer 130 fills the opening 201. In the embodiment of the present disclosure, the structure after step S410 is completed is shown in fig. 12.

In step S420, a planarization process is performed on the surface of the insulating and protecting material layer 130 away from the substrate 11.

The surface of the insulating and protecting material layer 130 can be ground, so that the height difference of different areas on the surface of the insulating and protecting material layer 130 is eliminated, a smooth reference is provided for the subsequent process, so that in the subsequent process of removing the insulating and protecting material layer 130 on the surface of the sacrificial layer 2, different areas of the insulating and protecting material layer 130 can be removed at the same time, and the bottom structure of the insulating and protecting material layer 130 is not damaged. In the embodiment of the present disclosure, the structure after step S420 is completed is shown in fig. 13.

In step S430, the insulating and protecting material layer 130 located on the surface of the sacrificial layer 2 is removed, and the top of the insulating and protecting material layer 130 located in the opening 201 is made to be flush with the surface of the sacrificial layer 2.

The insulating and protecting material layer 130 may be etched by a dry etching process, thereby removing the insulating and protecting material layer 130 located on the surface of the sacrificial layer 2, leaving only the insulating and protecting material layer 130 located in the opening 201 of the sacrificial layer 2, and making the surface of the insulating and protecting material layer 130 located in the opening 201 of the sacrificial layer 2 flush with the surface of the sacrificial layer 2. In the embodiment of the present disclosure, the structure after step S430 is completed is shown in fig. 11.

In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include step S170 and step S180, wherein:

in step S170, the sacrificial layer 2 is etched to form an insulating window 202 on at least one side of the intermediate bit line structure 200, and the second doped region is located between the insulating window 202 and the intermediate bit line structure 200.

As shown in fig. 14, a third mask layer 600 may be formed on the surface of the sacrificial layer 2, where the third mask layer 600 may be a single layer film or a multi-layer film, and the material may be at least one of carbide, siO ₂, siN, polysilicon, and SiON, and of course, may be other materials, which are not listed here.

In some embodiments, the structure of the third mask layer 600 may be the same as that of the second mask layer 500, and specific details of the third mask layer 600 may refer to the second mask layer 500, so that the description thereof is omitted herein.

The third photoresist layer 601 may be formed on the surface of the third mask layer 600 facing away from the substrate 11 by spin coating or other methods, and the material of the third photoresist layer 601 may be positive photoresist or negative photoresist, which is not particularly limited herein.

The third photoresist layer 601 may be exposed using a reticle whose pattern may be matched to the pattern required for the insulating window 202. Subsequently, the exposed third photoresist layer 601 may be developed, thereby forming a third development region 6011, the third development region 6011 may expose a surface of the third mask layer 600, and an orthographic projection of the third development region 601 on the substrate 11 and an orthographic projection of the intermediate bit line isolation structure 20 on the substrate 11 may not overlap.

The third mask layer 600 may be etched in the third developing region 6011 by a non-isotropic etching process, and the etched region may expose the sacrificial layer 2, thereby forming a third mask pattern on the third mask layer 600, which may have a stripe shape, and an orthographic projection of the initial bit line isolation structure 122 on the substrate 11 does not overlap with an orthographic projection of the third mask pattern on the substrate 11.

After the etching process is completed, the third photoresist layer 601 may be removed by cleaning with a cleaning solution or by ashing, so that the third mask layer 600 having the third mask pattern is not covered by the third photoresist layer 601.

The sacrificial layer 2 is anisotropically etched using the third mask layer 600 having the third mask pattern as a mask and using the substrate 11 or the insulating dielectric layer 700 as an etch stop layer to form the insulating window 202. When the number of intermediate bit line structures 200 is plural, at least one insulating window 202 is formed between two adjacent intermediate bit line structures 200. In the embodiment of the present disclosure, the structure after step S170 is completed is shown in fig. 15.

In step S180, an insulating material 410 is filled in the insulating window 202 to form an insulating layer 4.

As shown in fig. 16, the insulating material 410 may be deposited in the insulating window 202 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, and the insulating material 410 may be simultaneously deposited on the surface of the sacrificial layer 2 until the insulating window 202 is filled for the convenience of the process.

Subsequently, the insulating material 410 may be etched back by a dry etching process, thereby removing the insulating material 410 located on the surface of the sacrificial layer 2, and making the top of the insulating material 410 located in the insulating window 202 flush with the top of the sacrificial layer 2, the insulating material 410 remaining in the insulating window 202 may be defined as the insulating layer 4. In the embodiment of the present disclosure, the structure after step S180 is completed is shown in fig. 17.

In some embodiments of the present disclosure, insulating material 410 may be an acid-resistant material, for example, it may be silicon nitride, and of course, insulating material 410 may also be other materials, and specific materials of insulating material 410 are not particularly limited herein.

As shown in fig. 2, in step S150, the sacrificial layer is removed to form a first contact window on at least one side of the intermediate bit line structure.

The sacrificial layer 2 may be removed after the insulating layer 4 is formed, for example, the sacrificial layer 2 may be selectively etched by a wet etching process so as to remove the sacrificial layer 2, and after the sacrificial layer 2 is removed, a gap between the intermediate bit line structure 200 and the insulating layer 4 may be defined as the first contact window 203. When the number of the second doped regions is two, each second doped region forms a first contact window 203, and the two first contact windows 203 may be located at two sides of the intermediate bit line structure 200 and may expose the two second doped regions. In the embodiment of the present disclosure, the structure after step S150 is completed is shown in fig. 18.

For example, the sacrificial layer 2 may be selectively etched using an acidic solution. The acidic solution may be hydrofluoric acid, for example, buffered hydrofluoric acid (BHF), 49% hydrofluoric acid or dilute hydrofluoric acid (DHF), and when DHF is used as the acidic solution, the formulation ratio of hydrofluoric acid to deionized water may be 1:1 to 1:10. The kind, proportion, concentration, etc. of the acidic solution are not particularly limited herein.

It should be noted that, in the process of removing the sacrificial layer 2, the insulating dielectric layer 700 located at the bottom of the sacrificial layer 2 may be removed at the same time, so that the substrate 11 at the bottom of the sacrificial layer 2 is exposed, and a space formed after removing the sacrificial layer 2 and the insulating dielectric layer 700 may be defined as the first contact window 203, as shown in fig. 19.

As shown in fig. 2, in step S160, a conductive contact structure 3 is formed in the first contact window 203, and the conductive contact structure 3 is electrically connected to the second doped region.

Conductive contact structure 3 may be located on one or both sides of intermediate bit line structure 200, which may be used in connection with a capacitive contact, which may act as a storage node contact plug. For example, the conductive contact structure 3 may include a diffusion barrier layer 31 and a conductive layer 32, where the diffusion barrier layer 31 may cover the periphery of the conductive layer 32, and the diffusion barrier layer 31 may prevent ions in the conductive layer 32 from diffusing to other surrounding layers, which helps to improve structural stability. In the embodiment of the present disclosure, the structure after step S160 is completed is shown in fig. 20.

The conductive contact structure 3 may be formed in the first contact window 203 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or the like, and of course, the conductive contact structure 3 may be formed by other methods, and the forming method of the conductive contact structure 3 is not limited in particular.

In an exemplary embodiment of the present disclosure, forming the conductive contact structure 3 within the first contact window 203 (i.e., step S160) may include steps S510-S540, wherein:

In step S510, a contact plug material layer 310 is filled in the first contact window 203, and the contact plug material layer 310 contacts with the surface of the second doped region and fills the first contact window 203.

The contact plug material layer 310 may be a conductive material, which may be polysilicon, for example. The contact plug material layer 310 may be filled in the first contact window 203 by a vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, thermal evaporation, atomic layer deposition, or other processes, however, other processes may be used to fill the contact plug material layer 310, which are not further described herein. In order to accurately control the thickness of the contact plug material layer 310 later, the contact plug material layer 310 may be filled with at least the first contact window 203 during the process of filling the contact plug material layer 310, and in this process, the contact plug material layer 310 may be simultaneously deposited on top of the intermediate bit line structure 200 and the insulating layer 4 for process convenience. In the embodiment of the present disclosure, the structure after step S510 is completed is shown in fig. 21.

In step S520, the contact plug material layer 310 is selectively etched, so that the top of the contact plug material layer 310 is lower than the surface of the protection layer 13 near the substrate 11.

The contact plug material layer 310 may be selectively etched by dry etching, thereby removing the contact plug material layer 310 on top of the insulating layer 4 and the intermediate bit line structure 200, and etching a portion of the contact plug material layer 310 within the first contact window 203. It should be noted that, during the dry etching, since the front projection of the initial bit line isolation structure 122 on the substrate 11 is within the front projection of the protective layer 13 on the substrate 11, i.e., the width of the protective layer 13 is greater than the width of the initial bit line isolation structure 122 at the bottom thereof, the contact plug material layer 310 located directly under the protective layer 13 may not be etched away, i.e., the contact plug material layer 310 may still remain on the sidewalls of the initial bit line isolation structure 122. In the embodiment of the present disclosure, the structure after step S520 is completed is shown in fig. 22.

In step S530, the remaining contact plug material layer 310 and the intermediate bit line isolation structure 20 are etched to form a contact plug 5, a target bit line isolation structure and a second contact window 2031, wherein the tops of the first isolation layer 1222, the second isolation layer 1223 and the third isolation layer 1224 remaining in the target bit line isolation structure are higher than the tops of the bit line conductive structure 121 and the tops of the remaining contact plug material layer 310, and the target bit line isolation structure and the bit line conductive structure 121 form a target bit line structure 6.

The remaining contact plug material layer 310 may be etched by a wet etching process, and only the contact plug material layer 310 of a predetermined thickness remains, thereby forming the contact plug 5. The preset thickness may be set according to actual production requirements, and is not particularly limited herein. In this process, in order to ensure that the contact plug material layer 310 on the sidewall to be exposed in the intermediate bit line isolation structure 20 is completely removed, thereby reducing the risk of subsequent short circuits, a portion of the film layer of the intermediate bit line isolation structure 20 may be removed at the same time; compared to the embodiment without removing part of the film layer of the intermediate bit line isolation structure 20, the space of the second contact window 2031 can be enlarged after removing part of the film layer of the intermediate bit line isolation structure 20 in this embodiment, which is helpful to reduce the resistance of the conductive contact structure 3 formed in the second contact window 2031. In the embodiment of the present disclosure, the structure after step S530 is completed is shown in fig. 23.

For example, during the wet etching process, the third isolation layer 1224 partially located on the sidewall of the bit line conductive structure 121 may be etched at the same time; alternatively, during the wet etching process, the third isolation layer 1224 and the second isolation layer 1223 partially located on the sidewalls of the bit line conductive structure 121 may be etched at the same time; alternatively, during the wet etching process, the third isolation layer 1224, the second isolation layer 1223 and the first isolation layer 1222 partially located on the sidewall of the bit line conductive structure 121 may be etched at the same time; of course, in the wet etching process, the third isolation layer 1224, the second isolation layer 1223 and the first isolation layer 1222 partially located on the sidewall of the bit line conductive structure 121 may be etched at the same time, and the insulating cover layer 1221 may be thinned.

It should be noted that, after wet etching, the tops of the remaining first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may be higher than the tops of the bit line conductive structures 121 and the tops of the remaining contact plug material layers 310, so as to ensure an insulating effect between the bit line conductive structures 121 and the contact plug material layers 310 or the conductive contact structures 3 formed later, reduce the risk of short circuit, and help to improve the product yield.

In step S540, a conductive contact structure 3 is formed in the second contact window 2031, and the conductive contact structure 3 extends from the second contact window 2031 to the top of the target bit line structure 6 on one side thereof.

With continued reference to fig. 20, a conductive contact structure 3 may be formed within the second contact window 2031, the conductive contact structure 3 may be in contact connection with the contact plug material layer 310, and further connected to the second doped region through the contact plug material layer 310, and an end thereof remote from the contact plug material layer 310 may extend from the second contact window 2031 to a top of the target bit line structure 6 on one side thereof. In this process, since the top of the target bit line isolation structure is higher than the top of the bit line conductive structure 121, a higher isolation barrier is formed between the conductive contact structure 3 and the bit line conductive structure 121, so that the insulation effect can be enhanced, and the risk of short circuit between the conductive contact structure 3 and the bit line conductive structure 121 can be reduced.

In an exemplary embodiment of the present disclosure, forming the conductive contact structure 3 within the second contact window 2031 (i.e., step S540) may include steps S541-S543, wherein:

in step S541, a diffusion barrier layer 31 is formed to be attached to the surface of the structure formed by the insulating layer 4, the target bit line isolation structure and the contact plug 5.

The diffusion barrier layer 31 may be formed on the surface of the structure formed by the insulating layer 4, the target bit line isolation structure, and the contact plug 5 together by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or the like. The material of the diffusion barrier layer 31 may be titanium nitride, which can prevent ions in the conductive layer 32 formed later from diffusing into the insulating layer 4, the target bit line isolation structure and the contact plug 5 through the diffusion barrier layer 31, thereby contributing to improving structural stability and reliability.

In step S542, a conductive layer 32 is formed on the surface of the diffusion barrier layer 31, and the conductive layer 32 fills the second contact window 2031.

The conductive layer 32 may be formed on the surface of the diffusion barrier layer 31 by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or the like, and in order to precisely control the shape and thickness of the conductive layer 32, the conductive layer 32 may be at least filled with the second contact window 2031, that is, the deposition may be stopped after the conductive layer 32 is filled with the second contact window 2031. The material of the conductive layer 32 may be a metal material, for example, tungsten, but of course, may be other types of materials, as long as the conductive property is strong, and the material of the conductive layer 32 is not particularly limited. In the embodiment of the present disclosure, the structure after step S542 is completed is shown in fig. 24.

In step S543, the diffusion barrier layer 31 and the conductive layer 32 are etched, so that the diffusion barrier layers 31 corresponding to the adjacent second contact windows 2031 are disconnected from each other, and the conductive layers 32 corresponding to the adjacent second contact windows 2031 are disconnected from each other.

The diffusion barrier layers 31 and the conductive layers 32 can be selectively etched, so that the diffusion barrier layers 31 corresponding to the adjacent second contact windows 2031 are disconnected from each other and are not interfered with each other, the risk of short circuit between the diffusion barrier layers 31 in the adjacent second contact windows 2031 is reduced, and the product yield is improved; meanwhile, the conductive layers 32 corresponding to the adjacent second contact windows 2031 can be disconnected from each other and not interfere with each other, so that the risk of short circuit between the conductive layers 32 in the adjacent second contact windows 2031 is reduced, and the product yield can be further improved.

The contact plug 5, diffusion barrier 31 and conductive layer 32 may together form a storage node contact plug, which may act as a contact structure for a capacitor in order to store charge collected in the capacitor. In the embodiment of the present disclosure, the structure after completing step S543 is shown in fig. 20 and 25, where fig. 20 is a schematic view taken along aa direction in fig. 25.

It should be noted that although the steps of the method of forming a semiconductor structure in the present disclosure are depicted in a particular order in the figures, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

The embodiments of the present disclosure also provide a semiconductor structure that may be formed by the method of forming a semiconductor structure in any of the embodiments described above. Fig. 20 and 25 illustrate schematic views of a semiconductor structure of the present disclosure, which may include a substrate 11, a target bit line structure 6, and a conductive contact structure 3, as illustrated in fig. 20 and 25, wherein:

the substrate comprises an active region, wherein the active region comprises a first doped region and a second doped region;

The target bit line structure 6 is located on the substrate 11, the target bit line structure 6 comprises a bit line conductive structure and a target bit line isolation structure, the bit line conductive structure is electrically connected with the first doped region, the target bit line isolation structure covers the top and the side wall of the bit line conductive structure, the target bit line isolation structure sequentially comprises a first part and a second part from top to bottom, and the orthographic projection of the second part on the substrate 11 is located in the orthographic projection of the first part on the substrate 11;

the conductive contact structure 3 is located at least on one side of the target bit line structure 6 and is electrically connected to the second doped region.

According to the semiconductor structure, the bit line conducting structure can be insulated and protected through the target bit line isolation structure, the risk of short circuit or coupling between the bit line conducting structure and other surrounding structures is reduced, and the product yield is improved. Meanwhile, since the orthographic projection of the second portion of the target bit line isolation structure on the substrate 11 is located within the orthographic projection of the first portion on the substrate 11, that is, the width of the first portion is greater than that of the second portion, the thickness of the insulating structure between the conductive contact structures 3 formed subsequently can be increased through the design of the first portion, the risk of short circuit between the adjacent conductive contact structures 3 can be reduced, and the product yield can be further improved.

In an exemplary embodiment of the present disclosure, the target bit line isolation structure may include an insulating capping layer 1221, a first isolation layer 1222, a second isolation layer 1223, a third isolation layer 1224, and a protection layer 13, where the insulating capping layer 1221 is located on top of the bit line conductive structure 121, the first isolation layer 1222 is attached to a sidewall of the structure formed by the bit line conductive structure 121 and the insulating capping layer 1221, and the thickness of the first isolation layer 1222 may be 2nm to 4nm, for example, it may be 2nm, 3nm, 4nm, or the like; the second isolation layer 1223 covers the surface of the first isolation layer 1222, and may have a thickness of 1nm to 3nm, for example, 1nm, 2nm, 3nm, or the like; the third isolation layer 1224 is located on the surface of the structure formed by the first isolation layer 1222, the second isolation layer 1223 and the insulating cover layer 1221, and its thickness may be 4nm to 6nm, for example, it may be 4nm, 5nm or 6 nm. Of course, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may have other thicknesses, and the thicknesses of the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 are not particularly limited.

The protective layer 13 may be on top of the insulating cover layer 1221, and the material of the protective layer 13 may be an insulating acid-resistant material, so as to reduce consumption of the protective layer 13 during subsequent wet etching. For example, the material of the protection layer 13 may be silicon nitride.

The protective layer 13 may serve as a first portion of a target bit line isolation structure, the second portion of the target bit line isolation structure may include at least an insulating cap layer 1221, and in one embodiment, the insulating cap layer 1221, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 under the protective layer 13 may serve as a second portion of the target bit line isolation structure, an orthographic projection of the insulating cap layer 1221, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 on the substrate 11 is located within an orthographic projection of the protective layer 13 on the substrate 11, and the protective layer 13 and the insulating cap layer 1221, the first isolation layer 1222, the second isolation layer 1223, and the third isolation layer 1224 may together constitute the target bit line isolation structure in a "T-shape" (i.e., a cross-section of the first portion and the second portion of the target bit line isolation structure is in a T-shape in a direction perpendicular to the substrate 11). The design of the "T-shaped" target bit line isolation structure may help to increase the thickness of the insulating structure between the subsequently formed conductive contact structures 3, and may reduce the risk of shorting between adjacent conductive contact structures 3.

In some embodiments of the present disclosure, the number of target bit line structures 6 may be plural, the plurality of target bit line structures 6 may be distributed on the substrate 11 at intervals, and each target bit line structure 6 may be disposed in an insulating manner.

For example, the semiconductor structure of the present disclosure may further include an insulating layer 4, and the insulating layer 4 may be located at least at one side of the target bit line structure 6, and when the number of target bit line structures 6 is plural, the insulating layer 4 may be located between adjacent target bit line structures 6. The material of the insulating layer 4 may be an acid-resistant material, for example, it may be silicon nitride, and of course, the material of the insulating layer 4 may also be other materials, and the specific material of the insulating layer 4 is not particularly limited herein.

In an exemplary embodiment of the present disclosure, the insulating layer 4 is spaced apart from the target bit line structure 6, and a space therebetween may serve as the first contact window 203, the first contact window 203 may expose a surface of the second doped region, and the conductive contact structure 3 may be at least partially located within the first contact window 203 and may be connected to the second doped region. The conductive contact structure 3 may be used for contact connection with a capacitor and may serve as a storage node contact plug for the capacitor. For example, the conductive contact structure 3 may include a diffusion barrier layer 31 and a conductive layer 32, where the diffusion barrier layer 31 may cover the periphery of the conductive layer 32, and the diffusion barrier layer 31 may prevent ions in the conductive layer 32 from diffusing to other surrounding layers, which helps to improve structural stability. When the number of the second doped regions is two, the two first contact windows 203 may be respectively located at two sides of the target bit line structure 6, and each first contact window 203 exposes one second doped region correspondingly. One conductive contact structure 3 can be correspondingly formed in each first contact window, and two conductive contact structures 3 can be respectively connected with the corresponding second doped regions.

In one exemplary embodiment of the present disclosure, the semiconductor structure of the present disclosure may further include a contact plug 5, and the contact plug 5 may be located at the bottom of the first contact window 203 and may be in contact connection with the surface of the second doped region. The tops of the first isolation layer 1222, the second isolation layer 1223 and the third isolation layer 1224 are higher than the tops of the bit line conductive structures 121 and the tops of the contact plugs 5, so as to ensure the insulation effect between the bit line conductive structures 121 and the contact plugs 5 or the conductive contact structures 3 formed later, reduce the risk of short circuit, and help to improve the product yield.

The portion of the first contact window 203 not filled by the contact plug 5 is a second contact window 2031, the conductive contact structure 3 may be located in the second contact window 2031, the conductive contact structure 3 may be in contact connection with the contact plug 5 at the bottom of the second contact window 2031, and one end thereof away from the contact plug 5 may extend from the second contact window 2031 to the top of the target bit line structure 6 at one side thereof. In this process, since the top of the target bit line isolation structure is higher than the top of the bit line conductive structure 121, a higher isolation barrier is formed between the conductive contact structure 3 and the bit line conductive structure 121, so that the insulation effect can be enhanced, and the risk of short circuit between the conductive contact structure 3 and the bit line conductive structure 121 can be reduced.

In an embodiment, the diffusion barrier 31 of the conductive contact structure 3 may be attached to the bottom and the sidewall of the second contact window 2031, and extend from the second contact window 2031 to the top of the target bit line structure 6 on one side thereof. The conductive layer 32 may be located on the surface of the diffusion barrier 31.

The embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above embodiments, and specific details, forming processes and beneficial effects thereof have been described in detail in the corresponding semiconductor structure and the forming method of the semiconductor structure, which are not described herein again.

For example, the memory may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (static random access memory, SRAM), or the like. Of course, other storage devices are possible and are not listed here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a sacrificial layer covering the initial semiconductor structure;

2. The method of claim 1, wherein an orthographic projection of the initial bit line isolation structure onto the substrate is located within an orthographic projection of the protective layer onto the substrate.

3. The forming method according to claim 1, characterized in that before removing the sacrifice layer, the forming method further comprises:

4. The method of forming of claim 3, wherein forming the initial bit line structure comprises:

forming a second isolation layer on the surface of the first isolation layer;

5. The method of forming of claim 4, wherein the first contact window exposes a surface of the second doped region, forming a conductive contact structure within the first contact window, comprising:

Filling a contact plug material layer in the first contact window, wherein the contact plug material layer is in contact with the surface of the second doped region and fills the first contact window;

6. The method of forming of claim 5, wherein forming the conductive contact structure within the second contact window comprises:

7. The method of forming of claim 5, wherein a material of the first isolation layer is the same as a material of the third isolation layer, and wherein a material of the third isolation layer is different from a material of the second isolation layer.

8. The method of claim 1, wherein the active region includes two second doped regions, the first doped region is located between the two second doped regions, each of the second doped regions is correspondingly formed with one first contact window, and two first contact windows corresponding to the two second doped regions are respectively located at two sides of the intermediate bit line structure.

9. The method of forming of claim 1, wherein etching the sacrificial layer to form an opening exposing a top of the initial bit line isolation structure comprises:

Forming a first mask layer on the surface of the sacrificial layer;

forming a first photoresist layer on the surface of the first mask layer;

10. The forming method according to claim 1, wherein forming a protective layer in the opening includes:

11. A semiconductor structure, comprising:

12. The semiconductor structure of claim 11, wherein the first and second portions of the target bit line isolation structure are T-shaped in cross-section in a direction perpendicular to the substrate.

13. The semiconductor structure of claim 11, wherein the conductive contact structure extends from one side of the target bit line structure to a top of the target bit line structure.

14. The semiconductor structure of claim 11, wherein the target bit line isolation structure comprises an insulating cap layer, a first isolation layer, a second isolation layer, a third isolation layer, and a protective layer, the insulating cap layer is located on top of the bit line conductive structure, the protective layer is located on top of the insulating cap layer, the first isolation layer is conformally attached to a sidewall of a structure formed by the bit line conductive structure and the insulating cap layer, the second isolation layer is located on a surface of the first isolation layer, the third isolation layer is located on a surface of a structure formed by the first isolation layer, the second isolation layer, and the insulating cap layer, the protective layer is used as the first portion, and the second portion comprises at least the insulating cap layer.

15. The semiconductor structure of claim 14, wherein a material of the first isolation layer is the same as a material of the third isolation layer, and wherein a material of the third isolation layer is different from a material of the second isolation layer.

16. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises:

17. The semiconductor structure of claim 16, wherein the first contact window exposes a surface of the second doped region, the semiconductor structure further comprising:

18. The semiconductor structure of claim 17, wherein the conductive contact structure comprises:

and the conductive layer is positioned on the surface of the barrier layer.

19. The semiconductor structure of claim 11, wherein the active region comprises two second doped regions, the first doped region is located between the two second doped regions, each of the second doped regions is respectively formed with one of the conductive contact structures, and two of the conductive contact structures corresponding to the two second doped regions are respectively located at two sides of the target bit line structure.

20. A memory comprising the semiconductor structure of any of claims 11-19.