CN118334987A - Burn-in control circuit and related device - Google Patents
Burn-in control circuit and related device Download PDFInfo
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- CN118334987A CN118334987A CN202410756044.0A CN202410756044A CN118334987A CN 118334987 A CN118334987 A CN 118334987A CN 202410756044 A CN202410756044 A CN 202410756044A CN 118334987 A CN118334987 A CN 118334987A
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- 238000009966 trimming Methods 0.000 claims abstract description 172
- 238000012360 testing method Methods 0.000 claims abstract description 34
- 238000001514 detection method Methods 0.000 claims abstract description 22
- 230000008439 repair process Effects 0.000 claims description 2
- 238000007664 blowing Methods 0.000 claims 2
- 238000013100 final test Methods 0.000 abstract description 17
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- 230000005669 field effect Effects 0.000 description 8
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- 230000008569 process Effects 0.000 description 6
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 4
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 3
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 3
- 101150110298 INV1 gene Proteins 0.000 description 3
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 3
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- 230000009471 action Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
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- 238000013102 re-test Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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Abstract
The present disclosure provides a programming control circuit and related apparatus. The programming control circuit includes: the programming module comprises a first passage, wherein the first passage comprises a fuse resistor and is used for receiving a trimming code programming voltage at a first end of the first passage under the condition that the trimming code is not programmed in the one-time programmable memory, and determining that the trimming code is not programmed in the one-time programmable memory when the detection current flowing through the first passage is a first preset value; the programming control module is used for providing a programming switch signal for the programming module under the condition that the trimming code is not programmed in the one-time programmable memory, providing the trimming code programming voltage for the one-time programmable memory when the programming switch signal is at a first level, and fusing the fuse resistance to disconnect the trimming code programming voltage and the one-time programmable memory when the programming switch signal is at a second level, so that the test time of the chip in the final test stage is reduced.
Description
Technical Field
The disclosure belongs to the technical field of integrated circuits, and in particular relates to a programming control circuit and a related device.
Background
In electronic devices, the performance of a chip often directly affects whether the electronic device can realize a predetermined function, and errors caused by processes such as chip manufacturing and packaging can cause deviation between an actual test value and a design value of the chip. In order to improve the yield of chip production, a developer usually sets a trimming circuit in the chip. In the final test (FINAL TEST, FT) stage, the trimming code is obtained by calculating the deviation between the actual test value and the design value of the chip, and the trimming code is programmed in the one-time programmable memory, and after all trimming codes are programmed, the write-protection bit is programmed in the one-time programmable memory to prevent the one-time programmable memory from being wrongly programmed. After the chip is electrified, the actual test value of the chip is trimmed by the trimming circuit according to the trimming code, so that the actual test value of the chip can reach the design value, and the chip can have very good consistency when leaving the factory. However, in the final test (FINAL TEST, FT) stage, a part of "bad chips" is screened out, and in order to improve the yield of chip production, the above process needs to be repeated to retest the "bad chips", and the retest time increases with the increase of the trimming number.
Disclosure of Invention
In view of the foregoing, the present disclosure provides a programming control circuit and related device, which are aimed at determining whether a trimming code has been programmed in a one-time programmable memory by detecting a detection current flowing through a first path including a fuse resistor in order to reduce a test time of a chip in a final test stage in case of preventing a one-time programmable memory from being burned by mistake.
According to a first aspect of the present disclosure, there is provided a programming control circuit including:
The programming module comprises a first passage, wherein the first passage comprises a fuse resistor and is used for receiving a trimming code programming voltage at a first end of the first passage under the condition that the trimming code is not programmed in the one-time programmable memory, and the trimming code is determined not to be programmed in the one-time programmable memory when the detection current flowing through the first passage is a first preset value;
And the programming control module is used for providing a programming switch signal for the programming module under the condition that the trimming code is not programmed in the one-time programmable memory, providing the trimming code programming voltage for the one-time programmable memory when the programming switch signal is at a first level, and fusing the fuse resistance to disconnect the trimming code programming voltage and the one-time programmable memory when the programming switch signal is at a second level.
Optionally, the programming module is further configured to receive a test voltage at a first end of the first path and detect a detection current flowing through the first path, determine that the trimming code is not programmed in the one-time programmable memory when the detection current is a first preset value, and determine that the trimming code is programmed in the one-time programmable memory when the detection current is 0.
Optionally, the programming module further includes: the first switch tube and the first resistor, the first passageway still includes first resistor, first resistor with fuse resistance series connection, first resistor parallel connection is in between first passageway end and the second passageway end of first switch tube, the control end of first switch tube receives the switching signal that burns, the first passageway end of first switch tube with the first series connection node of the second end of fuse resistance links to each other with the one-time programmable memory, the first end of fuse resistance is received repair adjustment sign indicating number burns and writes voltage or test voltage.
Optionally, the programming control circuit further includes:
And the programming enabling module is connected with the programming module and the one-time programmable memory and is used for providing a programming enabling signal when the programming switching signal is at a first level and providing the trimming code programming voltage for the one-time programmable memory when the programming enabling signal is valid.
Optionally, the programming enabling module includes: a first inverter and a second switching tube,
The first end of the first inverter receives the programming enabling signal, the second end of the first inverter is connected with the control end of the second switching tube, the first path end of the second switching tube is connected with the first series connection node, the second path end of the second switching tube is connected with the one-time programmable memory, the second path end of the second switching tube is used for providing the trimming code programming voltage for the one-time programmable memory when the programming enabling signal is valid,
The second switching tube is opposite to the first switching tube in conductivity type.
Optionally, the programming enabling module includes: a third switching tube, a fourth switching tube and a second resistor,
The control end of the third switch tube is connected with the first serial connection node, the first end of the second switch tube is connected with the first channel end of the fourth switch tube, the control end of the fourth switch tube is connected with the second serial connection node of the first channel end of the third switch tube and the second end of the second resistor, the second channel end of the fourth switch tube is connected with the one-time programmable memory, the second channel end of the fourth switch tube is used for providing the trimming programming voltage to the one-time programmable memory when the programming enabling signal is effective,
The third switching tube has the same conductivity type as the first switching tube, and the fourth switching tube has the opposite conductivity type as the first switching tube.
Optionally, the programming enabling module includes: a fifth switching tube is arranged on the upper surface of the first switch tube,
The control end of the fifth switching tube receives the programming enabling signal, the second path end of the fifth switching tube is connected with the first series connection node, the first path end of the fifth switching tube is connected with the one-time programmable memory, the first path end of the fifth switching tube is used for providing the trimming code programming voltage for the one-time programmable memory when the programming enabling signal is valid,
The fifth switching tube is opposite to the first switching tube in conductivity type.
Optionally, the programming enabling module includes: a sixth switching tube, a seventh switching tube, a second resistor and a second inverter,
The sixth switching tube is connected in series with the second resistor, the first end of the second inverter receives the programming enabling signal, the second end of the second inverter is connected with the control end of the sixth switching tube, the first end of the second resistor and the first pass end of the seventh switching tube are connected with the first series connection node, the control end of the seventh switching tube is connected with the second series connection node of the first pass end of the sixth switching tube and the second end of the second resistor, the second pass end of the seventh switching tube is connected with the one-time programmable memory, the second pass end of the seventh switching tube is used for providing the trimming programming voltage to the one-time programmable memory when the programming enabling signal is valid,
The sixth switching tube has the same conductivity type as the first switching tube, and the seventh switching tube has the opposite conductivity type to the first switching tube.
Optionally, the programming control module is further configured to provide the programming switch signal to the programming module according to a programming control signal when the trimming code is not programmed in the otp memory.
According to a second aspect of the present disclosure, there is provided a driving circuit of a display panel, including:
a driving current generating circuit for supplying a driving current to the LEDs in the display panel;
a one-time programmable memory;
the trimming circuit is used for providing a trimming signal for trimming the driving current according to the trimming code;
The programming control circuit of any one of the preceding claims, configured to provide a trimming code programming voltage to the one-time programmable memory in order to program a trimming code in the one-time programmable memory in the case that a trimming code is not programmed in the one-time programmable memory, and to blow a fuse resistor to disconnect the trimming code programming voltage and the one-time programmable memory after programming a trimming code in the one-time programmable memory.
According to a third aspect of the present disclosure, there is provided a display device including:
A display panel;
A driving circuit as described above.
According to a fourth aspect of the present disclosure, there is provided a driving chip of a display panel, including:
a driving current generating circuit for supplying a driving current to the LEDs in the display panel;
a one-time programmable memory;
the trimming circuit is used for providing a trimming signal for trimming the driving current according to the trimming code;
The programming control circuit is used for providing the trimming code programming voltage to the one-time programmable memory so as to program the trimming code in the one-time programmable memory in the condition that the trimming code is not programmed in the one-time programmable memory, and fusing a fuse resistor to disconnect the trimming code programming voltage and the one-time programmable memory after programming the trimming code in the one-time programmable memory.
The present disclosure brings the following beneficial effects:
The programming control circuit comprises a programming module and a programming control module, wherein the programming module comprises a first passage, the first passage comprises a fuse resistor, when a detection current flowing through the first passage is a first preset value, it is determined that a trimming code is not programmed in a one-time programmable memory, and when the trimming code is not programmed in the one-time programmable memory, a trimming code programming voltage is received at a first end of the first passage; the programming control module provides a programming switch signal to the programming module when the trimming code is not programmed in the one-time programmable memory, provides a trimming code programming voltage to the one-time programmable memory when the programming switch signal is at a first level, fuses the fuse resistor to disconnect the trimming code programming voltage and the one-time programmable memory when the programming switch signal is at a second level, so that in the case that the one-time programmable memory is prevented from being programmed by mistake, whether the trimming code is programmed in the one-time programmable memory is determined by detecting a detection current flowing through a first path including the fuse resistor, provides the trimming code programming voltage to the one-time programmable memory when the trimming code is not programmed in the one-time programmable memory, and fuses the fuse resistor to disconnect the trimming code programming voltage and the one-time programmable memory after the trimming code is programmed in the one-time programmable memory, further, the test chip is protected from the one-time programmable memory in a final test stage, and the test time is reduced.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and drawings.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a test system provided according to one embodiment of the present disclosure;
Fig. 2 is a schematic diagram of a structure of a programming control circuit 121A according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a structure of a programming control circuit 121B according to an embodiment of the disclosure;
Fig. 4 is a schematic diagram of a structure of a programming control circuit 121C according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a structure of a programming control circuit 121D according to an embodiment of the present disclosure;
Fig. 6 is a schematic diagram of a structure of a programming control circuit 121E according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a structure of a programming control circuit 121F according to an embodiment of the present disclosure.
Detailed Description
Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following terms are used herein:
One-time programmable memory (One-Time Programmable Memory, OTP) is a memory that can be programmed only once. Once the data is written into the OTP, it cannot be modified or erased again. This feature makes OTP very useful when sensitive data such as a one-time configuration or key needs to be stored, providing greater security and tamper resistance.
Fig. 1 shows a schematic structural diagram of a test system provided according to one embodiment of the present disclosure. As shown in fig. 1, a test system 1000 provided in an embodiment of the present disclosure includes: a display device 100 and a tester 200. The display device 100 includes a display panel 110, a driving circuit (may also be referred to as a display driving chip) 120. The driving circuit 120 includes a programming control circuit 121, a one-time programmable memory 122, a trimming circuit 123, and a driving current generating circuit 124. The display panel 110 of the display device 100 is exemplified by, for example, a liquid crystal display panel (i.e., LCD display panel), a light emitting diode display panel (i.e., LED display panel), an organic light emitting diode display panel (i.e., OLED display panel), an active matrix organic light emitting diode display panel (i.e., AMOLED display panel), an organic electroluminescent display panel (i.e., OLED display panel), a plasma display panel (i.e., PDP display panel), and a phosphor display panel (i.e., CRT display panel).
In some embodiments, a plurality of pixel units Px arranged in an array are disposed in the display panel 110. The driving current generating circuit 124 supplies a driving current to the LEDs in the pixel unit Px. The otp memory 122 is used for storing the trimming code. It should be noted that, when the trimming code is required to perform trimming processing on a parameter in the driving circuit 120 (may be any parameter in the driving circuit 120, for example, a driving current provided by an LED in the pixel unit Px), the trimming code corresponding to the parameter in the driving circuit 120. In one example, when the driving circuit 120 performs the final test (FINAL TEST, FT) before shipment, if it is necessary to perform the trimming process on the driving circuit 120, the trimming code may be obtained by calculating a deviation between an actual test value and a design value of a parameter of the driving circuit 120 (e.g., a driving current provided to the LED in the pixel unit Px).
In some embodiments, the programming control circuit 121 determines whether the TRIM code has been programmed in the one-time programmable memory 122, provides the TRIM code programming voltage TRIM to the one-time programmable memory 122 in order to program the TRIM code in the one-time programmable memory 122 in the event that the TRIM code has not been programmed in the one-time programmable memory 122, and fuses the fuse resistor fuse to disconnect the TRIM code programming voltage TRIM and the one-time programmable memory 122 after programming the TRIM code in the one-time programmable memory 122. In some embodiments, after the display device 100 is powered up in the case that the trimming code has been programmed in the otp memory 122, the trimming circuit 123 may obtain the trimming code from the otp memory 122 and provide a trimming signal for trimming the actual test value of the parameter (e.g., the driving current provided to the LED in the pixel unit Px) in the driving circuit 120 according to the trimming code. In some embodiments, the driving current generating circuit 124 may trim the actual test value of the driving current provided to the LED in the pixel unit Px according to the trimming signal so that the driving current can reach the design value.
The programming control circuit 121 may be disposed outside the driving circuit 120.
Fig. 2 is a schematic diagram of a structure of a programming control circuit 121A according to an embodiment of the present disclosure. In some embodiments, as shown in fig. 2, the programming control circuit 121A includes a programming module 220 and a programming control module 210.
In some embodiments, the programming module 220 includes a first path including a fuse resistor fuse and a first resistor R1, the fuse resistor fuse and the first resistor R1 being connected in series. In some embodiments, the programming module 220 further includes a first switching transistor (e.g., an N-type field effect transistor) M1. The resistance of the first resistor R1 is much larger than that of the fuse resistor fuse. The first resistor R1 is connected in parallel between a first path terminal (e.g., drain terminal) and a second path terminal (e.g., source terminal) of the first switching transistor M1. The first series connection node Q of the first pass terminal of the first switching tube M1 and the second terminal of the fuse resistor fuse is connected to the one-time programmable memory 122. The first end of the first resistor R1 is connected with the first series connection node Q, and the second end of the first resistor R1 and the second path of the first switch tube M1 are grounded. The first end of the fuse resistor fuse is the first end of the first path.
Referring back to fig. 1, as shown in fig. 1, the tester 100 tests parameters in the drive circuit 120 during the final test (FINAL TEST, FT) phase. As shown in fig. 1 and 2, in some embodiments, the detection voltage Vtest is provided to the first end of the first path by the tester 100. The detection voltage Vtest may be provided by connecting the corresponding chip pin to a detection voltage source. In some embodiments, the test machine 100 detects the test current Itest flowing through the first path while the test voltage Vtest is provided to the first end of the first path, and determines that the trimming code is not programmed in the otp memory 122 when the test current Itest is a first preset value (e.g., approximately the test voltage Vtest/the first resistor R1). When the detection current Itest is 0, it is determined that the trimming code has been programmed in the one-time programmable memory 122. In some embodiments, in the case that it is determined that the trimming code has been programmed in the otp memory 122, the trimming circuit 123 reads the trimming code from the otp memory 122, outputs a trimming signal according to the trimming code, and the driving current generating circuit 124 outputs the driving current Iout after trimming the actual test value of the driving current Iout according to the trimming signal. It can be appreciated that the trimmed driving current Iout can reach a design value, and the driving circuit 120 can have very good consistency when shipped from the factory.
In some embodiments, the trim code programming voltage Vfuse is provided to the first end of the first path by the tester 100 in the event that the trim code is not programmed in the one-time programmable memory 122. The trimming code programming voltage Vfuse can be provided by connecting the corresponding chip pins to a trimming code programming voltage source, and the trimming code programming voltage source needs to have the capability of outputting more than 200 mA current. The trimming code writing voltage Vfuse and the detecting voltage Vtest can be provided through the same chip pin. In some embodiments, the programming control module 210 provides the programming switch signal wr_rpo to the programming module 220 if the trimming code is not programmed in the otp memory 122. The control terminal (e.g., gate terminal) of the first switching transistor M1 receives the write switching signal wr_rpo. When the write switch signal wr_rpo is at the first level (e.g., '0'), the first switch tube M1 is turned off, and the resistance of the first resistor R1 is far greater than the resistance of the fuse resistor fuse, so that the write voltage TRIM provided to the otp memory 122 is approximately the trimming code write voltage Vfuse, so that the trimming code write voltage Vfuse is provided to the otp memory 122, so that the trimming code can be written in the otp memory 122. When the programming switch signal wr_rpo is at the second level (e.g., '1'), the first switching transistor M1 is turned on, and a large current instantaneously flows through the series path of the fuse resistor fuse and the first switching transistor M1, and the fuse resistor fuse is blown, thereby disconnecting the trimming programming voltage Vfuse from the one-time programmable memory 122. The one-time programmable memory 122 is grounded through the first resistor R1, the programming voltage TRIM provided to the one-time programmable memory 122 is approximately 0, the one-time programmable memory 122 cannot be programmed again, and the one-time programmable memory 122 is prevented from being burned by mistake.
It is easy to understand that in the case where the one-time programmable memory 122 is implemented to prevent the false burn, whether the trimming code has been programmed in the one-time programmable memory 122 is determined by detecting the detection current Itest flowing through the first path, in the case where the trimming code has not been programmed in the one-time programmable memory 122, the trimming code programming voltage Vfuse is provided to the one-time programmable memory 122 so that the trimming code can be programmed in the one-time programmable memory 122, and after the trimming code is programmed in the one-time programmable memory 122, the fuse is blown to disconnect the trimming code programming voltage Vfuse and the one-time programmable memory 122, and further, the programming protection bit does not need to be read from the one-time programmable memory 122 in the final test stage, reducing the test time for the chip in the final test stage.
In some embodiments, the programming control module 210 provides the programming switch signal wr_rpo to the programming module 220 according to the programming control signal if the trimming code is not programmed in the otp memory 122. In some embodiments, the programming control module 210 may include any one of a set of AND gates (AND gates) AND NAND gates (NAND gates). Referring back to fig. 2, in fig. 2, taking the example of the programming control module 210 including the AND gate AND, the input terminal of the AND gate AND receives the programming control signal wr_pro1 AND the programming control signal wr_pro2, AND the default values of the programming control signal wr_pro1 AND the programming control signal wr_pro2 are both the first level (e.g., '0'). When the programming control signal wr_pro1 and the programming control signal wr_pro2 are configured to a first level (e.g., '0'), the programming switch signal wr_rpo is at the first level (e.g., '0'), the first switch tube M1 is turned off, and the programming voltage TRIM provided to the otp memory 122 is approximately the trimming code programming voltage Vfuse, thereby providing the trimming code programming voltage Vfuse to the otp memory 122. When the programming control signal wr_pro1 and the programming control signal wr_pro2 are configured to be at the second level (e.g., '1'), the programming switch signal wr_rpo is at the second level (e.g., '1'), the first switching transistor M1 is turned on, and a large current instantaneously flows through the series path of the fuse resistor fuse and the first switching transistor M1, and the fuse resistor fuse is blown, so that the trimming code programming voltage Vfuse cannot be supplied to the one-time programmable memory 122. The one-time programmable memory 122 is grounded through the first resistor R1, the programming voltage TRIM provided to the one-time programmable memory 122 is approximately 0, the one-time programmable memory 122 cannot be programmed again, and the one-time programmable memory 122 is prevented from being burned by mistake.
Fig. 3 is a schematic diagram of a structure of a programming control circuit 121B according to an embodiment of the disclosure. The programming control circuit 121A shown in fig. 2 is substantially the same as the programming control circuit 121B shown in fig. 3. The difference is that the programming control circuit 121B shown in fig. 3 further includes a programming enabling module 230.
In some embodiments, the burn-in enable module 230 is coupled to the burn-in module 220 and the one-time programmable memory 122. The write enable module 230 provides the write enable signal TRIM_EN when the write switch signal WR_RPO is at a first level (e.g., '0'), and provides the trimming code write voltage Vfuse to the one-time programmable memory 122 when the write enable signal TRIM_EN is asserted. In some embodiments, the programming enabling module 230 includes a first inverter INV1 and a second switching transistor (e.g., a P-type field effect transistor) M2. A first end of the first inverter INV1 receives the programming enable signal trim_en, and a second end of the first inverter INV1 is connected to a control end (e.g., a gate end) of the second switching transistor M2. A first pass terminal (e.g., drain terminal) of the second switching tube M2 is connected to the first series connection node Q, and a second pass terminal (e.g., source terminal) of the second switching tube M2 is connected to the otp memory 122. The default value of the programming enable signal trim_en is a first level (e.g., '0'). The second path terminal of the second switching tube M2 provides the trimming and writing voltage Vfuse to the otp memory 122 when the writing enable signal trim_en is valid (e.g., the writing enable signal trim_en is at the second level (e.g., '1'), and controls the trimming and writing voltage Vfuse to be unable to be provided to the otp memory 122 when the writing enable signal trim_en is invalid (e.g., the writing enable signal trim_en is at the first level (e.g., '0'), and the second switching tube M2 is turned off). The second switching tube M1 is opposite to the first switching tube M2 in conductivity type.
Fig. 4 is a schematic diagram of a structure of a programming control circuit 121C according to an embodiment of the disclosure. The programming control circuit 121A shown in fig. 2 is substantially the same as the programming control circuit 121C shown in fig. 4. The difference is that the programming control circuit 121C shown in fig. 4 further includes a programming enabling module 330.
In some embodiments, the burn-in enable module 330 is coupled to the burn-in module 220 and the one-time programmable memory 122. The write enable module 330 provides the write enable signal TRIM_EN when the write switch signal WR_RPO is at a first level (e.g., '0'), and provides the trimming code write voltage Vfuse to the one-time programmable memory 122 when the write enable signal TRIM_EN is asserted. In some embodiments, the programming enable module 330 includes a third switching transistor (e.g., an N-type field effect transistor) M3, a fourth switching transistor (e.g., a P-type field effect transistor) M4, and a second resistor R2. The resistance of the second resistor R2 is much larger than that of the fuse resistor fuse. The third switching tube M3 and the second resistor R2 are connected in series, the control end (e.g., gate end) of the third switching tube M3 receives the programming enable signal trim_en, and the first end of the second resistor R2 and the first path end (e.g., drain end) of the fourth switching tube M4 are connected to the first series connection node Q. A control terminal (e.g., a gate terminal) of the fourth switching tube M4 is connected to a second series connection node N of a first path terminal (e.g., a drain terminal) of the third switching tube M3 and a second terminal of the second resistor R2. The second pass terminal (e.g., source terminal) of the fourth switching tube M4 is connected to the otp memory 122. The default value of the programming enable signal trim_en is a first level (e.g., '0'). The second path terminal (e.g., source terminal) of the fourth switching tube M4 provides the trimming programming voltage Vfuse to the one-time programmable memory 122 when the programming enable signal trim_en is valid (e.g., the programming enable signal trim_en is at the second level (e.g., '1'), the third switching tube M3 and the fourth switching tube M4 are turned on), and controls the trimming programming voltage Vfuse not to be provided to the one-time programmable memory 122 when the programming enable signal trim_en is invalid (e.g., the programming enable signal trim_en is at the first level (e.g., '0'), the third switching tube M3 and the fourth switching tube M4 are turned off). The third switching tube M3 has the same conductivity type as the first switching tube M1, and the fourth switching tube M4 has the opposite conductivity type as the first switching tube M1.
Fig. 5 is a schematic diagram of a structure of a programming control circuit 121D according to an embodiment of the present disclosure. In some embodiments, as shown in fig. 5, the programming control circuit 121D includes a programming module 420 and a programming control module 410.
In some embodiments, the programming module 420 includes a first path including a fuse resistor fuse and a first resistor R1, the fuse resistor fuse and the first resistor R1 being connected in series. In some embodiments, the programming module 220 further includes a first switching transistor (e.g., a P-type field effect transistor) M1. The resistance of the first resistor R1 is much larger than that of the fuse resistor fuse. The first resistor R1 is connected in parallel to a first path terminal (e.g., source terminal) and a second path terminal (e.g., drain terminal) of the first switching transistor M1. The first series connection node Q of the first pass terminal of the first switching tube M1 and the second terminal of the fuse resistor fuse is connected to the one-time programmable memory 122. The first terminal of the first resistor R1 is connected to the first series connection node Q. The second path terminal of the first switching tube M1 and the second terminal of the first resistor R1 are connected to the power supply voltage VDD1. The first end of the fuse resistor fuse is the first end of the first path.
Referring back to fig. 1, as shown in fig. 1, the tester 100 tests parameters in the drive circuit 120 during the final test (FINAL TEST, FT) phase. As shown in fig. 1 and 5, in some embodiments, the detection voltage Vtest is provided to the first end of the first path by the tester 100. The detection voltage Vtest may be provided by connecting the corresponding chip pin to a detection voltage source. In some embodiments, the test current Itest flowing through the first path is detected by the test machine 100 with the test voltage Vtest provided to the first end of the first path, and when the test current Itest is a first value (e.g., approximately (power supply voltage VDD 1-test voltage Vtest)/first resistor R1), it is determined that the trimming code is not programmed in the one-time programmable memory 122. When the detection current Itest is 0, it is determined that the trimming code has been programmed in the one-time programmable memory 122. In some embodiments, in the case that it is determined that the trimming code has been programmed in the otp memory 122, the trimming circuit 123 reads the trimming code from the otp memory 122, outputs a trimming signal according to the trimming code, and the driving current generating circuit 124 outputs the driving current Iout after trimming the actual test value of the driving current Iout according to the trimming signal. It can be appreciated that the trimmed driving current Iout can reach a design value, and the driving circuit 120 can have very good consistency when shipped from the factory.
In some embodiments, the trim code programming voltage Vfuse is provided to the first end of the first path by the tester 100 in the event that the trim code is not programmed in the one-time programmable memory 122. The trimming code programming voltage Vfuse can be provided by connecting the corresponding chip pins to a trimming code programming voltage source, and the trimming code programming voltage source needs to have the capability of absorbing more than 200mA current. The power voltage VDD1 is greater than the trimming code programming voltage Vfuse. The trimming code writing voltage Vfuse and the detecting voltage Vtest can be provided through the same chip pin. In some embodiments, the programming control module 410 provides the programming switch signal wr_rpo to the programming module 420 if the trimming code is not programmed in the otp memory 122. The control terminal (e.g., gate terminal) of the first switching transistor M1 receives the write switching signal wr_rpo. When the write switch signal wr_rpo is at the second level (e.g., '1'), the first switch tube M1 is turned off, and the resistance of the first resistor R1 is far greater than the resistance of the fuse resistor fuse, so that the write voltage TRIM provided to the otp memory 122 is approximately the trimming code write voltage Vfuse, so that the trimming code write voltage Vfuse is provided to the otp memory 122, so that the trimming code can be written in the otp memory 122. When the programming switch signal wr_rpo is at a first level (e.g., '0'), the first switching transistor M1 is turned on, and a large current instantaneously flows through a series path of the fuse resistor fuse and the first switching transistor M1, so that the fuse resistor fuse is blown, and the trimming programming voltage Vfuse and the one-time programmable memory 122 are disconnected. The one-time programmable memory 122 is connected with the power supply voltage VDD1 through the first resistor R1, so that the one-time programmable memory 122 cannot be re-programmed, and the one-time programmable memory 122 is prevented from being burned by mistake.
In some embodiments, the programming control module 410 provides the programming switch signal wr_rpo to the programming module 420 according to the programming control signal if the trimming code is not programmed in the otp memory 122. In some embodiments, the programming control module 410 may include any one of a set of AND gates (AND gates) AND NAND gates (NAND gates). Referring back to fig. 5, in fig. 5, taking the example that the programming control module 410 includes a NAND gate NAND, an input terminal of the NAND gate NAND receives the programming control signal wr_pro1 and the programming control signal wr_pro2, and default values of the programming control signal wr_pro1 and the programming control signal wr_pro2 are both the first level (e.g., '0'). When the programming control signal wr_pro1 and the programming control signal wr_pro2 are configured to a first level (e.g., '0'), the programming switch signal wr_rpo is at a second level (e.g., '1'), the first switch tube M1 is turned off, and the programming voltage TRIM provided to the otp memory 122 is approximately the trimming code programming voltage Vfuse, so that the trimming code programming voltage Vfuse is provided to the otp memory 122. When the programming control signal wr_pro1 and the programming control signal wr_pro2 are configured to the second level (e.g., '1'), the programming switch signal wr_rpo is at the first level (e.g., '0'), the first switching transistor M1 is turned on, and a large current instantaneously flows through the series path of the fuse resistor fuse and the first switching transistor M1, and the fuse resistor fuse is blown, thereby disconnecting the trimming code programming voltage Vfuse from the one-time programmable memory 122. The one-time programmable memory 122 is connected with the power supply voltage VDD1 through the first resistor R1, so that the one-time programmable memory 122 cannot be re-programmed, and the one-time programmable memory 122 is prevented from being burned by mistake.
Fig. 6 is a schematic diagram of a structure of a programming control circuit 121E according to an embodiment of the disclosure. The programming control circuit 121D shown in fig. 5 is substantially the same as the programming control circuit 121E shown in fig. 6. The difference is that the programming control circuit 121E shown in fig. 6 further includes a programming enable module 430.
In some embodiments, the burn-in enable module 430 is coupled to the burn-in module 420 and the one-time programmable memory 122. The write enable module 430 provides the write enable signal trim_en when the write switch signal wr_rpo is at a second level (e.g., '1'), and provides the trimming code write voltage Vfuse to the otp memory 122 when the write enable signal trim_en is active. In some embodiments, the programming enable module 430 includes a fifth switching transistor (e.g., an N-type field effect transistor) M5. The control terminal (e.g., gate terminal) of the fifth switching transistor M5 receives the programming enable signal trim_en, and the second path terminal (e.g., source terminal) of the fifth switching transistor M5 is connected to the first series connection node Q. A first pass terminal (e.g., drain terminal) of the fifth switching transistor M5 is connected to the otp memory 122. The default value of the programming enable signal trim_en is a first level (e.g., '0'). The first pass terminal of the fifth switch tube M5 provides the trimming programming voltage Vfuse to the otp memory 122 when the programming enable signal trim_en is valid (e.g., the programming enable signal trim_en is at the second level (e.g., '1'), and controls the trimming programming voltage Vfuse to be unable to be provided to the otp memory 122 when the programming enable signal trim_en is invalid (e.g., the programming enable signal trim_en is at the first level (e.g., '0'), and the fifth switch tube M5 is turned off). The first switching transistor M1 is opposite to the fifth switching transistor M5 in conductivity type.
Fig. 7 is a schematic diagram of a structure of a programming control circuit 121F according to an embodiment of the present disclosure. The programming control circuit 121D shown in fig. 5 is substantially the same as the programming control circuit 121F shown in fig. 7. The difference is that the programming control circuit 121F shown in fig. 7 further includes a programming enabling module 530.
In some embodiments, the burn-in enable module 530 is coupled to the burn-in module 420 and the one-time programmable memory 122. The write enable module 530 provides the write enable signal trim_en when the write switch signal wr_rpo is at a second level (e.g., '1'), and provides the trimming code write voltage Vfuse to the otp memory 122 when the write enable signal trim_en is active. In some embodiments, the programming enabling module 530 includes a sixth switching transistor (e.g., a P-type field effect transistor) M6, a seventh switching transistor (e.g., an N-type field effect transistor) M7, a second resistor R2, and a second inverter INV2. The resistance of the second resistor R2 is much larger than that of the fuse resistor fuse. The sixth switching tube M6 and the second resistor R2 are connected in series, the first end of the second inverter INV2 receives the programming enable signal trim_en, the second end of the second inverter INV2 is connected to the control end (e.g., the gate end) of the sixth switching tube M6, and the first end of the second resistor R2 and the first path end (e.g., the source end) of the seventh switching tube M7 are connected to the first series connection node Q. The control terminal (e.g., gate terminal) of the seventh switching tube M7 is connected to the second series connection node N of the first path terminal (e.g., source terminal) of the sixth switching tube M6 and the second terminal of the second resistor R2. The second path terminal (e.g., drain terminal) of the sixth switching tube M6 is connected to the power supply voltage VDD 2. The second path terminal (e.g., drain terminal) of the seventh switching tube M7 is connected to the otp memory 122. The default value of the programming enable signal trim_en is a first level (e.g., '0'). The second path terminal of the seventh switching tube M7 provides the trimming programming voltage Vfuse to the one-time programmable memory 122 when the programming enable signal trim_en is valid (e.g., the programming enable signal trim_en is at the second level (e.g., '1'), the sixth switching tube M6 and the seventh switching tube M7 are turned on), and controls the trimming programming voltage Vfuse to be unable to be provided to the one-time programmable memory 122 when the programming enable signal trim_en is invalid (e.g., the programming enable signal trim_en is at the first level (e.g., '0'), the sixth switching tube M6 and the seventh switching tube M7 are turned off). The sixth switching tube M6 has the same conductivity type as the first switching tube M1, and the seventh switching tube M7 has the opposite conductivity type to the first switching tube M1.
In summary, the programming control circuit provided by the present disclosure determines whether the trimming code has been programmed in the one-time programmable memory by detecting a detection current flowing through a first path including a fuse resistor when the one-time programmable memory is implemented to prevent the error programming, provides a trimming code programming voltage to the one-time programmable memory so that the trimming code can be programmed in the one-time programmable memory when the trimming code is not programmed in the one-time programmable memory, and fuses the resistor to disconnect the trimming code programming voltage and the one-time programmable memory after the trimming code is programmed in the one-time programmable memory, thereby eliminating the need to read programming protection bits from the one-time programmable memory in a final test stage, and reducing test time for a chip in the final test stage.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
These embodiments are not all details described in detail above in accordance with the present disclosure, nor are they intended to limit the disclosure to the particular embodiments described. The above description is only of the preferred embodiments of the present disclosure, and it is not intended to limit the present disclosure, but it is intended to cover all modifications, equivalents, or improvements within the spirit and principles of the present disclosure as may be made by those skilled in the art without departing from the scope of the present disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, to thereby enable others skilled in the art to best utilize the disclosure and its modifications as are suited to the particular use contemplated.
Claims (12)
1. A programming control circuit comprising:
The programming module comprises a first passage, wherein the first passage comprises a fuse resistor and is used for receiving a trimming code programming voltage at a first end of the first passage under the condition that the trimming code is not programmed in the one-time programmable memory, and the trimming code is determined not to be programmed in the one-time programmable memory when the detection current flowing through the first passage is a first preset value;
And the programming control module is used for providing a programming switch signal for the programming module under the condition that the trimming code is not programmed in the one-time programmable memory, providing the trimming code programming voltage for the one-time programmable memory when the programming switch signal is at a first level, and fusing the fuse resistance to disconnect the trimming code programming voltage and the one-time programmable memory when the programming switch signal is at a second level.
2. The programming control circuit of claim 1, wherein the programming module is further configured to receive a test voltage at a first end of the first path and detect a detection current flowing through the first path, determine that the trimming code is not programmed in the one-time programmable memory when the detection current is a first preset value, and determine that the trimming code is programmed in the one-time programmable memory when the detection current is 0.
3. The programming control circuit of claim 2, wherein the programming module further comprises: the first switch tube and the first resistor, the first passageway still includes first resistor, first resistor with fuse resistance series connection, first resistor parallel connection is in between first passageway end and the second passageway end of first switch tube, the control end of first switch tube receives the switching signal that burns, the first passageway end of first switch tube with the first series connection node of the second end of fuse resistance links to each other with the one-time programmable memory, the first end of fuse resistance is received repair adjustment sign indicating number burns and writes voltage or test voltage.
4. The programming control circuit of claim 3, wherein the programming control circuit further comprises:
And the programming enabling module is connected with the programming module and the one-time programmable memory and is used for providing a programming enabling signal when the programming switching signal is at a first level and providing the trimming code programming voltage for the one-time programmable memory when the programming enabling signal is valid.
5. The programming control circuit of claim 4, wherein the programming enable module comprises: a first inverter and a second switching tube,
The first end of the first inverter receives the programming enabling signal, the second end of the first inverter is connected with the control end of the second switching tube, the first path end of the second switching tube is connected with the first series connection node, the second path end of the second switching tube is connected with the one-time programmable memory, the second path end of the second switching tube is used for providing the trimming code programming voltage for the one-time programmable memory when the programming enabling signal is valid,
The second switching tube is opposite to the first switching tube in conductivity type.
6. The programming control circuit of claim 4, wherein the programming enable module comprises: a third switching tube, a fourth switching tube and a second resistor,
The control end of the third switch tube is connected with the first serial connection node, the first end of the second switch tube is connected with the first channel end of the fourth switch tube, the control end of the fourth switch tube is connected with the second serial connection node of the first channel end of the third switch tube and the second end of the second resistor, the second channel end of the fourth switch tube is connected with the one-time programmable memory, the second channel end of the fourth switch tube is used for providing the trimming programming voltage to the one-time programmable memory when the programming enabling signal is effective,
The third switching tube has the same conductivity type as the first switching tube, and the fourth switching tube has the opposite conductivity type as the first switching tube.
7. The programming control circuit of claim 4, wherein the programming enable module comprises: a fifth switching tube is arranged on the upper surface of the first switch tube,
The control end of the fifth switching tube receives the programming enabling signal, the second path end of the fifth switching tube is connected with the first series connection node, the first path end of the fifth switching tube is connected with the one-time programmable memory, the first path end of the fifth switching tube is used for providing the trimming code programming voltage for the one-time programmable memory when the programming enabling signal is valid,
The fifth switching tube is opposite to the first switching tube in conductivity type.
8. The programming control circuit of claim 4, wherein the programming enable module comprises: a sixth switching tube, a seventh switching tube, a second resistor and a second inverter,
The sixth switching tube is connected in series with the second resistor, the first end of the second inverter receives the programming enabling signal, the second end of the second inverter is connected with the control end of the sixth switching tube, the first end of the second resistor and the first pass end of the seventh switching tube are connected with the first series connection node, the control end of the seventh switching tube is connected with the second series connection node of the first pass end of the sixth switching tube and the second end of the second resistor, the second pass end of the seventh switching tube is connected with the one-time programmable memory, the second pass end of the seventh switching tube is used for providing the trimming programming voltage to the one-time programmable memory when the programming enabling signal is valid,
The sixth switching tube has the same conductivity type as the first switching tube, and the seventh switching tube has the opposite conductivity type to the first switching tube.
9. The programming control circuit of claim 4, wherein the programming control module is further configured to provide the programming switch signal to the programming module according to a programming control signal if the trimming code is not programmed in the one-time programmable memory.
10. A driving circuit of a display panel, comprising:
a driving current generating circuit for supplying a driving current to the LEDs in the display panel;
a one-time programmable memory;
the trimming circuit is used for providing a trimming signal for trimming the driving current according to the trimming code;
The programming control circuit of any one of claims 1 to 9, for providing a trimming code programming voltage to the one-time programmable memory in order to program a trimming code in the one-time programmable memory in the case where a trimming code is not programmed in the one-time programmable memory, and for blowing a fuse resistance to disconnect the trimming code programming voltage and the one-time programmable memory after programming a trimming code in the one-time programmable memory.
11. A display device, comprising:
A display panel;
the drive circuit of claim 10.
12. A driving chip of a display panel, comprising:
a driving current generating circuit for supplying a driving current to the LEDs in the display panel;
a one-time programmable memory;
the trimming circuit is used for providing a trimming signal for trimming the driving current according to the trimming code;
The programming control circuit of any one of claims 1 to 9, for providing a trimming code programming voltage to the one-time programmable memory in order to program a trimming code in the one-time programmable memory in the case where a trimming code is not programmed in the one-time programmable memory, and for blowing a fuse resistance to disconnect the trimming code programming voltage and the one-time programmable memory after programming a trimming code in the one-time programmable memory.
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