CN118316765A - Continuous time linear equalization circuit for high-speed data interface - Google Patents

Abstract

The invention relates to a continuous time linear equalization circuit for a high-speed data interface, comprising: a first-stage continuous-time linear equalizer circuit, a second-stage continuous-time linear equalizer circuit, a programmable gain amplifier circuit, and a negative capacitance circuit, which are sequentially connected in series; the first-stage continuous time linear equalizer circuit is used for inputting a high-speed data signal, compensating high-frequency attenuation and intermediate-frequency attenuation in the high-speed data signal, and combining high-frequency gain compensation and intermediate-frequency gain compensation to obtain a first-stage compensation signal; the second-stage continuous time linear equalizer circuit is used for compensating high-frequency attenuation in the first-stage compensation signal to obtain a second-stage compensation signal; the programmable gain amplifier circuit is used for amplifying the second-stage compensation signal, increasing the swing amplitude of the signal and outputting the signal; the negative capacitance circuit is used to generate a negative capacitance to further expand the circuit bandwidth. The continuous time linear equalization circuit provided by the invention can meet the requirements of high-speed data transmission while having small area and low power consumption.

Description

Continuous time linear equalization circuit for high-speed data interface

Technical Field

The invention belongs to the field of time linear equalization circuits, and particularly relates to a continuous time linear equalization circuit for a high-speed data interface.

Background

High-speed wired data interfaces are a key technology for supporting the great improvement of the performance of computers and communication systems. With the rapid development of technologies such as multi-chip modules and core particles in the latter molar age, the demand for short-distance and high-speed wired interfaces is increasing. During data transmission, high frequency components of the signal may be attenuated during transmission due to non-ideal effects of the channel, and an equalizer is required to compensate the signal to ensure signal transmission integrity. Continuous-time linear equalizer (CTLE) is an important equalizer, and the conventional Continuous-time linear equalizer (Current Mode Logic CTLE, CML CTLE) based on current-mode logic has not been able to meet the requirements of high-speed wired interfaces on power consumption and area under advanced technology due to the use of high power supply voltage and passive devices.

CTLE based on conventional current-mode logic architecture is shown in fig. 1, where poles and zero positions of CTLE are controlled by source degeneration impedance. This architecture has been widely adopted in the past few years, but CML-based CTLE fails to provide a power-efficient solution as CMOS process feature sizes shrink and supply voltages decrease, because it requires high supply voltages to maintain the normal operation of the three stacked devices. Meanwhile, the architecture utilizes the passive inductive peaking technology to improve the bandwidth, so that the occupied area is overlarge. In addition, since the power supply voltage is gradually reduced, the output swing of the conventional continuous-time linear equalizer based on the current-mode logic is reduced, so that the requirement of high-speed data transmission is difficult to meet.

Therefore, there is a need for a continuous-time linear equalization circuit that can satisfy high-speed data transmission while having a small area and low power consumption.

Disclosure of Invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a continuous time linear equalization circuit for a high-speed data interface. The technical problems to be solved by the invention are realized by the following technical scheme:

The invention provides a continuous time linear equalization circuit for a high-speed data interface, which is characterized by comprising the following components: a first-stage continuous-time linear equalizer circuit, a second-stage continuous-time linear equalizer circuit, a programmable gain amplifier circuit, and a negative capacitance circuit, which are sequentially connected in series; wherein,

The first-stage continuous time linear equalizer circuit is used for inputting a high-speed data signal, compensating high-frequency attenuation and intermediate-frequency attenuation in the high-speed data signal, and combining high-frequency gain compensation and intermediate-frequency gain compensation to obtain a first-stage compensation signal;

The second-stage continuous time linear equalizer circuit is used for compensating high-frequency attenuation in the first-stage compensation signal to obtain a second-stage compensation signal;

the programmable gain amplifier circuit is used for amplifying the second-stage compensation signal and increasing the swing amplitude of the signal;

The negative capacitance circuit is used for reducing or completely counteracting the load capacitance in the continuous time linear equalization circuit for the high-speed data interface and outputting.

In one embodiment of the invention, the first stage continuous time linear equalizer circuit comprises: the first filter capacitor C _C1, the second filter capacitor C _C2, the first filter resistor R _C1, the second filter resistor R _C2, the first inverter G _m1, the second inverter G _m2, the third inverter G _m3, the first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate;

a first polar plate of the first filter capacitor C _C1 is connected to an inverting input end of the first-stage continuous-time linear equalizer circuit, a second polar plate is connected to a first end of the first filter resistor R _C1, and a second end of the first filter resistor R _C1 is connected to a non-inverting input end of the third inverter G _m3;

A first polar plate of the second filter capacitor C _C2 is connected to the non-inverting input end of the first-stage continuous-time linear equalizer circuit, a second polar plate is connected to the first end of the second filter resistor R _C2, and a second end of the second filter resistor R _C2 is connected to the inverting input end of the third inverter G _m3;

The non-inverting input end of the first inverter G _m1 is used as an inverting input end of a continuous time linear equalization circuit for a high-speed data interface, and inputs an inverted high-speed data signal Vin; the inverting input end of the first inverter G _m1 is used as the non-inverting input end of the continuous-time linear equalization circuit for the high-speed data interface, a non-inverting high-speed data signal Vip is input, the inverting output end is respectively connected with the inverting output end of the second inverter G _m2 and the inverting output end of the third inverter G _m3, and the non-inverting output end is respectively connected with the non-inverting output end of the second inverter G _m2 and the non-inverting output end of the third inverter G _m3;

The two transmission ends of the first transmission gate are respectively connected with the positive input end and the negative output end of the second inverter G _m2, one end of the control end is input with a first positive external control voltage, and the other end is input with a first negative external control voltage;

Two transmission ends of the second transmission gate are respectively connected with an inverting input end and a non-inverting output end of the second inverter G _m2, one end of the control end is input with a second non-inverting external control voltage, and the other end is input with a second inverting external control voltage;

Two transmission ends of the third transmission gate are respectively connected with a normal-phase input end and an opposite-phase output end of the third inverter G _m3, one end of the control end is input with a third normal-phase externally-applied control voltage, and the other end is input with a third opposite-phase externally-applied control voltage;

The two transmission ends of the fourth transmission gate are respectively connected with the inverting input end and the non-inverting output end of the third inverter G _m3, one end of the control end is input with a fourth non-inverting external control voltage, and the other end is input with a fourth inverting external control voltage.

In one embodiment of the present invention, the transfer function G _m1/m2(s) of the high-frequency path of the first-stage continuous-time linear equalizer circuit is expressed as follows:

Wherein G _m1 is the transconductance of the first inverter G _m1; g _m2 is the transconductance of the second inverter G _m2; r ₁ is the equivalent resistance of the first transmission gate; c _gs2 is the equivalent input capacitance of the second inverter G _m2; c ₁ is the equivalent load capacitance of the second inverter G _m2; s is the frequency of the high-speed data signal.

In one embodiment of the present invention, the transfer function G _mp(s) of the intermediate frequency path of the first stage continuous-time linear equalizer circuit is expressed as follows:

Wherein G _m3 is the transconductance of the third inverter G _m3; r ₃ is the equivalent resistance of the third transmission gate; c _gs3 is the equivalent input capacitance of the third inverter G _m3; r _C1 is the resistance of the first filter resistor R _C1; c _C1 is the capacitance of the first filter capacitor C _C1.

In one embodiment of the invention, the second stage continuous time linear equalizer circuit comprises: a fourth inverter G _m4, a fifth inverter G _m5, a sixth inverter G _m6, a fifth transfer gate, and a sixth transfer gate;

The positive input end of the fourth inverter G _m4 is connected to the negative output end of the first inverter G _m1, the negative input end is connected to the positive output end of the first inverter G _m1, the positive output end is respectively connected to the positive output end of the fifth inverter G _m5 and the positive output end of the sixth inverter G _m6, and the negative output end is respectively connected to the negative output end of the fifth inverter G _m5 and the negative output end of the sixth inverter G _m6;

two transmission ends of the fifth transmission gate are respectively connected with a positive input end and a negative output end of the fifth inverter G _m5, one end of the control end is input with a fifth positive externally applied control voltage, and the other end is input with a fifth negative externally applied control voltage;

Two transmission ends of the sixth transmission gate are respectively connected with an inverting input end and a non-inverting output end of the fifth inverter G _m5, one end of the control end is input with a sixth non-inverting externally applied control voltage, and the other end is input with a sixth inverting externally applied control voltage;

The positive input end of the sixth inverter G _m6 inputs the externally applied negative control signal VBN, and the negative input end inputs the externally applied positive control signal VBP.

In one embodiment of the present invention, the expression of the transfer function G _m4/m5(s) of the high-frequency path of the second-stage continuous-time linear equalizer circuit is:

Wherein G _m4 is the transconductance of the fourth inverter G _m4; g _m5 is the transconductance of the fifth inverter G _m5; r ₅ is the equivalent resistance of the fifth transmission gate; c _gs5 is the equivalent input capacitance of the fifth inverter G _m5; c ₂ is the equivalent load capacitance of the fifth inverter G _m5.

In one embodiment of the present invention, the programmable gain amplifier circuit includes: a seventh inverter G _m7, an eighth inverter G _m8, a seventh transmission gate, and an eighth transmission gate;

The positive input end of the seventh inverter G _m7 is connected to the negative output end of the fourth inverter G _m4, the negative input end is connected to the positive output end of the fourth inverter G _m4, the positive output end is connected to the positive output end of the eighth inverter G _m8, and the negative output end is connected to the negative output end of the eighth inverter G _m8;

A non-inverting output terminal of the seventh inverter G _m7; an inverting output terminal of the seventh inverter G _m7;

Two transmission ends of the seventh transmission gate are respectively connected with a positive input end and a negative output end of the eighth inverter G _m8, one end of the control end is input with a seventh positive externally applied control voltage, and the other end is input with a seventh negative externally applied control voltage;

The two transmission ends of the eighth transmission gate are respectively connected with the inverting input end and the non-inverting output end of the eighth inverter G _m8, one end of the control end is input with an eighth non-inverting external control voltage, and the other end is input with an eighth inverting external control voltage.

In one embodiment of the present invention, the first inverter G _m1, the second inverter G _m2, the third inverter G _m3, the fourth inverter G _m4, the fifth inverter G _m5, the sixth inverter G _m6, the seventh inverter G _m7, and the eighth inverter G _m8 have the same structure, each of which includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6;

The drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M2 and is used as an inverting signal output end of the inverter, the source electrode of the MOS tube M3 and the drain electrode of the MOS tube M5 are respectively connected with the source electrode of the MOS tube M3, and the grid electrode of the MOS tube M2 is connected with the grid electrode of the MOS tube M2 and is used as a positive phase signal input end of the inverter;

The source electrode of the MOS tube M2 is respectively connected with the source electrode of the MOS tube M4 and the drain electrode of the MOS tube M6;

The drain electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M4 and is used as a positive phase signal output end of the inverter, and the grid electrode of the MOS tube M4 is connected with the grid electrode and is used as an inverting signal input end of the inverter;

The grid electrode of the MOS tube M5 is input with an inverted externally-applied enabling signal, and the source electrode is connected with a power supply voltage end;

And a positive external enabling signal is input to the grid electrode of the MOS tube M6, and the source electrode is connected with the grounding end.

In one embodiment of the present invention, the negative capacitance circuit includes: MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, capacitor Cc, first load capacitor C _L1 and second load capacitor C _L2;

The drain electrode of the MOS tube M7 is respectively connected with the inverting output end of the seventh inverter G _m7 and the first polar plate of the first load capacitor C _L1, and the second polar plate of the first load capacitor C _L1 is connected with the grounding end; the drain electrode of the MOS tube M7 is used as an inverting output end of the continuous time linear equalization circuit for the high-speed data interface, an inverting output signal Vop is output, and the source electrode of the MOS tube M9 and the first polar plate of the capacitor Cc are respectively connected;

the drain electrode of the MOS tube M8 is respectively connected with the positive phase output end of the seventh inverter G _m7 and the first polar plate of the second load capacitor C _L2, and the second polar plate of the second load capacitor C _L2 is connected with the grounding end; the drain electrode of the MOS tube M8 is used as the positive output end of the continuous time linear equalization circuit for the high-speed data interface to output a positive output signal Von, the grid electrode is connected with the drain electrode of the MOS tube M7, and the source electrode is respectively connected with the drain electrode of the MOS tube M10 and the second polar plate of the capacitor Cc;

The grid electrode of the MOS tube M9 is connected with the grid electrode of the MOS tube M10 and is connected with an input external control signal Vb; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are both connected with a grounding end.

In one embodiment of the present invention, the equivalent impedance Z _NC(s) of the negative capacitance circuit is expressed as:

Wherein, R _NC is the equivalent resistance of the negative capacitor circuit, R _NC＝(C_gsc/C_C+2)/g_mc;g_mc is the transconductance of the MOS transistor M7 or the MOS transistor M8, and C _gsc is the gate-source capacitance of the MOS transistor M7 or the MOS transistor M8.

Compared with the prior art, the invention has the beneficial effects that:

The continuous time linear equalization circuit for the high-speed data interface adopts a two-stage CTLE circuit, and a unit gain buffer taking an active inductor as a load is introduced into the two-stage CTLE circuit for compensating attenuation of signals at a high frequency. Wherein the active inductance is implemented by an inverter with a transmission gate. A transconductance unit with band-pass characteristics is also introduced into the first-stage CTLE circuit and is used for compensating the intermediate frequency attenuation of signals; an offset voltage correction node is added in the second-stage CTLE circuit to solve the problems of asymmetry and PVT (Process Voltage Temperature ) change of the circuit. PGA is implemented by a Programmable transconductance amplifier using active inductance as a load by series connection of a Programmable gain amplifier (Programmable GAIN AMPLIFIER, PGA) after the two-stage CTLE circuit to increase the signal swing. Negative capacitance is generated by the negative capacitance circuit to reduce or completely cancel the load capacitance, further expanding the circuit bandwidth. By the four-stage circuits connected in series, the requirements of high-speed data transmission are met while the area and the low power consumption are small.

The inverter of the invention has tunable intensity, and in the active inductive load, the equivalent resistance of the transmission gate is also tunable as a zeroing resistance, thus providing a flexible design scheme with tunable inductance value for a circuit with given bandwidth requirements. In addition, the complementary transmission gate in the triode state is used as a zeroing resistor in the active inductor, instead of the traditional polysilicon resistor or trap resistor, the equivalent resistance of the transmission gate is regulated by regulating the transconductance of the MOS tube in the transmission gate, so that the tuning precision is improved, and the layout area and parasitic capacitance are greatly reduced.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of a CTLE based on a conventional current-mode logic architecture;

FIG. 2 is a schematic circuit diagram of a continuous-time linear equalization circuit for a high-speed data interface according to an embodiment of the present invention;

Fig. 3 is a schematic circuit diagram of an inverter-based active amplifier cell of the present invention;

Fig. 4 is a schematic circuit diagram of an inverter-based active resistive cell of the present invention;

fig. 5 is a schematic circuit diagram of an inverter-based active inductor cell of the present invention;

FIG. 6 is a schematic circuit diagram of an inverter-based transconductance amplifier driving an active inductive load of the present invention;

FIG. 7 is a transfer function curve of a first stage continuous time linear equalizer circuit provided by an embodiment of the present invention;

FIG. 8 is a transfer function curve of a second stage continuous time linear equalizer circuit provided by an embodiment of the present invention;

Fig. 9 is a circuit schematic of an inverter of the present invention.

Detailed Description

In order to further describe the technical means and effects adopted by the present invention to achieve the preset purpose, a continuous-time linear equalization circuit for a high-speed data interface according to the present invention is described in detail below with reference to the accompanying drawings and detailed description.

The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.

Example 1

In this embodiment, as shown in fig. 2, a continuous-time linear equalization circuit for a high-speed data interface includes: a first-stage continuous-time linear equalizer circuit, a second-stage continuous-time linear equalizer circuit, a programmable gain amplifier circuit, and a negative capacitance circuit, which are sequentially connected in series; the first-stage continuous time linear equalizer circuit is used for inputting a high-speed data signal, compensating high-frequency attenuation and intermediate-frequency attenuation in the high-speed data signal, and combining high-frequency gain compensation and intermediate-frequency gain compensation to obtain a first-stage compensation signal; the second-stage continuous time linear equalizer circuit is used for compensating high-frequency attenuation in the first-stage compensation signal to obtain a second-stage compensation signal; the programmable gain amplifier circuit is used for amplifying the second-stage compensation signal, increasing the swing amplitude of the signal and outputting the signal; the negative capacitance circuit is used for generating negative capacitance, reducing or completely counteracting the whole load capacitance of the continuous time linear equalization circuit so as to further expand the bandwidth of the circuit and improve the quality of output signals for output.

Since the inverter is generally related to digital design, the analog characteristics of the inverter are described below in order to facilitate understanding of the continuous-time linear equalizer of the present embodiment.

As shown in fig. 3, when the inverter is properly biased and both PMOS and NMOS devices are in saturation, the inverter can be regarded as a transconductance cell, and assuming that the device transconductance of the PMOS and NMOS devices in the inverter circuit is equal and the drain-source small conductances G _ds of the PMOS and NMOS devices are ignored, the expression of the total transconductance G _m of the inverter is:

G_m＝g_mp+g_mn＝2g_m； (1)

Wherein G _m is the total transconductance of the inverter; g _mp is the transconductance of the PMOS transistor in the inverter; g _mn is the transconductance of the NMOS transistor in the inverter; g _m represents the transconductance of any device in the inverter;

The transconductance of the inverter can be regarded as twice that of a single MOS transistor.

As shown in fig. 4, the diode-connected inverter behaves as a self-biased active resistance unit, with nominal output voltages between the supply and ground potentials when the PMOS and NMOS devices are driven at the same strength, and a circuit bias point (Vo) can place the drive transistors in saturation, thereby ensuring that the output has sufficient swing. Similarly, ignoring the drain-source small signal conductance of the active resistive load, the expression for the equivalent active resistive load R is:

wherein R is the resistance of an equivalent active resistance load; g _ds is the drain-source conductance of the active resistive load.

That is, the equivalent active resistance load R is related to the transconductance of the MOS transistor, and the larger the transconductance is, the smaller the R is.

The cost of the inverter unit for the chip area is reduced by using an active inductor instead of a passive inductor, the circuit structure of which is shown in fig. 5, assuming C _gsn＝c_gsp＝c_gs, the equivalent gate capacitance C _gs of the inverter is expressed as:

C_gs＝c_gsn+c_gsp＝2c_gs (3)

Wherein, C _gs is the equivalent gate capacitance of the inverter; c _gsn is the equivalent gate capacitance of the NMOS transistor; c _gsp is the equivalent gate capacitance of the PMOS tube; c _gs is the equivalent gate capacitance of the inverter.

Similarly ignoring the output conductance g _ds and solving the small signal model, the input impedance Z of the active inductor is expressed as:

Wherein Z is the input impedance of the active inductor; s is the frequency of the high-speed data signal; omega _Z is zero frequency, omega _Z＝1/RC_gs;ω_T is the cut-off frequency of the inverter, omega _T＝C_gs/G_m;

when the actual operating frequency ω of the inverter satisfies: when ω < ω _T, the expression of the input impedance Z of the active inductor can be reduced to:

I.e. the input impedance Z of the active inductor is both R, G _m and ω _T, and the larger G _m and ω _T, the larger Z, the larger R, and the larger Z.

As shown in fig. 6, the circuit gain can be expressed approximately as the ratio of the transconductance amplifier to the active inductive load, and then the circuit gain G _m/mL(s) is expressed as:

Where G _m/mL(s) is the circuit gain, i.e., the transfer function of the circuit.

In fig. 3 to 6, the circuit model, the specific circuit structure diagram, the small signal model of the circuit and the simplification of the small signal model are sequentially shown, and then the formulas (1) to (5) are obtained by performing simplified calculation according to fig. 3 to 6, wherein the formulas (1) to (5) show that the inverter structure can be equivalent to a transconductance unit, an active resistor, an active inductor and a transconductance amplifier.

Referring back to fig. 2, in the present embodiment, the first stage continuous time linear equalizer circuit includes: the first filter capacitor C _C1, the second filter capacitor C _C2, the first filter resistor R _C1, the second filter resistor R _C2, the first inverter G _m1, the second inverter G _m2, the third inverter G _m3, the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate.

Specifically, a first polar plate of the first filter capacitor C _C1 is connected to an inverting input end of the first-stage continuous-time linear equalizer circuit, a second polar plate is connected to a first end of the first filter resistor R _C1, and a second end of the first filter resistor R _C1 is connected to a non-inverting input end of the third inverter G _m3; The first polar plate of the second filter capacitor C _C2 is connected with the non-inverting input end of the first-stage continuous time linear equalizer circuit, the second polar plate is connected with the first end of the second filter resistor R _C2, and the second end of the second filter resistor R _C2 is connected with the inverting input end of the third inverter G _m3; The non-inverting input end of the first inverter G _m1 is used as an inverting input end of a continuous time linear equalization circuit for a high-speed data interface, and an inverted high-speed data signal Vin is input; The inverting input terminal of the first inverter G _m1 is used as the non-inverting input terminal of the continuous time linear equalization circuit for high-speed data interface, the non-inverting high-speed data signal Vip is input, the inverting output terminal is respectively connected with the inverting output terminal of the second inverter G _m2 and the inverting output terminal of the third inverter G _m3, The positive phase output end is respectively connected with the positive phase output end of the second inverter G _m2 and the positive phase output end of the third inverter G _m3; Two transmission ends of the first transmission gate are respectively connected with a positive input end and a negative output end of the second inverter G _m2, one end of the control end is input with a first positive external control voltage, and the other end is input with a first negative external control voltage; two transmission ends of the second transmission gate are respectively connected with an inverting input end and a non-inverting output end of the second inverter G _m2, one end of the control end is input with a second non-inverting external control voltage, and the other end is input with a second inverting external control voltage; Two transmission ends of the third transmission gate are respectively connected with a normal phase input end and an opposite phase output end of the third inverter G _m3, one end of the control end is input with a third normal phase external control voltage, and the other end is input with a third opposite phase external control voltage; the two transmission ends of the fourth transmission gate are respectively connected with the inverting input end and the non-inverting output end of the third inverter G _m3, one end of the control end is input with a fourth non-inverting external control voltage, and the other end is input with a fourth inverting external control voltage.

In this embodiment, the expression of the transfer function of the first-stage continuous-time linear equalizer circuit is:

wherein G _m1/m2(s) is; g _m1 is the transconductance of the first inverter Gm ₁; g _m2 is the transconductance of the second inverter G _m2; r ₁ is the equivalent resistance of the first transmission gate; c _gs2 is the equivalent input capacitance of the second inverter G _m2; c ₁ is the equivalent load capacitance of the second inverter G _m2;

Wherein G _mp(s) is; g _m3 is the transconductance of the third inverter Gm ₃; r ₃ is the equivalent resistance of the third transmission gate; c _gs3 is the equivalent input capacitance of the third inverter G _m3; r _C1 is the resistance of the first filter resistor R _C1; c _C1 is the capacitance of the first filter capacitance C _C1.

The transfer function curve of the first-stage continuous-time linear equalizer circuit is shown in fig. 7, and the gain and compensation strength of the high-frequency signal can be adjusted by adjusting the transconductance G _m1 of the first inverter G _m1 and the equivalent resistance R ₁ of the first transmission gate; by adjusting the resistor R _C1 of the first filter resistor R _C1, the capacitor C _C1 of the first filter capacitor C _C1, and the transconductance G _m3 of the third inverter G _m3, the intermediate frequency signal gain and the intermediate frequency signal compensation strength can be adjusted. The equivalent resistance of the transmission gate is regulated by the positive externally applied control voltage V _P and the negative externally applied control voltage V _N.

In this embodiment, the second stage continuous time linear equalizer circuit includes: a fourth inverter G _m4, a fifth inverter G _m5, a sixth inverter G _m6, a fifth transfer gate, and a sixth transfer gate; specifically, the positive input end of the fourth inverter G _m4 is connected to the negative output end of the first inverter G _m1, the negative input end is connected to the positive output end of the first inverter G _m1, the positive output end is respectively connected to the positive output end of the fifth inverter G _m5 and the positive output end of the sixth inverter G _m6, and the negative output end is respectively connected to the negative output end of the fifth inverter G _m5 and the negative output end of the sixth inverter G _m6; two transmission ends of the fifth transmission gate are respectively connected with a positive input end and a negative output end of the fifth inverter G _m5, one end of the control end is input with a fifth positive externally applied control voltage, and the other end is input with a fifth negative externally applied control voltage; two transmission ends of the sixth transmission gate are respectively connected with an inverting input end and a non-inverting output end of the fifth inverter G _m5, one end of the control end is input with a sixth non-inverting externally applied control voltage, and the other end is input with a sixth inverting externally applied control voltage; the non-inverting input terminal of the sixth inverter G _m6 inputs the externally applied inverted control signal VBN, and the inverting input terminal inputs the externally applied non-inverting control signal VBP.

In this embodiment, the expression of the transfer function of the second-stage continuous-time linear equalizer circuit is:

Wherein G _m4 is the transconductance of the fourth inverter G _m4; g _m5 is the transconductance of the fifth inverter G _m5; r ₅ is the equivalent resistance of the fifth transmission gate; c _gs5 is the equivalent input capacitance of the fifth inverter G _m5; c ₂ is the equivalent load capacitance of the fifth inverter G _m5.

The transfer function curve of the second-stage continuous-time linear equalizer circuit is shown in fig. 8, and the high-frequency signal gain and the high-frequency signal compensation strength of the circuit can be further adjusted based on the first-stage continuous-time linear equalizer circuit by adjusting the transconductance G _m4 of the fourth inverter G _m4 and the equivalent resistance R ₅ of the fifth transmission gate. The equivalent resistance of the transmission gate is regulated by the positive applied control voltage V _P and the negative applied control voltage V _N, similar to the second stage continuous time linear equalizer circuit.

In this embodiment, a programmable gain amplifier circuit includes: a seventh inverter G _m7, an eighth inverter G _m8, a seventh transmission gate, and an eighth transmission gate; specifically, the positive input end of the seventh inverter G _m7 is connected to the negative output end of the fourth inverter G _m4, the negative input end is connected to the positive output end of the fourth inverter G _m4, the positive output end is connected to the positive output end of the eighth inverter G _m8, and the negative output end is connected to the negative output end of the eighth inverter G _m8; a non-inverting output terminal of the seventh inverter G _m7; an inverting output terminal of the seventh inverter G _m7; two transmission ends of the seventh transmission gate are respectively connected with a positive input end and a negative output end of the eighth inverter G _m8, one end of the control end is input with a seventh positive externally applied control voltage, and the other end is input with a seventh negative externally applied control voltage; the two transmission ends of the eighth transmission gate are respectively connected with the inverting input end and the non-inverting output end of the eighth inverter G _m8, one end of the control end is input with an eighth non-inverting external control voltage, and the other end is input with an eighth inverting external control voltage.

As shown in fig. 9, in the first-stage continuous-time linear equalizer circuit, the second-stage continuous-time linear equalizer circuit, and the programmable gain amplifier circuit, the transconductance of each inverter is controlled by the positive-phase externally applied enable signal EN and the negative-phase externally applied enable signalTo make adjustments.

Specifically, the first inverter G _m1, the second inverter G _m2, the third inverter G _m3, the fourth inverter G _m4, the fifth inverter G _m5, the sixth inverter G _m6, the seventh inverter G _m7, and the eighth inverter G _m8 have the same structure, and each inverter includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6;

The drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M2 and is used as an inverting signal output end of the inverter, the source electrode of the MOS tube M3 is respectively connected with the source electrode of the MOS tube M5, and the grid electrode of the MOS tube M2 is connected with the grid electrode of the MOS tube M2 and is used as a positive phase signal input end of the inverter; the source electrode of the MOS tube M2 is respectively connected with the source electrode of the MOS tube M4 and the drain electrode of the MOS tube M6; the drain electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M4 and is used as a positive phase signal output end of the inverter, and the grid electrode of the MOS tube M4 is connected with the grid electrode and is used as an inverting signal input end of the inverter; grid electrode input inversion externally-applied enabling signal of MOS tube M5 The source electrode is connected with the power supply voltage end; the gate of the MOS tube M6 inputs a positive additional enable signal EN, and the source is connected with the grounding end.

In this embodiment, the negative capacitance circuit includes: MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, capacitor Cc, first load capacitor C _L1 and second load capacitor C _L2; specifically, the drain electrode of the MOS transistor M7 is connected to the inverting output end of the seventh inverter G _m7 and the first polar plate of the first load capacitor C _L1, and the second polar plate of the first load capacitor C _L1 is connected to the ground end; the drain electrode of the MOS tube M7 is used as an inverting output end of a continuous time linear equalization circuit for a high-speed data interface, an inverting output signal Vop is output, and the source electrode of the MOS tube M9 and the first polar plate of the capacitor Cc are respectively connected; the drain electrode of the MOS tube M8 is respectively connected with the positive output end of the seventh inverter G _m7 and the first polar plate of the second load capacitor C _L2, and the second polar plate of the second load capacitor C _L2 is connected with the grounding end; the drain electrode of the MOS tube M8 is used as a positive output end of a continuous time linear equalization circuit for a high-speed data interface, a positive output signal Von is output, the grid electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M7, and the source electrode of the MOS tube M10 and the second polar plate of the capacitor Cc are respectively connected; the grid electrode of the MOS tube M9 is connected with the grid electrode of the MOS tube M10 and is connected with an input external control signal Vb; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are both connected with the grounding end.

In the present embodiment, the expression of the equivalent impedance Z _NC(s) of the negative capacitance circuit is:

Wherein, R _NC is the equivalent resistance of the negative capacitor circuit, R _NC＝(C_gsc/C_C+2)/g_mc;g_mc is the transconductance of the MOS transistor M7 or the MOS transistor M8, and C _gsc is the gate-source capacitance of the MOS transistor M7 or the MOS transistor M8.

The working principle and working process of the invention are as follows: the input signal is usually a high-speed data signal with loss after passing through a channel, after the input signal is input to a first-stage continuous-time linear equalizer circuit, the first-stage continuous-time linear equalizer circuit compensates intermediate frequency and high-frequency components of the input signal, a second-stage continuous-time linear equalizer circuit further compensates the high-frequency components, a variable gain amplifier amplifies the signal to increase the swing amplitude of the signal, a negative capacitance circuit generates a negative capacitance, the load capacitance of the whole continuous-time linear equalizer circuit is reduced or even completely counteracted, the circuit bandwidth is further expanded, the quality of the output signal is improved, and finally the equalized high-speed data signal is output.

Further, an inverter structure with a transmission gate is provided in the first stage continuous time linear equalizer circuit, the second stage continuous time linear equalizer circuit and the programmable gain amplifier, the structure can be equivalent to an active inductor and act as a load, and a combination of the first inverter and the second inverter, a combination of the fourth inverter and the fifth inverter, and a combination of the seventh inverter and the eighth inverter respectively form a unit gain buffer, which can compensate attenuation of a signal at a high frequency. In the first-stage continuous-time linear equalizer circuit, the third inverter, which is a transconductance unit having a bandpass characteristic, is also capable of compensating for intermediate frequency attenuation of the signal. In the second-stage continuous time linear equalizer circuit, a node connected with the sixth inverter and the fourth inverter is used as an offset voltage correction node so as to solve the problems of asymmetry and PVT variation of the circuit. The signal swing is increased by the amplification of the programmable gain amplifier circuit. The negative capacitance is generated by the negative capacitance circuit, so that the whole load capacitance of the continuous time linear equalization circuit is reduced or even completely counteracted, the circuit bandwidth is further expanded, and the quality of output signals is improved.

The continuous time linear equalization circuit for the high-speed data interface adopts a two-stage CTLE circuit, and a unit gain buffer taking an active inductor as a load is introduced into the two-stage CTLE circuit for compensating attenuation of signals at a high frequency. Wherein the active inductance is implemented by an inverter with a transmission gate. A transconductance unit with band-pass characteristics is also introduced into the first-stage CTLE circuit and is used for compensating the intermediate frequency attenuation of signals; an offset voltage correction node is added in the second-stage CTLE circuit to solve the problems of asymmetry and PVT (Process Voltage Temperature ) change of the circuit. PGA is implemented by a Programmable transconductance amplifier using active inductance as a load by series connection of a Programmable gain amplifier (Programmable GAIN AMPLIFIER, PGA) after the two-stage CTLE circuit to increase the signal swing. Negative capacitance is generated by the negative capacitance circuit to reduce or completely cancel the load capacitance, further expanding the circuit bandwidth. By the four-stage circuits connected in series, the requirements of high-speed data transmission are met while the area and the low power consumption are small.

The inverter of the invention has tunable intensity, and in the active inductive load, the equivalent resistance of the transmission gate is also tunable as a zeroing resistance, thus providing a flexible design scheme with tunable inductance value for a circuit with given bandwidth requirements. In addition, the complementary transmission gate in the triode state is used as a zeroing resistor in the active inductor, instead of the traditional polysilicon resistor or trap resistor, the equivalent resistance of the transmission gate is regulated by regulating the transconductance of the MOS tube in the transmission gate, so that the tuning precision is improved, and the layout area and parasitic capacitance are greatly reduced.

It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description and to simplify the description, and is not indicative or implying that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. A continuous-time linear equalization circuit for a high-speed data interface, comprising: a first-stage continuous-time linear equalizer circuit, a second-stage continuous-time linear equalizer circuit, a programmable gain amplifier circuit, and a negative capacitance circuit, which are sequentially connected in series; wherein,

The first-stage continuous time linear equalizer circuit is used for inputting a high-speed data signal, compensating high-frequency attenuation and intermediate-frequency attenuation in the high-speed data signal, and combining high-frequency gain compensation and intermediate-frequency gain compensation to obtain a first-stage compensation signal;

The second-stage continuous time linear equalizer circuit is used for compensating high-frequency attenuation in the first-stage compensation signal to obtain a second-stage compensation signal;

the programmable gain amplifier circuit is used for amplifying the second-stage compensation signal and increasing the swing amplitude of the signal;

The negative capacitance circuit is used for reducing or completely counteracting the load capacitance in the continuous time linear equalization circuit for the high-speed data interface and outputting.

2. The continuous-time linear equalizer circuit for a high-speed data interface of claim 1, wherein the first stage continuous-time linear equalizer circuit comprises: the first filter capacitor C _C1, the second filter capacitor C _C2, the first filter resistor R _C1, the second filter resistor R _C2, the first inverter G _m1, the second inverter G _m2, the third inverter G _m3, the first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate;

a first polar plate of the first filter capacitor C _C1 is connected to an inverting input end of the first-stage continuous-time linear equalizer circuit, a second polar plate is connected to a first end of the first filter resistor R _C1, and a second end of the first filter resistor R _C1 is connected to a non-inverting input end of the third inverter G _m3;

A first polar plate of the second filter capacitor C _C2 is connected to the non-inverting input end of the first-stage continuous-time linear equalizer circuit, a second polar plate is connected to the first end of the second filter resistor R _C2, and a second end of the second filter resistor R _C2 is connected to the inverting input end of the third inverter G _m3;

The non-inverting input end of the first inverter G _m1 is used as an inverting input end of a continuous time linear equalization circuit for a high-speed data interface, and inputs an inverted high-speed data signal Vin; the inverting input end of the first inverter G _m1 is used as the non-inverting input end of the continuous-time linear equalization circuit for the high-speed data interface, a non-inverting high-speed data signal Vip is input, the inverting output end is respectively connected with the inverting output end of the second inverter G _m2 and the inverting output end of the third inverter G _m3, and the non-inverting output end is respectively connected with the non-inverting output end of the second inverter G _m2 and the non-inverting output end of the third inverter G _m3;

The two transmission ends of the first transmission gate are respectively connected with the positive input end and the negative output end of the second inverter G _m2, one end of the control end is input with a first positive external control voltage, and the other end is input with a first negative external control voltage;

Two transmission ends of the second transmission gate are respectively connected with an inverting input end and a non-inverting output end of the second inverter G _m2, one end of the control end is input with a second non-inverting external control voltage, and the other end is input with a second inverting external control voltage;

Two transmission ends of the third transmission gate are respectively connected with a normal-phase input end and an opposite-phase output end of the third inverter G _m3, one end of the control end is input with a third normal-phase externally-applied control voltage, and the other end is input with a third opposite-phase externally-applied control voltage;

The two transmission ends of the fourth transmission gate are respectively connected with the inverting input end and the non-inverting output end of the third inverter G _m3, one end of the control end is input with a fourth non-inverting external control voltage, and the other end is input with a fourth inverting external control voltage.

3. The continuous-time linear equalizer circuit for a high-speed data interface of claim 2, wherein the expression of the transfer function G _m1/m2(s) of the high-frequency path of the first-stage continuous-time linear equalizer circuit is:

Wherein G _m1 is the transconductance of the first inverter G _m1; g _m2 is the transconductance of the second inverter G _m2; r ₁ is the equivalent resistance of the first transmission gate; c _gs2 is the equivalent input capacitance of the second inverter G _m2; c ₁ is the equivalent load capacitance of the second inverter G _m2; s is the frequency of the high-speed data signal.

4. A continuous-time linear equalizer circuit for a high-speed data interface as claimed in claim 3, wherein the transfer function G _mp(s) of the intermediate frequency path of the first stage continuous-time linear equalizer circuit has the expression:

Wherein G _m3 is the transconductance of the third inverter G _m3; r ₃ is the equivalent resistance of the third transmission gate; c _gs3 is the equivalent input capacitance of the third inverter G _m3; r _C1 is the resistance of the first filter resistor R _C1; c _C1 is the capacitance of the first filter capacitor C _C1.

5. The continuous-time linear equalizer circuit for a high-speed data interface of claim 2, wherein the second stage continuous-time linear equalizer circuit comprises: a fourth inverter G _m4, a fifth inverter G _m5, a sixth inverter G _m6, a fifth transfer gate, and a sixth transfer gate;

The positive input end of the fourth inverter G _m4 is connected to the negative output end of the first inverter G _m1, the negative input end is connected to the positive output end of the first inverter G _m1, the positive output end is respectively connected to the positive output end of the fifth inverter G _m5 and the positive output end of the sixth inverter G _m6, and the negative output end is respectively connected to the negative output end of the fifth inverter G _m5 and the negative output end of the sixth inverter G _m6;

two transmission ends of the fifth transmission gate are respectively connected with a positive input end and a negative output end of the fifth inverter G _m5, one end of the control end is input with a fifth positive externally applied control voltage, and the other end is input with a fifth negative externally applied control voltage;

Two transmission ends of the sixth transmission gate are respectively connected with an inverting input end and a non-inverting output end of the fifth inverter G _m5, one end of the control end is input with a sixth non-inverting externally applied control voltage, and the other end is input with a sixth inverting externally applied control voltage;

The positive input end of the sixth inverter G _m6 inputs the externally applied negative control signal VBN, and the negative input end inputs the externally applied positive control signal VBP.

6. The continuous-time linear equalizer circuit for a high-speed data interface of claim 5, wherein the expression of the transfer function G _m4/m5(s) of the high-frequency path of the second-stage continuous-time linear equalizer circuit is:

Wherein G _m4 is the transconductance of the fourth inverter G _m4; g _m5 is the transconductance of the fifth inverter G _m5; r ₅ is the equivalent resistance of the fifth transmission gate; c _gs5 is the equivalent input capacitance of the fifth inverter G _m5; c ₂ is the equivalent load capacitance of the fifth inverter G _m5.

7. The continuous-time linear equalization circuit for a high-speed data interface of claim 5, wherein said programmable gain amplifier circuit comprises: a seventh inverter G _m7, an eighth inverter G _m8, a seventh transmission gate, and an eighth transmission gate;

The positive input end of the seventh inverter G _m7 is connected to the negative output end of the fourth inverter G _m4, the negative input end is connected to the positive output end of the fourth inverter G _m4, the positive output end is connected to the positive output end of the eighth inverter G _m8, and the negative output end is connected to the negative output end of the eighth inverter G _m8;

A non-inverting output terminal of the seventh inverter G _m7; an inverting output terminal of the seventh inverter G _m7;

Two transmission ends of the seventh transmission gate are respectively connected with a positive input end and a negative output end of the eighth inverter G _m8, one end of the control end is input with a seventh positive externally applied control voltage, and the other end is input with a seventh negative externally applied control voltage;

The two transmission ends of the eighth transmission gate are respectively connected with the inverting input end and the non-inverting output end of the eighth inverter G _m8, one end of the control end is input with an eighth non-inverting external control voltage, and the other end is input with an eighth inverting external control voltage.

8. The continuous-time linear equalization circuit for a high-speed data interface of claim 7, wherein said first inverter G _m1, said second inverter G _m2, said third inverter G _m3, said fourth inverter G _m4, said fifth inverter G _m5, said sixth inverter G _m6, said seventh inverter G _m7, and said eighth inverter G _m8 are identical in structure, each inverter comprising: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6;

The drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M2 and is used as an inverting signal output end of the inverter, the source electrode of the MOS tube M3 and the drain electrode of the MOS tube M5 are respectively connected with the source electrode of the MOS tube M3, and the grid electrode of the MOS tube M2 is connected with the grid electrode of the MOS tube M2 and is used as a positive phase signal input end of the inverter;

The source electrode of the MOS tube M2 is respectively connected with the source electrode of the MOS tube M4 and the drain electrode of the MOS tube M6;

The drain electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M4 and is used as a positive phase signal output end of the inverter, and the grid electrode of the MOS tube M4 is connected with the grid electrode and is used as an inverting signal input end of the inverter;

The grid electrode of the MOS tube M5 is input with an inverted externally-applied enabling signal, and the source electrode is connected with a power supply voltage end;

And a positive external enabling signal is input to the grid electrode of the MOS tube M6, and the source electrode is connected with the grounding end.

9. The continuous-time linear equalization circuit for a high-speed data interface of claim 7, wherein said negative capacitance circuit comprises: MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, capacitor Cc, first load capacitor C _L1 and second load capacitor C _L2;

The drain electrode of the MOS tube M7 is respectively connected with the inverting output end of the seventh inverter G _m7 and the first polar plate of the first load capacitor C _L1, and the second polar plate of the first load capacitor C _L1 is connected with the grounding end; the drain electrode of the MOS tube M7 is used as an inverting output end of the continuous time linear equalization circuit for the high-speed data interface, an inverting output signal Vop is output, and the source electrode of the MOS tube M9 and the first polar plate of the capacitor Cc are respectively connected;

the drain electrode of the MOS tube M8 is respectively connected with the positive phase output end of the seventh inverter G _m7 and the first polar plate of the second load capacitor C _L2, and the second polar plate of the second load capacitor C _L2 is connected with the grounding end; the drain electrode of the MOS tube M8 is used as the positive output end of the continuous time linear equalization circuit for the high-speed data interface to output a positive output signal Von, the grid electrode is connected with the drain electrode of the MOS tube M7, and the source electrode is respectively connected with the drain electrode of the MOS tube M10 and the second polar plate of the capacitor Cc;

The grid electrode of the MOS tube M9 is connected with the grid electrode of the MOS tube M10 and is connected with an input external control signal Vb; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are both connected with a grounding end.

10. The continuous-time linear equalization circuit for a high-speed data interface of claim 9, wherein the equivalent impedance Z _NC(s) of said negative capacitance circuit is expressed as:

Wherein, R _NC is the equivalent resistance of the negative capacitor circuit, R _NC＝(C_gsc/C_C+2)/g_mc;g_mc is the transconductance of the MOS transistor M7 or the MOS transistor M8, and C _gsc is the gate-source capacitance of the MOS transistor M7 or the MOS transistor M8.