CN118316430A

CN118316430A - High-side switch driving circuit, driving method and driving system

Info

Publication number: CN118316430A
Application number: CN202410472055.6A
Authority: CN
Inventors: 屈文超; 续阳
Original assignee: Beijing Xidi Microelectronics Co ltd
Current assignee: Beijing Xidi Microelectronics Co ltd
Filing date: 2024-04-18
Publication date: 2024-07-09

Abstract

The application discloses a high-side switch driving circuit, a driving method and a driving system, and relates to the technical field of electronic circuits. The high-side switch driving circuit comprises a grid driving module and a controlled current module. The gate driving module drives the high-side switch to be turned off in response to a first edge signal in the enable signal. The gate driving module includes a first current unit. The first current unit outputs a first discharge current to drive the high-side switch to turn off in response to the first edge signal. The controlled current module enters an enabling state after a first edge signal starts to delay for a first preset time, and outputs a second discharge current after the output voltage of the load end rises to be greater than a first preset voltage threshold value for the first time, wherein the second discharge current acts on the first current unit to enable the first discharge current to increase. By the method, LC resonance which can be generated by turning off the high-side switch when the load end is connected with the inductive load can be reduced or even eliminated, so that the reliability of a system comprising the high-side switch is improved.

Description

High-side switch driving circuit, driving method and driving system

Technical Field

The application relates to the technical field of electronic circuits, in particular to a high-side switch driving circuit, a driving method and a driving system.

Background

With the continued advancement of technology, semiconductor switches such as high-side switches are increasingly replacing mechanical switches, relays, and fuses in automotive systems. The high side switch is mainly used for controlling and managing the distribution of electric energy in automobiles. High-side switches are commonly used to control the lighting of automobiles, manage the power supply to power electronic components such as sensors and actuators, and protect against and handle short circuits and overcurrents. The high-side switch provides a convenient and efficient solution for the control circuit, so that the safety and the energy efficiency of the automobile are improved while the integral function is realized.

In practice, the high-side switch is configured to make or break a connection between the load and the power supply. The high side switch may be controlled by an external signal. When the high side switch is turned off, the high side switch can prevent current from flowing from the power supply to the load; when the high side switch is turned on, a conductive path is established between the load and the power supply.

However, when the load is an inductive load, LC resonance may occur after the high-side switch is turned off, and even the system including the high-side switch is damaged, i.e., the reliability of the system including the high-side switch is poor.

Disclosure of Invention

The application aims to provide a high-side switch driving circuit, a driving method and a driving system, which can reduce or even eliminate LC resonance which can occur when the high-side switch is connected with an inductive load, so as to improve the reliability of a system comprising the high-side switch.

To achieve the above object, in a first aspect, the present application provides a high-side switch driving circuit, the high-side switch being connected between an input voltage bus and a load terminal for connection to a load, the high-side switch driving circuit comprising:

A gate drive module connected to the high-side switch, the gate drive module configured to receive an enable signal and drive the high-side switch to begin to turn off in response to a first edge signal in the enable signal;

The grid driving module comprises a first current unit, wherein a first end of the first current unit is connected with a grid electrode of the high-side switch, and the first current unit is configured to respond to the first edge signal to enable and output a first discharging current to the grid electrode of the high-side switch so as to discharge the grid electrode of the high-side switch and drive the high-side switch to start to be turned off;

And a controlled current module, a first end of which is connected with the load end, a second end of which is connected with the second end of the first current unit, the controlled current module being configured to enter an enabled state after a delay from the first edge signal by a first preset time period, and to output a second discharge current by being controlled by an output voltage of the load end after a voltage of the load end rises to be greater than a first preset voltage threshold for the first time during the period in which the controlled current module is in the enabled state, wherein the second discharge current acts on the first current unit to increase the first discharge current, thereby pulling down a gate voltage of the high-edge switch.

In an alternative manner, the first preset voltage threshold is ground potential.

In an alternative manner, the time when the first preset duration ends is earlier than the time when the output current of the load end first drops to zero.

In an alternative manner, the first current unit includes a first current source, a first enable switch, and a current mirror;

The first enable switch is connected between the first current source and the current mirror, the first enable switch being configured to establish a connection between the first current source and the current mirror in response to the first edge signal to enable the first current cell;

The current mirror is connected to a gate of the high-side switch, the current mirror being configured to output the first discharge current based on a current of the first current source when the current mirror is connected to the first current source.

In an alternative manner, the current mirror includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

The drain electrode of the first transistor is respectively connected with the drain electrode of the first enabling switch, the grid electrode of the first transistor and the grid electrode of the second transistor, the source electrode of the first enabling switch is connected with the negative electrode of the first current source, the positive electrode of the first current source is grounded, the source electrode of the first transistor and the source electrode of the second transistor are both connected with a bias voltage bus, the drain electrode of the second transistor is respectively connected with the drain electrode of the third transistor, the grid electrode of the third transistor and the grid electrode of the fourth transistor, the source electrode of the third transistor is respectively connected with the source electrode of the fourth transistor and the load end, and the drain electrode of the fourth transistor is connected with the grid electrode of the high-side switch.

In an alternative manner, the second end of the first current unit is a source of the first enabling switch, or the second end of the first current unit is a drain of the first enabling switch.

In an alternative manner, the controlled current module includes a fifth transistor, a first resistor, and a second enable switch;

The drain electrode of the fifth transistor is a second end of the controlled current module, the source electrode of the fifth transistor is grounded, the grid electrode of the fifth transistor is connected to the load end through the first resistor, and the grid electrode of the fifth transistor is also connected with the second enabling switch.

In an alternative manner, the controlled current module further comprises a first zener diode, or a second zener diode, and at least one first diode, or at least one second diode;

The first zener diode is connected between the gate of the fifth transistor and ground;

The at least one first diode and the second zener diode are connected in series between the gate of the fifth transistor and ground;

The at least one second diode is connected in series between the gate of the fifth transistor and ground.

In an alternative, the controlled current module further comprises a second resistor;

the source of the fifth transistor is grounded through the second resistor.

In an alternative in the manner of (a), the second enabling switch is connected to the between the gate of the fifth transistor and ground;

Wherein the high-side switch is configured to start to turn off the connection between the input voltage bus and the load terminal in response to the first edge signal;

After delaying the first edge signal for the first preset period of time, the second enabling switch is configured to be turned off so as to enable the controlled current module.

In an alternative manner, the second enabling switch and the first resistor are connected in series between the gate of the fifth transistor and the load terminal;

after the first preset time period is delayed from the first edge signal, the second enabling switch is configured to be turned on so as to enable the controlled current module.

In an alternative manner, the gate driving module further includes a second current source and a gate driving resistor;

The second current source is connected between a bias voltage bus and the grid electrode of the high-side switch, and the grid electrode driving resistor is connected between the grid electrode of the high-side switch and the load end.

In an alternative manner, the gate driving module includes at least one third zener diode, or at least one fourth zener diode and at least one third diode;

The at least one third zener diode is connected in series between the input voltage bus and the gate of the high-side switch, or the at least one third zener diode is connected in series between the input voltage bus and the load terminal;

The at least one fourth zener diode and the at least one third diode are connected in series between the input voltage bus and the gate of the high-side switch, or the at least one fourth zener diode and the at least one third diode are connected in series between the input voltage bus and the load terminal.

In a second aspect, the present application provides a high-side switch driving method, where the high-side switch is connected between an input voltage bus and a load end, and the load end is used for being connected with a load, and the high-side switch driving method includes:

in response to a first edge signal of an enabling signal, configuring a first current unit in a grid driving module to be in an enabling state so that the first current unit outputs a first discharging current to a grid of the high-side switch and drives the high-side switch to start to be turned off;

After a first edge signal of the enabling signal is delayed for a first preset time period, configuring a controlled current module to be in an enabling state, so that the controlled current module is controlled by the output voltage of the load end to output a second discharge current after the voltage of the load end is firstly increased to be greater than a first preset voltage threshold;

Wherein the second discharge current acts on the first current cell to increase the first discharge current, thereby pulling down the gate voltage of the high-side switch.

In an alternative manner, the first current unit includes a first current source, a first enabling switch, and a current mirror, and the current mirror includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

The drain electrode of the first transistor is respectively connected with the drain electrode of the first enabling switch, the gate electrode of the first transistor and the gate electrode of the second transistor, the source electrode of the first enabling switch is connected with the negative electrode of the first current source, the positive electrode of the first current source is grounded, the source electrode of the first transistor and the source electrode of the second transistor are both connected with a bias voltage bus, the drain electrode of the second transistor is respectively connected with the drain electrode of the third transistor, the gate electrode of the third transistor and the gate electrode of the fourth transistor, the source electrode of the third transistor is respectively connected with the source electrode of the fourth transistor and the load end, and the drain electrode of the fourth transistor is connected with the gate electrode of the high-side switch, wherein the second end of the first current unit is the source electrode or the drain electrode of the first enabling switch;

the configuration of the first current unit in the gate driving module to an enabled state in response to the first edge signal of the enable signal includes:

And responding to a first edge signal of an enabling signal, and configuring the first enabling switch to be conducted so as to enable the first current unit to be in an enabling state.

In an alternative manner, the controlled current module includes a fifth transistor connected between the second terminal of the first current cell and ground, a first resistor connected between the gate of the fifth transistor and the load terminal, and a second enable switch connected between the gate of the fifth transistor and ground;

After the delay of the first edge signal of the enabling signal for a first preset period, configuring the controlled current module to be in an enabling state, including:

and after the first edge signal is delayed for the first preset time period, the second enabling switch is configured to be turned off, so that the controlled current module is configured to be in an enabling state.

In an alternative manner, the controlled current module includes a fifth transistor connected between the second terminal of the first current cell and ground, and a first resistor and a second enable switch connected in series between the gate of the fifth transistor and the load terminal;

And after the first edge signal is delayed for the first preset time period, the second enabling switch is configured to be conducted so as to configure the controlled current module to be in an enabling state.

In an alternative manner, the controlled current module includes a fifth transistor connected between the second terminal of the first current cell and ground, and a sixth transistor connected between the gate of the fifth transistor and the load terminal;

the method further comprises the steps of:

Configuring the sixth transistor to be turned off before the first edge signal, and configuring the sixth transistor to remain turned off for a period of time from a time point when the first edge signal starts to a time point when the first preset duration ends;

After a delay of a first preset period from the first edge signal, configuring the sixth transistor as a variable resistor, and controlling the rate of rise of the gate voltage of the fifth transistor by adjusting the equivalent resistance of the sixth transistor.

In a third aspect, the present application provides a drive system comprising a high side switch and a high side switch drive circuit as described above;

the high-side switch is connected between the input voltage bus and a load end, the load end is used for being connected with a load, and the high-side switch driving circuit is connected with the high-side switch.

The beneficial effects of the application are as follows: the high-side switch in the high-side switch driving circuit provided by the application is connected between an input voltage bus and a load end, and the load end is used for being connected with a load. The high-side switch driving circuit comprises a grid driving module and a controlled current module. The gate driving module is connected with the high-side switch, and is configured to receive the enabling signal and drive the high-side switch to start to be turned off in response to a first edge signal in the enabling signal. The grid driving module comprises a first current unit, wherein a first end of the first current unit is connected with a grid electrode of the high-side switch, and the first current unit is configured to respond to a first edge signal to enable and output a first discharging current to the grid electrode of the high-side switch so as to discharge the grid electrode of the high-side switch and drive the high-side switch to start to be turned off. The first end of the controlled current module is connected with the load end, the second end of the controlled current module is connected with the second end of the first current unit, the controlled current module is configured to enter an enabling state after a first preset time period is delayed from the first edge signal, and during the period that the controlled current module is in the enabling state, the controlled current module is controlled by the output voltage of the load end to output a second discharging current after the voltage of the load end is firstly increased to be larger than a first preset voltage threshold value. Wherein the second discharging current acts on the first current unit to increase the first discharging current, thereby pulling down the gate voltage of the high-side switch, and further reducing or even eliminating LC resonance that may occur when the high-side switch is turned off when the high-side switch is connected to the inductive load, so as to improve the reliability of the system including the high-side switch.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic structural diagram of a high-side switch driving circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a circuit structure corresponding to the structure shown in FIG. 1;

fig. 3 is a schematic circuit diagram of a driving circuit of a high-side switch according to an embodiment of the present application without including a controlled current module;

FIG. 4 is a schematic diagram of signals in the circuit structure shown in FIG. 3;

FIG. 5 is a schematic diagram of signals in the circuit structure shown in FIG. 2;

FIG. 6 is a second schematic diagram of a circuit structure corresponding to the structure shown in FIG. 1;

FIG. 7 is a schematic diagram of a high side switch driving circuit in the related art;

FIG. 8 is a schematic diagram III of a circuit configuration corresponding to the configuration shown in FIG. 1;

FIG. 9 is a schematic diagram IV of a circuit configuration corresponding to the configuration shown in FIG. 1;

FIG. 10 is a schematic diagram V of a circuit configuration corresponding to the configuration shown in FIG. 1;

FIG. 11 is a schematic diagram of a circuit configuration corresponding to the configuration shown in FIG. 1;

FIG. 12 is a schematic diagram seven of a circuit configuration corresponding to the configuration shown in FIG. 1;

FIG. 13 is a schematic diagram eight of a circuit configuration corresponding to the configuration described in FIG. 1;

fig. 14 is a schematic diagram nine of a circuit configuration corresponding to the configuration shown in fig. 1;

fig. 15 is a schematic diagram of a circuit configuration corresponding to the configuration shown in fig. 1;

Fig. 16 is a schematic diagram eleven of a circuit configuration corresponding to the configuration shown in fig. 1;

FIG. 17 is a schematic diagram showing two ways of replacing the first Zener diode according to the embodiment of the present application;

Fig. 18 is a schematic diagram showing three ways of replacing a third zener diode according to an embodiment of the present application;

Fig. 19 is a flowchart of a high-side switch driving method according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a high-side switch driving circuit according to an embodiment of the application. The high-side switch QA1 is connected between the input voltage bus VBB and a load terminal VOUT, which is used for connecting with the load 200. In some embodiments, load 200 is an inductive load. In some embodiments, the high-side switch QA1 is implemented by an N-type MOS transistor, the drain of the high-side switch QA1 is connected to the input voltage bus VBB, and the source of the high-side switch QA1 is connected to the load terminal VOUT. In other embodiments, the high-side switch QA1 is a load switch connected between a power source (e.g., the positive pole of a battery) and various loads in an automotive vehicle.

As shown in fig. 1, the high-side switch driving circuit 100 includes a gate driving module 10 and a controlled current module 20.

The gate driving module 10 is connected to the high-side switch QA 1. The gate driving module 10 is configured to receive the enable signal EN and drive the high-side switch QA1 to start to be turned off in response to a first edge signal in the enable signal EN. The first edge signal is a rising edge signal or a falling edge signal.

In an embodiment, the gate driving module 10 is further configured to drive the high-side switch QA1 to start conducting in response to the second edge signal in the enable signal EN. The second edge signal is a rising edge signal or a falling edge signal, and the first edge signal is different from the second edge signal.

The first edge signal is taken as a falling edge signal, and the second edge signal is taken as a rising edge signal as an example. The high-side switch QA1 is driven to start to be turned off in response to the falling edge signal in the enable signal EN, and remains low until the next rising edge signal of the enable signal EN comes, and the high-side switch QA1 remains turned off. During the off period of the high-side switch QA1, the input voltage bus VBB stops supplying power to the load 200. Until the next rising edge signal of the enable signal EN, the high-side switch QA1 starts to be turned on in response to the rising edge signal.

In the following embodiments, the first edge signal is taken as a falling edge signal, and the second edge signal is taken as a rising edge signal as an example.

The gate driving module 10 includes a first current unit 11. A first terminal of the first current unit 11 is connected to the gate of the high-side switch QA 1. The first current unit 11 is configured to enable and output a first discharge current to the gate of the high-side switch QA1 in response to the first edge signal to discharge the gate of the high-side switch QA1 and drive the high-side switch QA1 to start to be turned off. In another embodiment, the first current unit 11 is further configured to stop enabling and stopping outputting the first discharge current to the gate of the high-side switch QA1 in response to the second edge signal. Wherein the first current unit 11 operates when the first current unit 11 is enabled; conversely, when the first current unit 11 is disabled, the first current unit 11 is disabled.

A first terminal of the controlled current module 20 is connected to the load terminal VOUT. A second terminal of the controlled current module 20 is connected to a second terminal of the first current cell 11. The controlled current module 20 is configured to enter the enabled state after a first predetermined period of time delay from the first edge signal, and during the period in which the controlled current module 20 is in the enabled state, the controlled current module 20 outputs the second discharge current by being controlled by the output voltage of the load terminal VOUT after the voltage of the load terminal VOUT first rises to be greater than the first predetermined voltage threshold. Wherein the second discharge current acts on the first current unit 11 to increase the first discharge current, thereby pulling down the gate voltage of the high-side switch QA 1. Further, it is possible to achieve reduction or even elimination of LC resonance occurring in the system including the high-side switch QA1 when the load 200 is an inductive load, to improve reliability of the system including the high-side switch QA 1. The first preset duration is a preset duration, the first preset voltage threshold is a preset voltage threshold, and the first preset duration and the first preset voltage threshold can be set according to practical application conditions, which is not particularly limited in the embodiment of the present application. In some embodiments, the first preset voltage threshold may be set to ground potential.

In practice, the high-side switch QA1 starts to turn off once the enable signal EN changes from the logic high level to the logic low level. The controlled current module 20 is configured to be in an enabled state after a first preset period of time has elapsed from the time when the high level of the enable signal EN transitions to the low level (i.e., the falling edge). More specifically, in some embodiments, the controlled current module 20 is further configured to output the second discharge current under the output voltage Vo of the load terminal VOUT after the output voltage Vo of the load terminal VOUT becomes high (e.g., the output voltage Vo first rises above the first preset voltage threshold). Wherein the second discharge current acts on the first current unit 11 to increase the first discharge current, thereby pulling down the gate voltage of the high-side switch QA 1. To prevent the high-side switch QA1 from being turned on again due to resonance of the voltage of the load terminal VOUT.

Referring to fig. 2, fig. 2 illustrates a first circuit configuration of a driving circuit 100 of a high-side switch. As shown in fig. 2, the first current unit 11 includes a first current source I1, a first enabling switch Q1, and a current mirror.

The first enabling switch Q1 is connected between the first current source I1 and the current mirror. The first enable switch Q1 is configured to establish a connection between the first current source I1 and the current mirror in response to the first edge signal to enable the first current cell 11. In this embodiment, the first enable switch Q1 is controlled by the inverted signal of the enable signal ENAs an example. Then, when the enable signal EN is a falling edge, the enable signal EN is invertedIs a rising edge; when the enable signal EN is a rising edge, the enable signal EN is invertedIs the falling edge. It can be seen that the first edge signal of the enable signal EN corresponds to the inverted signal of the enable signal ENIs a second edge signal of (a); the second edge signal of the enable signal EN corresponds to the inverted signal of the enable signal ENIs included. At this time, the first enable switch Q1 is configured to establish a connection between the first current source I1 and the current mirror in response to the first edge signal of the enable signal En, which may correspond to the inverted signal of the first enable switch Q1 in response to the enable signal EnIs turned on to establish a connection between the first current source I1 and the current mirror.

The current mirror is connected to the gate of the high-side switch QA 1. The current mirror is configured to output a first discharge current based on a current of the first current source I1 when the current mirror is connected with the first current source I1. Specifically, after the first enabling switch Q1 is turned on, a connection between the first current source I1 and the current mirror is established, and the current mirror outputs the first discharge current Id based on the current of the first current source I1, so that the high-side switch QA1 starts to be turned off.

In this embodiment, the current mirror includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4.

The drain of the first transistor M1 is connected to the drain of the first enable switch Q1, the gate of the first transistor M1, and the gate of the second transistor M2, respectively. The source of the first enable switch Q1 is connected to the cathode of the first current source I1. The positive pole of the first current source I1 is grounded. The source of the first transistor M1 and the source of the second transistor M2 are both connected to the bias voltage bus VCP. The drain of the second transistor M2 is connected to the drain of the third transistor M3, the gate of the third transistor M3, and the gate of the fourth transistor M4, respectively. The source of the third transistor M3 is connected to the source of the fourth transistor M4 and the load terminal VOUT, respectively. The drain of the fourth transistor M4 is connected to the gate of the high-side switch QA 1. Wherein the voltage on the bias voltage bus VCP is generated by a suitable bias circuit, such as a charge pump circuit. The voltage on bias voltage bus VCP is greater than the voltage on input voltage bus VBB.

Specifically, when the first enable switch Q1 is turned on, the current outputted by the first current source I1 is mirrored to the current flowing from the drain to the source of the fourth transistor M4 through the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, and the current is the first discharge current Id.

In this embodiment, the gate driving module 10 further includes a second current source I2, a gate driving resistor RA1 and a third zener diode ZA1.

The second current source I2 is connected between the bias voltage bus VCP and the gate of the high-side switch QA 1. The gate driving resistor RA1 is connected between the gate of the high-side switch QA1 and the load terminal VOUT. An anode of the third zener diode ZA1 is connected to the gate of the high-side switch QA1, and a cathode of the third zener diode ZA1 is connected to the input voltage bus VBB.

In this embodiment, the second terminal of the controlled current module 20 is connected to the source of the first enable switch Q1. Specifically, the controlled current module 20 includes a fifth transistor M5, a first resistor R1, and a second enable switch Q2.

The drain of the fifth transistor M5 is the second end of the controlled current module 20, the source of the fifth transistor M5 is grounded GND, the gate of the fifth transistor M5 is connected to the load terminal VOUT through the first resistor R1, and the gate of the fifth transistor M5 is grounded GND through the second enable switch Q2.

Wherein the high-side switch QA1 is configured to start to turn off the connection between the input voltage bus VBB and the load terminal VOUT in response to the first edge signal. After a delay of a first preset period from the first edge signal, the second enable switch Q2 is configured to be turned off to bring the controlled current module 20 into an enabled state.

The conventional high-side switching circuit configuration shown in fig. 3 is explained below.

First, the controlled current module 20 is removed on the basis of that shown in fig. 2, and then as shown in fig. 3. At this time, when the load 200 is an inductive load (fig. 3 is an example of the load 200 being equivalent to a resistor ROUT and an inductor LOUT), LC resonance may occur when the high-side switch QA1 is turned off, and the following procedure is specifically described:

as shown in fig. 3, the second current source I2 is controlled by the enable signal EN, and the first current unit 11 is controlled by the inverted signal of the enable signal EN And (5) controlling. When the high-side switch QA1 is enabled to cause the voltage on the input voltage bus VBB to supply power to the load 200, the enable signal EN enables the second current source I2, and the second current source I2 outputs the charging current Ic to start charging the gate of the high-side switch QA1 until it is charged to a voltage greater than or equal to the sum of the voltage on the input voltage bus VBB and the on-voltage threshold (denoted as Δv) of the high-side switch QA 1. In other words, the gate-source voltage (voltage difference between the gate and the source) of the high-side switch Q1 is greater than or equal to the on-voltage threshold Δv of the high-side switch QA 1. Thus, the high side switch QA1 is turned on to cause the voltage on the input voltage bus VBB to power the load 200.

When the high-side switch QA1 is disabled, the input voltage bus VBB stops providing power to the load 200, the second current source I2 stops charging the gate of the high-side switch QA1, and when the first enable switch Q1 is powered by the inverted signal of the enable signal ENThe turn-on is controlled, and the current outputted by the first current source I1 is mirrored to the current flowing from the drain to the source of the fourth transistor M4, i.e. the first discharging current Id, through the first enabling switch Q1 and the current mirror circuit composed of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, so as to start discharging the gate of the high-side switch QA1 until the voltage at the load terminal VOUT is zero. In other words, the gate-source voltage of the high-side switch QA1 is reduced to zero, and then the high-side switch QA1 is turned off. Thus, current is prevented from flowing from the input voltage bus VBB to the load 200.

The gate drive resistor RA1 has the effect that when the high side switch QA1 is turned off and the first current unit 11 is not available, the gate drive resistor RA1 can ensure that the high side switch QA1 is still turned off by continuously discharging the gate of the high side switch QA1. In some embodiments, the resistance value of the gate driving resistor RA1 is configured to be in a range of about 100kΩ to about 300kΩ. However, this small resistance value of the gate drive resistor RA1 makes the design of the current limiting function of the high-side switch Q1 more complex and challenging. To relax the design of the high-side switch QA1 current limiting function, the resistance value of the gate driving resistor RA1 must be increased to several mega ohms. However, the higher resistance of the gate driving resistor RA1 reduces the gate passive pull-down effect of the high-side switch QA1, so that the pull-down process becomes less effective. In some applications where the load 200 is inductive, the gate drive resistor RA1 with a higher resistance value cannot reliably turn off the high-side switch QA1 when the high-side switch QA1 needs to be turned off. If the load 200 is an inductive load, the high-side switch QA1 is turned off to cause an abnormal situation such as LC resonance, and further, components such as the high-side switch QA1 may be damaged.

Referring to fig. 3 and fig. 4 together, fig. 4 is a schematic diagram showing signals in the circuit structure shown in fig. 3. Wherein the abscissa of fig. 4 represents time. The ordinate includes three signals from top to bottom, the first signal being the enable signal EN; the second signal is the output voltage VO on the load terminal VOUT; the third signal is the output current IOUT flowing through the load 200. The various waveforms shown in fig. 4 illustrate the operation of the circuit shown in fig. 3 when load 200 is an inductive load.

At time t10, the enable signal EN has a logic high level. The high-side switch QA1 has been fully turned on. Since the high-side switch QA1 is fully on, the output voltage VO is approximately equal to the voltage on the input voltage bus VBB (i.e., ≡vbb in fig. 4). Power is supplied from the input voltage bus VBB to the inductive load. The current flowing into the inductive load is IL. The gate of the high-side switch QA1 is controlled by a second current source I2. The voltage on the gate of high-side switch QA1 is equal to or greater than the sum of the voltage on input voltage bus VBB and the on-voltage threshold Δv of high-side switch QA 1.

At time t11, the enable signal EN changes from a logic high level to a logic low level (i.e., a falling edge). In response to the falling edge, the first discharge current Id and the gate driving resistor RA1 start discharging the gate voltage of the high-side switch QA1, and the high-side switch QA1 starts turning off. At the same time, the inductive load begins to draw current from the parasitic capacitance (e.g., parasitic capacitance CP in fig. 3, which is the parasitic capacitance of load terminal VOUT) to maintain output current IOUT. Once the inductive load begins to discharge through the parasitic capacitance CP, the output voltage VO of the load terminal VOUT begins to drop rapidly, and the output current IOUT begins to drop from time t11 to time t 12.

At time t12, the output voltage VO drops below zero (ground) and further drops to a negative voltage. Once the output voltage VO drops too low, the voltage clamping mechanism of the third zener diode ZA1 is triggered. As the third zener diode ZA1 begins to breakdown due to the reverse bias voltage being too high, the third zener diode ZA1 supports current flowing from the input voltage bus VBB to the gate of the high side switch QA1 and then to the load terminal VOUT. This breakdown current establishes a bias voltage between the gate and source of the high-side switch QA1 through the gate drive resistor RA 1. This bias keeps the high side switch QA1 on and reaches equilibrium at time t 12.

From time t12 to time t13, the output voltage VO is held at a negative voltage level. The output current IOUT decreases linearly with a slope equal to (VO/LOUT). As the output current IOUT decreases linearly, the bias voltage between the gate and source of the high-side switch QA1 corresponding to the output current IOUT to be supplied decreases. Therefore, the output voltage VO slowly increases. During this time, the parasitic capacitance CP is also charged to the negative voltage-V _clamp. In some embodiments, after the third zener diode ZA1 is broken down, the sum of the voltage of the input voltage bus VBB and V _clamp is the breakdown voltage of the third zener diode ZA 1.

At time t13, the output current IOUT decreases to zero. This means that no current needs to pass through the high side switch QA1 and its gate drive resistor RA1. Thus, the high-side switch QA1 is turned off for the first time. After the zero crossing of the output current IOUT, the output current IOUT continues to decrease to a negative current. This is because the parasitic capacitance CP of the load terminal VOUT starts to discharge through the inductive load, forming an LC resonance. Therefore, in the case where the high-side switch Q1 is turned off, the output voltage VO starts to rise rapidly from time t13 to time t 14. When the parasitic capacitance CP completes the discharge of the inductive load, the output voltage VO crosses zero and the discharge is started by the inductive load.

At time t14, the output voltage VO reaches its peak voltage, at which time the output current IOUT crosses zero again. The peak voltage of the output voltage VO at time t14 may be as high as the sum of the voltages of the input voltage bus VBB and the voltage VBD. The voltage VBD is the forward conduction voltage drop of the parasitic body diode BD1 of the high-side switch QA 1. In LC resonance, energy is injected into the input voltage bus VBB.

After time t14, the output voltage VO drops again because the inductive load tries to draw current to maintain the resonant current. At this time, the high-side switch QA1 is turned on again to supply current to the load 200. Specifically, the output voltage VO drops linearly from time t14 to time t15 and in so doing generates sufficient current to flow through the parasitic capacitance Cgd between the drain and gate of the high-side switch QA1 to establish a sufficient bias voltage across the relatively large gate drive resistor RA1 to sufficiently turn on the high-side switch QA1 to maintain the varying output current IOUT. In this process, the output voltage VO crosses zero potential because the output current IOUT again peaks. The inductive load completes the process of discharging its stored magnetic energy into the parasitic capacitance CP of the load terminal VOUT. After this, the parasitic capacitance CP starts to discharge its stored energy again to the inductive load, resulting in a decrease of the output current IOUT.

At time t15, the output current IOUT decreases again to zero. Since no current needs to flow through the high side switch QA1 and its parasitic bias path, the high side switch QA1 is turned off a second time. Then, the resonance period starts again. Thereafter, the output voltage VO reaches another peak value at time t 16. The high side switch QA1 will then be turned on again to maintain the output current IOUT. In some cases, this resonance will last for many cycles. The peak value of the output voltage VO reaching or exceeding the voltage of the input voltage bus VBB is a dangerous operation state of the system (e.g. at time t 13), based on which the embodiment of the present application further provides the controlled current module 20 to reduce or eliminate LC resonance caused by turning off the high-side switch QA1 when the inductive load 200 is connected, thereby achieving the purpose of protecting the system including the high-side switch QA1 from damage.

Referring back to fig. 2, in practical application, in response to the falling edge of the enable signal EN, the gate of the high-side switch Q1 discharges through the first discharge current Id mirrored from the first current unit 11 and the gate driving resistor RA1, and the high-side switch QA1 starts to turn off. After a first preset period of time from the instant of the falling edge of the enable signal EN, the controlled current module 20 is configured to be in an enabled state. The enabled controlled current module 20 outputs a second discharging current Ip after the voltage of the load terminal VOUT rises to be greater than the first preset voltage threshold for the first time, the second discharging current Ip is added to the output current of the first current source I1, and the first discharging current Id is mirrored onto the fourth transistor M4 through the current mirror in the first current unit 11 to increase, so that the gate voltage of the high-side switch QA1 is pulled down. Once the gate voltage of the high-side switch QA1 is pulled low, the high-side switch QA1 may be kept off to prevent current from flowing through the high-side switch QA1 to the load 200, thereby reducing the output voltage VO to zero.

The controlled current module 20 may be enabled or disabled by a second enable switch Q2 controlled by the delayed enable signal DEN. The delayed enable signal DEN has a delayed falling edge compared to the enable signal EN, i.e. the falling edge of the delayed enable signal is delayed by the falling edge of the corresponding enable signal EN. The second enable switch Q2 is controlled by the delay enable signal DEN, and the second enable switch Q2 can pull the gate of the fifth transistor M5 to ground, thereby disabling the fifth transistor M5.

Since the gate of the fifth transistor M5 is connected to the load terminal VOUT, the first resistor R1 is used to protect the load terminal VOUT from being shorted to the ground GND during the period when the high-side switch QA1 is turned on. The resistance value of the first resistor R1 can be selected by analyzing the minimum load of the system so that it does not affect the operation of the minimum load. For example, if the equivalent resistance value of the minimum load is equal to Rmin, the resistance value of the first resistor R1 is at least ten times that of Rmin.

By providing the controlled current module 20, the gate voltage of the high-side switch QA1 can be reliably pulled down to the ground voltage potential, and the high-side switch QA1 can be reliably turned off. Reliable turn-off of high-side switch QA1 helps to reduce or eliminate LC resonance caused by turn-off of high-side switch QA1 when an inductive load is connected, thereby protecting components of the system (e.g., components in high-side switch QA1 and/or load 200) from damage during the transition of high-side switch QA1 from on to off.

Referring to fig. 2 and fig. 5 together, fig. 5 shows a schematic diagram of signals in the circuit structure shown in fig. 2. Wherein the abscissa of fig. 5 represents time. The ordinate includes four signals from top to bottom, the first signal being an enable signal EN; the second signal is a delay enable signal DEN; the third signal is the output voltage VO on the load terminal VOUT; the fourth signal is the output current IOUT flowing through the load 200. The various waveforms shown in fig. 5 illustrate the operation of the circuit shown in fig. 2 when load 200 is an inductive load.

As shown in fig. 5, the falling edge of the delayed enable signal DEN occurs after the falling edge of the enable signal EN. The interval between these two falling edges is a predetermined time td. the duration of td is determined by the off time of the high-side switch QA 1. The duration between time t21 and time t22 is the off time of the high-side switch QA 1. In some embodiments, td is greater than the off time of the high-side switch QA 1. Therefore, the controlled current module 20 can cause the high-side switch QA1 not to be turned off too quickly through the discharge path of the fifth transistor M5. The off slope is typically a design requirement of the high-side switch QA1 and is determined mainly by the gate driving module 10. In addition, the controlled current module 20 needs to be enabled by the delay enable signal DEN before the output current IOUT falls to zero (i.e. before the output voltage VO rises again or before the high-side switch QA1 is completely turned off), for example, before time t 23. In other words, the controlled current module 20 needs to be enabled before the time t23, specifically corresponding to the time when the first preset period ends being earlier than the time when the output current IOUT of the load terminal VOUT first drops to zero (time t 23). The controlled current module 20 is enabled by the falling edge of the delay enable signal DEN. The falling edge of the delay enable signal DEN occurs between the time t22 and the time t 23.

Once the high-side switch QA1 transitions from the on state to the off state, the output voltage VO is limited by the controlled current module 20. As shown in fig. 5, the output voltage VO can only reach a voltage level equal to the voltage drop across the first resistor R1 at time t 24. At time t24, the output voltage VO is sufficient to turn on the fifth transistor M5, and the second discharge current Ip is immediately generated to act on the first current unit 11 to increase the first discharge current Id, thereby discharging the gate of the high-side switch QA1, and turning off the high-side switch QA1, so that the output voltage oscillation is not generated any more. At time t24, the output voltage VO starts to fall. And when the output voltage VO reaches zero, the LC resonance stops.

In other embodiments, as shown in fig. 6, when the load 200 to which the load terminal VOUT is connected includes the battery BAT, it is possible to prevent the battery BAT from having an abnormal leakage while reducing or even eliminating LC resonance.

Specifically, in the related art, as shown in fig. 7, the direct connection of the drain of the fifth transistor M5 to the gate of the high-side switch QA1 can also achieve reduction or even elimination of LC resonance caused by turning off the high-side switch QA1 when an inductive load is connected. However, in this embodiment, when the fifth transistor M5 is turned on, a path is formed between the battery BAT, the body diode of the fourth transistor M4, and the fifth transistor M5 and the ground GND, and then the battery BAT has a discharging path. It can be seen that the battery BAT is always in a leaky state, causing additional loss of energy.

In the embodiment of the present application, the gate of the fifth transistor M5 is connected to the first enable switch Q1, instead of directly connected to the gate of the high-side switch QA1, so that the LC resonance caused by turning off the high-side switch QA1 when the inductive load is connected can be reduced or even eliminated. And, at the same time, a path for discharging the battery BAT when the battery is connected is avoided, so that no extra loss of energy is caused.

In one embodiment, as shown in fig. 8, the controlled current module 20 further includes a first zener diode Z1.

The first zener diode Z1 is connected between the gate of the fifth transistor M5 and the ground GND. The first zener diode Z1 is added at the gate of the fifth transistor M5 to prevent the gate of the fifth transistor M5 from being damaged by an overvoltage occurring during the transition of the high-side switch QA1 from on to off.

Specifically, first, the first zener diode Z1 clamps the output voltage VO to prevent the output voltage VO from being excessively high after the high-side switch QA1 is turned off. This prevents the input voltage bus VBB from injecting more energy into the inductive load to facilitate LC resonance when the load 200 comprises an inductive load. Next, while the first zener diode Z1 clamps the output voltage VO, the fifth transistor M5 is turned on because the clamping voltage of the first zener diode Z1 is higher than the turn-on threshold gate-source voltage of the fifth transistor M5. The turned-on fifth transistor M5 generates a second discharge current Ip mirrored to the fourth transistor M4 through the current mirror in the first current unit 11, thereby increasing the first discharge current Id to accelerate the gate discharge of the high-side switch Q1, thereby maintaining the high-side switch QA1 turned off and preventing the high-side switch QA1 from being turned on again, which is beneficial for reducing or eliminating the subsequent LC resonance.

In one embodiment, as shown in fig. 9, the controlled current module 20 further includes a second resistor R2.

The source of the fifth transistor M5 is grounded GND through the second resistor R2, and the second enabling switch Q2 is connected between the gate of the fifth transistor M5 and the ground GND. The second resistor R2 is used for controlling the magnitude of the second discharge current Ip.

The embodiment of the application also provides another connection mode for the second enabling switch Q2 and the first resistor R1 in fig. 2, 6, 8 and 9. In particular, another connection method between the second enable switch Q2 and the first resistor R1 in fig. 10 is illustrated as an example.

As shown in fig. 10, the fifth transistor M5, the second resistor R2 and the first zener diode Z1 are connected in the same manner as in fig. 9, except that in this embodiment, the second enabling switch Q2 and the first resistor R1 are connected in series between the gate of the fifth transistor M1 and the load terminal VOUT.

In this embodiment, the high-side switch QA1 is configured to stop the voltage on the input voltage bus VBB from powering the load 300 in response to the falling edge of the enable signal EN. The second enable switch Q2 is configured to be turned on after a first preset period of time (e.g., td in fig. 5) elapses after a falling edge of the enable signal EN. In response to the conduction of the second enable switch Q2, the voltage on the load terminal VOUT is applied to the gate of the fifth transistor M5. The fifth transistor M5 is turned on after the output voltage VO of the load terminal VOUT rises above a first predetermined voltage threshold (e.g., ground). Then, the fifth transistor M5 is controlled by the output voltage of the load terminal VOUT to generate the second discharge current Ip flowing through the fifth transistor M5. The second discharging current Ip is added to the output current of the first current source I1, and mirrored onto the fourth transistor M4 through the current mirror in the first current unit 11, so as to increase the first discharging current Id to accelerate the gate discharge of the high-side switch Q1, thereby maintaining the high-side switch QA1 turned off and preventing the high-side switch QA1 from being turned on again, which is beneficial to reducing or eliminating the subsequent LC resonance.

In an embodiment, the second enabling switch Q2 and the first resistor R1 in the structure shown in fig. 10 may also be implemented as a combination of one transistor (the sixth transistor M6 in this embodiment).

As shown in fig. 11, the sixth transistor M6 is connected between the gate of the fifth transistor M5 and the load terminal VOUT. The first zener diode Z1 is connected between the gate of the fifth transistor M5 and the ground GND. The fifth transistor M5 and the second resistor R2 are connected in series between the source of the first enable switch Q1 and the ground GND.

The controlled current module 20 in fig. 11 is similar to the controlled current module 20 in fig. 10, except that the second enable switch Q2 and the first resistor R1 are combined into one MOS transistor (e.g., the sixth transistor M6 in fig. 11). The sixth transistor M6 is configured to be turned off before the falling edge of the enable signal EN. After a first preset period of time from the falling edge of the enable signal EN, the sixth transistor M6 is biased in the linear region such that the sixth transistor M6 exhibits a variable resistance. Further, the rising rate of the gate voltage of the fifth transistor M5 may be controlled by adjusting the bias voltage of the sixth transistor M6.

In the embodiments shown in fig. 2, 6 and 8-11, since the drain of the fifth transistor M5 is connected to the source of the first enable switch Q1, the second discharge current Ip generated on the fifth transistor M5 needs to be dependent on the conduction of the first enable switch Q1 to be effective. To eliminate this dependency, embodiments of the present application also provide a way to connect the second terminal of the controlled current module 20 to the drain of the first enabling switch Q1 to be able to more reliably reduce or even eliminate the LC resonance generated by turning off the high-side switch QA1 when an inductive load is connected.

For example, in one embodiment, if the drain of the fifth transistor M5 shown in fig. 6 is connected to the drain of the first enable switch Q1, then it is shown in fig. 12.

Specifically, the enable signal EN is generated after the system is powered up. The enable signal EN and the first current source I1 require power in the system other than the voltage on the input voltage bus VBB. At the same time, the bias voltage VCP is generated by the voltage on the input voltage bus VBB through the charge pump circuit, and can be maintained as the voltage on the input voltage bus VBB minus one body diode drop even when the system is not powered up. As shown in fig. 12, when the system is not powered up, the second discharging current Ip generated in the fifth transistor M5 can act on the fourth transistor M4 through the current mirror in the first current unit 11 as long as the fifth transistor M5 is driven to operate in the linear region, thereby accelerating the turn-off of the high-side switch QA 1. Compared to the embodiment shown in fig. 6, the second discharge current Ip generated in the fifth transistor M5 in the embodiment shown in fig. 11 can function to accelerate the turn-off of the high-side switch QA1 without depending on the turn-on of the first enable switch Q1, which is more reliable.

As another example, in one embodiment, if the drain of the fifth transistor M5 shown in fig. 8 is connected to the drain of the first enable switch Q1, then it is shown in fig. 13. In an embodiment, if the drain of the fifth transistor M5 shown in fig. 9 is connected to the drain of the first enable switch Q1, then it is shown in fig. 14. In an embodiment, if the drain of the fifth transistor M5 shown in fig. 10 is connected to the drain of the first enable switch Q1, then it is shown in fig. 15. In an embodiment, if the drain of the fifth transistor M5 shown in fig. 11 is connected to the drain of the first enable switch Q1, then it is shown in fig. 16. The specific implementation of the embodiment shown in fig. 13-16 may refer to the description of the embodiment shown in fig. 12, which is within the scope of those skilled in the art to easily understand, and will not be repeated here.

It should be noted that, in the above-described embodiments, the first zener diode Z1 and the third zener diode ZA1 are used as the voltage clamp in the high-side switch driving circuit 100 in each embodiment to implement the voltage clamping function. While the above-described implementation of the first zener diode Z1 and the third zener diode ZA1 is merely an example, it should not unduly limit the scope of the claims, and those skilled in the art will recognize many variations, alternatives, and modifications.

For example, the first zener diode ZS1 can also be replaced by two ways as shown in fig. 17.

Specifically, as shown in part a of fig. 17, the controlled current module 20 further includes a second zener diode Z2 and at least one first diode. The at least one first diode comprises a first diode DA1 and a second first diode DA2 … ith first diode DAi, wherein i is an integer more than or equal to 1.

At least one first diode and a second zener diode are connected in series between the gate of the fifth transistor M5 and the ground GND. Specifically, the anode of the second zener diode Z2 is grounded, and the cathode of the second zener diode Z2 is connected to the cathode of the first diode DA 1. The anode of the first diode DA1 is connected with the cathode of the second first diode DA2, the anode of the second first diode DA2 is connected with the cathode of the third first diode DA3, … the anode of the i-1 th first diode DAi-1 is connected with the cathode of the i-th first diode DAi. The anode of the i-th first diode DAi is connected to the gate of the fifth transistor M5.

As shown in part b of fig. 17, the controlled current module 20 further comprises at least one second diode. The at least one second diode comprises a first second diode DB1, a second diode DB2 … and a j-th second diode DBj, wherein j is an integer more than or equal to 1.

At least one second diode is connected in series between the gate of the fifth transistor M5 and ground GND. Specifically, the cathode of the first second diode DB2 is grounded GND. The anode of the first second diode DB1 is connected to the cathode of the second diode DB2, the anode of the second diode DB2 is connected to the cathode of the third second diode DB3, and the anode of the j-1 th second diode DBj-1 is connected to the cathode of the j-th second diode DBj …. The anode of the j-th second diode DBj is connected to the gate of the fifth transistor M5.

As another example, the third zener diode ZA1 can also be replaced by the three ways shown in fig. 18.

Specifically, as shown in part c of fig. 18, the gate driving module 10 further includes a plurality of third zener diodes. The plurality of third zener diodes includes a first third zener diode ZA1, a second third zener diode ZA2 …, a kth third zener diode ZAk, and k is an integer greater than or equal to 2.

In some embodiments, a plurality of third zener diodes are connected in series between the input voltage bus VBB and the gate of the high-side switch QA 1. Specifically, the anode of the first third zener diode ZA1 is connected to the gate of the high-side switch QA 1. The cathode of the first third zener diode ZA1 is connected to the anode of the second third zener diode ZA2, the cathode of the second third zener diode ZA2 is connected to the anode of the third zener diode ZA3, the cathode of the k-1 th third zener diode ZAk-1 is connected … to the anode of the k third zener diode ZAk. The cathode of the kth third zener diode ZAk is connected to the input voltage bus VBB.

In other embodiments, a plurality of third zener diodes are connected in series between the input voltage bus VBB and the load terminal VOUT. Specifically, the anode of the first third zener diode ZA1 is connected to the load terminal VOUT. The cathode of the first third zener diode ZA1 is connected to the anode of the second third zener diode ZA2, the cathode of the second third zener diode ZA2 is connected to the anode of the third zener diode ZA3, the cathode of the k-1 th third zener diode ZAk-1 is connected … to the anode of the k third zener diode ZAk. The cathode of the kth third zener diode ZAk is connected to the input voltage bus VBB.

As shown in part d of fig. 17, the gate driving module 10 also includes k third zener diodes.

In some embodiments, k third zener diodes are connected in series between the input voltage bus VBB and the gate of the high-side switch QA 1. Specifically, the anode of the first third zener diode ZA1 is connected to the gate of the high-side switch Q1. The cathode of the first third zener diode ZA1 is connected to the cathode of the second third zener diode ZA2, the anode of the second third zener diode ZA2 is connected … to the anode of the third zener diode ZA3, and the cathode of the kth-1 third zener diode ZAk-1 is connected to the cathode of the kth third zener diode ZAk. An anode of the kth third zener diode ZAk is connected to the input voltage bus VBB.

In other embodiments, k third zener diodes are connected in series between the input voltage bus VBB and the load terminal VOUT. I.e. the anode of the first third zener diode ZA1 is connected to the load terminal VOUT. The cathode of the first third zener diode ZA1 is connected to the cathode of the second third zener diode ZA2, the anode of the second third zener diode ZA2 is connected … to the anode of the third zener diode ZA3, and the cathode of the kth-1 third zener diode ZAk-1 is connected to the cathode of the kth third zener diode ZAk. An anode of the kth third zener diode ZAk is connected to the input voltage bus VBB.

As shown in part e of fig. 18, the gate driving module 10 also includes at least one fourth zener diode and at least one third diode. The at least one fourth zener diode comprises a first fourth zener diode ZB1, a second fourth zener diode ZB2 …, an mth fourth zener diode ZBm, and m is an integer greater than or equal to 1. The at least one third diode comprises a first third diode DC1, a second third diode DC2 … and a p-th third diode DCp, wherein p is an integer more than or equal to 1.

In some embodiments, at least one fourth zener diode and at least one third diode are connected in series between the input voltage bus VBB and the gate of the high-side switch QA 1. Specifically, the cathode of the first fourth zener diode ZB1 is connected to the cathode of the first third diode DC 1. The anode of the first fourth zener diode ZB1 is connected to the cathode of the second fourth zener diode ZB2, the anode of the second fourth zener diode ZB2 is connected to the cathode of the third fourth zener diode ZB3, and the anode of the m-1 th fourth zener diode ZBm-1 is connected to the cathode of the m-th fourth zener diode ZBm. An anode of the mth fourth zener diode ZBm is connected to the gate of the high-side switch QA 1. The anode of the first third diode DC1 is connected to the cathode of the second third diode DC2, the anode of the second third diode DC2 is connected to the cathode of the third diode DC2 … the anode of the p-1 th third diode DCp-1 is connected to the cathode of the p-th third diode DCp. The anode of the p-th third diode DCp is connected to the input voltage bus VBB.

In other embodiments, at least one fourth zener diode and at least one third diode are connected in series between the input voltage bus VBB and the load terminal VOUT. Specifically, the cathode of the first fourth zener diode ZB1 is connected to the cathode of the first third diode DC 1. The anode of the first fourth zener diode ZB1 is connected to the cathode of the second fourth zener diode ZB2, the anode of the second fourth zener diode ZB2 is connected to the cathode of the third fourth zener diode ZB3, and the anode of the m-1 th fourth zener diode ZBm-1 is connected to the cathode of the m-th fourth zener diode ZBm. An anode of the mth fourth zener diode ZBm is connected to the load terminal VOUT. The anode of the first third diode DC1 is connected to the cathode of the second third diode DC2, the anode of the second third diode DC2 is connected to the cathode of the third diode DC2 … the anode of the p-1 th third diode DCp-1 is connected to the cathode of the p-th third diode DCp. The anode of the p-th third diode DCp is connected to the input voltage bus VBB.

It should be noted that each diode or zener diode shown in fig. 17 and 18 may be implemented as other suitable semiconductor devices, for example, the diode may be implemented by a MOS transistor. Meanwhile, the modes shown in fig. 17 and 18 are applicable to all the schemes of the embodiment of the present application.

Referring to fig. 19, fig. 19 is a flowchart of a high-side switch driving method according to an embodiment of the application. The high-side switch is connected between the input voltage bus and a load end, and the load end is used for being connected with a load.

As shown in fig. 19, the high-side switch driving method includes the following method steps:

Step 1901: in response to a first edge signal of the enabling signal, a first current unit in the grid driving module is configured to be in an enabling state, so that the first current unit outputs a first discharging current to a grid of the high-side switch and drives the high-side switch to start to be turned off.

Step 1902: after a first edge signal of the enabling signal is delayed for a first preset time period, configuring the controlled current module into an enabling state, so that the controlled current module is controlled by the output voltage of the load end to output a second discharge current after the voltage of the load end is firstly increased to be greater than a first preset voltage threshold; wherein the second discharge current acts on the first current cell to increase the first discharge current, thereby pulling down the gate voltage of the high-side switch.

In one embodiment, the first current unit includes a first current source, a first enable switch and a current mirror, and the current mirror includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain electrode of the first transistor is connected with the drain electrode of the first enabling switch, the grid electrode of the first transistor and the grid electrode of the second transistor respectively. The source of the first enabling switch is connected with the cathode of the first current source. The positive pole of the first current source is grounded. The source of the first transistor and the source of the second transistor are both connected to the bias voltage bus. The drain electrode of the second transistor is respectively connected with the drain electrode of the third transistor, the grid electrode of the third transistor and the grid electrode of the fourth transistor. The source electrode of the third transistor is respectively connected with the source electrode and the load end of the fourth transistor. The drain of the fourth transistor is connected to the gate of the high side switch. The second end of the first current unit is a source electrode or a drain electrode of the first enabling switch.

In step 1901, in response to the first edge signal of the enable signal, a specific implementation process for configuring the first current unit in the gate driving module to be in the enabled state includes the following steps: in response to a first edge signal of the enable signal, a first enable switch is configured to be turned on to enable the first current unit.

In an embodiment, the controlled current module includes a fifth transistor connected between the second terminal of the first current cell and ground, a first resistor connected between the gate of the fifth transistor and the load terminal, and a second enable switch connected between the gate of the fifth transistor and ground.

In step 1902, after a delay of a first preset duration from a first edge signal of the enable signal, a specific implementation process of configuring the controlled current module to be in an enable state includes the following steps: after a first preset time period is delayed from the first edge signal, the second enabling switch is configured to be turned off, so that the controlled current module is configured to be in an enabling state.

In an embodiment, the controlled current module includes a fifth transistor connected between the second terminal of the first current cell and ground, and a first resistor and a second enable switch connected in series between the gate of the fifth transistor and the load terminal.

In step 1902, after a delay of a first preset duration from a first edge signal of the enable signal, a specific implementation process of configuring the controlled current module to be in an enable state includes the following steps: after a first preset time period is delayed from the first edge signal, the second enabling switch is configured to be conducted so as to configure the controlled current module to be in an enabling state.

In one embodiment, the controlled current module includes a fifth transistor connected between the second terminal of the first current cell and ground and a sixth transistor connected between the gate of the fifth transistor and the load terminal.

The high-side switch driving method further comprises the following method steps: configuring the sixth transistor to be turned off before the first edge signal, and configuring the sixth transistor to remain turned off for a period of time from a time point when the first edge signal starts to a time point when the first preset period of time ends; after a delay of a first preset period from the first edge signal, the sixth transistor is configured as a variable resistor, and the rate of rise of the gate voltage of the fifth transistor is controlled by adjusting the equivalent resistance of the sixth transistor.

It should be appreciated that, in the method embodiment, specific control and beneficial effects of the high-side switch may refer to corresponding descriptions in the embodiments of the high-side switch driving circuit, which are not repeated herein for brevity.

Embodiments of the present application also provide a drive system that includes a high-side switch and a high-side switch drive circuit 100 in any of the embodiments of the present application. The high-side switch is connected between the input voltage bus and the load end, the load end is used for being connected with a load, and the driving circuit of the high-side switch is connected with the high-side switch.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the application as described above, which are not provided in detail for the sake of brevity; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A high side switch drive circuit, wherein, high side switch connects between input voltage bus and load end, the load end is used for being connected with the load, high side switch drive circuit includes:

2. The high side switch driving circuit according to claim 1, wherein the first preset voltage threshold is ground potential.

3. The high-side switch driving circuit according to claim 1, wherein the first preset time period ends earlier than the time period when the output current of the load terminal first drops to zero.

4. The high-side switch driving circuit according to claim 1, wherein the first current unit comprises a first current source, a first enable switch and a current mirror;

5. The high-side switch driving circuit according to claim 4, wherein the current mirror comprises a first transistor, a second transistor, a third transistor, and a fourth transistor;

6. The high side switch driving circuit according to claim 4, wherein the second terminal of the first current cell is a source of the first enable switch or the second terminal of the first current cell is a drain of the first enable switch.

7. The high-side switch driving circuit according to claim 6, wherein the controlled current module comprises a fifth transistor, a first resistor and a second enable switch;

8. The high-side switch drive circuit of claim 7, wherein the controlled current module further comprises a first zener diode, or a second zener diode, and at least one first diode, or at least one second diode;

9. The high-side switch drive circuit of claim 7, wherein the controlled current module further comprises a second resistor;

the source of the fifth transistor is grounded through the second resistor.

10. The high-side switch driving circuit according to any one of claims 7 to 9, wherein the second enable switch is connected between a gate of the fifth transistor and ground;

11. The high-side switch driving circuit according to any one of claims 7 to 9, wherein the second enable switch and the first resistor are connected in series between a gate of the fifth transistor and the load terminal;

12. The high side switch driving circuit according to claim 1, wherein the gate driving module further comprises a second current source and a gate driving resistor;

13. The high-side switch drive circuit of claim 1, wherein the gate drive module comprises at least one third zener diode, or at least one fourth zener diode and at least one third diode;

14. The high-side switch driving method is characterized in that the high-side switch is connected between an input voltage bus and a load end, the load end is used for being connected with a load, and the high-side switch driving method comprises the following steps:

15. The method of claim 14, wherein the first current cell comprises a first current source, a first enable switch, and a current mirror, the current mirror comprising a first transistor, a second transistor, a third transistor, and a fourth transistor;

16. The high-side switch driving method according to claim 14, wherein the controlled current module includes a fifth transistor connected between a second terminal of the first current cell and ground, a first resistor connected between a gate of the fifth transistor and the load terminal, and a second enable switch connected between the gate of the fifth transistor and ground;

17. The high-side switch driving method according to claim 14, wherein the controlled current module includes a fifth transistor connected between a second terminal of the first current cell and ground, and a first resistor and a second enable switch connected in series between a gate of the fifth transistor and the load terminal;

18. The high-side switch driving method according to claim 14, wherein the controlled current module includes a fifth transistor connected between a second terminal of the first current cell and ground and a sixth transistor connected between a gate of the fifth transistor and the load terminal;

the method further comprises the steps of:

19. A drive system comprising a high side switch and a high side switch drive circuit as claimed in any one of claims 1 to 13;