CN118314943B - Method and device for determining optimal read voltage parameters of flash memory and flash memory equipment - Google Patents
Method and device for determining optimal read voltage parameters of flash memory and flash memory equipment Download PDFInfo
- Publication number
- CN118314943B CN118314943B CN202410756574.5A CN202410756574A CN118314943B CN 118314943 B CN118314943 B CN 118314943B CN 202410756574 A CN202410756574 A CN 202410756574A CN 118314943 B CN118314943 B CN 118314943B
- Authority
- CN
- China
- Prior art keywords
- offset value
- voltage offset
- read
- bit
- new
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000011478 gradient descent method Methods 0.000 claims description 15
- 230000006870 function Effects 0.000 claims description 14
- 238000004590 computer program Methods 0.000 claims description 10
- 230000007306 turnover Effects 0.000 claims description 10
- 230000003044 adaptive effect Effects 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 4
- 238000013461 design Methods 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000032683 aging Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010223 real-time analysis Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 238000012417 linear regression Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Read Only Memory (AREA)
Abstract
The application relates to the technical field of storage, and provides a method and a device for determining optimal read voltage parameters of a flash memory and flash memory equipment, wherein the method comprises the following steps: acquiring a new read retry voltage offset value corresponding to the minimum predicted bit flip number of the flash memory according to a linear relation model between the read retry voltage offset value and the bit flip number; judging whether the data can be successfully read under the new reading retry voltage offset value; if yes, adding the new reading retry voltage offset value to the head of the reading retry offset table to form a new reading retry offset table; and updating the linear relation model through the self-adaptive learning model according to the new reading retry offset table. The application can improve the success rate of data recovery and reduce the performance loss through the high-efficiency voltage parameter determination method with the self-adaptive effect.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to a method and an apparatus for determining an optimal read voltage parameter of a flash memory, and a flash memory device.
Background
NAND FLASH memories are widely used in modern electronic devices due to their high density and non-volatile nature. As technology advances, the storage density of NAND FLASH memories is increasing, but at the same time, the reliability of the memory cells is challenging. As memory usage time increases, memory cells may age, so too does charge loss or the cumulative impact of program/erase cycles, resulting in an increased probability of read errors. To address this challenge, the prior art has employed READ RETRY (read retry offset) mechanisms that attempt to find a parameter configuration that can successfully read data by retrying the read operation multiple times and adjusting certain read parameters in each retry.
The existing READ RETRY technology relies mainly on preset parameter gears, which are usually determined according to the standard characteristics of Flash. When the read operation fails, the controller attempts these preset gear steps one by one. While this approach can effectively recover data in some situations, it also has some significant limitations. First, the preset gear may not cover all possible error modes, especially when the memory ages or operates under non-standard environmental conditions. Second, this approach often lacks flexibility in finding a valid gear because it cannot be adjusted to real-time errors. Furthermore, due to the limited number of preset gears, the conventional READ RETRY method may result in an unnecessary performance degradation when all gears cannot successfully correct errors. Thus, the prior art is deficient in addressing the adaptability and efficiency of data recovery in NAND FLASH, especially in the face of complex or unexpected errors.
Disclosure of Invention
In view of this, the embodiments of the present application provide a method, an apparatus, and a flash memory device for determining an optimal read voltage parameter of a flash memory with high efficiency and an adaptive effect, which can improve the success rate of data recovery and reduce performance loss.
In a first aspect, an embodiment of the present application provides a method for determining an optimal read voltage parameter of a flash memory, including:
acquiring a new read retry voltage offset value corresponding to the predicted minimized bit-flipping number according to a linear relation model between the read retry voltage offset value and the bit-flipping number;
judging whether the data can be successfully read under the new reading retry voltage offset value;
if yes, adding the new reading retry voltage offset value to the head of the reading retry offset table to form a new reading retry offset table;
And updating the linear relation model through the self-adaptive learning model according to the new reading retry offset table.
In some embodiments, before the obtaining the new read retry voltage offset value corresponding to the predicted minimum bit-flipping number according to the linear relation model between the read retry voltage offset value and the bit-flipping number, the method further includes:
The construction of the linear relation model specifically comprises the following steps:
performing read retry operation on the memory page according to each read retry voltage offset value in the read retry offset table to obtain a group of bit-flipping number data sets;
Each element in the data set is in one-to-one correspondence with a read retry voltage offset value;
and constructing a linear relation model containing w independent variables according to the number w of the registers in the flash memory.
In some embodiments, the linear relationship model is:
；
Wherein y is the number of bit flips and the argument Retry voltage offset values for reads applied to different of the registers, theTo the point ofFor the coefficients of the linear relation model, theIs the amount of difference between the actually observed number of bit-flips and the number of bit-flips predicted by the linear relation model.
In some embodiments, the determining of the coefficients of the linear relationship model comprises:
Minimizing the amount of difference Square sum of (2);
Calculating a partial derivative of each coefficient, and enabling the partial derivative to be 0 to obtain a group of regular equations;
and obtaining the value of the coefficient according to the regular equation.
In some embodiments, the minimizing the amount of varianceThe sum of squares of (2) is given by:
；
Wherein, Is the firstThe number of bit flips observed after a read operation,Is the firstThe second reading operation corresponds toReading the retry voltage offset value;
The formula for partial derivative of each coefficient is:
；
The set of canonical equations is obtained:
；
Wherein, In order to design the matrix,Is the vector of the observed number of bit flips,Is a coefficient vector;
Wherein, ，，；
Obtaining the coefficients according to the regular equationThe vector value is given by the formula:。
In some embodiments, the obtaining a new read retry voltage offset value corresponding to the predicted minimum bit-flipping number according to the linear relation model between the read retry voltage offset value and the bit-flipping number includes:
Acquiring a new read retry voltage offset value corresponding to the predicted minimum bit-flipping number by adopting a gradient descent method according to a linear relation model between the read retry voltage offset value and the bit-flipping number;
the step of obtaining a new read retry voltage offset value corresponding to the predicted minimum bit flip number by using a gradient descent method includes:
Selecting a read retry voltage offset value with the minimum bit turnover number from the read retry offset table as an initial read retry voltage offset value for iteration of a gradient descent method;
for each iteration, calculating a gradient of the predicted bit flip number with respect to each read retry voltage offset value, and updating the read retry voltage offset value;
Applying the read retry voltage offset value obtained in each iteration to a read retry operation, and recording the corresponding bit turnover number;
And when the iteration termination condition is reached, terminating the iteration of the gradient descent method, outputting a read retry voltage offset value of the current iteration, and taking the current read retry voltage offset value as the new read retry voltage offset value.
In some embodiments, the terminating iteration condition comprises:
terminating the iteration if the variation of the read retry voltage offset value in the iteration process is smaller than the minimum adjustment granularity supported by hardware; or (b)
And stopping iteration when the maximum preset iteration times are reached.
In some embodiments, the updating the linear relationship model by an adaptive learning model according to a new read retry offset table comprises:
Updating the coefficient of the linear relation model through a self-adaptive learning model according to the new reading retry offset table to obtain an updated linear relation model, which comprises the following steps:
Applying the new read retry voltage offset value to the linear relation model to obtain an adaptive update rule of coefficients in the linear relation model;
the new reading retry voltage offset value is applied to the linear relation model, and the obtained formula is as follows:
；
Wherein, Retry the voltage offset value for the new read,Based on the current coefficientA predicted value of the calculated bit flip number;
Wherein the updating rule of the coefficient is that ；
Wherein,As a function of the loss,Is the loss function versus coefficientIs a partial derivative of (c).
In a second aspect, an embodiment of the present application provides a device for determining an optimal read voltage parameter of a flash memory, including:
the acquisition module is used for acquiring a new read retry voltage offset value corresponding to the predicted minimum bit turnover number according to a linear relation model between the read retry voltage offset value and the bit turnover number;
The judging module is used for judging whether the data can be successfully read under the new reading retry voltage offset value;
The adding module is used for adding the new reading retry voltage offset value to the head of the reading retry offset table if yes, so as to form a new reading retry offset table;
And the updating module is used for updating the linear relation model through the self-adaptive learning model according to the new reading retry offset table.
In a third aspect, an embodiment of the present application provides a flash memory device, where the flash memory device includes a processor and a memory, where the memory stores a computer program, and the processor is configured to execute the computer program to implement the above-mentioned method for determining an optimal read voltage parameter of a flash memory.
The embodiment of the application has the following beneficial effects: the application remarkably improves the accuracy and reliability of the flash memory in the data reading process by the way of real-time analysis and dynamic adjustment of the read retry voltage parameter, and the dynamic adjustment mechanism of the application enables the flash memory to be self-adaptive to various working conditions and aging states.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating a first flow chart of a method for determining optimal read voltage parameters of a flash memory according to an embodiment of the application;
FIG. 2 is a schematic diagram illustrating a second flow chart of a method for determining optimal read voltage parameters of a flash memory according to an embodiment of the present application;
Fig. 3 is a schematic structural diagram of a flash memory optimal read voltage parameter determining apparatus according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.
The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
The terms "comprises," "comprising," "including," or any other variation thereof, are intended to cover a specific feature, number, step, operation, element, component, or combination of the foregoing, which may be used in various embodiments of the present application, and are not intended to first exclude the presence of or increase the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the application.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The embodiments described below and features of the embodiments may be combined with each other without conflict.
The method for determining the optimal read voltage parameter of the flash memory is described below with reference to specific embodiments.
Fig. 1 is a schematic flow chart of a method for determining an optimal read voltage parameter of a flash memory according to an embodiment of the application. The method for determining the optimal read voltage parameter of the flash memory comprises the following steps:
step S100, obtaining a new read retry voltage offset value corresponding to the predicted minimum bit flip number according to a linear relation model between the read retry voltage offset value and the bit flip number.
The method of the application analyzes the relation between the read retry voltage offset value (READ RETRY voltage parameter) and the bit flip number stored in the SSD (solid state disk) main control in real time, and dynamically adjusts the voltage offset value to reduce the bit flip number (bit flip number).
After the method starts, when the firmware enters a read retry (READ RETRY) operation, firstly checking whether a linear relation model between the read retry voltage offset value constructed before and the bit-flipping number is stored in the solid state disk, and if so, executing step S100.
If the linear relation model between the read retry voltage offset value and the bit flip number is not stored in the solid state disk, the linear relation model is built first.
As shown in fig. 2, the step of constructing the linear relation model includes:
Said constructing said linear relationship model comprises:
step S110, performing read retry operation on the memory page according to each read retry voltage offset value in the read retry offset table to obtain a group of bit flip number data sets.
In this step, in the read retry operation, a plurality of read operations are performed on pages (memory pages) according to READ RETRY Offset Table (read retry Offset Table) to obtain a set of bit-flipping number data setsFor a length ofIs a read retry offset table, data setComprisesAnd the elements respectively represent the bit turnover numbers corresponding to each group of data in the application read retry offset table.
Simultaneously recording each set of read retry voltage offset values (offset values) corresponding to each read retry operation, wherein each set of read retry voltage offset values, i.e., a row of the read retry offset table, is essentially a vector, forming each set of read retry voltage offset values corresponding to each read retry operation into a data corresponding setComprising elements ofEach element of which is a vector.
Step S120, collecting the dataEach bit flip value and set of (a)The read retry voltage offset values of each group in (a) are in one-to-one correspondence.
In this step, data setsIs obtained by performing read retry operation under each set of read retry voltage offset values, i.e. setEach set of read retry voltage offset values in (1) corresponds to a data setIs an element of the group.
Step S130, constructing a linear relation model containing w independent variables according to the number w of the registers in the flash memory.
In this step, each flash memory has different numbers of read voltages to be adjusted according to the number of bits that it can store, and these are controlled by the corresponding number of read voltage offset registers, and the NAND read voltages can be adjusted by writing each set of read retry voltage offset values into the corresponding registers, for example, 1 register is corresponding to SLC (single-level cell flash), and 7 registers are corresponding to TLC (three-level cell flash). In the multiple linear relation model, the voltage offset of each register (namely the corresponding read retry voltage offset value) is taken as an independent variable to construct a multi-element linear relation model withLinear relation model of individual arguments, the linear relation model can be represented by formula 1, wherein formula 1 is:
。
Wherein y is the number of bit flips and the argument Retry voltage offset values for reads applied to different of the registers, theTo the point ofFor the linear relation model coefficient, theCapturing all other factors which possibly influence the bit flip number except the voltage offset, namely, the difference between the actually observed bit flip number and the bit flip number predicted by the linear relation model; wherein,The number of read voltage offset registers representing the flash memory cell, namely:
。
That is, if the flash memory is in SLC mode, then Equal to 1; if the flash memory is in MLC mode, thenEqual to 3; if the flash memory is in TLC mode, thenEqual to 7, etc., the value of w can also be different from the values described above for other modes of flash memory, and is not particularly limited herein.
It should be noted that, the linear relation model in the present application is a multiple linear regression model.
The purpose of the present application is to obtain a set of coefficientsThe difference between the number of bit-turns predicted by the linear relation model and the number of actually observed bit-turns, which can be obtained from the firmware after each read operation, is minimized. In the present application, coefficients in the linear relation model are determined by the least square method.
Coefficients in the linear relationship modelThe determination of (2) comprises:
coefficients in a linear relationship model are obtained by minimizing the amount of difference Is obtained by summing the squares of the pairs.
Wherein said minimizing said amount of varianceThe formula of the sum of squares of (2) is formula 2; wherein, formula 2 is:
。
Wherein, Each time a read operation is indexed,Represent the firstIn the secondary read operationVoltage offset values written on individual registers, dependent variablesRepresenting the corresponding number of bit flips, i.e. in equation 2Is the firstThe number of bit flips observed after a read operation,Is the firstThe second reading operation corresponds toThe read retry voltage offset value.
Further, if the amount of difference is to be minimizedThe sum of squares of (2) requires that for each of the coefficients in equation 2Solving a partial derivative, wherein the other partial derivative is 0, as shown in a formula 3; wherein, formula 3 is:
。
Further, according to the formula 3, a set of regular equations can be obtained, as shown in formula 4; wherein, formula 4 is:
。
wherein in equation 4 To design a matrix, each row of which corresponds to a voltage offset value for one read operation,Is the vector of the observed number of bit flips,Is a coefficient vector;
Wherein, ，，。
Further, the coefficient vector is obtained according to the regular equation formula 4As shown in equation 5; wherein, formula 5 is:
。
coefficients according to equation 5 So that the number of bit flips predicted by the linear relation model is closest to the actual observed value.
In obtaining coefficientsAfter the value of (2), the application adopts a gradient descent method to find the read retry voltage offset value capable of minimizing the predicted bit flip number, and the gradient descent method is an iterative optimization algorithm for solving the local minimum value of the derivative function. The application iteratively updates the voltage offset value by a gradient descent method to reduce the number of predicted bit-flips.
Specifically, the step of obtaining the new read retry voltage offset value corresponding to the flash memory minimized bit flip number by using the gradient descent method includes:
And firstly, selecting a read retry voltage offset value which minimizes the bit flip number from the read retry offset table as an initial read retry voltage offset value of the iteration of the gradient descent method. Wherein the initial read retry voltage offset value is 。
Then, for each iteration, the read retry voltage offset value is updated by calculating a gradient of the predicted bit flip number with respect to each read retry voltage offset value according to equation 6.
Wherein, formula 6 is:
。
In the formula 6 of the present invention, ; Gradient ofIndicating the predicted bit flip number with respect to the firstThe rate of change of the individual read retry voltage offset values,Is the learning rate, which determines the size of the update step, t is the number of iterations.
Further, the read retry voltage offset value obtained for each iteration is applied in a read retry operation, and the corresponding number of bit flips is recorded.
And when each iteration is performed, taking the read retry voltage offset value obtained last time as the read retry voltage offset value of the iteration.
And finally, when the iteration termination condition is reached, terminating the iteration of the gradient descent method, outputting a read retry voltage offset value of the current iteration, and taking the current read retry voltage offset value as the new read retry voltage offset value. I.e. when any iteration termination condition is satisfied, terminating the iteration and outputting the last updated read retry voltage offset value。
Wherein the terminating iteration condition includes:
(1) If the read retry voltage offset value in the iterative process is less than the minimum adjustment granularity supported by hardware Indicating that the read retry voltage offset value has stabilized, the iteration may be terminated.
I.e.At that point, the iteration may be terminated.
(2) To avoid endless iteration, a maximum number of iterations is presetIf this number of times is reached, the iteration is stopped, i.eThe iteration may be stopped.
Step S200, determining whether the data can be successfully read under the new reading retry voltage offset value.
If the number can be successfully read, step S300 is executed, in which the new reading retry voltage offset value is added to the header of the reading retry offset table to form a new reading retry offset table. If the reading is not successful, the round of algorithm is ended, and error information is output. In this step, the new read retry voltage offset value is added to the header of the read retry offset table, which is beneficial to later debugging and migration.
And step 400, updating the linear relation model through the self-adaptive learning model according to the new reading retry offset table.
The self-adaptive learning model in the step is an online learning method.
In order to ensure that the linear relation model is always optimized, the coefficient of the linear relation model is dynamically updated by adopting an online learning method so as to form a new linear relation model, the online learning method allows the linear relation model to reflect a new data mode in real time without retraining the whole model, and the step S400 specifically comprises the following steps:
substituting the new read retry voltage offset value into formula 1 to obtain formula 7;
wherein, formula 7 is:
。
In equation 7 Retry the voltage offset value for the new read,Based on the current coefficientAnd the predicted value of the calculated bit flip number.
Obtaining coefficients according to said equation 7Is updated on line; wherein the update rule is that. Wherein,Is the learning rate.
Wherein,As a loss function, square loss is used here，Is the loss function versus coefficientIs a partial derivative of (c). From the above, the coefficientThe update rule of (c) may be:
。
In this embodiment, after a new linear relationship model is formed in step S400, the new linear relationship model and the new read retry offset table are saved.
According to the above steps, coefficients are obtainedAnd a new read retry voltage offset value according to the coefficientAnd the new reading retry voltage offset value can obtain a new linear relation model and the new reading retry offset table, and in the embodiment, the new linear relation model and the new reading retry offset table are stored for the next use.
According to a linear relation model between a read retry voltage offset value and a bit flip number, acquiring a new read retry voltage offset value corresponding to the minimum predicted bit flip number of a flash memory; if the data can be successfully read under the new reading retry voltage offset value; adding the new reading retry voltage offset value to the head of the reading retry offset table to form a new reading retry offset table; and updating the linear relation model through a self-adaptive learning model according to the new reading retry offset table to form a new linear relation model. The application remarkably improves the accuracy and reliability of the flash memory in the data reading process by the way of real-time analysis and dynamic adjustment of the read retry voltage parameter, and the dynamic adjustment mechanism of the application enables the flash memory to be self-adaptive to various working conditions and aging states.
Fig. 3 is a schematic structural diagram of a flash memory optimal read voltage parameter determining apparatus according to an embodiment of the application. The flash memory optimal read voltage parameter determining apparatus includes:
The obtaining module 10 is configured to obtain a new read retry voltage offset value corresponding to the predicted minimum bit-flipping number according to a linear relation model between the read retry voltage offset value and the bit-flipping number.
The judging module 20 is configured to judge whether the data can be successfully read under the new reading retry voltage offset value.
And the adding module 30 is configured to add the new reading retry voltage offset value to the header of the reading retry offset table to form a new reading retry offset table if the data can be successfully read under the new reading retry voltage offset value.
And the updating module 40 is used for updating the linear relation model through the adaptive learning model according to the new reading retry offset table.
It can be understood that the apparatus of this embodiment corresponds to the method for determining the optimal read voltage parameter of the flash memory of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so the description thereof will not be repeated here.
The application also provides a flash memory device, which exemplarily comprises a processor and a memory, wherein the memory stores a computer program, and the processor enables the terminal device to execute the functions of each module in the above-mentioned method for determining the optimal read voltage parameter of the flash memory or the above-mentioned device for determining the optimal read voltage parameter of the flash memory by running the computer program.
The processor may be an integrated circuit chip with signal processing capabilities. The processor may be a general purpose processor including at least one of a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU) and a network processor (Network Processor, NP), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application.
The Memory may be, but is not limited to, random access Memory (Random Access Memory, RAM), read Only Memory (ROM), programmable Read Only Memory (Programmable Read-Only Memory, PROM), erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc. The memory is used for storing a computer program, and the processor can correspondingly execute the computer program after receiving the execution instruction.
The present application also provides a readable storage medium storing the computer program for use in the above terminal device.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flow diagrams and block diagrams in the figures, which illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules or units in various embodiments of the application may be integrated together to form a single part, or the modules may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.
Claims (8)
1. The method for determining the optimal read voltage parameter of the flash memory is characterized by comprising the following steps of:
constructing a linear relation model between the read retry voltage offset value and the bit flip number;
Acquiring a new read retry voltage offset value corresponding to the predicted minimum bit turnover number according to the linear relation model;
judging whether the data can be successfully read under the new reading retry voltage offset value;
if yes, adding the new reading retry voltage offset value to the head of the reading retry offset table to form a new reading retry offset table;
updating the linear relation model through a self-adaptive learning model according to a new reading retry offset table;
wherein the linear relationship model is:
；
Wherein y is the number of bit flips, the argument For read retry voltage offset values applied on different registers,To the point ofAs coefficients of the linear relation model,For the amount of difference between the actually observed number of bit-flips and the number of bit-flips predicted by the linear relation model, w is the number of registers in the flash memory;
wherein, according to the linear relation model, obtaining a new read retry voltage offset value corresponding to the predicted minimum bit flip number comprises:
Acquiring a new read retry voltage offset value corresponding to the predicted minimum bit-flipping number by adopting a gradient descent method according to a linear relation model between the read retry voltage offset value and the bit-flipping number;
wherein updating the linear relationship model according to the new read retry offset table by the adaptive learning model comprises:
Applying the new read retry voltage offset value to the linear relation model to obtain an adaptive update rule of coefficients in the linear relation model;
the new reading retry voltage offset value is applied to the linear relation model, and the obtained formula is as follows:
；
Wherein, Retry the voltage offset value for the new read,Based on the current coefficientA predicted value of the calculated bit flip number;
wherein, the updating rule of the coefficient is as follows: ；
Wherein, As a function of the loss,Is the loss function versus coefficientIs used for the partial derivative of (a),In order for the rate of learning to be high,The number of toggles for the new bit.
2. The method of claim 1, wherein constructing a linear relationship model between read retry voltage offset value and number of bit flip comprises:
performing read retry operation on the memory page according to each read retry voltage offset value in the read retry offset table to obtain a group of bit-flipping number data sets;
Each element in the data set is in one-to-one correspondence with a read retry voltage offset value;
and constructing a linear relation model containing w independent variables according to the number w of the registers in the flash memory.
3. The method of claim 1, wherein determining the coefficients of the linear relationship model comprises:
Minimizing the amount of difference Square sum of (2);
Calculating a partial derivative of each coefficient, and enabling the partial derivative to be 0 to obtain a group of regular equations;
and obtaining the value of the coefficient according to the regular equation.
4. The method for determining optimal read voltage parameters of a flash memory according to claim 3, wherein,
Said minimizing said amount of differenceThe sum of squares of (2) is given by:
；
Wherein, Is the firstThe number of bit-flips observed after a read operation, n being the maximum number of bit-flips read operations,Is the firstThe second reading operation corresponds toReading the retry voltage offset value;
The formula for partial derivative of each coefficient is:
；
The set of canonical equations is obtained:
；
Wherein, In order to design the matrix,Is the vector of the observed number of bit flips,Is a coefficient vector;
Wherein, ，，；
Obtaining the coefficients according to the regular equationThe vector value is given by the formula:。
5. The method for determining the optimal read voltage parameter of the flash memory according to claim 1, wherein the obtaining the new read retry voltage offset value corresponding to the predicted minimum bit flip number by the gradient descent method comprises:
Selecting a read retry voltage offset value with the minimum bit turnover number from the read retry offset table as an initial read retry voltage offset value for iteration of a gradient descent method;
for each iteration, calculating a gradient of the predicted bit flip number with respect to each read retry voltage offset value, and updating the read retry voltage offset value;
Applying the read retry voltage offset value obtained in each iteration to a read retry operation, and recording the corresponding bit turnover number;
And when the iteration termination condition is reached, terminating the iteration of the gradient descent method, outputting a read retry voltage offset value of the current iteration, and taking the current read retry voltage offset value as the new read retry voltage offset value.
6. The method for determining the optimal read voltage parameter of the flash memory according to claim 5, wherein the terminating iteration condition comprises:
terminating the iteration if the variation of the read retry voltage offset value in the iteration process is smaller than the minimum adjustment granularity supported by hardware; or (b)
And stopping iteration when the maximum preset iteration times are reached.
7. An apparatus for determining an optimal read voltage parameter of a flash memory, comprising:
The construction module is used for constructing a linear relation model between the read retry voltage offset value and the bit turnover number;
The acquisition module is used for acquiring a new read retry voltage offset value corresponding to the predicted minimum bit turnover number according to the linear relation model;
The judging module is used for judging whether the data can be successfully read under the new reading retry voltage offset value;
The adding module is used for adding the new reading retry voltage offset value to the head of the reading retry offset table if yes, so as to form a new reading retry offset table;
the updating module is used for updating the linear relation model through the self-adaptive learning model according to the new reading retry offset table;
wherein the linear relationship model is:
；
Wherein y is the number of bit flips, the argument For read retry voltage offset values applied on different registers,To the point ofAs coefficients of the linear relation model,A difference amount between the actually observed bit flip number and the bit flip number predicted by the linear relation model;
wherein, according to the linear relation model, obtaining a new read retry voltage offset value corresponding to the predicted minimum bit flip number comprises:
Acquiring a new read retry voltage offset value corresponding to the predicted minimum bit-flipping number by adopting a gradient descent method according to a linear relation model between the read retry voltage offset value and the bit-flipping number;
wherein updating the linear relationship model according to the new read retry offset table by the adaptive learning model comprises:
Applying the new read retry voltage offset value to the linear relation model to obtain an adaptive update rule of coefficients in the linear relation model;
the new reading retry voltage offset value is applied to the linear relation model, and the obtained formula is as follows:
；
Wherein, Retry the voltage offset value for the new read,Based on the current coefficientThe predicted value of the calculated bit turning quantity, w is the quantity of registers in the flash memory;
wherein, the updating rule of the coefficient is as follows: ；
Wherein, As a function of the loss,Is the loss function versus coefficientIs used for the partial derivative of (a),In order for the rate of learning to be high,The number of toggles for the new bit.
8. A flash memory device, characterized in that it comprises a processor and a memory, the memory storing a computer program, the processor being adapted to execute the computer program to implement the flash memory optimal read voltage parameter determination method according to any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410756574.5A CN118314943B (en) | 2024-06-13 | 2024-06-13 | Method and device for determining optimal read voltage parameters of flash memory and flash memory equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410756574.5A CN118314943B (en) | 2024-06-13 | 2024-06-13 | Method and device for determining optimal read voltage parameters of flash memory and flash memory equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118314943A CN118314943A (en) | 2024-07-09 |
| CN118314943B true CN118314943B (en) | 2024-08-30 |
Family
ID=91733827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410756574.5A Active CN118314943B (en) | 2024-06-13 | 2024-06-13 | Method and device for determining optimal read voltage parameters of flash memory and flash memory equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118314943B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118502677A (en) * | 2024-07-17 | 2024-08-16 | 成都佰维存储科技有限公司 | Memory read re-table optimization method and device, readable storage medium and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105324819A (en) * | 2013-05-31 | 2016-02-10 | 西部数据技术公司 | Reading voltage calculation in solid-state storage devices |
| CN117076189A (en) * | 2023-07-17 | 2023-11-17 | 湖北长江万润半导体技术有限公司 | Flash memory voltage fast reading retry error correction method and device based on self-adaptive learning |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114333951A (en) * | 2021-12-30 | 2022-04-12 | 合肥大唐存储科技有限公司 | Method and device for re-reading flash memory |
| CN116301629A (en) * | 2023-03-20 | 2023-06-23 | 江苏芯盛智能科技有限公司 | Optimal rereading gear searching method, system, equipment and storage medium based on voltage threshold data |
| CN116778986A (en) * | 2023-06-21 | 2023-09-19 | 哈尔滨工业大学 | Method and device for constructing read reference voltage calibration model, and calibration method and device |
-
2024
- 2024-06-13 CN CN202410756574.5A patent/CN118314943B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105324819A (en) * | 2013-05-31 | 2016-02-10 | 西部数据技术公司 | Reading voltage calculation in solid-state storage devices |
| CN117076189A (en) * | 2023-07-17 | 2023-11-17 | 湖北长江万润半导体技术有限公司 | Flash memory voltage fast reading retry error correction method and device based on self-adaptive learning |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118314943A (en) | 2024-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN118314943B (en) | Method and device for determining optimal read voltage parameters of flash memory and flash memory equipment | |
| US8386860B2 (en) | Methods of calculating compensation voltage and adjusting threshold voltage and memory apparatus and controller | |
| US9922706B2 (en) | Solid state storage device using state prediction method | |
| KR101891378B1 (en) | System and method of adjusting a programming step size for a block of a memory | |
| US8576625B1 (en) | Decoder parameter estimation using multiple memory reads | |
| US10643715B2 (en) | Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read | |
| KR101891429B1 (en) | Threshold voltage analysis | |
| US8578245B2 (en) | Data reading method, memory storage apparatus, and controller thereof | |
| US8266368B2 (en) | Memory controller, memory system, and control method for memory system | |
| US8391076B2 (en) | Nonvolatile memory device using interleaving technology and programming method thereof | |
| KR20130084901A (en) | Flash memory device and reading method of flash memory device | |
| US10983854B2 (en) | Memory controller and initialization method for use in data storage device | |
| CN115295057B (en) | Method for rapidly acquiring NAND optimal read data | |
| JP6001093B2 (en) | Analog memory cell programming and erasing methods | |
| CN112732181A (en) | Data migration method of SSD and related device | |
| CN115470052B (en) | Bad block detection method and device for memory chip and memory medium | |
| US10706897B2 (en) | Read threshold voltage selection | |
| TWI497505B (en) | Method of programming a multi-bit per cell non-volatile memory | |
| US8924819B2 (en) | Memory device and operation method thereof | |
| TWI442406B (en) | Method for enhancing verification efficiency regarding error handling mechanism of a controller of a flash memory, and associated memory device and controller thereof | |
| CN113419688B (en) | Error rate analysis method, system and device of MLC chip | |
| CN113241112B (en) | Bad block screening method and device, computer readable storage medium and electronic equipment | |
| US11176988B2 (en) | Control method for memory and non-transitory computer-readable media | |
| CN113805815A (en) | Data recovery method, device and system for flash memory | |
| CN110322907A (en) | The method of adjustment, system and 3D flash memory of threshold voltage in 3D flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |