CN118299271A

CN118299271A - Method for manufacturing semiconductor device and semiconductor device

Info

Publication number: CN118299271A
Application number: CN202410726728.6A
Authority: CN
Inventors: 丁文凤; 吴卓杰; 唐凌; 王岩; 覃庆媛
Original assignee: Hangzhou Jihai Semiconductor Co ltd
Current assignee: Hangzhou Jihai Semiconductor Co ltd
Filing date: 2024-06-06
Publication date: 2024-07-05

Abstract

The invention provides a preparation method of a semiconductor device and the semiconductor device, and particularly relates to the technical field of semiconductors. The preparation method of the semiconductor device comprises the following steps: providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate; forming a first lightly doped drain region and a second lightly doped drain region in the semiconductor substrate at two sides of the grid structure respectively; implanting fluorine ions into the junction area between the semiconductor substrate below the gate structure and the first lightly doped drain region in an inclined implantation mode, and performing annealing treatment; forming side walls on two sides of the grid structure, forming a drain region in the semiconductor substrate on one side of the first lightly doped drain region, and forming a source region in the semiconductor substrate on one side of the second lightly doped drain region. The preparation method can effectively improve the hot carrier injection effect of the semiconductor device.

Description

Method for manufacturing semiconductor device and semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device and the semiconductor device.

Background

As the integration of semiconductor devices continues to increase, the feature size of the devices gradually decreases. While the reduction in the size of semiconductor devices brings about performance improvement and power consumption reduction, the resulting reliability problems become increasingly severe. The lateral electric field intensity of the channel of the semiconductor device increases with the continuous reduction of the size of the device, and particularly, the electric field near the drain electrode is strongest. The carriers are accelerated under the action of the electric field to become hot carriers, and collide with the crystal lattice to generate electron-hole pairs, and the generated electrons are likely to be injected into the gate oxide layer to generate oxide layer charge defects and/or interface defects, which is commonly referred to as hot carrier injection (Hot Carrier Injection, abbreviated as HCI) effect. The HCI effect can cause drift or degradation in the parameters of the device, thereby affecting the reliability of the device, ultimately leading to circuit failure.

Accordingly, there is a need to provide a method of manufacturing a semiconductor device and a semiconductor device to improve the hot carrier injection effect of the device.

Disclosure of Invention

In view of the above drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, so as to improve the hot carrier injection effect of the semiconductor device.

To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device, the method comprising at least the steps of:

providing a semiconductor substrate;

Forming a gate structure on the semiconductor substrate;

Forming a first lightly doped drain region in the semiconductor substrate at one side of the gate structure, and forming a second lightly doped drain region in the semiconductor substrate at the other side of the gate structure;

Implanting fluorine ions into the junction area between the semiconductor substrate and the first lightly doped drain region under the gate structure in an inclined implantation mode, and performing annealing treatment;

forming side walls on two sides of the grid structure;

and forming a drain region in the semiconductor substrate at one side of the first lightly doped drain region, and forming a source region in the semiconductor substrate at one side of the second lightly doped drain region.

In an example of the present invention, an angle between the implantation direction of the fluorine ions and the surface of the semiconductor substrate is 5 ° to 45 °.

In one example of the present invention, the ion implantation concentration of the fluoride ion is 1E13 ions/cm ² to 1E15 ions/cm ².

In one example of the present invention, the ion implantation energy of the fluoride ion is 1KeV to 15KeV.

In one example of the present invention, the annealing treatment is performed at a temperature of 500 ℃ to 900 ℃.

In an example of the present invention, before forming the gate structure on the semiconductor substrate, the preparation method further includes:

Forming an isolation structure and an active region in the semiconductor substrate;

And forming a P-type well region in the active region.

In an example of the present invention, forming a drain region in the semiconductor substrate on the side of the first lightly doped drain region and forming a source region in the semiconductor substrate on the side of the second lightly doped drain region includes:

Injecting N-type doping ions into the semiconductor substrate at one side of the first lightly doped drain region and the semiconductor substrate at one side of the second lightly doped drain region respectively;

and annealing the semiconductor substrate to form a drain region and a source region.

In one example of the present invention, forming a gate structure on the semiconductor substrate includes:

forming a gate oxide layer on the semiconductor substrate;

forming a gate electrode on the gate oxide layer;

And forming an oxidation repair layer on the top wall and the side wall of the grid electrode and the side wall of the grid oxide layer.

The present invention also provides a semiconductor device including: the semiconductor device comprises a semiconductor substrate, a grid structure, a lightly doped drain region, a fluorine ion implantation region, a side wall, a source region and a drain region, wherein the grid structure is arranged on the semiconductor substrate; the lightly doped drain region comprises a first lightly doped drain region and a second lightly doped drain region; the first lightly doped drain region is arranged in the semiconductor substrate at one side of the gate structure, and the second lightly doped drain region is arranged in the semiconductor substrate at the other side of the gate structure; the fluorine ion implantation region is arranged in the junction region of the semiconductor substrate below the grid structure and the first lightly doped drain region; the side walls are arranged on two sides of the grid structure; the drain region is arranged in the semiconductor substrate at one side of the first lightly doped drain region; the source region is arranged in the semiconductor substrate at one side of the second lightly doped drain region.

In an example of the present invention, the gate structure includes a gate oxide layer, a gate electrode and an oxide repair layer, the gate oxide layer is disposed on the semiconductor substrate, the gate electrode is disposed on the gate oxide layer, and the oxide repair layer is disposed on a top wall and a side wall of the gate electrode and a side wall of the gate oxide layer.

After the lightly doped drain region is formed, fluorine ions are injected into the junction region between the semiconductor substrate below the grid structure and the first lightly doped drain region in an inclined injection mode, and a silicon-fluorine bond with higher bond energy is formed at the position corresponding to the strongest electric field in the semiconductor substrate through annealing treatment, so that the hot carrier injection effect can be effectively improved, and the reliability of the semiconductor device is further improved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing a structure of a semiconductor substrate according to an embodiment of the method for fabricating a semiconductor device of the present invention;

FIG. 3 is a flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating fluorine ion implantation in an embodiment of a method for fabricating a semiconductor device according to the present invention;

fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention.

Description of element reference numerals

100. A semiconductor substrate; 101. an isolation structure; 102. a P-type well region; 103. a first lightly doped drain region; 104. a second lightly doped drain region; 105. a fluorine ion implantation region; 200. a gate structure; 210. a gate oxide layer; 220. a gate; 230. oxidizing the repair layer; 300. a side wall; 400. a source region; 410. and a drain region.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.

In the present application, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship based on that shown in the drawings, for convenience of description and simplicity of description, only, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.

The HCI effect refers to accelerating the movement of carriers under the action of a high electric field, so that the carriers are changed into hot carriers with high energy, and when the energy of the hot carriers exceeds the barrier height of the interface between a channel and a gate oxide layer, the hot carriers can be directly injected into the gate oxide layer or enter the gate oxide layer through a tunneling effect, so that oxide layer charge defects and/or interface defects are generated, and drift of device parameters is caused. Since the mean free path of electrons and holes is different, the probability of injection of electrons is 3 orders of magnitude higher than that of holes, and thus an NMOS (N-CHANNEL METAL-Oxide-Semiconductor) transistor is more likely to cause HCI than a PMOS (P-CHANNEL METAL-Oxide-Semiconductor).

Currently, in order to suppress HCI effect, a lightly doped drain region (Lightly Doped Drain, LDD) is usually provided between a channel and source and drain electrodes, and the concentration gradient at the junction between the channel and drain and source electrodes is reduced by the LDD structure, so that the electric field strength of the source and drain electrodes is reduced to some extent, thereby suppressing HCI effect. However, as the device size decreases, the junction depth becomes shallower, and the existing LDD structure has not been able to effectively reduce the high electric field in the drain region.

Based on the above, the application provides a preparation method of a semiconductor device and the semiconductor device, so as to improve HCI effect of the semiconductor device. In order to facilitate understanding of the technical scheme of the present application, a method for manufacturing a semiconductor device and a structure of the semiconductor device provided by the present application will be specifically described with reference to the accompanying drawings and the detailed description.

Referring to fig. 1 to 7, the present invention provides a method for manufacturing a semiconductor device, which at least includes the following steps:

s1, providing a semiconductor substrate 100;

S2, forming a gate structure 200 on the semiconductor substrate 100;

S3, forming a first lightly doped drain region 103 in the semiconductor substrate 100 at one side of the gate structure 200, and forming a second lightly doped drain region 104 in the semiconductor substrate 100 at the other side of the gate structure 200;

s4, fluorine ions are injected into the junction area between the semiconductor substrate 100 and the first lightly doped drain region 103 under the gate structure 200 in an inclined injection mode, and annealing treatment is carried out;

s5, forming side walls 300 on two sides of the grid structure 200;

S6, forming a drain region 410 in the semiconductor substrate 100 at the side of the first lightly doped drain region 103, and forming a source region 400 in the semiconductor substrate 100 at the side of the second lightly doped drain region 104.

Referring to fig. 1 and 2, the semiconductor substrate 100 provided in step S1 may be a silicon substrate, a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), or the like. In an embodiment of the present invention, the semiconductor substrate 100 is a silicon substrate. Typically, one semiconductor substrate 100 may be used to form a plurality of semiconductor devices, and thus, isolation structures 101 are also formed within the semiconductor substrate 100 to separate the semiconductor substrate 100 into a plurality of active regions, each of which may be used to form a semiconductor device. The isolation structures 101 may be formed in a manner conventional in the art.

In one embodiment, the isolation structure 101 is a shallow trench isolation structure (Shallow Trench Isolation, STI), i.e., the semiconductor substrate 100 is etched to form a shallow trench, and the etched shallow trench is filled with an insulating material, so as to form a shallow trench isolation structure to electrically isolate adjacent active regions. The forming process of the shallow trench isolation structure specifically comprises the following steps:

A pad oxide layer is formed on the semiconductor substrate 100. The pad oxide layer is, for example, a dense silicon oxide material, and can be prepared by, for example, a thermal oxidation method (Thermal Oxidation Method) or a chemical vapor deposition (Chemical Vapor Deposition, CVD) method.

A pad nitride layer is formed on the pad oxide layer. The pad nitride layer is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and may be formed by chemical vapor deposition or the like.

A patterned photoresist layer is formed over the pad nitride layer, examples of which are as follows: and spin-coating a photoresist layer on the pad nitride layer, and then exposing and developing the photoresist layer to form a plurality of windows, so that the pad nitride layer is exposed at the positions corresponding to the windows. The photoresist in this embodiment may be either a positive photoresist or a negative photoresist. A plurality of windows on the patterned photoresist layer are used to define the locations of the isolation structures 101.

Etching is performed in the direction of the semiconductor substrate 100 by using the patterned photoresist layer as a mask, so as to form a shallow trench inside the semiconductor substrate 100. The etching may employ an etching process conventional in the art, for example, dry etching, and the etching gas includes, for example, one or a mixture of chlorine (Cl ₂), trifluoromethane (CHF ₃), difluoromethane (CH ₂F₂), nitrogen trifluoride (NF ₃), sulfur hexafluoride (SF ₆), hydrogen bromide (HBr), nitrogen (N ₂), or the like. The shallow grooves formed by etching are grooves with wide upper part and narrow lower part, and the structure is beneficial to more uniformly distributing stress caused by thermal circulation and mechanical stress in the manufacturing process, reducing the problems of cracks and breakage caused by stress concentration and improving the reliability of devices.

And filling insulating materials into the shallow trenches so as to form the shallow trench isolation structure. Specifically, a liner oxide layer is formed in the shallow trench by a thermal oxidation method to repair etching damage in the process of forming the shallow trench, so that the leakage condition of the semiconductor device is reduced. Then, the shallow trench is filled with oxide, for example, by chemical vapor deposition (Chemical Vapor Deposition, CVD), and the oxide is an insulating material such as silicon oxide, to form an isolation structure. After the oxide deposition is completed, the oxide and pad nitride layer are planarized by a Chemical Mechanical Polishing (CMP) process, and then the pad nitride layer and the pad oxide layer are removed to form the isolation structure 101. In the above process, the pad oxide layer may protect the semiconductor substrate 100 and provide a flat surface for the subsequent steps; the pad nitride layer acts as a hard mask material that helps to protect the active region during STI oxide deposition and acts as a barrier material during Chemical Mechanical Polishing (CMP). However, it will be appreciated by those skilled in the art that the isolation structure 101 of the present invention may be formed by other methods known in the art, and is not limited to the above-mentioned manufacturing process.

Since the NMOS transistor is more likely to cause HCI effect, the present application takes the semiconductor device to be formed as an NMOS transistor as an example, and details the process of manufacturing the same.

Since the semiconductor device to be formed is an NMOS transistor, after the isolation structure 101 and the active region are formed, forming a P-type well region 102 in the active region is also included. The P-type ions, such as boron ions, gallium ions, indium ions and other trivalent ions, are implanted into the active region by adopting an ion implantation process. In other embodiments, the step of forming the P-type well region 102 may also be performed before forming the isolation structure 101. After the well implant is completed, a thermal treatment, such as a rapid thermal annealing process (RAPID THERMAL ANNEAL, RTA), is performed to activate the implanted P-type dopant ions and repair lattice damage during the ion implantation.

In other embodiments, if the semiconductor substrate 100 is a P-type doped substrate, the process step of forming the P-type well region 102 may be omitted.

Referring to fig. 1,3 and 4, step S2 is performed to form a gate structure 200 on the semiconductor substrate 100. The specific process is as follows:

S21, a gate oxide layer 210 is formed on the semiconductor substrate 100. The gate oxide layer 210 is formed on the surface of the P-well region 102, and the gate oxide layer 210 is, for example, silicon dioxide, and the forming method of the gate oxide layer 210 includes, but is not limited to, wet oxidation, dry oxidation, and In-situ vapor generation (In-Situ Steam Generation, ISSG). The wet oxidation, i.e. introducing water vapor into the reaction chamber at high temperature to perform oxidation reaction with the surface of the semiconductor substrate 100 to form a silicon oxide layer, and the growth speed of the wet oxidation is relatively high. Dry oxidation, i.e. introducing dry oxygen into the reaction chamber at high temperature to perform oxidation reaction with the surface of the semiconductor substrate 100 to form a silicon oxide layer, wherein the dry oxidation can form an oxide film with high uniformity and density. ISSG is to introduce hydrogen and oxygen into the reaction cavity according to a certain proportion at high temperature, and the hydrogen and the oxygen react chemically at high temperature to generate a large amount of gas-phase active free radicals, wherein the main component is oxygen atom free radicals. The silicon oxide layer is obtained by reacting with silicon on the surface of the semiconductor substrate 100 due to the strong oxidation of the oxygen radical. The gate oxide layer 210 obtained by using the ISSG process has fewer defects in the body and a smaller interface state density.

S22, a gate 220 is formed on the gate oxide layer 210. In one embodiment, the gate 220 is a polysilicon gate, which is prepared as follows: a polysilicon layer is deposited on the surface of the gate oxide layer 210 by a deposition method including, but not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), magnetron sputtering, physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or the like. The thickness of the polysilicon layer is required to meet the thickness requirement of the gate and the processing of the subsequent steps. After the polysilicon layer is deposited, a photoresist layer is spin-coated on the polysilicon layer, and a non-grid region is exposed through exposure and development steps, and a grid 220 region is covered by the photoresist; the exposed non-gate regions are etched to form the gate 220, and at the same time, the uncovered gate oxide layer 210 under the polysilicon layer is also etched away. The etching method is, for example, dry etching, wet etching, or a process combining dry etching and wet etching. And after etching, removing the photoresist layer by utilizing an ashing process. In other embodiments, the gate 220 may also be a metal gate, such as a metal material with a small thermal expansion coefficient, such as nickel, molybdenum, or tungsten.

S23, an oxidation repair layer 230 is formed on the top wall and the side wall of the gate 220 and the side wall of the gate oxide layer 210. The gate 220 etching process may cause the lattice structure of the gate 220 and the sidewall of the gate oxide layer 210 to be damaged, thereby affecting the performance of the semiconductor device. The formation of the oxide repair layer 230 may repair damage to the gate electrode 220 and the gate oxide layer 210 during etching. The Oxidation repair layer 230 is formed, for example, by using a Rapid Thermal Oxidation (RTO) method, in which the semiconductor substrate 100 formed with the gate oxide layer 210 and the gate electrode 220 is fed into a reaction chamber of an RTO device, and rapidly heated, so that surfaces of the gate electrode 220 and the gate oxide layer 210 exposed to the reaction chamber react with oxygen at a high temperature to form the Oxidation repair layer 230. This process enables the oxidation repair layer 230 to be generated in a shorter time, thus having no effect on other layers or structures on the semiconductor substrate 100. In other embodiments, the oxidation repair layer 230 may also be formed using dry oxidation, wet oxidation, ISSG, and the like.

Referring to fig. 1 and 5, step S3 is performed to form lightly doped drain regions (Lightly Doped Drain, LDD) in the semiconductor substrate 100 at both sides of the gate structure 200. Namely: photoresist layers are formed on the surfaces of the semiconductor substrate 100 and the gate structure 200, the photoresist layers are exposed and developed to form patterned photoresist mask layers, openings of the patterned photoresist mask layers correspond to lightly doped drain regions, and the exposed semiconductor substrate 100 regions are subjected to low-energy and low-doping-concentration N-type ion implantation under the protection of the patterned photoresist mask layers to form N-type LDD structures. The N-type ion is, for example, a pentavalent ion such as a phosphorus ion or an arsenic ion. The introduction of the LDD structure can reduce the high electric field near the source region and the drain region, thereby reducing the hot carrier injection effect and improving the reliability of the device. For convenience of the following description, lightly doped drain regions on both sides of the gate structure 200 are respectively referred to as a first lightly doped drain region 103 and a second lightly doped drain region 104.

Referring to fig. 1 and 6, step S4 is performed to implant fluorine ions into the semiconductor substrate 100 under the gate structure 200. The fluorine ions implanted into the semiconductor substrate 100 can react with silicon near the surface of the semiconductor substrate 100 to form silicon-fluorine bonds, which can block hot carriers in the channel region from being implanted into the gate oxide layer 210, improve the reliability of the gate oxide layer 210, and alleviate the hot carrier implantation effect of the NMOS transistor.

Since the gate oxide layer 210 and the gate electrode 220 are formed on the semiconductor substrate 100, if fluorine ions are implanted in a direction perpendicular to the semiconductor substrate 100, damage is caused to the gate oxide layer 210 and the gate electrode 220, which affects the performance of the semiconductor device. If fluorine ions are directly injected into the semiconductor substrate 100 before the formation of the gate oxide layer 210, a silicon-oxygen bond may be formed between the gate oxide layer 210 and the semiconductor substrate 100 when the gate oxide layer 210 is formed on the surface of the semiconductor substrate 100, and the silicon-oxygen bond may damage a portion of the silicon-fluorine bond, so that the effect of improving the hot carrier injection effect in the NMOS transistor is reduced. Therefore, in the present invention, after the LDD structure is formed, fluorine ions are implanted into the semiconductor substrate 100 by inclined implantation with respect to the oxide repair layer 230 of the gate structure 200, and the fluorine ion implantation region 105 is formed in the junction region between the semiconductor substrate 100 and the first lightly doped drain region 103 under the gate structure 200. The oblique implantation method allows fluorine ions to directly enter the semiconductor substrate 100, so as to prevent the fluorine ions from penetrating the gate structure 200 and causing unnecessary damage to the gate 220 and the gate oxide layer 210.

The inclination angle at the time of fluorine ion implantation is required to be such that the gate structure 200 is not damaged, and therefore, the implantation direction of fluorine ions (see the arrow direction in fig. 6) should be deviated from the gate structure 200 as much as possible, i.e., the angle θ of the implantation direction of fluorine ions with respect to the surface of the semiconductor substrate 100 is not easily excessively large. Further, the included angle θ between the implantation direction of the fluorine ions and the surface of the semiconductor substrate 100 ranges from 5 ° to 45 °, and further, the included angle θ between the implantation direction of the fluorine ions and the surface of the semiconductor substrate 100 ranges from 10 ° to 35 °, for example, θ may be 15 °,20 °, 25 °,30 °, or the like.

The ion implantation concentration of the fluorine ions is low, the improvement effect on the hot carrier implantation effect is low, and the silicon substrate is consumed more if the ion implantation concentration of the fluorine ions is high. As an example, the ion implantation concentration of the fluorine ion is 1e13 ions/cm ² to 1e15 ions/cm ², further, the ion implantation concentration of the fluorine ion may be 1e13 ions/cm ²、1E14 ions/cm² or 1e15 ions/cm ², or the like, which is not limited in the present application.

The implantation energy of the fluorine ions influences the depth of the fluorine ion implantation area, and if the implantation energy is low, the depth of the fluorine ion implantation area is shallow; the high implantation energy can severely damage the silicon of the semiconductor substrate 100. For example, the implantation energy of the fluorine ions may be in the range of 1KeV to 15KeV, for example, the implantation energy of the fluorine ions may be 1KeV, 5KeV, 10KeV or 15KeV, etc.

After the fluorine ion implantation is completed, a fluorine ion implantation region 105 is formed in the semiconductor substrate 100 under the gate structure 200 toward the first lightly doped drain region 103. The semiconductor substrate 100 with the gate structure 200 formed thereon is placed in a thermal processing chamber for a low temperature anneal process to activate the dopant ions of the dopant ions fluorine and LDD regions and repair the lattice damage. The annealing treatment temperature in the application is 500-900 ℃, for example, the annealing temperature can be 500 ℃, 700 ℃ or 900 ℃, and the like. The application adopts low-temperature annealing treatment, which can prevent the doped ions of the P-type well region 102 from diffusing to the two sides of the channel.

Referring to fig. 1 and 7, step S5 is performed to form side walls 300 on both sides of the gate structure 200. The formation of the sidewall 300 helps to protect the gate 220 and serves as a mask during subsequent source and drain implants. The sidewall 300 may be a single-layer or multi-layer structure composed of an insulating material such as silicon dioxide and/or silicon nitride. I.e., a layer of insulating material such as silicon dioxide, silicon nitride, etc. is covered on two sides of the gate structure 200 by chemical vapor deposition, and then the insulating material is etched to form the sidewall 300. Etching methods include, but are not limited to, dry etching, wet etching, or a process combining dry etching and wet etching.

Referring to fig. 1 and 7, step S6 is performed to form source region 400 and drain region 410 within semiconductor substrate 100.

Photoresist layers are formed on the surfaces of the semiconductor silicon substrate 100 and the gate structure 200, the photoresist layers are exposed and developed to form photoresist masks, openings of the photoresist masks correspond to the source region 400 and the drain region 410, and N-type ion implantation is performed on the semiconductor substrate 100 on one side of the first lightly doped drain region 103 and the semiconductor substrate 100 on one side of the second lightly doped drain region 104 by using the photoresist masks and the side walls 300 to form the drain region 410 and the source region 400. The ion implantation depth of the source region 400 and the drain region 410 is greater than that of the lightly doped drain region, and the ion implantation concentration of the source region 400 and the drain region 410 is greater than that of the lightly doped drain region. The ions implanted in the source region 400 and the drain region 410 are pentavalent ions such as phosphorus ions and arsenic ions. An annealing process is also performed after the implantation of the source region 400 and the drain region 410 is completed to activate the dopant ions and repair the lattice damage.

When the NMOS transistor operates, a voltage difference between the source region 400 and the drain region 410 generates an electric field in a channel region between the source and drain. Since the potential on the drain region 410 side is higher than that on the source region 400 side, the electric field lines are most concentrated near the drain region 410 where the electric field strength is greatest and the hot carrier injection effect is strongest. To better improve the hot carrier injection effect, the drain region 410 should be formed at one side of the fluorine ion injection region 105. For example, if fluorine ions are implanted into the semiconductor substrate 100 at one side of the first lightly doped drain region 103, the drain region 410 should be formed at one side of the first lightly doped drain region 103, and the source region 400 should be formed at one side of the second lightly doped drain region 104.

Referring to fig. 7, the present invention also provides a semiconductor device, which includes: the semiconductor substrate 100, the gate structure 200, the lightly doped drain region, the fluorine ion implantation region 105, the sidewall 300, the source region 400 and the drain region 410. The semiconductor device is prepared by adopting the preparation method.

Specifically, the semiconductor substrate 100 may be a silicon substrate, a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), or the like. A well region is formed in the semiconductor substrate 100, and the type of the well region is related to the type of the semiconductor device. In one embodiment, the semiconductor device is an NMOS transistor, and the P-well region 102 is formed in the semiconductor substrate 100.

The gate structure 200 is disposed on the semiconductor substrate 100. The gate structure 200 includes a gate oxide layer 210, a gate 220, and an oxide repair layer 230, wherein the gate oxide layer 210 is disposed on the surface of the P-type well region 102, and the gate oxide layer 210 is, for example, silicon oxide; the gate 220 is disposed on the gate oxide layer 210, and the gate 220 may be, for example, a polysilicon gate, or a metal gate made of a metal material with a small thermal expansion coefficient, for example, nickel, molybdenum, tungsten, or the like; the oxidation repair layer 230 is disposed on the top wall and the side wall of the gate 220 and the side wall of the gate oxide layer 210, and the formation of the oxidation repair layer 230 can repair the damage caused by the gate 220 and the gate oxide layer 210 during the etching process, and also can protect the gate 220, and the oxidation repair layer 230 is, for example, silicon oxide.

The lightly doped drain region includes a first lightly doped drain region 103 and a second lightly doped drain region 104, the first lightly doped drain region 103 being disposed in the semiconductor substrate 100 on one side of the gate structure 200, and the second lightly doped drain region 104 being disposed in the semiconductor substrate 100 on the other side of the gate structure 200.

The fluorine ion implantation region 105 is disposed in the semiconductor substrate below the gate structure 200 at the junction region with the first lightly doped drain region 103.

The spacers 300 are disposed on two sides of the gate structure 200 and cover portions of the semiconductor substrate 100 on two sides of the gate structure 200, and the spacers 300 are made of an insulating material such as silicon oxide or silicon nitride.

The source region 400 is disposed in the semiconductor substrate 100 on the side of the second lightly doped drain region 104, and the drain region 410 is disposed in the semiconductor substrate 100 on the side of the first lightly doped drain region 103 and close to the fluorine ion implantation region 105. The fluorine ions in the fluorine ion implantation region 105 can form a silicon-fluorine bond between the semiconductor substrate 100 and the gate oxide layer 210, and since the bond energy of the silicon-fluorine bond is higher than that of a silicon-hydrogen bond, interface states are not easy to generate in the NMOS operation process, thereby improving the hot carrier implantation effect of the NMOS transistor.

After the lightly doped drain region is formed, fluorine ions are injected into the junction region of the lightly doped drain region in the semiconductor substrate below the grid structure and at the drain region side in an inclined injection mode, and a silicon-fluorine bond with higher bond energy is formed at the position corresponding to the strongest electric field in the semiconductor substrate through annealing treatment, so that the hot carrier injection effect can be effectively improved, and the reliability of the semiconductor device is further improved. Therefore, the invention effectively overcomes some practical problems in the prior art, thereby having high utilization value and use significance.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor device comprising at least the steps of:

providing a semiconductor substrate;

Forming a gate structure on the semiconductor substrate;

forming side walls on two sides of the grid structure;

2. The method according to claim 1, wherein an angle between an implantation direction of the fluorine ions and a surface of the semiconductor substrate is 5 ° to 45 °.

3. The method according to claim 1, wherein the fluorine ion has an ion implantation concentration of 1e13 ions/cm ² to 1e15 ions/cm ².

4. The method according to claim 1, wherein the ion implantation energy of the fluorine ion is 1KeV to 15KeV.

5. The method of claim 1, wherein the annealing treatment is performed at a temperature of 500 ℃ to 900 ℃.

6. The method of manufacturing of claim 1, wherein prior to forming a gate structure on the semiconductor substrate, the method of manufacturing further comprises:

And forming a P-type well region in the active region.

7. The method of manufacturing according to claim 6, wherein forming a drain region in the semiconductor substrate on the first lightly doped drain side and forming a source region in the semiconductor substrate on the second lightly doped drain side, comprises:

8. The method of manufacturing of claim 1, wherein forming a gate structure on the semiconductor substrate comprises:

forming a gate oxide layer on the semiconductor substrate;

forming a gate electrode on the gate oxide layer;

9. A semiconductor device, comprising:

A semiconductor substrate;

a gate structure disposed on the semiconductor substrate;

the lightly doped drain region comprises a first lightly doped drain region and a second lightly doped drain region, the first lightly doped drain region is arranged in the semiconductor substrate at one side of the grid structure, and the second lightly doped drain region is arranged in the semiconductor substrate at the other side of the grid structure;

a fluorine ion implantation region disposed in the semiconductor substrate below the gate structure and in a junction region with the first lightly doped drain region;

the side walls are arranged on two sides of the grid structure;

The drain region is arranged in the semiconductor substrate at one side of the first lightly doped drain region;

and the source region is arranged in the semiconductor substrate at one side of the second lightly doped drain region.

10. The semiconductor device of claim 9, wherein the gate structure comprises a gate oxide layer, a gate electrode, and an oxide repair layer, the gate oxide layer being disposed on the semiconductor substrate, the gate electrode being disposed on the gate oxide layer, the oxide repair layer being disposed on top and side walls of the gate electrode and on side walls of the gate oxide layer.