CN118282333A

CN118282333A - Variable gain amplifier, signal link circuit and electronic equipment

Info

Publication number: CN118282333A
Application number: CN202211729715.1A
Authority: CN
Inventors: 王红玉
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Filing date: 2022-12-30
Publication date: 2024-07-02

Abstract

The embodiment of the application discloses a variable gain amplifier, a signal link circuit and electronic equipment, relates to the technical field of electronics, and solves the problem that the linearity of the conventional variable gain amplifier is poor. The specific scheme is as follows: there is provided a variable gain amplifier having a differential signal output and a differential signal input, and comprising: the first resistor, the second resistor, the first transistor, the second transistor, the first current source, the second current source, the transistor circuit and the control circuit. The control circuit is coupled with the grid electrode of the transistor circuit, and is used for receiving a control voltage, selectively applying one of the control voltage and a reference voltage to the grid electrode of the transistor circuit as a regulating voltage, wherein the reference voltage is a critical voltage corresponding to a linear change region and a nonlinear change region of the resistance value of the transistor circuit.

Description

Variable gain amplifier, signal link circuit and electronic equipment

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to a variable gain amplifier, a signal link circuit and electronic equipment.

Background

A Variable Gain Amplifier (VGA) is a basic circuit block in radio frequency, analog and high frequency integrated circuits that is used to adjust the gain of the signal link circuit based on the variation in the amplitude of the input signal or based on the requirements on the amplitude of the output signal. For example, in a chip including radio frequency, analog, and high frequency integrated circuits, continuous variation of gain is adjustable by a variable gain amplifier, and the chip has a high requirement for linearity of the variable gain amplifier.

However, the linearity of the existing variable gain amplifier is poor, so it is needed to provide a variable gain amplifier with high linearity to meet the requirement of the chip on the linearity of the variable gain amplifier.

Disclosure of Invention

The embodiment of the application provides a variable gain amplifier, a signal link circuit and electronic equipment, which solve the problem of poor linearity of the conventional variable gain amplifier.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

In a first aspect of an embodiment of the present application, there is provided a variable gain amplifier having a differential signal output and a differential signal input, and comprising: the first transistor, the second transistor, the first resistor, the second resistor, the first current source, the second current source, the transistor circuit and the control circuit. The grid electrode of the first transistor and the grid electrode of the second transistor are differential signal input ends, and the input ends of the first transistor and the second transistor are differential signal output ends. One end of the first resistor is coupled with the voltage source, the other end of the first resistor is coupled to the input end of the first transistor, one end of the second resistor is coupled with the voltage source, and the other end of the second resistor is coupled to the input end of the second transistor. One end of the first current source is coupled with the output end of the first transistor to the first node, the other end of the first current source is coupled with the ground end, one end of the second current source is coupled with the output end of the second transistor to the second node, and the other end of the second current source is coupled with the ground end. Two connection terminals of the transistor circuit are coupled between the first node and the second node, wherein the connection terminals comprise at least one of a source and a drain of the transistor. The control circuit is coupled to the gate of the transistor circuit.

The control circuit is used for receiving a control voltage, and selectively applying one of the control voltage and a reference voltage to the grid electrode of the transistor circuit as a regulating voltage, wherein the reference voltage is a critical voltage corresponding to a linear change area and a nonlinear change area of the resistance value of the transistor circuit.

According to the variable gain amplifier provided by the embodiment of the application, the control circuit receives the control voltage, one of the control voltage and the reference voltage is selectively applied to the grid electrode of the transistor circuit as the adjustment voltage, the reference voltage is the critical voltage corresponding to the linear change area and the nonlinear change area of the resistance value of the transistor circuit, the generated adjustment voltage can linearly adjust the resistance value of the transistor circuit, and meanwhile, the current sources and the current sources output constant currents, so that the voltages at two ends of the transistor circuit can be linearly adjusted, the voltage of the differential signal output end can be linearly adjusted, and the gain of the variable gain amplifier circuit can be linearly adjusted.

With reference to the first aspect, in one possible implementation manner, the adjustment voltage is equal to the control voltage when the control voltage is greater than the reference voltage, or is equal to the reference voltage when the control voltage is less than or equal to the reference voltage.

According to the variable gain amplifier provided by the embodiment of the application, the control circuit generates the regulating voltage according to the reference voltage and the control voltage, and the regulating voltage is larger than or equal to the reference voltage, so that the resistance of the transistor circuit can be regulated linearly by the regulating voltage, and the voltage at two ends of the transistor circuit can be regulated linearly by the current source and the current source to output constant current, so that the voltage of the differential signal output end can be regulated linearly, and the gain of the variable gain amplifying circuit can be regulated linearly.

With reference to the first aspect, in one possible implementation manner, the transistor circuit includes at least one sub-transistor circuit, and the sub-transistor circuit includes a third transistor and a fourth transistor. The first terminal of the third transistor is coupled to the first terminal of the fourth transistor, the second terminal of the third transistor and the second terminal of the fourth transistor serve as two connection terminals of the sub-transistor circuit, and the gate of the third transistor and the gate of the fourth transistor serve as gates of the sub-transistor circuit.

Alternatively, the third transistor and the fourth transistor may be NMOS transistors, or may be PMOS transistors, which is not limited by the embodiment of the present application.

Alternatively, the above-mentioned sub-transistor circuit may include 2 transistors, or may include 2n transistors, where n is a natural number greater than or equal to 1, which is not limited by the embodiment of the present application.

The variable gain amplifier provided by the embodiment of the application comprises the third transistor and the fourth transistor, so that the resistance value of the sub-transistor circuit can be linearly adjusted by utilizing the variable resistance regions of the third transistor and the fourth transistor, and the voltage at two ends of the transistor circuit can be linearly adjusted, thereby linearly adjusting the voltage at the output end of the differential signal and linearly adjusting the gain of the variable gain amplifying circuit.

With reference to the first aspect, in one possible implementation manner, the control circuit includes at least one sub-control circuit, and the sub-control circuit includes a third current source, a fifth transistor, a first configurable resistor, a first comparator, and a first selector. One end of the third current source is used for being coupled with a voltage source, and the other end of the third current source is coupled with the grid electrode of the fifth transistor and the first end of the fifth transistor and used for outputting a reference voltage. The second terminal of the fifth transistor is coupled to one terminal of the first configurable resistor, and the other terminal of the first configurable resistor is coupled to the first terminal of the third transistor. The first input terminal of the first comparator and the first input terminal of the first selector are coupled to the first terminal of the fifth transistor, the second input terminal of the first comparator and the second input terminal of the first selector are for receiving the control voltage, the output terminal of the first comparator is coupled to the selection terminal of the first selector, and the output terminal of the first selector is for outputting the regulated voltage.

Alternatively, the fifth transistor may be an NMOS transistor or may be a PMOS transistor, which is not limited by the embodiment of the present application.

According to the variable gain amplifier provided by the embodiment of the application, the other end of the first configurable resistor is coupled with the first end of the third transistor, so that the sub-control circuit can generate the reference voltage corresponding to the voltage of the first end of the third transistor at the first end of the fifth transistor through the first configurable resistor, the fifth transistor and the current source, the reference voltage can follow the voltage change of the first end of the third transistor, and the reference voltage can be flexibly configured according to voltage sources with different voltage values.

With reference to the first aspect, in one possible implementation manner, the transistor circuit includes a plurality of sub-transistor circuits coupled in parallel, and the control circuit includes a plurality of sub-control circuits coupled in one-to-one correspondence with the plurality of sub-control circuits. The regulating voltage generated by each sub-control circuit in the plurality of sub-control circuits is used for linearly regulating the resistance value of the sub-transistor circuit corresponding to the sub-control circuit.

According to the variable gain amplifier provided by the embodiment of the application, the plurality of sub-transistor circuits are arranged in parallel in the transistor circuit, the plurality of sub-control circuits corresponding to the plurality of sub-transistor circuits are arranged in the control circuit, and each sub-control circuit can independently control the resistance value of a corresponding sub-transistor circuit, so that the resistance value adjusting range of the transistor circuit can be expanded, and the gain adjusting range of the variable gain amplifier can be expanded.

With reference to the first aspect, in one possible implementation manner, the transistor circuit includes a sixth transistor, a first terminal of the sixth transistor and a second terminal of the sixth transistor serve as two connection terminals of the transistor circuit, and a gate of the sixth transistor serves as a gate of the transistor circuit.

Alternatively, the sixth transistor may be an NMOS transistor or may be a PMOS transistor, which is not limited by the embodiment of the present application.

The transistor circuit of the variable gain amplifier provided by the embodiment of the application comprises the sixth transistor, so that the resistance value of the transistor circuit can be linearly adjusted by utilizing the variable resistance region of the sixth transistor, and the voltage at two ends of the transistor circuit can be linearly adjusted, so that the voltage at the output end of the differential signal can be linearly adjusted, and the gain of the variable gain amplifier circuit can be linearly adjusted.

With reference to the first aspect, in one possible implementation manner, the control circuit includes a fourth current source, a second configurable resistor, a seventh transistor, a second comparator, and a second selector. One end of the fourth current source is used for being coupled with a voltage source, and the other end of the fourth current source is coupled with the first end of the second configurable resistor and used for outputting a reference voltage. The second terminal of the second configurable resistor is coupled to the first terminal of the seventh transistor and the gate of the seventh transistor, and the second terminal of the seventh transistor is coupled to ground. A first input of the second comparator and a first input of the second selector are coupled to a first end of the second configurable resistor; the second input of the second comparator and the second input of the second selector are for receiving the control voltage, the output of the second comparator is coupled to the selection terminal of the second selector, and the output of the second selector is for outputting the regulated voltage.

Alternatively, the seventh transistor may be an NMOS transistor or may be a PMOS transistor, which is not limited by the embodiment of the present application.

According to the variable gain amplifier provided by the embodiment of the application, the control circuit generates the reference voltage, and the regulating voltage is generated according to the reference voltage and the control voltage, so that the regulating voltage can be ensured to be greater than or equal to the reference voltage, and the resistance value of the transistor circuit can be ensured to be in a linear variation interval, and thus the gain of the variable gain amplifier circuit can be ensured to be adjusted linearly, and the linearity of the variable gain amplifier circuit is higher.

With reference to the first aspect, in one possible implementation manner, the first transistor and the second transistor are NMOS transistors, an input terminal of the first transistor and an input terminal of the second transistor are drains, and an output terminal of the first transistor and an output terminal of the second transistor are sources;

or the first transistor and the second transistor are PMOS transistors, the input end of the first transistor and the input end of the second transistor are sources, and the output end of the first transistor and the output end of the second transistor are drains.

In a second aspect of the embodiments of the present application, there is provided a signal link circuit, the signal link circuit comprising an amplifier, and a variable gain amplifier coupled to the amplifier, the variable gain amplifier being as described in the first aspect or any one of the possible implementations of the first aspect.

With reference to the second aspect, in one possible implementation manner, the signal link circuit is one of a radio frequency circuit, an analog circuit, or a high frequency integrated circuit.

In a third aspect of the embodiment of the present application, an electronic device is provided, where the electronic device includes a transmitter and a receiver, and the transmitter and the receiver each include a signal link circuit, where the signal link circuit is a signal link circuit as described in the second aspect or any one of the possible implementation manners of the second aspect.

The description of the second and third aspects of the present application may refer to the detailed description of the first aspect; moreover, the advantages described in the second aspect and the third aspect may refer to the analysis of the advantages of the first aspect, and are not described herein.

Drawings

FIG. 1 is a schematic diagram of a signal link circuit;

FIG. 2 is a schematic diagram of a variable gain amplifier;

FIG. 3 is a schematic diagram of another variable gain amplifier;

FIG. 4 is a schematic diagram of an NMOS transistor output characteristic;

fig. 5 is a schematic structural diagram of a variable gain amplifier according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another variable gain amplifier according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a gain characteristic of a variable gain amplifier;

Fig. 8 is a schematic diagram of a structure of another variable gain amplifier according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of still another variable gain amplifier according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a signal link circuit according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The making and using of the various embodiments are discussed in detail below. It should be appreciated that the numerous applicable inventive concepts provided by the present application may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the description and technology, and do not limit the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this case, "for" is used to connote structure by indicating that circuitry/components includes structure (e.g., circuitry) that performs one or more tasks during operation. Thus, a given circuit/component may be said to be used to perform that task even when the circuit/component is not currently operational (e.g., not open). Circuits/components used with the term "for" include hardware, such as circuitry to perform operations, etc.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and order.

In the present application, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

Before describing the embodiments of the present application, the background art to which the present application relates will be described first.

Threshold voltage: refers to a gate (G) voltage, commonly referred to as V _TH, when a specified current is present between a source (S) and a drain (D) of a metal-oxide-semiconductor (MOS) transistor.

Gate-source voltage: refers to the voltage between the gate and the source of the MOS transistor, and is generally referred to as V _GS.

Drain-source voltage: refers to the voltage between the drain and the source of the MOS transistor, and is generally abbreviated as V _DS.

Pre-pinching off: refers to the demarcation point of the variable resistance region and the saturation region of the MOS transistor.

Transfer characteristic curve: the transfer characteristic curve is a visual representation of the transfer characteristic of the MOS transistor, and the transfer characteristic curve refers to a functional relationship between the drain current I _D and the gate-source voltage V _GS by taking the drain-source voltage V _DS as a parameter, and reflects the control action of the gate-source voltage V _GS on the drain current I _D.

The variable gain amplifier is a basic circuit block in radio frequency, analog and high frequency integrated circuits. When the module is applied to a signal link circuit, the module can be used for adjusting the gain of the signal link circuit according to the change of the amplitude of an input signal or according to the requirement on the amplitude of an output signal.

For example, as shown in fig. 1, a schematic structure of a signal link circuit includes a first amplifier AMP (amplifier), a variable gain amplifier VGA, and a second amplifier AMP2, which are coupled in series. The signal link circuit can be applied to a communication chip or an analog chip, and continuous variation and adjustability of gain can be realized by adopting the signal link circuit.

Specifically, fig. 2 is a schematic structural diagram of a variable gain amplifier VGA. The variable gain amplifier VGA has a differential signal output end and a differential signal input end, and comprises a resistor Ra, a resistor Rb, an NMOS (NEGATIVE CHANNEL MOS) tube a, an NMOS tube b, a variable resistor Rc, a current source Ia and a current source Ib.

Wherein, one end of resistance Ra and one end of resistance Rb are used for coupling with voltage source VDD, and the other end of resistance Ra and the other end of resistance Rb are coupled with differential signal output. The grid Ga of the NMOS tube a and the grid Gb of the NMOS tube b are coupled with differential signal input ends, the drain Da of the NMOS tube a and the drain Db of the NMOS tube b are coupled with differential signal output ends, the source Sa of the NMOS tube a is coupled with one end of a current source Ia and is coupled with a first node, the source Sb of the NMOS tube b is coupled with one end of a current source Ib and is coupled with a second node, and the other end of the current source Ia and the other end of the current source Ib are coupled with a Ground (GND). The two connection terminals of the variable resistor Rc are coupled between the first node and the second node.

It will be appreciated that since the current sources Ia and Ib output constant currents, the voltage across the variable resistor Rc can be adjusted by adjusting the resistance value of the variable resistor Rc, and the voltage at the differential signal output terminal can be adjusted, so that the gain of the variable gain amplifier circuit VGA can be adjusted.

The variable resistor Rc can be a variable resistor realized by an NMOS tube, and the resistance value of the on-resistance of the NMOS tube can be adjusted by adjusting the gate voltage of the NMOS tube to adjust the gate-source voltage or the gate-drain voltage of the NMOS tube by utilizing the characteristic that the on-resistance of the NMOS tube changes along with the gate voltage.

For example, as shown in fig. 3, an NMOS transistor c may be used as the variable resistor Rc, the source Sc and the drain Dc of the NMOS transistor c may be used as two connection terminals of the variable resistor Rc, and the gate Gc of the NMOS transistor c may be used to receive an adjustment voltage, and the resistance value of the NMOS transistor c is adjusted according to the adjustment voltage.

Specifically, the output characteristic curve of the NMOS transistor c is shown in fig. 4 (a). When V _GS<V_TH is reached, the conduction channel in the NMOS transistor is not formed, the current of the drain Dc is 0, the NMOS transistor c is in the cut-off state, and the area under the V _GS＝V_TH curve may also be referred to as the cut-off area of the NMOS transistor c. When V _GS>V_TH and V _DS≤(V_GS-V_TH), the resistance of the NMOS transistor c is affected by V _GS, which may be referred to as the variable resistance region of the NMOS transistor c, or as the linear region of the NMOS transistor c, such as the portion of the V _GS1、V_GS2 and V _GS3 curves to the left of the pre-pinch-off locus curve. When V _GS>V_TH, and V _DS≥(V_GS-V_TH), this region may be referred to as the saturation region of NMOS transistor c, e.g., the portion of the V _GS1、V_GS2 and V _GS3 curves to the right of the pre-pinch-off locus curve. According to the output characteristic curve of the NMOS c, a transfer characteristic curve as shown in (b) of fig. 4 can be obtained by a plotting method, I _D linearly varies with V _GS when V _GS>V_TH2, and when V _GS<V_TH2, I _D varies nonlinearly with V _DS.

As can be seen from fig. 4 (a), in the variable resistor region, when V _GS is different, the resistance of the NMOS transistor c is different, the NMOS transistor c can be used as a variable resistor, and I _D rises with the increase of V _GS, and the two are in a linear relationship, so that the NMOS transistor c can be regarded as a linear resistor. When V _GS is larger, the range of the linear region of the resistance of the NMOS tube C is larger, the influence of V _DS fluctuation on the resistance of the NMOS tube C is smaller, and when V _GS is smaller, the range of the linear region of the resistance of the NMOS tube C is smaller, and the influence of V _DS fluctuation on the resistance of the NMOS tube C is quite obvious. Meanwhile, as can be seen from (b) in fig. 4, when V _GS approaches V _TH, for example, when V _GS<V_TH2, V _GS cannot linearly control I _D. In summary, when V _GS is smaller, the resistance of the NMOS c will be nonlinear, which results in nonlinear gain variation of the VGA, resulting in poor linearity of the VGA.

In order to solve the problem that the linearity of the VGA of the variable gain amplifier is poor, the embodiment of the application provides the variable gain amplifier which can meet the requirement on the linearity of the variable gain amplifier.

Fig. 5 is a schematic structural diagram of a variable gain amplifier according to an embodiment of the present application. The variable gain amplifier has a differential signal output and a differential signal input, and includes: the first resistor R1, the second resistor R2, the first transistor T1, the second transistor T2, the first current source I1, the second current source I2, the transistor circuit 510 and the control circuit 520.

The gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 are differential signal input ends, and the input ends of the first transistor T1 and the second transistor T2 are differential signal output ends. One end of the first resistor R1 is coupled to the voltage source VDD, the other end of the first resistor R1 is coupled to the input end of the first transistor T1, one end of the second resistor R2 is coupled to the voltage source VDD, and the other end of the second resistor R2 is coupled to the input end of the second transistor T2. One end of the first current source I1 is coupled to the first node with the output end of the first transistor T1, the other end of the first current source I1 is coupled to the ground GND, one end of the second current source I2 is coupled to the second node with the output end of the second transistor T2, and the other end of the second current source I2 is coupled to the ground GND. Two connection terminals of the transistor circuit 510 are coupled between the first node and the second node, wherein the connection terminals comprise at least one of a source and a drain of the transistor, and the control circuit 520 is coupled to a gate of the transistor circuit 510.

The control circuit 520 is configured to receive the control voltage Vctl, and selectively apply one of the control voltage Vctl and a reference voltage Vc0 as a regulating voltage Vgc to the gate of the transistor circuit 510, where the reference voltage Vc0 is a threshold voltage corresponding to a linear variation region and a nonlinear variation region of the resistance value of the transistor circuit 510.

It will be understood that when the reference voltage Vc0 is a critical voltage and the control circuit 520 selectively uses one of the control voltage Vctl and the reference voltage Vc0 as the adjustment voltage Vgc, a voltage capable of linearly adjusting the resistance value of the transistor circuit 510 may be selected as the adjustment voltage Vgc, and the resistance value of the transistor circuit 510 may be linearly adjusted by the adjustment voltage Vgc, and since the current sources I1 and I2 output constant currents, the voltages at both ends of the transistor circuit 510 may be linearly adjusted, so that the voltage at the differential signal output end may be linearly adjusted, and the gain of the variable gain amplifying circuit may be linearly adjusted.

Alternatively, the first transistor T1 and the second transistor T2 may be NMOS transistors, the input terminal of the first transistor T1 and the input terminal of the second transistor T2 are drains, the output terminal of the first transistor T1 and the output terminal of the second transistor T2 are sources, or the first transistor T1 and the second transistor T2 may be PMOS (positive channel MOS) transistors, the input terminal of the first transistor T1 and the input terminal of the second transistor T2 are sources, and the output terminal of the first transistor T1 and the output terminal of the second transistor T2 are drains, which is not limited by the embodiment of the present application, and the following embodiment is exemplified by taking the first transistor T1 and the second transistor T2 as NMOS transistors.

In the variable gain amplifier provided by the embodiment of the application, the control circuit 520 receives the control voltage Vctl, and selectively applies one of the control voltage Vctl and the reference voltage Vc0 as the adjustment voltage Vgc to the gate of the transistor circuit 510, where the reference voltage Vc0 is a critical voltage corresponding to a linear variation region and a nonlinear variation region of the resistance value of the transistor circuit 510, so that the generated adjustment voltage Vgc can linearly adjust the resistance value of the transistor circuit 510, and meanwhile, since the current sources I1 and I2 output constant currents, the voltages at both ends of the transistor circuit 510 can be linearly adjusted, so that the voltage at the output end of the differential signal can be linearly adjusted, and the gain of the variable gain amplifier circuit can be linearly adjusted.

Specifically, when the control voltage Vctl is greater than the reference voltage Vc0, the adjustment voltage Vgc is equal to the control voltage Vctl, or when the control voltage Vctl is less than or equal to the reference voltage Vc0, the adjustment voltage Vctl is equal to the reference voltage Vc0. The control circuit 520 generates the regulated voltage Vgc based on the reference voltage Vc0 and the control voltage Vctl, and may include various implementations, as will be described in detail below.

In a first possible implementation, the transistor circuit 510 includes at least one sub-transistor circuit, and the control circuit 520 includes at least one sub-control circuit, which is in one-to-one correspondence with the at least one sub-control circuit. The embodiment of the present application is not limited to a specific number of sub-transistor circuits included in the transistor circuit 510 and a specific number of sub-control circuits included in the control circuit 520.

In one embodiment, as shown in fig. 6, the transistor circuit 510 includes a sub-transistor circuit 511, and the control circuit 520 includes a sub-control circuit 521.

The sub-transistor circuit 511 includes a third transistor T3 and a fourth transistor T4. The first terminal of the third transistor T3 and the first terminal of the fourth transistor T4 are coupled, the second terminal of the third transistor T3 and the second terminal of the fourth transistor T4 serve as two connection terminals of the sub-transistor circuit 511, and the gate G3 of the third transistor T3 and the gate G4 of the fourth transistor T4 serve as gates of the sub-transistor circuit 511.

At this time, the resistance Ron of the sub-transistor circuit 511 can be expressed as:

Where K _n is the conductance constant, V _TH is the threshold voltage of the third transistor T3 or the fourth transistor T4, V _D1 is the drain voltage of the transistor T1, and V _D2 is the drain voltage of the transistor T2.

Alternatively, the above-mentioned sub-transistor circuit 511 may include 2 transistors, or may include 2n transistors, where n is a natural number greater than or equal to 1, and the embodiment of the present application is not limited thereto, and the following embodiment of the present application will be exemplified by taking the sub-transistor circuit 511 including the third transistor T3 and the fourth transistor T4 as an example.

Illustratively, taking the example that the sub-transistor circuit 511 includes M1 to M4 of the 4 transistors, the first terminal of M1 and the first terminal of M4 may serve as two connection terminals of the sub-transistor circuit 511, the second terminal of M1 is coupled to the first terminal of M2, the second terminal of M2 is coupled to the first terminal of M3, the second terminal of M3 is coupled to the second terminal of M4, and the gates of the 4 transistors may serve as gates of the sub-transistor circuit 511.

The above-described sub-control circuit 521 includes a third current source I3, a fifth transistor T5, a first configurable resistor Rtr1, a first Comparator (COMP) 1, and a first data selector (MUX, which may also be simply referred to as a selector) 1. One end of the third current source I3 is coupled to the voltage source VDD, and the other end of the third current source I3 is coupled to the gate G5 of the fifth transistor T5 and the first end of the fifth transistor T5, for outputting the reference voltage Vc0. The second terminal of the fifth transistor T5 is coupled to one terminal of a first configurable resistance Rtr1, the other terminal of the first configurable resistance Rtr1 being coupled to the first terminal of the third transistor T3.

Alternatively, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 may be NMOS transistors, and the drain terminal of the third transistor T3 and the drain terminal of the fourth transistor T4 may be two connection terminals of the sub-transistor circuit 511, or may be PMOS transistors, which is not limited by the embodiment of the present application.

Alternatively, when the sub-transistor circuit 511 includes 2n transistors, n is greater than 1, the other end of the first configurable resistance Rtr1 is coupled to the common mode terminal of the n-th transistor and the n+1th transistor of the 2n transistors.

For example, taking the example in which the sub-transistor circuit 511 includes the above-described transistors M1 to M4 (n is 2), the other end of the first configurable resistance Rtr1 is coupled to the common mode terminal of the transistor M2 and the transistor M3.

It will be appreciated that by coupling the other end of the first configurable resistance Rtr1 with the first end of the third transistor T3, the sub-control circuit 521 may generate the reference voltage Vc0 corresponding to the voltage Va at the first end of the fifth transistor T5 through the first configurable resistance Rtr1, the fifth transistor T5 and the current source I3. The voltage Va is the voltage of the common mode terminal of the third transistor T3 and the fourth transistor T4, and the reference voltage Vc0 may follow the change of the voltage Va, so that the reference voltage Vc0 may be flexibly configured according to the voltage sources VDD with different voltage values.

A first input of the first comparator COMP1 and a first input of the first selector MUX1 are coupled to a first end of the fifth transistor T5. A second input terminal of the first comparator COMP1 and a second input terminal of the first selector MUX1 are for receiving the control voltage Vctl, an output terminal of the first comparator COMP1 is coupled to a selection terminal of the first selector MUX1, and an output terminal of the first selector MUX1 is for outputting the adjustment voltage Vgc.

It will be appreciated that both the first comparator COMP1 and the first selector MUX1 may acquire the reference voltage Vc0 and the control voltage Vctl, and that the voltage output by the first comparator COMP1 is also used for selection control of the output voltage of the first selector MUX 1.

Specifically, when the control voltage Vctl is greater than the reference voltage Vc0, the first comparator COMP1 outputs the control voltage Vctl, which may control the first selector MUX1 to output the control voltage Vctl, and the adjustment voltage Vgc is equal to the control voltage Vctl. When the control voltage Vctl is less than the reference voltage Vc0, the first comparator COMP1 outputs the reference voltage Vc0, and the reference voltage Vc0 may control the first selector MUX1 to output the reference voltage Vc0, and the adjustment voltage Vgc is equal to the reference voltage Vc0.

It will be appreciated that by generating the reference voltage Vc0 by the sub-control circuit 521, and generating the adjustment voltage Vgc described above from the reference voltage Vc0 and the control voltage Vctl, it is possible to ensure that the adjustment voltage Vgc is greater than or equal to the reference voltage Vc0, and thus it is possible to ensure that the adjustment voltage Vgc can linearly adjust the gain of the variable gain amplifying circuit.

Specifically, V _D1 and V _D2 described above may be expressed as:

And (3) making:

V_GS3＝V_GS4＝V_GS5

V_m＝V_a+V_GS3-V_cmi+V_GS1＝V_c0-I₃*R_tr-(V_cmi-V_GS1)+(V_GS5-V_GS3)＝V_c0-I₃*R_tr-(V_cmi-V_GS1)

Wherein V _cmi is a common mode voltage of the first transistor T1 and the second transistor T2, V _GS1 is a gate-source voltage of the first transistor T1, V _GS2 is a gate-source voltage of the second transistor T2, V _in is a voltage for inputting a differential signal, V _GS3 is a gate-source power supply of the third transistor T3, R _tr is a resistance value of the first configurable resistor Rtr1, V _GS4 is a gate-source power supply of the fourth transistor T4, V _GS5 is a gate-source power supply of the fifth transistor T5, and I ₃ is a current outputted by the third current source I3.

The expressions for bringing the above V _D1、V_D2 and V _m into the resistance Ron of the above sub-transistor circuit 511 are as follows:

the reference voltage Vc0 may be expressed as:

V_c0＝V_cmi+(V_GS5-V_GS1)+I₃*R_tr

the gain G ₀ of the variable gain amplifier can be expressed as:

Wherein RL is the resistance of the first resistor R1 or the second resistor R2, and g _m is the transconductance of the first transistor T1 or the second transistor T2. As shown in fig. 7 (a), the control signal transfer curve of the variable gain amplifier is shown in fig. 7 (b), and according to the 2 drawings, when the control voltage Vctl is less than or equal to the reference voltage Vc0, the sub-transistor circuit 511 receives the adjustment voltage Vgc equal to the reference voltage Vc0, the gain of the variable gain amplifier is equal to G1, and when the control voltage Vctl is greater than the reference voltage Vc0, the sub-transistor circuit 511 receives the adjustment voltage Vgc equal to the control voltage Vctl, and the gain of the variable gain amplifier linearly varies with the control voltage Vctl.

In another embodiment, as shown in fig. 8, the transistor circuit 510 includes a plurality of sub-transistor circuits 511 coupled in parallel, where the plurality of sub-transistor circuits 511 may also be referred to as a variable resistor array, and the control circuit 520 includes a plurality of sub-control circuits 521, where the plurality of sub-transistor circuits 511 are coupled in a one-to-one correspondence with the plurality of sub-control circuits 521. Wherein, the adjustment voltage Vgc generated by each sub-control circuit 521 of the plurality of sub-control circuits 521 is used for linearly adjusting the resistance value of the sub-transistor circuit 511 corresponding to the sub-control circuit 521.

In the variable gain amplifier according to the embodiment of the present application, the plurality of sub-transistor circuits 511 are arranged in parallel in the transistor circuit 510, and the plurality of sub-control circuits 521 corresponding to the plurality of sub-transistor circuits 511 are arranged in the control circuit 520, and each sub-control circuit 521 can individually control the resistance value of a corresponding one of the sub-transistor circuits 511, so that the resistance value adjustment range of the transistor circuit 510 can be expanded, and the gain adjustment range of the variable gain amplifier can be expanded.

In a second possible implementation, as shown in fig. 9, the transistor circuit 510 includes a sixth transistor T6, where a first terminal of the sixth transistor T6 and a second terminal of the sixth transistor T6 serve as two connection terminals of the transistor circuit 510, and are coupled to a first node and a second node, respectively, and a gate G6 of the sixth transistor T6 serves as a gate of the transistor circuit 510.

As shown in fig. 9, the control circuit 520 includes a fourth current source I4, a second configurable resistor Rtr2, a seventh transistor T7, a second comparator COMP2, and a second selector MUX2. One end of the fourth current source I4 is coupled to the voltage source VDD, and the other end of the fourth current source I4 is coupled to the first end of the second configurable resistor Rtr2, so as to output the reference voltage Vc0. The second terminal of the second configurable resistor Rtr2 is coupled to the first terminal of the seventh transistor T7 and the gate G7 of the seventh transistor T7, and the second terminal of the seventh transistor T7 is coupled to the ground GND. The first input terminal of the second comparator COMP2 and the first input terminal of the second selector MUX2 are coupled to the first terminal of the second configurable resistor Rtr2, the second input terminal of the second comparator COMP2 and the second input terminal of the second selector MUX2 are for receiving the control voltage Vctl, the output terminal of the second comparator COMP is coupled to the selection terminal of the second selector MUX, and the output terminal of the second selector MUX is for outputting the adjustment voltage Vgc.

Alternatively, the sixth transistor T6 and the seventh transistor T7 may be NMOS transistors, and the source terminal and the drain terminal of the sixth transistor T6 may be two connection terminals of the transistor circuit 510, or may be PMOS transistors, which is not limited by the embodiment of the present application.

It will be appreciated that the reference voltage Vc0 can be generated by the fourth current source I4, the second configurable resistor Rtr2 and the seventh transistor T7, and the reference voltage Vc0 and the control voltage Vctl can be obtained by both the second comparator COMP2 and the second selector MUX2, and the voltage output by the second comparator COMP2 is also used for the selection control of the output voltage of the second selector MUX 2.

Alternatively, the reference voltage Vc0 may be a preset voltage determined through an experimental test.

When the control voltage Vctl is greater than the reference voltage Vc0, the second comparator COMP2 may output the control voltage Vctl, which may control the second selector MUX2 to output the control voltage Vctl, and the adjustment voltage Vgc is equal to the control voltage Vctl. When the control voltage Vctl is less than the reference voltage Vc0, the second comparator COMP2 may output the reference voltage Vc0, and the reference voltage Vc0 may control the second selector MUX2 to output the reference voltage Vc0, and the adjustment voltage Vgc is equal to the reference voltage Vc0. Accordingly, the adjustment voltage received by the transistor circuit 510 is greater than or equal to the reference voltage, and when the control voltage Vctl is greater than the reference voltage Vc0, the adjustment voltage Vgc received by the transistor circuit 510 is equal to the control voltage Vctl, and the gain of the variable gain amplifier linearly varies with the control voltage Vctl.

It should be noted that, for the description of the second possible implementation manner, reference may be made to the description of the first possible implementation manner, and the embodiment of the present application is not described herein.

According to the variable gain amplifier provided by the embodiment of the application, the control circuit 520 generates the reference voltage Vc0, and the adjusting voltage Vgc is generated according to the reference voltage Vc0 and the control voltage Vctl, so that the adjusting voltage Vgc is larger than or equal to the reference voltage Vc0, and the resistance of the transistor circuit 510 is ensured to be in a linear variation range, and the gain of the variable gain amplifying circuit can be ensured to be adjusted linearly, so that the linearity of the variable gain amplifying circuit is higher.

Based on this, as shown in fig. 10, the embodiment of the present application further provides a signal link circuit 1000, where the signal link circuit 1000 includes an amplifier A1 and a variable gain amplifier 1010 coupled to the amplifier A1, and the variable gain amplifier 1010 has the structure of the variable gain amplifier shown in any one of fig. 5, 6, 8 and 9.

Alternatively, the signal link circuit 1000 is one of a radio frequency circuit, an analog circuit, or a high frequency integrated circuit.

As shown in fig. 11, an embodiment of the present application further provides an electronic device 1100, where the electronic device 1100 includes a transmitter 1110 and a receiver 1120, and the transmitter 1110 and the receiver 1120 each include a signal link circuit 1000, and the structure of the signal link circuit 1000 may be the structure of the signal link circuit 1000 shown in fig. 10.

The above detailed descriptions of the variable gain amplifier can be correspondingly incorporated into the signal link circuit 1000 and the electronic device 1100, and the detailed descriptions of the embodiments of the present application are omitted here. The circuits and devices provided in the embodiments of the present application all include the functions of the variable gain amplifier in the above embodiments, so that the same effects as those of the variable gain amplifier can be achieved.

The foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A variable gain amplifier, comprising:

The device comprises a first transistor and a second transistor, wherein the grid electrode of the first transistor and the grid electrode of the second transistor are differential signal input ends, and the input ends of the first transistor and the second transistor are differential signal output ends;

a first resistor, one end of which is coupled with a voltage source, and the other end of which is coupled to the input end of the first transistor;

a second resistor, one end of which is coupled with the voltage source, and the other end of which is coupled to the input end of the second transistor;

a first current source, one end of which is coupled with the output end of the first transistor to a first node, and the other end of which is coupled with a ground end;

A second current source, one end of which is coupled with the output end of the second transistor and is coupled with a second node, and the other end of which is coupled with the ground end;

A transistor circuit having two connection terminals coupled between the first node and the second node, wherein the connection terminals include at least one of a source and a drain of a transistor;

a control circuit coupled to the gate of the transistor circuit;

The control circuit is used for receiving a control voltage, selectively applying one of the control voltage and a reference voltage to the grid electrode of the transistor circuit as a regulating voltage, wherein the reference voltage is a critical voltage corresponding to a linear variation region and a nonlinear variation region of the resistance value of the transistor circuit.

2. The variable gain amplifier of claim 1, wherein,

When the control voltage is greater than the reference voltage, the regulated voltage is equal to the control voltage,

Or when the control voltage is less than or equal to the reference voltage, the adjustment voltage is equal to the reference voltage.

3. A variable gain amplifier according to claim 1 or 2, wherein the transistor circuit comprises at least one sub-transistor circuit comprising a third transistor and a fourth transistor;

The first end of the third transistor and the first end of the fourth transistor are coupled, the second end of the third transistor and the second end of the fourth transistor serve as two connection ends of the sub-transistor circuit, and the gate of the third transistor and the gate of the fourth transistor serve as gates of the sub-transistor circuit.

4. A variable gain amplifier according to claim 3, wherein the control circuit comprises at least one sub-control circuit comprising a third current source, a fifth transistor, a first configurable resistor, a first comparator and a first selector;

One end of the third current source is used for being coupled with the voltage source, and the other end of the third current source is coupled with the grid electrode of the fifth transistor and the first end of the fifth transistor and is used for outputting the reference voltage; a second terminal of the fifth transistor is coupled to one terminal of the first configurable resistance, and the other terminal of the first configurable resistance is coupled to the first terminal of the third transistor;

A first input of the first comparator and a first input of the first selector are coupled to a first end of the fifth transistor; the second input terminal of the first comparator and the second input terminal of the first selector are used for receiving the control voltage, the output terminal of the first comparator is coupled with the selection terminal of the first selector, and the output terminal of the first selector is used for outputting the regulating voltage.

5. The variable gain amplifier of claim 4 wherein the transistor circuit comprises a plurality of sub-transistor circuits coupled in parallel, the control circuit comprising a plurality of sub-control circuits, the plurality of sub-transistor circuits being coupled in one-to-one correspondence with the plurality of sub-control circuits;

And the regulating voltage generated by each sub-control circuit in the plurality of sub-control circuits is used for linearly regulating the resistance value of the sub-transistor circuit corresponding to the sub-control circuit.

6. A variable gain amplifier according to claim 1 or 2, wherein the transistor circuit comprises a sixth transistor, the first terminal of the sixth transistor and the second terminal of the sixth transistor being the two connection terminals of the transistor circuit, the gate of the sixth transistor being the gate of the transistor circuit.

7. The variable gain amplifier of claim 6 wherein the control circuit comprises a fourth current source, a second configurable resistor, a seventh transistor, a second comparator, and a second selector;

One end of the fourth current source is used for being coupled with the voltage source, and the other end of the fourth current source is coupled with the first end of the second configurable resistor and used for outputting the reference voltage; a second terminal of the second configurable resistor is coupled to the first terminal of the seventh transistor and the gate of the seventh transistor, the second terminal of the seventh transistor being coupled to the ground terminal;

A first input of the second comparator and a first input of the second selector are coupled to a first end of the second configurable resistor; the second input end of the second comparator and the second input end of the second selector are used for receiving the control voltage, the output end of the second comparator is coupled with the selection end of the second selector, and the output end of the second selector is used for outputting the regulating voltage.

8. The variable gain amplifier of any of claims 1-7 wherein the first and second transistors are NMOS transistors, the input of the first transistor and the input of the second transistor are drains, and the output of the first transistor and the output of the second transistor are sources;

9. A signal link circuit comprising an amplifier, and a variable gain amplifier coupled to the amplifier, the variable gain amplifier being the variable gain amplifier of any of claims 1-8.

10. The signal link circuit of claim 9, wherein the signal link circuit is one of a radio frequency circuit, an analog circuit, or a high frequency integrated circuit.

11. An electronic device comprising a transmitter and a receiver, the transmitter and the receiver each comprising a signal link circuit, the signal link circuit being the signal link circuit of claim 9 or claim 10.