CN118280983A - Method for forming semiconductor structure - Google Patents
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- CN118280983A CN118280983A CN202211732264.7A CN202211732264A CN118280983A CN 118280983 A CN118280983 A CN 118280983A CN 202211732264 A CN202211732264 A CN 202211732264A CN 118280983 A CN118280983 A CN 118280983A
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- 238000000034 method Methods 0.000 title claims abstract description 240
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 235000012431 wafers Nutrition 0.000 claims abstract description 84
- 238000010801 machine learning Methods 0.000 claims abstract description 63
- 238000012360 testing method Methods 0.000 claims abstract description 32
- 238000012549 training Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 57
- 239000012792 core layer Substances 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000003062 neural network model Methods 0.000 claims description 6
- 238000004886 process control Methods 0.000 claims description 6
- 238000013527 convolutional neural network Methods 0.000 claims description 3
- 230000000306 recurrent effect Effects 0.000 claims description 3
- 238000005259 measurement Methods 0.000 abstract description 8
- 238000001312 dry etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012545 processing Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
A method of forming a semiconductor structure, comprising: providing process data of a plurality of historical wafers, wherein the process data of the plurality of historical wafers comprises process data of a plurality of training wafers and process data of a plurality of test wafers, and the process data comprises process parameters of a first process and critical dimension parameters of a process structure formed by the first process; training and testing a machine learning system based on the process data of the historical wafer until the prediction accuracy of the machine learning system reaches a preset threshold; providing a wafer to be detected; inputting the process parameters of the first process in the wafer to be detected into a machine learning system, and outputting the critical dimension parameters of the process structure by the machine learning system. The process parameters of the first process in the wafer to be detected are input into the machine learning system, and the machine learning system outputs the critical dimension parameters of the process structure of the wafer to be detected, so that the measurement time of the critical dimension parameters of the process structure is reduced, and the process efficiency is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
Semiconductor integrated circuit chips are manufactured by mass processing, and a large number of various types of semiconductor devices are formed on the same substrate and are connected to each other to have complete electronic functions. The dimensional deviations generated in any one of the steps may cause failure of circuit fabrication. Therefore, in the manufacturing process, it is often necessary to measure the critical dimension parameters of the manufactured structure in each step of the process, and if a deviation between the measured dimension and the target dimension is found, the measured dimension and the target dimension are adjusted in the subsequent process to ensure that the critical dimension parameters of the finally formed semiconductor device structure conform to the preset dimension.
However, there are still problems associated with the prior art measurement of critical dimension parameters of devices.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which is used for reducing the measurement time of critical dimension parameters of a process structure and improving the process efficiency.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing process data of a plurality of historical wafers, wherein the process data of the historical wafers comprise process data of a plurality of training wafers and process data of a plurality of test wafers, and the process data comprise process parameters of a first process and critical dimension parameters of a process structure formed by the first process; inputting process parameters of a first process in a plurality of training wafers and critical dimension parameters of a process structure formed by the first process into a machine learning system for model training; after model training, inputting process parameters of a first process in a plurality of test wafers into the trained machine learning system, and outputting predicted critical dimension parameters of a process structure by the machine learning system; comparing the predicted critical dimension parameter of the process structure output by the machine learning system with the critical dimension parameter of the process structure in the test wafer until the prediction accuracy of the machine learning system reaches a preset threshold value, and completing the model test of the machine learning system; providing a wafer to be detected; inputting the technological parameters of the first process in the wafer to be detected into the machine learning system for completing the model test, and outputting the critical dimension parameters of the process structure of the wafer to be detected by the machine learning system.
Optionally, the wafer to be inspected includes: the device comprises a substrate, a layer to be etched, a mask layer, a second core layer and a first core layer, wherein the layer to be etched is positioned on the substrate, the mask layer is positioned on the layer to be etched, the second core layer is positioned on the mask layer, and the first core layer is positioned on the second core layer.
Optionally, before the first process is performed on the wafer to be inspected, the method further includes: a patterned layer is formed on the first core layer, the patterned layer exposing a portion of a top surface of the first core layer.
Optionally, the first process includes: and etching the first core layer until the top surface of the second core layer is exposed, so that the first core layer forms a first patterned structure.
Optionally, the process parameters of the first process include: one or more of etch temperature, etch pressure, etch gas flow, and etch bias power.
Optionally, the process structure includes: the first patterned structure; the critical dimension parameters of the process structure include: the width dimension of the first patterned structure is in a direction perpendicular to the side wall direction of the first patterned structure.
Optionally, after the machine learning system outputs the critical dimension parameter of the process structure of the wafer to be inspected, the method further includes: and acquiring a critical dimension parameter deviation according to the outputted critical dimension parameter.
Optionally, the method for obtaining the deviation of the critical dimension parameter according to the outputted critical dimension parameter includes: and comparing the outputted critical dimension parameter with a target critical dimension parameter to obtain the critical dimension parameter deviation.
Optionally, after obtaining the critical dimension parameter bias, the method further includes: and performing a second process on the wafer to be detected based on an advanced process control technology according to the critical dimension parameter deviation, so as to eliminate the critical dimension parameter deviation of the first process after the second process adjusts the process parameters.
Optionally, the second process includes: a first sidewall material layer is formed on the sidewalls and top surface of the first pattern structure and the top surface of the second core layer.
Optionally, after forming the first sidewall material layer, the method further includes: etching back the first side wall material layer until the top surface of the first patterned structure and the top surface of the second core layer are exposed, and forming a first side wall on the side wall of the first patterned structure; removing the first patterned structure, and etching the second core layer by taking the first side wall as a mask to form a plurality of second patterned structures; forming a second side wall on the side wall of the second graphical structure; removing the second patterned structure, and etching the mask layer by taking the second side wall as a mask to form a plurality of third patterned structures; and etching the layer to be etched by taking the third patterned structure as a mask to form a plurality of semiconductor structures.
Optionally, the method for forming the second side wall includes: forming a second side wall material layer on the side wall and the top surface of the second graph structure and the top surface of the mask layer; and etching the second side wall material layer until the top surface of the second patterned structure and the top surface of the mask layer are exposed, and forming the second side wall on the side wall of the second patterned structure.
Optionally, the semiconductor structure includes: fin structure.
Optionally, the ratio of the number of training wafers to the number of test wafers is 4:1.
Optionally, the machine learning system includes: a back propagation neural network model, a convolutional neural network model, or a recurrent neural network model.
Compared with the prior art, the technical scheme of the invention has the following advantages:
According to the method for forming the semiconductor structure, the machine learning system is trained and tested, after the prediction accuracy based on the machine learning system reaches the preset threshold, the process parameters of the first process in the wafer to be detected are input into the machine learning system for completing the model test, and the machine learning system outputs the critical dimension parameters of the process structure of the wafer to be detected, so that the critical dimension parameter measurement time of the process structure is effectively shortened, and the process efficiency is improved.
Further, after obtaining the critical dimension parameter bias, the method further comprises: and performing a second process on the wafer to be detected based on an advanced process control technology according to the critical dimension parameter deviation so as to eliminate the critical dimension parameter deviation after the second process. And adjusting the second process by the advanced process control technology, so as to compensate the deviation of critical dimension parameters brought by the first process, thereby ensuring the accuracy of subsequent graphical transmission and improving the production yield and reliability of the finally formed semiconductor structure.
Drawings
FIG. 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 2 to 10 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, there are still problems associated with the measurement of critical dimension parameters of devices in the prior art. The following will specifically explain.
With the rapid development of Ultra LARGE SCALE Integration (ULSI), the Integration of chips is higher and the size of the process structure is smaller, which takes longer time for measuring the size of the process structure, thereby affecting the process efficiency.
On the basis, the invention provides a method for forming a semiconductor structure, which comprises the steps of training and testing a machine learning system, inputting process parameters of a first process in a wafer to be detected into the machine learning system for completing model test after the prediction accuracy based on the machine learning system reaches a preset threshold, and outputting critical dimension parameters of the process structure of the wafer to be detected by the machine learning system, so that the critical dimension parameter measurement time of the process structure is effectively reduced, and the process efficiency is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention, including:
Step S101, providing process data of a plurality of historical wafers, wherein the process data of the historical wafers comprise process data of a plurality of training wafers and process data of a plurality of test wafers, and the process data comprise process parameters of a first process and critical dimension parameters of a process structure formed by the first process;
Step S102, inputting process parameters of a first process in a plurality of training wafers and critical dimension parameters of a process structure formed by the first process into a machine learning system for model training;
step S103, after model training, inputting the process parameters of the first process in a plurality of test wafers into the trained machine learning system, and outputting the predicted critical dimension parameters of the process structure by the machine learning system;
Step S104, comparing the predicted critical dimension parameter of the process structure output by the machine learning system with the critical dimension parameter of the process structure in the test wafer until the prediction accuracy of the machine learning system reaches a preset threshold value, and completing the model test of the machine learning system;
step S105, providing a wafer to be detected;
Step S106, inputting the process parameters of the first process in the wafer to be detected into the machine learning system for completing the model test, and outputting the critical dimension parameters of the process structure of the wafer to be detected by the machine learning system.
The following describes the steps of the method for de-embedding a transmission line in detail with reference to the accompanying drawings.
Fig. 2 to 10 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, process data of a plurality of history wafers is provided, wherein the process data of the plurality of history wafers includes process data of a plurality of training wafers 100 and process data of a plurality of test wafers 200, and the process data includes process parameters of a first process and critical dimension parameters of a process structure formed by the first process.
In this embodiment, the history wafer is a processed wafer, and the process data of the history wafer includes known process parameters in each process and critical dimension parameter data corresponding to the process structure.
In this embodiment, the ratio of the number of the training wafers 100 to the number of the test wafers 200 is 4:1. I.e., the training wafer 100 is 80% of the history wafer and the test wafer 200 is 20% of the history wafer.
With continued reference to fig. 2, the process parameters of the first process in the plurality of training wafers 100 and the critical dimension parameters of the process structure formed by the first process are input into a machine learning system for model training.
In this embodiment, in the model training stage, the process parameters of the first process and the critical dimension parameters of the corresponding process structure in the training wafer 100 are simultaneously input into the machine learning system, and the mapping relationship between the process parameters and the critical dimension parameters is automatically learned and established by the machine learning system.
In this embodiment, the machine learning system employs a convolutional neural network model.
In other embodiments, the machine learning system may also employ a back propagation neural network model or a recurrent neural network model.
With continued reference to fig. 2, after model training, the process parameters of the first process in the plurality of test wafers 200 are input into the trained machine learning system, and the machine learning system outputs predicted critical dimension parameters of the process structure.
Since it is necessary to verify whether the machine learning system can accurately predict after the model training stage is completed, by taking the process parameters of the first process in the plurality of test wafers 200 as the inputs of the machine learning system, the machine learning system predicts and outputs the mapping relationship established in the training stage, and compares the predicted critical dimension parameters of the output process structure of the machine learning system with the critical dimension parameters of the process structure in the test wafer 200 until the prediction accuracy of the machine learning system reaches the preset threshold value, thereby completing the model test of the machine learning system.
The model training stage and the model testing stage of the machine learning system are completed, and the machine learning system is subsequently applied to the actual process to replace the actual measurement of the critical dimension parameters of the process structure in the wafer to be tested.
Referring to fig. 3, a wafer 300 to be inspected is provided.
In this embodiment, the wafer 300 to be inspected includes: a substrate 301, a layer to be etched 302 on the substrate 301, a mask layer 303 on the layer to be etched 302, a second core layer 304 on the mask layer 303, and a first core layer 305 on the second core layer 304.
Referring to fig. 4, the process parameters of the first process in the wafer 300 to be inspected are input into the machine learning system for performing the model test, and the critical dimension parameters of the process structure of the wafer 300 to be inspected are output by the machine learning system.
In this embodiment, before the first process is performed on the wafer 300 to be inspected, the method further includes: a patterned layer (not shown) is formed over the first core layer 305, exposing a portion of the top surface of the first core layer 305.
In this embodiment, the first process includes: the first core layer 305 is etched until the top surface of the second core layer 304 is exposed, such that the first core layer 305 forms a first patterned structure 306.
In this embodiment, after the first process, the method further includes: and removing the patterned layer.
In this embodiment, the process parameters of the first process include: one or more of etch temperature, etch pressure, etch gas flow, and etch bias power.
In this embodiment, the process structure is the first patterned structure 306; the critical dimension parameter of the process structure is the width dimension d1 of the first patterned structure 306, and the direction of the width dimension d1 is perpendicular to the sidewall direction of the first patterned structure 306.
In this embodiment, after the prediction accuracy based on the machine learning system reaches the preset threshold, the process parameters of the first process in the wafer 300 to be detected are input into the machine learning system for completing the model test, and the machine learning system outputs the critical dimension parameters of the process structure of the wafer 300 to be detected, so that the measurement time of the critical dimension parameters of the process structure is effectively reduced, and the process efficiency is improved.
In this embodiment, after the machine learning system outputs the critical dimension parameters of the process structure of the wafer to be inspected, the method further includes: and acquiring a critical dimension parameter deviation according to the outputted critical dimension parameter.
In this embodiment, the method for obtaining the deviation of the critical dimension parameter according to the outputted critical dimension parameter includes: and comparing the outputted critical dimension parameter with a target critical dimension parameter to obtain the critical dimension parameter deviation delta d.
Referring to fig. 5, after the cd parameter deviation Δd is obtained, a second process is performed on the wafer 300 to be inspected based on an advanced process control technique according to the cd parameter deviation Δd, so as to eliminate the cd parameter deviation Δd after the second process.
In this embodiment, the second process includes: a first sidewall material layer 307 is formed on the sidewalls and top surface of the first pattern structure 306 and the top surface of the second core layer 304.
In this embodiment, the advanced process control technology adjusts the second process, so as to compensate the deviation Δd of the critical dimension parameter brought by the first process, thereby ensuring the accuracy of the subsequent patterned transfer and improving the production yield and reliability of the finally formed semiconductor structure.
Referring to fig. 6, after the first sidewall material layer 307 is formed, the first sidewall material layer 307 is etched back until the top surface of the first patterned structure 306 and the top surface of the second core layer 304 are exposed, and a first sidewall 308 is formed on the sidewall of the first patterned structure 306.
In this embodiment, the process of etching back the first sidewall material layer 307 uses a wet etching process.
In other embodiments, the process of etching back the first sidewall material layer may also use a dry etching process.
Referring to fig. 7, the first patterned structure 306 is removed, and the second core 304 is etched using the first sidewall 308 as a mask, so as to form a plurality of second patterned structures 309.
In this embodiment, the process of etching the second core layer 304 using the first sidewall 308 as a mask uses a wet etching process.
In other embodiments, the process of etching the second core layer with the first sidewall as a mask may also use a dry etching process.
With continued reference to fig. 7, in this embodiment, after forming the second patterned junction 309, the method further includes: the first sidewall 308 is removed.
Referring to fig. 8, a second sidewall 310 is formed on the sidewall of the second patterned structure 309.
In this embodiment, the method for forming the second sidewall 310 includes: forming a second sidewall material layer (not shown) on the sidewalls and top surface of the second pattern structure 309 and the top surface of the mask layer 303; and etching the second sidewall material layer back until the top surface of the second patterned structure 309 and the top surface of the mask layer 303 are exposed, and forming the second sidewall 310 on the sidewall of the second patterned structure 309.
In this embodiment, a wet etching process is used for etching back the second sidewall material layer.
In other embodiments, the process of etching back the second sidewall material layer may also use a dry etching process.
Referring to fig. 9, the second patterned structure 309 is removed, and the mask layer 303 is etched with the second sidewall 310 as a mask, so as to form a plurality of third patterned structures 311.
In this embodiment, the process of etching the mask layer 303 with the second sidewall 310 as a mask uses a wet etching process.
In other embodiments, the process of etching the mask layer by using the second sidewall as a mask may also use a dry etching process.
With continued reference to fig. 9, in this embodiment, after forming the third patterned junction 311, the method further includes: the second sidewall 310 is removed.
Referring to fig. 10, the third patterned structure 311 is used as a mask to etch the layer 302 to be etched to form a plurality of semiconductor structures 312
In this embodiment, the semiconductor structure 312 is a fin structure.
In this embodiment, the process of etching the layer to be etched 302 using the third patterned structure 311 as a mask uses a wet etching process.
In other embodiments, the process of etching the layer to be etched by using the third patterned structure as a mask may also use a dry etching process.
With continued reference to fig. 10, in this embodiment, after forming the semiconductor structure 312, the method further includes: the third patterned structure 311 is removed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
Providing process data of a plurality of historical wafers, wherein the process data of the historical wafers comprise process data of a plurality of training wafers and process data of a plurality of test wafers, and the process data comprise process parameters of a first process and critical dimension parameters of a process structure formed by the first process;
Inputting process parameters of a first process in a plurality of training wafers and critical dimension parameters of a process structure formed by the first process into a machine learning system for model training; after model training, inputting process parameters of a first process in a plurality of test wafers into the trained machine learning system, and outputting predicted critical dimension parameters of a process structure by the machine learning system;
comparing the predicted critical dimension parameter of the process structure output by the machine learning system with the critical dimension parameter of the process structure in the test wafer until the prediction accuracy of the machine learning system reaches a preset threshold value, and completing the model test of the machine learning system;
Providing a wafer to be detected;
Inputting the technological parameters of the first process in the wafer to be detected into the machine learning system for completing the model test, and outputting the critical dimension parameters of the process structure of the wafer to be detected by the machine learning system.
2. The method of forming a semiconductor structure of claim 1, wherein the wafer to be inspected comprises: the device comprises a substrate, a layer to be etched, a mask layer, a second core layer and a first core layer, wherein the layer to be etched is positioned on the substrate, the mask layer is positioned on the layer to be etched, the second core layer is positioned on the mask layer, and the first core layer is positioned on the second core layer.
3. The method of claim 2, further comprising, prior to performing the first process on the wafer to be inspected: a patterned layer is formed on the first core layer, the patterned layer exposing a portion of a top surface of the first core layer.
4. The method of forming a semiconductor structure of claim 3, wherein the first process comprises: and etching the first core layer until the top surface of the second core layer is exposed, so that the first core layer forms a first patterned structure.
5. The method of forming a semiconductor structure of claim 4, wherein the process parameters of the first process comprise: one or more of etch temperature, etch pressure, etch gas flow, and etch bias power.
6. The method of forming a semiconductor structure of claim 4, wherein the process structure comprises: the first patterned structure; the critical dimension parameters of the process structure include: the width dimension of the first patterned structure is in a direction perpendicular to the side wall direction of the first patterned structure.
7. The method of claim 4, wherein after outputting the critical dimension parameters of the process structure of the wafer to be inspected by the machine learning system, further comprising: and acquiring a critical dimension parameter deviation according to the outputted critical dimension parameter.
8. The method of forming a semiconductor structure of claim 7, wherein the method of deriving a cd parameter bias from the outputted cd parameter comprises: and comparing the outputted critical dimension parameter with a target critical dimension parameter to obtain the critical dimension parameter deviation.
9. The method of forming a semiconductor structure of claim 7, further comprising, after obtaining the critical dimension parameter bias: and performing a second process on the wafer to be detected based on an advanced process control technology according to the critical dimension parameter deviation, so as to eliminate the critical dimension parameter deviation of the first process after the second process adjusts the process parameters.
10. The method of forming a semiconductor structure of claim 9, wherein the second process comprises: a first sidewall material layer is formed on the sidewalls and top surface of the first pattern structure and the top surface of the second core layer.
11. The method of forming a semiconductor structure of claim 10, further comprising, after forming the first sidewall material layer: etching back the first side wall material layer until the top surface of the first patterned structure and the top surface of the second core layer are exposed, and forming a first side wall on the side wall of the first patterned structure; removing the first patterned structure, and etching the second core layer by taking the first side wall as a mask to form a plurality of second patterned structures; forming a second side wall on the side wall of the second graphical structure; removing the second patterned structure, and etching the mask layer by taking the second side wall as a mask to form a plurality of third patterned structures; and etching the layer to be etched by taking the third patterned structure as a mask to form a plurality of semiconductor structures.
12. The method for forming a semiconductor structure according to claim 11, wherein the method for forming a second sidewall comprises: forming a second side wall material layer on the side wall and the top surface of the second graph structure and the top surface of the mask layer; and etching the second side wall material layer until the top surface of the second patterned structure and the top surface of the mask layer are exposed, and forming the second side wall on the side wall of the second patterned structure.
13. The method of forming a semiconductor structure of claim 11, wherein the semiconductor structure comprises: fin structure.
14. The method of claim 1, wherein a ratio of the number of training wafers to the number of test wafers is 4:1.
15. The method of forming a semiconductor structure of claim 1, wherein the machine learning system comprises: a back propagation neural network model, a convolutional neural network model, or a recurrent neural network model.
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| CN202211732264.7A CN118280983A (en) | 2022-12-30 | 2022-12-30 | Method for forming semiconductor structure |
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| CN202211732264.7A CN118280983A (en) | 2022-12-30 | 2022-12-30 | Method for forming semiconductor structure |
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