CN118276985A - RISC-V chip starting method, equipment and medium - Google Patents
RISC-V chip starting method, equipment and medium Download PDFInfo
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Abstract
The invention discloses a RISC-V chip starting method, equipment and medium, which belongs to the RISC-V chip technical development field, and aims to solve the technical problems of avoiding the starting failure of a starting chip to the maximum extent and assisting a chip user to check the reasons of the starting failure and abnormality, and adopts the following technical scheme: after the RISC-V chip is electrified, a preset starting source is obtained, whether the starting source is effective or not is judged, program information stored on the starting source is checked, and a user program stored on the starting source is operated; the starting source comprises a chip ROM, a chip built-in eflash, an sd controller and a spiflash controller; and judging whether the chip ROM is started or not.
Description
Technical Field
The invention relates to the technical development field of RISC-V chips, in particular to a RISC-V chip starting method, a device and a medium.
Background
The chip starting is a complex process and mainly comprises the steps of determining a starting mode, initializing an internal module and a peripheral interface, judging whether bootloader operation needs to be executed or not and the like. Determining a starting mode: after the chip is powered up, the starting mode used is determined according to certain hardware states (such as states of certain pins). Devices supporting multiple boot modes need to sample these hardware states to determine the subsequent boot flow. Common boot modes include booting from main flash memory, booting from system memory, booting from embedded memory, and the like. These start modes can be realized by setting boot0 and boot1 pins. Initializing an internal module and a peripheral interface: after a specific starting mode is determined, the internal module and the peripheral interface required by the current starting mode are initialized by the program solidified in the on-chip ROM before the chip leaves the factory. These initialization operations include register clearing, setting a start-up mode, loading the values of the SP and PC registers, etc. Various problems may be encountered during the chip start-up process, such as start-up failure, incorrect firmware operation after start-up, difficult search of problems after start-up failure or operation abnormality, etc.
Therefore, how to avoid the start failure of the start chip to the maximum extent and help the chip user to check the reasons of the start failure and the abnormality is a technical problem to be solved in the prior art.
Disclosure of Invention
The technical task of the invention is to provide a RISC-V chip starting method, a device and a medium, which are used for solving the problems of avoiding the starting failure of the starting chip to the maximum extent and assisting a chip user in checking the reasons of the starting failure and abnormality.
The invention aims to realize the technical task in the following way, namely a RISC-V chip starting method, which is to acquire a preset starting source after the RISC-V chip is electrified, judge whether the starting source is effective or not, check the program information stored on the starting source and run the user program stored on the starting source; the starting source comprises a chip ROM, a chip built-in eflash, an sd controller and a spiflash controller; judging whether the chip ROM is started or not:
If the ROM is started, the chip runs a fixed program and waits for receiving serial port data; the fixed program is a program solidified into a chip ROM in the production process of the RISC-V chip and is used for completing the initialization work of the chip serial port, the timer, the spiflash and the sd controller;
If the starting source is not the ROM starting, verifying the starting source, and verifying the user program information and the user program content stored on the starting source; after passing the verification, running a user program stored on a starting source; the non-ROM starting source comprises a chip built-in eflash, an sd controller and a spiflash controller; the user program is a code written by a user and running on a RISC-V chip and having a setting function;
If the chip fails to start, the chip records invalid information to a built-in eflash backup area of the chip, the RISC-V chip jumps to a chip ROM, and a user checks the reason of the chip start failure through instructions.
Preferably, when the user program is packaged, reserving a plurality of bytes of user program information segments; the user program information comprises a hardware version number, a software version number, a code length and MD5;
The user program content comprises binary files and verification information which are compiled and generated by a user.
Preferably, after the fixed program is started, an upper computer instruction is received through a serial port, so that the selection of the burn-in sources of the built-in eflash controller, the sd controller and the spiglash controller of the chip is realized, the upper computer data is received, the program area erasing and burn-in work is completed, the upper computer instruction is received, and the starting error information stored in the built-in eflash backup area of the chip is sent to the upper computer.
Preferably, when the starting source is set to be non-ROM starting, after the RISC-V chip is powered on, signature information on the starting source is obtained, and whether the signature information is valid or not is judged:
if the signature information is valid, the starting source is valid, which means that the user program is started from the starting source, the user program information is obtained, and the user program code is checked:
If the verification is successful, the RISC-V chip normally starts the user program from the starting source;
if the verification fails, recording failure information to a built-in eflash backup area of the chip, resetting and jumping to a fixed program stored in the ROM by the RISC-V chip, and checking the reason of the starting failure by a user through an instruction;
If the signature information is invalid, the starting source is invalid, the chip records the invalid information to a built-in eflash backup area of the chip, the RISC-V chip resets and jumps to a fixed program of the ROM area, and a user checks the reason of the starting failure through instructions.
Preferably, the method for acquiring the start source signature information is specifically as follows:
for on-chip eflash read chip design, a eflash status register is reserved:
if the read-back status word is consistent with the written-in when designed, eflash operates normally;
if the read-back status word is inconsistent with the written-in when designed, eflash runs abnormally;
for the sd controller and the spiflash controller, when the sd controller and the spiflash controller are designed, the ID information of the sd controller or the spiflash controller is read:
if the reply ID information is not received, the starting source is considered invalid.
More preferably, the reading of the user program in the start source is specifically as follows:
Judging whether the software and hardware version numbers are consistent;
MD5 of all data of the code area is calculated according to the code length;
judging whether MD5 of all data of the code area is consistent with MD5 in the program information field:
if the codes are consistent, the user program codes are correct, and the operation is continued;
if not, terminating the operation of the user program.
Preferably, the core of the RISC-V chip employs a RISC-V instruction set for executing instructions, performing operations, and controlling the operation of the entire chip.
Preferably, the chip ROM is a memory, which is characterized in that once data is written, it can only be read, but cannot be modified or deleted, for storing a program or data that does not need to be changed frequently, i.e., storing a start-up program of the chip;
The built-in eflash of the chip is also called as embedded flash and is used for internal data cache or instruction storage of the chip;
The spiflash controller is used for controlling the read and write operations of the spiflash memory data;
The sd controller is used for managing and controlling communication and data transmission between the sd controller and the RISC-V chip, namely a bridge between the sd controller and the host, and ensures reliable transmission and storage of data.
An electronic device, comprising: a memory and at least one processor;
wherein the memory has a computer program stored thereon;
the at least one processor executes the computer program stored by the memory, causing the at least one processor to perform a RISC-V chip start-up method as described above.
A computer readable storage medium having stored therein a computer program executable by a processor to implement a RISC-V chip start-up method as described above.
The RISC-V chip starting method, the RISC-V chip starting equipment and the RISC-V chip medium have the following advantages:
the RISC-V chip of the invention supports a plurality of starting sources to start, and mainly comprises a chip ROM, a chip built-in eflash, a sd controller and a spilash controller. The risk of program start failure can be reduced to the greatest extent through verification of a start source and verification of a user application program, and a user can be assisted to find the reason of the program start failure through writing and reading of a start log, so that debugging of products is facilitated;
The invention can furthest reduce the occurrence of the starting failure problem, the ROM program can read the starting failure log information written in the external eflash backup area, and simultaneously assist the user to quickly locate the product problem, thereby improving the competitiveness of the product and the use experience of the user.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a RISC-V chip;
FIG. 2 is a block diagram of a RISC-V chip start-up process.
Detailed Description
The RISC-V chip starting method, apparatus and medium of the present invention are described in detail below with reference to the drawings and specific examples of the present invention.
Example 1: the embodiment provides a RISC-V chip starting method, which comprises the steps of acquiring a preset starting source after a RISC-V chip is electrified, judging whether the starting source is effective, checking program information stored on the starting source, and running a user program stored on the starting source; as shown in fig. 1, the starting source comprises a chip ROM, a chip built-in eflash, an sd controller and a spilash controller; judging whether the chip ROM is started or not:
If the ROM is started, the chip runs a fixed program and waits for receiving serial port data; the fixed program is a program solidified into a chip ROM in the production process of the RISC-V chip and is used for completing the initialization work of the chip serial port, the timer, the spiflash and the sd controller;
If the starting source is not the ROM starting, verifying the starting source, and verifying the user program information and the user program content stored on the starting source; after passing the verification, running a user program stored on a starting source; the non-ROM starting source comprises a chip built-in eflash, an sd controller and a spiflash controller; the user program is a code written by a user and running on a RISC-V chip and having a setting function;
If the chip fails to start, the chip records invalid information to a built-in eflash backup area of the chip, the RISC-V chip jumps to a chip ROM, and a user checks the reason of the chip start failure through instructions.
In this embodiment, when the user program is packaged, a plurality of bytes of user program information segments are reserved; the user program information comprises a hardware version number, a software version number, a code length and MD5;
The user program content comprises binary files and verification information which are compiled and generated by a user.
In this embodiment, after the fixed program is started, an instruction of the upper computer is received through the serial port, so as to select the burn-in source of the built-in eflash controller, the sd controller and the spilash controller of the chip, receive the data of the upper computer, complete the erasing and burn-in work of the program area, receive the instruction of the upper computer, and send the starting error information stored in the backup area of the built-in eflash of the chip to the upper computer.
In this embodiment, when the starting source is set to be non-ROM, after powering up the RISC-V chip, the signature information on the starting source is obtained, and whether the signature information is valid is determined:
if the signature information is valid, the starting source is valid, which means that the user program is started from the starting source, the user program information is obtained, and the user program code is checked:
If the verification is successful, the RISC-V chip normally starts the user program from the starting source;
if the verification fails, recording failure information to a built-in eflash backup area of the chip, resetting and jumping to a fixed program stored in the ROM by the RISC-V chip, and checking the reason of the starting failure by a user through an instruction;
If the signature information is invalid, the starting source is invalid, the chip records the invalid information to a built-in eflash backup area of the chip, the RISC-V chip resets and jumps to a fixed program of the ROM area, and a user checks the reason of the starting failure through instructions.
In this embodiment, the method for acquiring the start source signature information is specifically as follows:
for on-chip eflash read chip design, a eflash status register is reserved:
if the read-back status word is consistent with the written-in when designed, eflash operates normally;
if the read-back status word is inconsistent with the written-in when designed, eflash runs abnormally;
for the sd controller and the spiflash controller, when the sd controller and the spiflash controller are designed, the ID information of the sd controller or the spiflash controller is read:
if the reply ID information is not received, the starting source is considered invalid.
In this embodiment, the reading of the user program in the starting source is specifically as follows:
Judging whether the software and hardware version numbers are consistent;
MD5 of all data of the code area is calculated according to the code length;
judging whether MD5 of all data of the code area is consistent with MD5 in the program information field:
if the codes are consistent, the user program codes are correct, and the operation is continued;
if not, terminating the operation of the user program.
In this embodiment, the core of the RISC-V chip adopts a RISC-V instruction set, which is used for executing instructions, performing operations, and controlling the operation of the entire chip.
In this embodiment, the chip ROM is a memory, and is characterized in that once data is written, the data can only be read, but cannot be modified or deleted, so as to store a program or data which does not need to be changed frequently, i.e. store a start-up program of the chip;
The built-in eflash of the chip is also called as embedded flash and is used for internal data cache or instruction storage of the chip;
The spiflash controller is used for controlling the read and write operations of the spiflash memory data;
The sd controller is used for managing and controlling communication and data transmission between the sd controller and the RISC-V chip, namely a bridge between the sd controller and the host, and ensures reliable transmission and storage of data.
Example 2: as shown in fig. 2, the present embodiment provides a RISC-V chip starting method, which specifically includes the following steps:
S1, acquiring a preset starting source by a RISC-V chip, wherein the acquiring mode is realized by externally connecting a starting source pin to a reading chip, the starting source pin 00 is a chip built-in eflash, the starting source pin 01 is a chip ROM, the starting source pin 10 is an sd controller, and the starting source pin 11 is a spiflash controller;
s2, when the starting source pin is selected as a starting source pin 01, the ROM starts a fixed program and runs the program of the step S3;
S3, after the ROM fixed program is started, the program areas of the built-in eflash, spiflash controller and the sd controller can be erased and programmed by receiving the instruction of the upper computer, and the starting error information recorded in the built-in eflash backup area of the chip can also be read;
S4, when the starting source pin is selected as the starting source pin 00, the starting source pin 10 or the starting source pin 11, the RISC-V chip is designated to be started from a user program, and whether the starting source is normal needs to be further verified;
s5, after the RISC-V chip is started, starting source signature information is obtained from an address set by a starting source;
s6, verifying whether a starting source is valid:
If the starting source is a built-in chip eflash, when the chip design is read, a reserved built-in chip eflash state register is built, if the read-back state word value is 0xaa5555aa, the built-in chip eflash operates normally, otherwise, the built-in chip eflash operates abnormally;
If the starting source is the sd controller or the spiflash controller, when the corresponding sd controller or spiflash controller is designed, the ID information of the sd controller or spiflash controller is read: if the returned ID information is not received, the SPIFASH or the SD card is considered to be invalid, and the program cannot be started in the mode; under the condition that signature verification fails, writing failure information into a built-in eflash backup area of the chip, automatically jumping a chip program to a step S2, and running a fixed program of the ROM area;
S7, reading user program information stored in a starting source, wherein the first 64 bytes of a starting address of each starting source are information of a current user program by convention, and mainly comprise a hardware version number, a software version number, a code length and MD5;
s8, verifying whether a program is effective or not, specifically:
reading the hardware version number of the program, and if the hardware version number is inconsistent with the version number stored in the program, considering the program to be invalid;
reading a program software version number, and if the current program version number is smaller than the version number stored in the current program version number, considering the program to be invalid; and then calculating MD5 value of the user program area data, and comparing with MD5 in the program information to judge whether the MD5 value is consistent or not:
if the task programs are inconsistent, the task programs are invalid; the program verification is invalid, failure information is written into a built-in eflash backup area of the chip, the chip program automatically jumps to step S2, and a fixed program of the ROM area is operated;
s9, the user program is successfully verified, and the user program passing the security authentication continues to run.
Example 3: the embodiment also provides an electronic device, including: a memory and a processor;
wherein the memory stores computer-executable instructions;
The processor executes the computer-executable instructions stored by the memory, causing the processor to perform the RISC-V chip activation method in any of the embodiments of the present invention.
The processor may be a Central Processing Unit (CPU), but may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory may be used to store computer programs and/or modules, and the processor implements various functions of the electronic device by running or executing the computer programs and/or modules stored in the memory, and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the terminal, etc. The memory may also include high-speed random access memory, but may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, memory card only (SMC), secure Digital (SD) card, flash memory card, at least one disk storage period, flash memory device, or other volatile solid state memory device.
Example 4: the present embodiment also provides a computer-readable storage medium having stored therein a plurality of instructions to be loaded by a processor, to cause the processor to execute the RISC-V chip booting method according to any of the embodiments of the present invention. Specifically, a system or apparatus provided with a storage medium on which a software program code realizing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be caused to read out and execute the program code stored in the storage medium.
In this case, the program code itself read from the storage medium may realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code form part of the present invention.
Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-R, CD-RW, DVD-ROMs, DVD-RYM, DVD-RW, DVD+RW), magnetic tapes, nonvolatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer by a communication network.
Further, it should be apparent that the functions of any of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform part or all of the actual operations based on the instructions of the program code.
Further, it is understood that the program code read out by the storage medium is written into a memory provided in an expansion board inserted into a computer or into a memory provided in an expansion unit connected to the computer, and then a CPU or the like mounted on the expansion board or the expansion unit is caused to perform part and all of actual operations based on instructions of the program code, thereby realizing the functions of any of the above embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. The RISC-V chip starting method is characterized in that after the RISC-V chip is electrified, a preset starting source is obtained, whether the starting source is effective or not is judged, program information stored on the starting source is checked, and a user program stored on the starting source is operated; the starting source comprises a chip ROM, a chip built-in eflash, an sd controller and a spiflash controller; judging whether the chip ROM is started or not:
If the ROM is started, the chip runs a fixed program and waits for receiving serial port data; the fixed program is a program solidified into a chip ROM in the production process of the RISC-V chip and is used for completing the initialization work of the chip serial port, the timer, the spiflash and the sd controller;
If the starting source is not the ROM starting, verifying the starting source, and verifying the user program information and the user program content stored on the starting source; after passing the verification, running a user program stored on a starting source; the non-ROM starting source comprises a chip built-in eflash, an sd controller and a spiflash controller; the user program is a code written by a user and running on a RISC-V chip and having a setting function;
If the chip fails to start, the chip records invalid information to a built-in eflash backup area of the chip, the RISC-V chip jumps to a chip ROM, and a user checks the reason of the chip start failure through instructions.
2. The RISC-V chip starting method according to claim 1, wherein the user program reserves a user program information section of several bytes when the user program is packed; the user program information comprises a hardware version number, a software version number, a code length and MD5;
The user program content comprises binary files and verification information which are compiled and generated by a user.
3. The method for starting RISC-V chip according to claim 1, wherein after the fixed program is started, the instruction of the upper computer is received through the serial port, so as to realize the selection of the burn-in sources of the built-in eflash controller, the sd controller and the spilash controller of the chip, receive the data of the upper computer, complete the erasing and burn-in work of the program area, receive the instruction of the upper computer, and send the start-up error information stored in the backup area of the built-in eflash of the chip to the upper computer.
4. The method for starting up RISC-V chip according to claim 1, wherein when the starting source is set as non-ROM starting, after the RISC-V chip is powered up, the signature information on the starting source is obtained, and whether the signature information is valid is judged:
if the signature information is valid, the starting source is valid, which means that the user program is started from the starting source, the user program information is obtained, and the user program code is checked:
If the verification is successful, the RISC-V chip normally starts the user program from the starting source;
if the verification fails, recording failure information to a built-in eflash backup area of the chip, resetting and jumping to a fixed program stored in the ROM by the RISC-V chip, and checking the reason of the starting failure by a user through an instruction;
If the signature information is invalid, the starting source is invalid, the chip records the invalid information to a built-in eflash backup area of the chip, the RISC-V chip resets and jumps to a fixed program of the ROM area, and a user checks the reason of the starting failure through instructions.
5. The method for starting up RISC-V chip according to claim 1, wherein the method for acquiring the signature information of the starting source is as follows:
for on-chip eflash read chip design, a eflash status register is reserved:
if the read-back status word is consistent with the written-in when designed, eflash operates normally;
if the read-back status word is inconsistent with the written-in when designed, eflash runs abnormally;
for the sd controller and the spiflash controller, when the sd controller and the spiflash controller are designed, the ID information of the sd controller or the spiflash controller is read:
if the reply ID information is not received, the starting source is considered invalid.
6. The RISC-V chip starting method according to any one of claims 1-5, wherein the reading of the user program in the starting source is specifically as follows:
Judging whether the software and hardware version numbers are consistent;
MD5 of all data of the code area is calculated according to the code length;
judging whether MD5 of all data of the code area is consistent with MD5 in the program information field:
if the codes are consistent, the user program codes are correct, and the operation is continued;
if not, terminating the operation of the user program.
7. The method of claim 1, wherein the RISC-V chip core employs a RISC-V instruction set for executing instructions, performing operations, and controlling the operation of the entire chip.
8. The RISC-V chip starting method according to claim 1, wherein the chip ROM is a memory for storing a program or data which is not changed, i.e., storing a starting program of the chip;
the built-in eflash of the chip is used for internal data cache or instruction storage of the chip;
The spiflash controller is used for controlling the read and write operations of the spiflash memory data;
The sd controller is used for managing and controlling communication and data transmission between the sd controller and the RISC-V chip, namely a bridge between the sd controller and the host, and ensures reliable transmission and storage of data.
9. An electronic device, comprising: a memory and at least one processor;
wherein the memory has a computer program stored thereon;
The at least one processor executing the computer program stored by the memory causes the at least one processor to perform the RISC-V chip booting method as claimed in any one of claims 1 to 8.
10. A computer readable storage medium having stored therein a computer program executable by a processor to implement a RISC-V chip start-up method as claimed in any one of claims 1 to 8.
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