CN118264214A - Multi-gain stage circuit and related correction method - Google Patents
Multi-gain stage circuit and related correction method Download PDFInfo
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- CN118264214A CN118264214A CN202310145693.2A CN202310145693A CN118264214A CN 118264214 A CN118264214 A CN 118264214A CN 202310145693 A CN202310145693 A CN 202310145693A CN 118264214 A CN118264214 A CN 118264214A
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- H—ELECTRICITY
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- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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Abstract
The invention discloses a multi-gain stage circuit and a related correction method, wherein the multi-gain stage circuit is used for receiving an input signal to generate an output signal, and comprises a first gain stage and a second gain stage which are connected in series, a gain control circuit and a correction circuit, wherein the second gain stage generates the output signal. The gain control circuit controls the first gain stage to have a first gain value so that the output signal is regarded as the product of a gain value of the second gain stage and an offset voltage of the second gain stage; and the correction circuit calculates the offset voltage of the second gain stage according to the output signal, and corrects the second gain stage according to the calculated offset voltage of the second gain stage.
Description
Technical Field
The invention relates to offset voltage (offset voltage) correction for a multi-gain stage (multi-GAIN STAGE).
Background
In the current system with multiple gain stages, in order to correct the offset voltage of each gain stage, an additional path and a related control circuit are required to be designed for the system to obtain the output signal of each gain stage, so as to detect and correct the offset voltage of each gain stage. However, this approach increases the complexity and manufacturing cost of the system, and these additional paths may cause additional loading effects on the original multi-gain stage, affecting its performance.
Disclosure of Invention
Therefore, an objective of the present invention is to provide a multi-gain stage and a calibration method thereof, which can calculate an offset voltage of each gain stage by using an output signal of the multi-gain stage without setting an additional path to solve the problems in the prior art.
In one embodiment of the present invention, a multi-gain stage circuit is disclosed for receiving an input signal to generate an output signal, and the multi-gain stage circuit comprises a first gain stage and a second gain stage connected in series, a gain control circuit and a correction circuit, wherein the second gain stage generates the output signal. The gain control circuit controls the first gain stage to have a first gain value so that the output signal is regarded as the product of a gain value of the second gain stage and an offset voltage of the second gain stage; and the correction circuit calculates the offset voltage of the second gain stage according to the output signal, and corrects the second gain stage according to the calculated offset voltage of the second gain stage.
In one embodiment of the present invention, a multi-gain stage circuit is disclosed for receiving an input signal to generate an output signal, and the multi-gain stage circuit includes a first gain stage, a second gain stage, a third gain stage, a gain control circuit, and a correction circuit connected in series, wherein the first gain stage receives the input signal, and the third gain stage generates the output signal. The gain control circuit controls the second gain stage to have a first gain value, and the correction circuit receives the output signal to obtain a first mode; the gain control circuit controls the second gain stage to have a second gain value different from the first gain value, and the correction circuit receives the output signal to obtain a second equation; and the correction circuit calculates offset voltages of the first gain stage and the third gain stage according to the first equation and the second equation.
In one embodiment of the present invention, a calibration method of a multi-gain stage circuit is disclosed, wherein the multi-gain stage circuit is configured to receive an input signal to generate an output signal, the multi-gain stage circuit comprises a first gain stage and a second gain stage connected in series, and the second gain stage generates the output signal; the correction method comprises the following steps: controlling the first gain stage to have a first gain value so that the output signal is regarded as the product of a gain value of the second gain stage and an offset voltage of the second gain stage; and calculating the offset voltage of the second gain stage according to the output signal, and correcting the second gain stage according to the calculated offset voltage of the second gain stage.
Drawings
Fig. 1 is a schematic diagram of a multi-gain stage circuit according to an embodiment of the invention.
FIG. 2 is a flow chart of correcting the offset voltage of the gain stage shown in FIG. 1 according to an embodiment of the present invention.
FIG. 3 is a flow chart of correcting the offset voltage of the gain stage shown in FIG. 1 according to another embodiment of the present invention.
Fig. 4 is a schematic diagram of a multi-gain stage circuit according to an embodiment of the invention.
FIG. 5 is a flow chart of correcting the offset voltage of the gain stage shown in FIG. 4 according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a multi-gain stage circuit according to an embodiment of the invention.
FIG. 7 is a flow chart of correcting the offset voltage of the gain stage shown in FIG. 6 according to an embodiment of the present invention.
FIG. 8 is a flow chart of correcting the offset voltage of the gain stage shown in FIG. 6 according to another embodiment of the present invention.
Symbol description
100: Multi-gain stage circuit
110_1 To 110_3: gain stage
120: Gain control circuit
130: Correction circuit
200-210: Step (a)
300 To 312: step (a)
400: Multi-gain stage circuit
410_1 To 410_3: gain stage
420: Gain control circuit
430: Correction circuit
500-512: Step (a)
600: Multi-gain stage circuit
610_1,610_2: Gain stage
620: Gain control circuit
630: Correction circuit
700-706: Step (a)
800-808: Step (a)
A1, A2, A3: gain value
Vos1, vos2, vos3: offset voltage
X: input signal
Y: output signal
Vc1, vc2: control signal
Detailed Description
Fig. 1 is a schematic diagram of a multi-gain stage circuit 100 according to an embodiment of the invention. As shown in fig. 1, the multi-gain stage circuit 100 includes gain stages 110_1 to 110_3, a gain control circuit 120 and a correction circuit 130 connected in series. In the present embodiment, the multi-gain stage 100 is configured to receive an input signal X and generate an output signal Y. The multi-gain stage circuit 100 can be used in any circuit or electronic product requiring gain adjustment, such as an output stage of a communication chip. In the present embodiment, the gain stages 110_1 to 110_3 have gain values A1 to A3, respectively, wherein at least the gain values A1, A2 are adjustable gain values. In addition, any of the gain stages 110_1-110_3 may be a controllable gain amplifier (Programmable GAIN AMPLIFIER, PGA), a filter, a digital-to-analog converter, or any other suitable gain stage.
In the multi-gain stage circuit 100, the gain stages 110_1 to 110_3 have their own offset voltages (input offset voltages), for example, the gain stage 110_1 has an offset voltage Vos1, the gain stage 110_2 has an offset voltage Vos2, and the gain stage 110_3 has an offset voltage Vos3. The offset voltages Vos1 to Vos3 cause offset of the input signal X, and thus distortion of the output signal Y. For example, assuming that the input signal X is "0", the output voltage of the gain stage 110_1 is Vos1×a1, not the ideal "0", due to the offset voltage Vos1 of the gain stage 110_1. Therefore, the multi-gain stage circuit 100 needs to be corrected to eliminate the influence of the offset voltage on the output signal Y. In the present embodiment, the multi-gain stage circuit 100 calculates (directly) offset voltages Vos1 to Vos3 of the gain stages 110_1 to 110_3 by using the output signal Y through the gain control circuit 120 and the correction circuit 130, and generates correction signals for correcting the gain stages 110_1 to 110_3. Therefore, since no additional paths are required to separately obtain the output signals of the gain stages 110_1 and 110_2, the complexity and the manufacturing cost can be effectively reduced.
Specifically, please refer to the flow chart of the offset voltages Vos1 to Vos3 of the correction gain stages 110_1 to 110_3 shown in fig. 2. At step 200, the flow begins and the multi-gain stage circuit 100 is powered up and begins to operate. In step 202, the gain control circuit 120 generates a gain control signal Vc2 to control the gain stage 110_2 to have a low gain value. In one embodiment, the gain control circuit 120 controls the gain stage 110_2 to have the lowest gain value that can be adjusted. In step 204, the correction circuit 130 receives the output signal Y, calculates the offset voltage Vos3 of the gain stage 110_3 according to the output signal Y, and corrects the gain stage 110_3 according to the calculated offset voltage Vos 3.
In detail, the output signal Y can be expressed as follows in equation (1):
Y＝A3*(A2*(A1*(X+Vos1)+Vos2)+Vos3)…………………………………(1)；
Since the gain value A2 is a low gain value, the output signal Y in equation (1) can be regarded as (approximately) the product of the gain value A3 of the gain stage 110_3 and the offset voltage Vos3 of the gain stage 110_3 (i.e., (A3 x Vos 3)). Therefore, since the gain A3 is known, the correction circuit 130 can calculate the offset voltage Vos3 of the gain stage 110_3 according to the output signal Y. After calculating the offset voltage Vos3, the correction circuit 130 may generate a correction signal according to the calculated offset voltage Vos3 to correct the gain stage 110_3, thereby eliminating the offset voltage Vos3. Regarding correction of offset voltage, the correction circuit 130 may be implemented by changing the input resistance, the input bias current, the common mode voltage, or the supply voltage … … of the gain stage 110_3, etc. Since the correction of offset voltage is well known to those skilled in the art, and the correction details of offset voltage are not important to the present invention, the related matters are not described in detail herein.
In step 206, after the offset voltage correction is completed by the gain stage 110_3, the gain control circuit 120 generates a gain control signal Vc1 to control the gain stage 110_1 to have a low gain value. In one embodiment, the gain control circuit 120 controls the gain stage 110_1 to have the lowest gain value that can be adjusted. At this time, the gain control circuit 120 may generate the gain control signal Vc2 to control the gain stage 110_2 to have an arbitrary gain value. In step 208, the correction circuit 130 receives the output signal Y, calculates the offset voltage Vos2 of the gain stage 110_2 according to the output signal Y, and corrects the gain stage 110_2 according to the calculated offset voltage Vos2. In detail, referring to the above equation (1), since the gain value A1 is a low gain value and the offset voltage Vos3 is corrected to a very low value, the output signal Y in the equation (1) can be regarded as (approximately) the product of the gain value A3 of the gain stage 110_2, the gain value A2 of the gain stage 110_2 and the offset voltage Vos2 of the gain stage 110_2 (i.e., a3×a2×vos 2). Therefore, since the gain values A2 and A3 are known, the correction circuit 130 can calculate the value of the offset voltage Vos2 of the gain stage 110_2 according to the output signal Y. After calculating the offset voltage Vos2, the correction circuit 130 generates a correction signal according to the calculated offset voltage Vos2 to correct the gain stage 110_2, thereby eliminating the offset voltage Vos2.
In step 210, after the offset voltage correction of the gain stage 110_2 is completed, the correction circuit 130 receives the output signal Y, calculates the offset voltage Vos1 of the gain stage 110_1 according to the output signal Y, and corrects the gain stage 110_1 according to the calculated offset voltage Vos1. At this time, the gain control circuit 120 may generate the gain control signals Vc1, vc2 to control the gain stages 110_1, 110_2 to have any gain value. In detail, referring to the above equation (1), since the offset voltages Vos2 and Vos3 are already corrected to be very low values, the output signal Y in the equation (1) can be approximated to (a3×a2×a1+vos1). Therefore, since the gain values A1, A2, A3 and the input signal X are known, the correction circuit 130 can calculate the value of the offset voltage Vos1 of the gain stage 110_1 according to the output signal Y. After calculating the offset voltage Vos1, the correction circuit 130 generates a correction signal according to the calculated offset voltage Vos1 to correct the gain stage 110_1, thereby eliminating the offset voltage Vos1.
The embodiment of FIG. 2 may effectively correct the offset voltages Vos 1-Vos 3 for each of the gain stages 110_1-110_3. However, it is contemplated that in some cases the gain stage 110_1 or 110_2 may not be set to a lower gain value, such that the offset voltages Vos 1-Vos 3 may be computationally erroneous. Thus, FIG. 3 provides a flow chart of correcting the offset voltages Vos 1-Vos 3 of the gain stages 110_1-110_3 according to another embodiment of the present invention. At step 300, the flow begins and the multi-gain stage circuit 100 is powered up and begins to operate. In step 302, the gain control circuit 120 generates the gain control signal Vc2 to control the gain stage 110_2 to have a low gain value. In one embodiment, the gain control circuit 120 controls the gain stage 110_2 to have the lowest gain value that can be adjusted. In step 304, the correction circuit 130 receives the output signal Y, calculates the offset voltage Vos3 of the gain stage 110_3 according to the output signal Y, and corrects the gain stage 110_3 according to the calculated offset voltage Vos3. In detail, the output signal Y can be expressed as the above equation (1). Since the gain value A2 is a low gain value, the output signal Y in equation (1) can be regarded as (approximately) (A3 Vos 3). Therefore, since the gain A3 is known, the correction circuit 130 can calculate the offset voltage Vos3 of the gain stage 110_3 according to the output signal Y. After calculating the offset voltage Vos3, the correction circuit 130 may generate a correction signal according to the calculated offset voltage Vos3 to correct the gain stage 110_3, thereby eliminating the offset voltage Vos3.
In step 306, after the gain stage 110_3 completes the offset voltage correction, the gain control circuit 120 generates the gain control signal Vc1 to control the gain stage 110_1 to have a low gain value. In one embodiment, the gain control circuit 120 controls the gain stage 110_1 to have the lowest gain value that can be adjusted. At this time, the gain control circuit 120 generates the gain control signal Vc2 to control the gain stage 110_2 to have a high gain value. In one embodiment, the gain control circuit 120 controls the gain stage 110_2 to have the highest gain value that can be adjusted. In step 308, the correction circuit 130 receives the output signal Y, calculates the offset voltage Vos2 of the gain stage 110_2 according to the output signal Y, and corrects the gain stage 110_2 according to the calculated offset voltage Vos2. In detail, referring to the above equation (1), since the gain value A1 is a low gain value and the gain value A2 is a high gain value, even if the offset voltage Vos3 cannot have a very low value due to the correction error, the output signal Y in the equation (1) can still be regarded as (approximately) (a3×a2×vos 2). Therefore, since the gain values A2 and A3 are known, the correction circuit 130 can calculate the value of the offset voltage Vos2 of the gain stage 110_2 according to the output signal Y. After calculating the offset voltage Vos2, the correction circuit 130 generates a correction signal according to the calculated offset voltage Vos2 to correct the gain stage 110_2, thereby eliminating the offset voltage Vos2.
In step 310, after the gain stage 110_2 completes the offset voltage correction, the gain control circuit 120 generates gain control signals Vc1, vc2 to control the gain stages 110_1, 110_2 to have high gain values. In one embodiment, the gain control circuit 120 controls the gain stages 110_1 and 110_2 to have the highest gain value that can be adjusted. In step 312, the correction circuit 130 receives the output signal Y of the multi-gain stage circuit 100, calculates the offset voltage Vos1 of the gain stage 110_1 according to the output signal Y, and corrects the gain stage 110_1 according to the calculated offset voltage Vos1. In detail, referring to the above equation (1), since the gain values A1 and A2 are both high, even if the offset voltages Vos2 and Vos3 cannot have very low values due to the correction error, the output signal Y in the equation (1) can be regarded as (approximately) (a3×a2×a1×x+vos1)). Therefore, since the gain values A1, A2, A3 and the input signal X are known, the correction circuit 130 can calculate the value of the offset voltage Vos1 of the gain stage 110_1 according to the output signal Y. After calculating the offset voltage Vos1, the correction circuit 130 generates a correction signal according to the calculated offset voltage Vos1 to correct the gain stage 110_1, thereby eliminating the offset voltage Vos1.
Fig. 4 is a schematic diagram of a multi-gain stage circuit 400 according to an embodiment of the invention. As shown in fig. 4, the multi-gain stage circuit 400 includes gain stages 410_1-410_3, a gain control circuit 420 and a correction circuit 430 connected in series. In this embodiment, the multi-gain stage 400 is configured to receive an input signal X and generate an output signal Y. The multi-gain stage circuit 400 can be used in any circuit or electronic product requiring gain adjustment, such as an output stage of a communication chip. In this implementation, the gain stages 410_1-410_3 have gain values A1-A3, respectively, wherein at least the gain value A2 is an adjustable gain value. In addition, the gain stage 410_2 may be a passive filter (PASSIVE FILTER).
In the multi-gain stage circuit 400, the gain stages 410_1, 410_3 have their own offset voltages (input offset voltages), e.g., the gain stage 410_1 has an offset voltage Vos1 and the gain stage 410_3 has an offset voltage Vos3. These offset voltages may cause distortion of the output signal Y, so the multi-gain stage circuit 400 needs to be corrected to eliminate the influence of these offset voltages on the output signal Y. In addition, since the gain stage 410_2 is a passive device, the offset voltage is negligible. In the present embodiment, the multi-gain stage circuit 400 calculates (directly) offset voltages Vos1 and Vos3 of the gain stages 410_1 and 410_3 by using the output signal Y through the gain control circuit 420 and the correction circuit 430, and generates correction signals for correcting the gain stages 410_1 and 410_3.
Specifically, please refer to the flow chart of the offset voltages Vos1, vos3 for the corrections 410_1, 410_3 shown in fig. 5. At step 500, the flow begins and the multi-gain stage circuit 400 is powered up and begins to operate. In step 502, the gain control circuit 420 generates a gain control signal Vc to control the gain stage 410_2 to have a first gain value A2_1. In step 504, the correction circuit 430 receives the output signal Y of the multi-gain stage 400 to obtain a first equation (2) including offset voltages Vos1 and Vos3 as follows:
Y＝A3*(A2_1*(A1*(X+Vos1))+Vos3)………………………………(2)；
the gain values A1, A2_1, A3, the input signal X and the output signal Y are known.
In step 506, the gain control circuit 420 generates the gain control signal Vc to control the gain stage 410_2 to have a second gain value A2_2. In step 508, the calibration circuit 430 receives the output signal Y of the multi-gain stage 400 to obtain a second equation (3) including offset voltages Vos1 and Vos3 as follows:
Y＝A3*(A2_2*(A1*(X+Vos1))+Vos3)………………………………(3)；
the gain values A1, A2_2, A3, the input signal X and the output signal Y are known.
In step 510, since the first equation and the second equation have only two unknowns, i.e., the offset voltages Vos1 and Vos3, the correction circuit 430 can solve the simultaneous equations to calculate the offset voltages Vos1 and Vos3.
In step 512, after calculating the offset voltages Vos1 and Vos3, the correction circuit 430 can generate a correction signal according to the calculated offset voltages Vos1 and Vos3 to correct the gain stages 410_1 and 410_3, thereby eliminating the offset voltages Vos1 and Vos3.
Fig. 6 is a schematic diagram of a multi-gain stage circuit 600 according to an embodiment of the invention. As shown in fig. 6, the multi-gain stage circuit 600 includes gain stages 610_1 and 610_2, a gain control circuit 620 and a correction circuit 630 connected in series. In this embodiment, the multi-gain stage circuit 600 is configured to receive an input signal X and generate an output signal Y. The multi-gain stage circuit 600 may be used in any circuit or electronic product requiring gain adjustment, such as an output stage of a communication chip. In this implementation, the gain stages 610_1, 610_2 have gain values A1, A2, respectively, wherein at least the gain value A1 is an adjustable gain value.
In the multi-gain stage circuit 600, the gain stages 610_1, 610_2 have their own offset voltages (input offset voltages), e.g., the gain stage 610_1 has an offset voltage Vos1 and the gain stage 610_2 has an offset voltage Vos2. The offset voltages Vos1 and Vos2 cause the input signal X to be offset, and thus cause the output signal Y to be distorted. Therefore, the multi-gain stage circuit 600 needs to be corrected to eliminate the influence of the offset voltage on the output signal Y. In the present embodiment, the multi-gain stage circuit 600 calculates (directly) offset voltages Vos1 and Vos2 of the gain stages 610_1 and 610_2 by using the output signal Y through the gain control circuit 620 and the correction circuit 630, and generates correction signals for correcting the gain stages 610_1 and 610_2. Therefore, since no additional path is required to separately obtain the output signal of the gain stage 610_1, the complexity and the manufacturing cost can be effectively reduced.
Specifically, please refer to the flow chart of the offset voltages Vos1 and Vos2 of the correction gain stages 610_1 and 610_2 shown in fig. 7. At step 700, the flow begins and the multi-gain stage circuit 600 powers up and begins operating. In step 702, the gain control circuit 620 generates a gain control signal Vc1 to control the gain stage 610_1 to have a low gain value. In one embodiment, the gain control circuit 620 controls the gain stage 610_1 to have the lowest gain value that can be adjusted. In step 704, the correction circuit 630 receives the output signal Y, calculates the offset voltage Vos2 of the gain stage 610_2 according to the output signal Y, and corrects the gain stage 610_2 according to the calculated offset voltage Vos 2. In detail, the output signal Y can be expressed as follows in equation (4):
Y＝A2*(A1*(X+Vos1)+Vos2)………………………………………(4)；
Since the gain value A1 is a low gain value, the output signal Y in equation (4) can be regarded as (approximately) the product of the gain value A2 of the gain stage 610_2 and the offset voltage Vos2 of the gain stage 610_2 (i.e., (A2 x Vos 2)). Therefore, since the gain A2 is known, the correction circuit 630 can calculate the offset voltage Vos2 of the gain stage 610_2 according to the output signal Y. After calculating the offset voltage Vos2, the correction circuit 630 may generate a correction signal according to the calculated offset voltage Vos2 to correct the gain stage 610_2, thereby eliminating the offset voltage Vos2.
In step 706, after the offset voltage correction of the gain stage 610_2 is completed, the correction circuit 630 receives the output signal Y, calculates the offset voltage Vos1 of the gain stage 610_1 according to the output signal Y, and corrects the gain stage 610_1 according to the calculated offset voltage Vos1. At this time, the gain control circuit 620 may generate the gain control signal Vc1 to control the gain stage 610_1 to have an arbitrary gain value. In detail, referring to the above equation (4), since the offset voltage Vos2 is already corrected to a very low value, the output signal Y in the equation (4) may be approximately A2X (A1 x+vos1)). Therefore, since the gain values A1 and A2 and the input signal X are known, the correction circuit 630 can calculate the value of the offset voltage Vos1 of the gain stage 610_1 according to the output signal Y. After calculating the offset voltage Vos1, the correction circuit 630 generates a correction signal according to the calculated offset voltage Vos1 to correct the gain stage 610_1, thereby eliminating the offset voltage Vos1.
The embodiment of fig. 7 can effectively correct the offset voltages Vos1, vos2 of each gain stage 610_1, 610_2. However, it is contemplated that in some cases the gain stage 610_1 may not be set to a lower gain value, such that there is a computational error in the offset voltages Vos1, vos2. Thus, fig. 8 provides a flow chart of correcting the offset voltages Vos1, vos2 of the gain stages 610_1, 610_2 according to another embodiment of the present invention. At step 800, the flow begins and the multi-gain stage circuit 600 powers up and begins operating. In step 802, the gain control circuit 620 generates a gain control signal Vc1 to control the gain stage 610_1 to have a low gain value. In one embodiment, the gain control circuit 620 controls the gain stage 610_1 to have the lowest gain value that can be adjusted. In step 804, the correction circuit 630 receives the output signal Y, calculates the offset voltage Vos2 of the gain stage 610_2 according to the output signal Y, and corrects the gain stage 610_2 according to the calculated offset voltage Vos2. In detail, the output signal Y can be expressed as the above equation (4). Since the gain value A1 is a low gain value, the output signal Y in equation (4) can be regarded as (approximately) (A2 Vos 2). Therefore, since the gain A2 is known, the correction circuit 630 can calculate the offset voltage Vos2 of the gain stage 610_2 according to the output signal Y. After calculating the offset voltage Vos2, the correction circuit 630 may generate a correction signal according to the calculated offset voltage Vos2 to correct the gain stage 610_2, thereby eliminating the offset voltage Vos2.
In step 806, after the gain stage 610_2 completes the offset voltage correction, the gain control circuit 620 generates a gain control signal Vc1 to control the gain stage 610_1 to have a high gain value. In one embodiment, the gain control circuit 620 controls the gain stage 610_1 to have the highest gain value that can be adjusted. In step 808, the correction circuit 630 receives the output signal Y of the multi-gain stage circuit 600, calculates the offset voltage Vos1 of the gain stage 610_1 according to the output signal Y, and corrects the gain stage 610_1 according to the calculated offset voltage Vos1. In detail, referring to the above equation (4), since the gain value A1 is a high gain value, even if the offset voltage Vos2 cannot have a very low value due to the correction error, the output signal Y in the equation (4) can be regarded as (approximately) a2X (A1 x+vos1)). Therefore, since the gain values A1 and A2 and the input signal X are known, the correction circuit 630 can calculate the value of the offset voltage Vos1 of the gain stage 610_1 according to the output signal Y. After calculating the offset voltage Vos1, the correction circuit 630 generates a correction signal according to the calculated offset voltage Vos1 to correct the gain stage 610_1, thereby eliminating the offset voltage Vos1.
Briefly summarized, in the multi-gain stage circuit of the present invention, the offset voltage of each gain stage is calculated by setting the gain value of the gain stage and using the output signal of the multi-gain stage circuit, and a correction signal is generated for correcting each gain stage, so that the purpose of offset voltage correction can be achieved without setting an additional path, thereby effectively reducing complexity and manufacturing cost.
The foregoing description is only of the preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims should be construed to fall within the scope of the present invention.
Claims (10)
1. A multi-gain stage circuit for receiving an input signal to generate an output signal, the multi-gain stage circuit comprising:
A first gain stage and a second gain stage connected in series, wherein the second gain stage generates the output signal;
a gain control circuit; and
A correction circuit;
Wherein the gain control circuit controls the first gain stage to have a first gain value such that the output signal is regarded as a product of a gain value of the second gain stage and an offset voltage of the second gain stage; and the correction circuit calculates the offset voltage of the second gain stage according to the output signal, and corrects the second gain stage according to the calculated offset voltage of the second gain stage.
2. The multi-gain stage circuit of claim 1, wherein the first gain value is a minimum gain value of the first gain stage that can be adjusted.
3. The multi-gain stage circuit of claim 1, wherein the gain control circuit controls the first gain stage to have a highest gain value that can be adjusted after the correction circuit corrects the second gain stage, and the correction circuit calculates the offset voltage of the first gain stage according to the output signal, and corrects the first gain stage according to the calculated offset voltage of the first gain stage.
4. The multi-gain stage circuit of claim 1, wherein the multi-gain stage circuit comprises a third gain stage, the first gain stage and the second gain stage connected in series, the third gain stage receiving the input signal; and after the correction circuit corrects the second gain stage, the gain control circuit controls the third gain stage to have a second gain value so that the output signal is regarded as a product of the gain value of the second gain stage, a gain value of the first gain stage and an offset voltage of the first gain stage; and the correction circuit calculates the offset voltage of the first gain stage according to the output signal, and corrects the first gain stage according to the calculated offset voltage of the first gain stage.
5. The multi-gain stage circuit of claim 4, wherein after the correction circuit corrects the first gain stage, the correction circuit calculates an offset voltage of the third gain stage according to the output signal, and corrects the third gain stage according to the calculated offset voltage of the third gain stage.
6. The multi-gain stage circuit of claim 1, wherein the multi-gain stage circuit comprises a third gain stage, the first gain stage and the second gain stage connected in series, the third gain stage receiving the input signal; and after the correction circuit corrects the second gain stage, the gain control circuit controls the third gain stage to have a second gain value and controls the first gain stage to have a third gain value, so that the output signal is regarded as a product of the gain value of the second gain stage, the third gain value of the first gain stage and an offset voltage of the first gain stage; and the correction circuit calculates the offset voltage of the first gain stage according to the output signal, and corrects the first gain stage according to the calculated offset voltage of the first gain stage.
7. The multi-gain stage circuit of claim 6, wherein the second gain value is a lowest gain value of the third gain stage that can be adjusted or the third gain value is a highest gain value of the first gain stage that can be adjusted.
8. The multi-gain stage circuit of claim 6, wherein after the correction circuit corrects the first gain stage, the gain control circuit controls the third gain stage to have a fourth gain value and controls the first gain stage to have a fifth gain value, and the correction circuit calculates an offset voltage of the third gain stage according to the output signal and corrects the third gain stage according to the calculated offset voltage of the third gain stage.
9. A multi-gain stage circuit for receiving an input signal to generate an output signal, the multi-gain stage circuit comprising:
A first gain stage, a second gain stage and a third gain stage connected in series, wherein the first gain stage receives the input signal and the third gain stage generates the output signal;
a gain control circuit for controlling the second gain stage; and
A correction circuit;
The gain control circuit controls the second gain stage to have a first gain value, and the correction circuit receives the output signal to obtain a first mode; the gain control circuit controls the second gain stage to have a second gain value different from the first gain value, and the correction circuit receives the output signal to obtain a second equation; and the correction circuit calculates offset voltages of the first gain stage and the third gain stage according to the first equation and the second equation.
10. The calibration method of the multi-gain stage circuit is characterized in that the multi-gain stage circuit is used for receiving an input signal to generate an output signal, and comprises a first gain stage and a second gain stage which are connected in series, wherein the second gain stage generates the output signal; the correction method comprises the following steps:
Controlling the first gain stage to have a first gain value such that the output signal is regarded as a product of a gain value of the second gain stage and an offset voltage of the second gain stage; and
Calculating the offset voltage of the second gain stage according to the output signal, and correcting the second gain stage according to the calculated offset voltage of the second gain stage.
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|---|---|---|---|
| TW111150376 | 2022-12-28 | ||
| TW111150376A TWI819938B (en) | 2022-12-28 | 2022-12-28 | Multi-gain stage and associated calibration method |
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| CN202310145693.2A Pending CN118264214A (en) | 2022-12-28 | 2023-02-21 | Multi-gain stage circuit and related correction method |
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| Country | Link |
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| US (1) | US20240223173A1 (en) |
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| TW (1) | TWI819938B (en) |
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| US5451895A (en) * | 1993-10-22 | 1995-09-19 | Lumisys, Inc. | Wideband amplifier with logarithmic output characteristic |
| JP4492713B2 (en) * | 2008-02-21 | 2010-06-30 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
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2022
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2023
- 2023-02-21 CN CN202310145693.2A patent/CN118264214A/en active Pending
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| US20240223173A1 (en) | 2024-07-04 |
| TWI819938B (en) | 2023-10-21 |
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