CN118264084A

CN118264084A - Control circuit, power supply circuit system and control method thereof

Info

Publication number: CN118264084A
Application number: CN202211679915.0A
Authority: CN
Inventors: 云梦晗; 安文杰; 乔泽宇; 孙锋锋; 刘铭
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2024-06-28

Abstract

The invention provides a control circuit, a power supply circuit system and a control method, when the power supply circuit system is in a low-load state, the conduction time of a power switch circuit can be controlled to be adjustable in a corresponding switch period, so that the peak value of the conduction current of the power switch circuit can be adjusted, and therefore, in low-load application, the energy transmitted by the power switch circuit in each switch period can be improved.

Description

Control circuit, power supply circuit system and control method thereof

Technical Field

The present invention relates to the field of power control technologies, and in particular, to a control circuit, a power circuit system, and a control method.

Background

In low load applications of DC-DC power supply circuitry, the overall energy transfer efficiency may be significantly reduced due to static power consumption of the circuitry and the switching losses in the power stage circuitry.

Disclosure of Invention

The invention aims to provide a control circuit, a power supply circuit system and a control method, which can reduce loss and improve the overall energy transfer efficiency of the power supply circuit system.

To achieve the above object, the present invention provides a control circuit coupled to a power switching circuit of a power supply circuit system and controlling on and off of the power switching circuit so that the power supply circuit system converts an input voltage into an output voltage, wherein the control circuit comprises:

A constant on-time module for generating an on-time signal from the input voltage and the output voltage;

The conduction control module is coupled with the constant conduction time module and is used for generating a conduction control signal according to the conduction time signal and the conduction current of the power switch circuit;

The switch control module is coupled with the conduction control module and is used for controlling the switching of the conduction and the disconnection of the corresponding power switch in the power switch circuit according to the conduction control signal and the corresponding pulse width modulation signal;

When the power supply circuit system is in a low-load state, under the control of the conduction control signal, the switch control module controls the power switch circuit to be adjustable in conduction time in a corresponding switch period so as to adjust the peak value of the conduction current.

Optionally, when the power supply circuit system is in a low-load state, under the control of the on control signal, the switch control module controls the on time of the power switch circuit in a corresponding switch period to be prolonged so as to increase the peak value of the on current.

Optionally, the power switch circuit includes an upper power switch and a lower power switch, a source electrode of the upper power switch is coupled to the input voltage, a drain electrode of the upper power switch is coupled to a drain electrode of the lower power switch, and a source electrode of the lower power switch is grounded; in a switching period, when the upper power switch is turned on, the lower power switch is turned off, and when the power supply circuit system is in a low-load state, the switch control module controls the upper power switch to be turned on for a prolonged time in the corresponding switching period.

Optionally, the conduction control module includes:

the current detection module is used for detecting the conducting current and generating a sensing voltage which changes along with the conducting current;

The turnover adjusting module is coupled with the constant conduction time module and is used for outputting turnover voltage related to the difference value between the input voltage and the output voltage under the control of the conduction time signal;

the first comparator is coupled to the current detection module and the flip adjustment module and is used for comparing the magnitudes of the sensing voltage and the flip voltage to generate the conduction control signal.

Optionally, the flip adjustment module includes:

A first input voltage detection circuit for detecting the input voltage and generating a first current that varies with the input voltage;

an output voltage detection circuit for detecting the output voltage and generating a second current that varies with the output voltage;

The current mirror image superposition circuit is coupled with the first input voltage detection circuit and the output voltage detection circuit and is used for respectively mirroring the first current and the second current, and superposing the mirrored currents and outputting the superposed currents;

the grid electrode of the third switch is coupled with the conduction time signal, the source electrode of the third switch is coupled with the current mirror image superposition circuit, the drain electrode of the third switch is coupled with one end of the first capacitor, the other end of the first capacitor is grounded, and the first capacitor is charged and discharged according to the current output by the current mirror image superposition circuit after the third switch is conducted so as to provide the turnover voltage.

Optionally, the first input voltage detection circuit includes a first error amplifier, a first switch and a first resistor, a first input end of the first error amplifier is coupled to the input voltage, an output end of the first error amplifier is coupled to a gate of the first switch, a second input end of the first error amplifier is coupled to a source of the first switch and one end of the first resistor, another end of the first resistor is grounded, and a drain electrode of the first switch is coupled to the current mirror superposition circuit.

Optionally, the output voltage detection circuit includes a second error amplifier, a second switch and a second resistor, where a first input end of the second error amplifier is coupled to the output voltage, an output end of the second error amplifier is coupled to a gate of the second switch, a second input end of the second error amplifier is coupled to a source of the second switch and one end of the second resistor, another end of the second resistor is grounded, and a drain of the second switch is coupled to the current mirror superposition circuit.

Optionally, the current detection module includes:

the inductive current copying circuit is coupled with the switch control module and is used for being conducted when the power switch is conducted so as to output copied inductive current;

a first current mirror circuit coupled to the inductor current replica circuit and configured to mirror the replicated inductor current;

And a sense resistor coupled to the first current mirror circuit and configured to generate the sense voltage based on a current provided by the first current mirror circuit.

Optionally, the control circuit further includes a low load state signal generating module coupled to the current detecting module and the switch control module, for generating a low load state signal based on the sensing voltage and the corresponding first reference voltage, and the power supply circuit system is in the low load state when the low load state signal is valid.

Optionally, the low load state signal generating module includes an RC filter circuit and a second comparator, where an input end of the RC filter circuit is coupled to an output end of the current detecting module, an output end of the RC filter circuit is coupled to a first input end of the second comparator, a second input end of the second comparator is coupled to the first reference voltage, and an output end of the second comparator outputs the low load state signal.

Optionally, the switch control module includes a trigger module and a logic driving module, a first input end of the trigger module is coupled to an output end of the conduction control module, a second input end of the trigger module is coupled to the pulse width modulation signal, an output end of the trigger module is coupled to a gate of the upper power switch and the logic driving module, and the trigger module is used for generating a first driving signal for controlling the upper power switch to be turned on and off according to the conduction control signal and the corresponding pulse width modulation signal; the logic driving module is used for generating a second driving signal for controlling the on and off of the lower power switch according to the first driving signal.

Optionally, the constant on-time module includes:

A second input voltage detection circuit for detecting the input voltage and generating a detection current that varies with the input voltage;

A second current mirror circuit coupled to the second input voltage detection circuit for mirroring the detected current;

One end of the second capacitor is coupled with the second current mirror circuit, and the other end of the second capacitor is grounded and used for converting the mirror current output by the second current mirror circuit into corresponding voltage;

And one input end of the third comparator is coupled with the output voltage, the other input end of the third comparator is coupled with one end of the second capacitor and is used for comparing the output voltage with one end voltage of the second capacitor and outputting the on-time signal according to a comparison result.

Optionally, the second input voltage detection circuit includes a third error amplifier, a detection switch and a detection resistor, where a first input end of the third error amplifier is coupled to the input voltage, an output end of the third error amplifier is coupled to a gate of the detection switch, a second input end of the third error amplifier is coupled to a source of the detection switch and one end of the detection resistor, another end of the detection resistor is grounded, and a drain electrode of the detection switch is coupled to the second current mirror circuit.

Optionally, the control circuit further includes:

the zero-crossing detection module is coupled with the power switch circuit and the switch control module and is used for generating a zero-crossing detection signal according to the output of the power switch circuit so as to be provided for the switch control module;

And the input end of the feedback module is coupled with the output voltage, and the output end of the feedback module is coupled with the constant conduction time module and is used for sampling and feeding back the output voltage.

Based on the same inventive concept, the invention also provides a power supply system comprising a power switch circuit, an output circuit and a control circuit according to the invention.

Based on the same inventive concept, the invention also provides a control method of a power supply circuit system, wherein the power supply circuit system converts an input voltage into an output voltage by controlling the power switch circuit to be turned on and off, and the control method comprises the following steps:

When the power supply circuit system is in a low-load state, the conduction time of the power switch circuit is controlled to be adjustable in a corresponding switch period so as to adjust the peak value of the conduction current of the power switch circuit.

Optionally, when the power supply circuitry is operating in a low load state, the on-time of the power switching circuit is controlled to be prolonged within a corresponding switching period to increase the peak value of the on-current.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. When the power supply circuit system is in a low-load state, the conduction time of the power switch circuit can be controlled to be adjustable in a corresponding switch period, so that the peak value of the conduction current of the power switch circuit can be adjusted, and therefore, in low-load application, the energy transmitted by the power switch circuit in each switch period can be improved.

2. The peak value of the on current of the power switch circuit can be automatically adjusted according to different input voltages and output voltages, and the problem of overlarge output voltage ripple is avoided.

3. Can be used in parallel with the existing constant on-time control mode (i.e., the COT mode) as a complementary control of the power circuitry in the low load mode.

Drawings

Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

Fig. 1 is a schematic diagram of a buck DC-DC power supply circuit system employing a COT mode.

Fig. 2 is a schematic diagram of the operational timing of the buck DC-DC power supply circuitry shown in fig. 1.

Fig. 3 is a schematic diagram of a control circuit and a power circuit system thereof according to an embodiment of the invention.

Fig. 4 is a schematic diagram of an operation timing of the control circuit shown in fig. 3.

Fig. 5 is a schematic circuit diagram of a flip-flop adjustment module in the control circuit shown in fig. 3.

Fig. 6 is a schematic circuit diagram of a current detection module in the control circuit shown in fig. 3.

Fig. 7 is a schematic circuit configuration diagram of a constant on-time module in the control circuit shown in fig. 3.

Fig. 8 is a schematic diagram of a control circuit and a power circuit system thereof according to another embodiment of the present invention.

Fig. 9 is a specific example schematic diagram of a circuit configuration of a switch control module in the control circuit shown in fig. 8.

Fig. 10 is a circuit configuration diagram of a zero-crossing detection module in the control circuit shown in fig. 8.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Referring to fig. 1, a buck DC-DC circuit employing a Constant-on-time mode (COT) is basically configured by an upper power transistor HS, a lower power LS, an inductor L, an output capacitor C _out, a Constant-on-time module U1, and a switch control module U0. The constant on-time module generates an on-time signal TON according to the input voltage V _IN and the output voltage V _OUT, the switch control module U0 drives the upper power tube HS and the lower power tube LS to be alternately turned on and off according to the corresponding pulse modulation signal PWM and the on-time signal TON, closed-loop control of the output voltage V _OUT is achieved, and in the whole control process, the on-time T _on of the upper power tube HS and the on-time T-T _on of the lower power tube LS are respectively constant.

In low load applications, the DC-DC circuit enters a discontinuous current control mode (Discontinuous Conduction Mod, DCM) and prevents reverse current generation by supplying a corresponding zero-crossing current detection signal ZCD to the switch control module U0 to avoid increasing system losses. In DCM, please refer to fig. 1 and 2, the DC-DC circuit transfers energy from the input terminal of V _IN to the output terminal of V _OUT through the inductor L, and the switch control module U0 switches the upper power tube HS and the lower power tube LS once according to the corresponding pulse modulation signal PWM and the on-time signal TON in each period T.

The specific operation time sequence of the existing power supply circuit system is shown in the following table:

from the above operation sequence and the graph shown in fig. 2, the inductor current I _L in the existing DC-DC circuit always reaches 0, so that the triangular waveform of the inductor current I _L is generated, and the area enclosed by the triangular waveform of the peak value I _LPEAKK＝t_on*(V_IN-V_OUT)/L.I_L and the X axis can represent the energy transferred by the DC-DC circuit, and the larger the enclosed area is, the more energy is transferred.

In each period T, because of the switching process of the upper power tube HS and the lower power tube LS, the DC-DC circuit has switching loss, and the overall energy transfer efficiency is reduced.

Therefore, the invention provides a new technical scheme which can improve the energy transmitted by the DC-DC circuit in each switching period, so that more energy can be transmitted to the output end under the same switching loss as the prior art, the loss is reduced, and the energy transmission efficiency is improved.

The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Referring to fig. 3, an embodiment of the present invention provides a control circuit IC coupled to a power switch circuit U3 of a power circuit system and controlling on and off of the power switch circuit U3, so that the power circuit system converts an input voltage V _IN into an output voltage V _OUT required by a load.

The power supply circuit system may be a switching power supply circuit of any suitable architecture, for example, a buck type switching power supply circuit architecture, which includes the control circuit IC, the power switch circuit U3 and the output circuit U4 of the present invention. The power switch circuit U3 includes an upper power switch HS and a lower power switch LS, wherein a source electrode of the upper power switch HS is coupled to the input voltage V _IN, a drain electrode of the upper power switch HS is coupled to a drain electrode of the lower power switch LS, and a source electrode of the lower power switch LS is grounded. The output circuit U4 includes an inductance L and an output capacitance C _OUT. The connection node SW of the upper power switch HS and the lower power switch LS is coupled to one end of the inductor L, the other end of the inductor L is coupled to one end of the output capacitor C _OUT and provides the output voltage V _OUT to a corresponding load (not shown), and the other end of the output capacitor C _OUT is grounded.

In this embodiment, the control circuit IC includes a constant on-time module U0, an on-control module U2, and a switch control module U1. The constant on-time module U0 is configured to generate an on-time signal TON according to the input voltage V _IN and the output voltage V _OUT. The turn-on control module U2 is coupled to the constant turn-on time module U0, and is configured to generate a turn-on control signal cmp_out according to the turn-on time signal TON and the turn-on current I _L (i.e. the current flowing through the inductor L) of the power switch circuit U3. The switch control module U1 is coupled to the conduction control module U2, and is configured to control the switching of the upper power switch HS and the lower power switch LS in the power switch circuit U2 according to the conduction control signal cmp_out, the corresponding pulse width modulation signal PWM, the zero crossing detection signal ZCD, and the like.

In this embodiment, the on control module U2 includes a current detection module U21, a flip-flop adjustment module U22, and a first comparator CMP1. The current detection module U21 is coupled to the power switch circuit U3, and is configured to detect an on current I _L of the power switch circuit U3 and generate a sense voltage Vsense that varies with the on current I _L. The flip adjustment module U22 is coupled to the constant on-time module U0, and is configured to output a flip voltage Vthr related to a difference between the input voltage V _IN and the output voltage V _OUT under the control of the on-time signal TON output by the constant on-time module U0. The first comparator CMP1 is coupled to the current detecting module U21 and the inversion adjusting module U22, and is used for comparing the magnitudes of the sensing voltage Vsense and the inversion voltage Vthr to generate the turn-on control signal cmp_out.

In this embodiment, when the low_load received by the switch control module U1 is valid (for example, when the low_load is at a high level or equal to "1"), the power supply circuit system is in a LOW LOAD state, and at this time, under the control of the on control signal cmp_out, the switch control module U1 outputs the first driving signal GP to control the on and off of the upper power switch HS in the power switch circuit U3, and simultaneously outputs the second driving signal GN to control the on and off of the lower power switch LS in the power switch circuit U3, so as to control the on time of the power switch circuit U3 in a corresponding switching period to be adjustable, so as to adjust the peak value of the on current (i.e. the peak value I _LPEAK of the inductor current I _L). The on time of the power switch circuit U3 refers to the duration of the state in which the upper power switch HS is turned on and the lower power switch LS is turned off in one switching period, and the off time of the power switch circuit U3 refers to the duration of the state in which the upper power switch HS is turned off and the lower power switch LS is turned on in one switching period.

As an example, referring to fig. 3 and 4, in the present embodiment, when the power supply circuit system is in a low-load state, under the control of the on control signal cmp_out, the switch control module U1 controls the on time of the upper power switch HS to be prolonged in the corresponding switching period to increase the peak value of the on current I _L. Specifically, referring to fig. 4, the operation timing of the power supply circuit system of this example is shown in the following table:

As can be seen from the above-described operation sequence and the graph shown in fig. 4, in the power supply circuit system of the present example, the upper power switch HS is turned on from t=0 to t=t _triggering, turned off after cmp_out turns high, the on time of the upper power switch HS is prolonged to T _triggering in one switching period T, the turning voltage Vthr is continuously increased from t=0 to t=t _on, constant from t=t _on to t=t _{triggering n}, and the on current I _L is gradually increased from t=0 to t=t _triggering.

As can be seen from comparing the graphs shown in fig. 4 and fig. 2, in this example, the on time of the upper power switch HS in one switching period T is prolonged by T _triggering-t_on compared with the prior art, so that the peak value of the on current I _L in this example is increased to (1+n) ×i _LPEAK. In the prior art TON control shown in fig. 2, I _LPEAK is the peak value of the on current I _L generated by the upper power switch HS in the on time T _on of one switching period T. n is a constant greater than zero, different values of n can be selected for different V _OUT ripple tolerances, the greater the V _OUT ripple tolerance, the greater the value of n can be selected. Wherein, optionally, 0< n <1, e.g., n=0.5.

Obviously, in this example, the area surrounded by the triangular waveform of the on-current I _L and the X-axis is larger than that surrounded by the prior art shown in fig. 2, and therefore, the transmitted energy is increased.

That is, the technical solution of this embodiment may be used in parallel with the existing constant on-time control mode COT mode, and as supplementary control in the low load mode, in low load application, the on-time of the upper power switch in one switching period may be improved, the switching frequency and loss may be reduced, and the energy conversion efficiency of the circuit may be improved.

Moreover, since the flip voltage Vthr is related to the difference between the input voltage V _IN and the output voltage V _OUT, and the trigger of the cmp_out flip is related to the difference between the sense voltage Vsense and the flip voltage Vthr, the peak value of the on current I _L can be automatically adjusted according to different input voltage V _IN and output voltage V _OUT, so as to avoid the overlarge ripple of V _OUT.

It should be understood that each module in the control circuit IC of the present embodiment may be implemented by any suitable circuit design, as long as the circuit function of the module can be implemented, which is not particularly limited by the present invention.

As an example, referring to fig. 5, the flip-flop adjustment module U22 of the present embodiment includes a first input voltage detection circuit U221, an output voltage detection circuit U222, a current mirror superposition circuit U223, a third switch M3, and a first capacitor C1.

The first input voltage detection circuit U221 is configured to detect an input voltage V _IN and generate a first current I ₁ that varies with the input voltage V _IN. Optionally, the first input voltage detection circuit U221 includes a first error amplifier EA1, a first switch M1, and a first resistor R1, a first input terminal "+" of the first error amplifier EA1 is coupled to the input voltage V _IN, an output terminal of the first error amplifier EA1 is coupled to the gate of the first switch M1, a second input terminal "-" of the first error amplifier EA1 is coupled to the source of the first switch M1 and one end of the first resistor R1, the other end of the first resistor R1 is grounded, and a drain of the first switch M1 is coupled to the current mirror superposition circuit U223. When the first switch M1 is turned on, the first input voltage detection circuit U221 supplies a first current I ₁＝V_IN/R1 to the current mirror superimposing circuit U223.

The output voltage detection circuit U221 is configured to detect the output voltage V _OUT and generate a second current I ₂ that varies with the output voltage V _OUT. Optionally, the output voltage detection circuit U221 includes a second error amplifier EA2, a second switch M2, and a second resistor R2, wherein a first input terminal "+" of the second error amplifier EA2 is coupled to the output voltage V _OUT, an output terminal of the second error amplifier EA2 is coupled to a gate of the second switch M2, a second input terminal "-" of the second error amplifier EA2 is coupled to a source of the second switch M2 and one end of the second resistor R2, the other end of the second resistor R2 is grounded, and a drain of the second switch M2 is coupled to the current mirror superposition circuit U223. When the second switch M2 is turned on, the output voltage detection circuit U222 supplies the second current I ₂＝V_OUT/R2 to the current mirror superimposing circuit U223.

The current mirror superposition circuit U223 is coupled to the first input voltage detection circuit U221 and the output voltage detection circuit U221, and is grounded through the protection circuit U224. The output terminal of the current mirror superposition circuit U223 is coupled to the source of the third switch M3. The current mirror image superposition circuit U223 is configured to mirror the first current I ₁ and the second current I ₂, and output the mirrored currents to the source of the third switch M3 after superposition. Optionally, the current mirror superposition circuit U223 performs 1:1 mirroring on the first current I ₁ and the second current I ₂, and the superposition current output by the current mirror superposition circuit U223 is I ₁-I₂.

The gate of the third switch M3 is coupled to the constant on-time module U0 to be coupled to the on-time signal TON, the source of the third switch M3 is coupled to the current mirror superposition circuit U223, the drain of the third switch M3 is coupled to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, and the first capacitor C1 is charged and discharged according to the current superposition current I ₁-I₂ output by the current mirror superposition circuit U223 after the third switch M3 is turned on to provide the flipping voltage Vthr.

Wherein, R1 and R2 can be resistors with the same resistance value or resistors with different resistance values. When the values of R1 and R2 are both R and the capacitance value of C1 is C, vthr=t _ON*(V_IN-V_OUT)/RC, where t _ON is the fixed on time of the upper power switch HS in one switching cycle in the low load state during TON control in the prior art.

Optionally, the flip-flop adjusting module U22 of the present embodiment further includes a fourth switch M4, a drain of the fourth switch M4 is coupled to the connection node of the first capacitor C1 and the third switch M3, a source of the fourth switch M4 is grounded, and a gate of the fourth switch M4 is coupled to the constant on-time module U0 to be coupled to the on-time signal TON. The fourth switch M4 provides a discharge path of the first capacitor C1 when turned on, and discharges the first capacitor C1.

In this example, the first switch M1, the second switch M2, and the fourth switch M4 are all NMOS transistors, the third switch M3 is a PMOS transistor, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, at least one of the first switch M1, the second switch M2, and the fourth switch M4 may be replaced with a PMOS transistor, and the third switch M3 may be replaced with an NMOS transistor, at this time, in the above example, the source of the original NMOS transistor is replaced with the drain of the new PMOS transistor, the drain of the original NMOS transistor is replaced with the source of the new PMOS transistor, and the drain of the original PMOS transistor is replaced with the source of the new NMOS transistor. In other embodiments, the fourth switch M4 may also be replaced with any suitable controllable discharge element or controllable discharge circuit design.

As an example, referring to fig. 6, the current detection module U21 includes an inductor current replica circuit U210, a first current mirror circuit U211, and a sense resistor Rsense.

The inductor current replica circuit U210 is coupled to the switch control module U10 and is configured to be turned on when the upper power switch HS is turned on to output a replica inductor current I _{L_copy}. Optionally, the inductor current replica circuit U210 includes an upper replica switch Q1 and a lower replica switch Q2, wherein a gate of the upper replica switch Q1 is coupled to the switch control module U10 and is connected to the first driving signal GP, a source of the upper replica switch Q1 is coupled to the input voltage V _IN, a drain of the upper replica switch Q1 is coupled to a drain of the lower replica switch Q2, a source of the lower replica switch Q2 is coupled to the first current mirror circuit U211, and a gate of the lower replica switch Q2 is connected to the second bias voltage VBIAS2. The connection node CSW of the upper replica switch Q1 and the lower replica switch Q2 is a replica of the connection node SW of the upper power switch HS and the lower power switch LS, and when the first driving signal GP controls the upper power switch HS to be turned on and the second driving signal GN controls the lower power switch LS to be turned off, the first driving signal GP also controls the upper replica switch Q1 to be turned on, and the second bias voltage VBIAS2 controls the lower replica switch Q2 to be turned off. The inductor current replica circuit U210 can thereby replicate the on current I _L of the power switch circuit U3, and the replicated inductor current I _{L_copy＝}I_L output by the inductor current replica circuit U210.

The first current mirror circuit U211 is coupled to the inductor current replica circuit U210 and is configured to mirror the replicated inductor current I _{L_copy}. The first current mirror circuit U211 may be implemented using any suitable circuit design, which is not particularly limited by the present invention. Alternatively, the first current mirror circuit U211 may mirror the replicated inductor current I _{L_copy} by a 1:1 ratio.

The sense resistor Rsense is coupled to the first current mirror circuit U211 and is configured to generate the sense voltage Vsense based on a current (i.e., I _L) provided by the first current mirror circuit U211. Thus, vsense=i _L ×rsense.

Accordingly, the first comparator CMP1 compares the magnitudes of the sensing voltage Vsense and the inversion voltage Vthr, and then outputs the turn-on control signal cmp_out according to the comparison result.

In this embodiment, please refer to fig. 4 to 6, when vsense=i _L*Rsense,Vthr＝t_ON*(V_IN-V_OUT)/RC, the condition of cmp_out turning high is as follows: (1+n) I _LPEAK rstense=vthr, i.e. (1+n) rstense t _on(V_IN-V_OUT)/L＝t_on*(V_IN-V_OUT)/RC. That is, in the design of the control circuit IC of this embodiment, R, C and Rsense are selected to satisfy the relation: rc=l/[ (1+n) ×rsense ].

Referring to fig. 6, the control circuit IC of the present embodiment further includes a low-load status signal generating module U23 coupled to the current detecting module U21 and the switch control module U10. The LOW LOAD state signal generating module U23 is configured to generate a LOW LOAD state signal low_load based on the sense voltage Vsense and the corresponding first reference voltage VREF1, and when the LOW LOAD state signal low_load is valid, the power supply circuit system is in a LOW LOAD state.

The low load status signal generating module U23 may be implemented using any suitable circuit design, which is not particularly limited by the present invention. As an example, the LOW LOAD status signal generating module U23 includes an RC filter circuit U230 and a second comparator CMP2, wherein an input terminal of the RC filter circuit U230 is coupled to an output terminal of the current detecting module U21, an output terminal of the RC filter circuit U230 is coupled to a first input terminal "+" of the second comparator CMP2, a second input terminal "-" of the second comparator CMP2 is coupled to the first reference voltage VREF1, and an output terminal of the second comparator CMP2 outputs the LOW LOAD status signal low_load.

As an example, referring to fig. 7, the constant on-time module U0 includes a second input voltage detection circuit U01, a second current mirror circuit U00, a second capacitor C2, and a third comparator CMP3.

The second input voltage detection circuit U01 is configured to detect an input voltage V _IN and generate a detection current I that varies with the input voltage V _IN. Optionally, the second input voltage detection circuit U01 includes a third error amplifier EA3, a detection switch N1, and a detection resistor Rton, a first input terminal "+" of the third error amplifier EA3 is coupled to the input voltage V _IN, an output terminal of the third error amplifier EA3 is coupled to the gate of the detection switch N1, a second input terminal "-" of the third error amplifier EA3 is coupled to the source of the detection switch N1 and one end of the detection resistor Rton, the other end of the detection resistor Rton is grounded, and a drain of the detection switch N1 is coupled to the second current mirror circuit U00. When the detection switch N1 is turned on, the second input voltage detection circuit U01 supplies the detection current i=v _IN/Rton to the second current mirror circuit U00.

The second current mirror circuit U00 is coupled to the second input voltage detection circuit U01 for mirroring the detection current I. Alternatively, the second current mirror circuit U00 may mirror the detected current I by a 1:1 ratio.

One end of the second capacitor C2 is coupled to the second current mirror circuit U00, and the other end is grounded and used for converting the mirror current output by the second current mirror circuit U00 into a corresponding voltage. When the capacitance of C2 is Cton, in a switching period T, the upper power switch HS is turned on for a period T, and the voltage v=q/Cton =i/Cton =v _IN ×t/(Rton × Cton) at one end of the second capacitor C2.

The third comparator CMP3 has an input terminal coupled to the output voltage V _OUT, and another input terminal coupled to one terminal of the second capacitor C2, and is configured to compare the output voltage V _OUT with the voltage V _IN/(Rton × Cton) at one terminal of the second capacitor C2, and output the on-time signal TON according to the comparison result. As can be seen, the on time t= Rton × Cton ×v _OUT/V_IN of the upper power switch HS.

Optionally, the constant on-time module U0 further includes a discharge switch N0, a drain of the discharge switch N0 is coupled to one end of the second capacitor C2, and the other end is grounded, and a gate of the discharge switch N0 is coupled to the switch control module 1 to be connected to the second driving signal GN. The discharge switch N0 provides a discharge path to the second capacitor C2 when turned on.

As an example, referring to fig. 8, the switch control module U1 includes a trigger module U11 and a logic driving module U12, a first input end of the trigger module U11 is coupled to an output end of the turn-on control module U2, a second input end of the trigger module U12 is coupled to a pulse width modulation signal PWM, an output end of the trigger module U11 is coupled to a gate of the upper power switch HS and the logic driving module U12, the trigger module U11 is configured to generate a first driving signal GP according to the turn-on control signal TON and the corresponding pulse width modulation signal PWM, and the first driving signal GP is configured to control the upper power switch HS to be turned on and off. The logic driving module U12 is configured to generate a second driving signal GN according to the first driving signal GP, where the second driving signal GN is used to control the lower power switch LS to be turned on and off.

The trigger module U11 and the logic driving module U12 may be implemented by any suitable circuit design. For example, referring to fig. 9, the trigger module U11 includes a first OR logic gate OR1 AND a second OR logic gate OR2, the logic driving module U12 includes an inverter A0 AND an AND logic gate AND1, one input terminal of the first OR logic gate OR1 is connected to the PWM signal PWM, the other input terminal of the first OR logic gate OR1 is connected to the output terminal of the second OR logic gate OR2, one input terminal of the second OR logic gate OR2 is connected to the turn-on control module U2 to be connected to the turn-on control signal cmp_out, the other input terminal of the second OR logic gate OR2 is connected to the output terminal of the first OR logic gate OR1 AND the input terminal of the inverter A0, the output terminal of the inverter A0 is connected to one input terminal of the AND logic gate AND1, AND the other input terminal of the AND logic gate AND1 is connected to the zero crossing detection signal ZCD. The output of the first OR gate OR1 thus outputs the first drive signal GP AND the logic gate AND1 outputs the second drive signal GN.

Optionally, referring to fig. 10, the control circuit IC of the present embodiment further includes a zero-crossing detection module U6 and a feedback module U5.

The zero-crossing detection module U6 is coupled to the connection node SW of the upper power switch HS and the lower power switch LS of the power switch circuit U3, and further coupled to the logic driving module U12 of the switch control module U1, where the zero-crossing detection module U6 is configured to generate a zero-crossing detection signal ZCD according to the voltage of the connection node SW of the power switch circuit U3, and provide the zero-crossing detection signal ZCD to the logic driving module U12.

The feedback module U5 has an input terminal coupled to the output voltage V _OUT, and an output terminal coupled to the constant on-time module U0, and is configured to sample and feedback the output voltage V _OUT to generate a feedback voltage VFB that is a feedback output voltage V _OUT. The constant on-time module U0 further generates the TON signal according to the feedback voltage VFB.

It should be understood that the drawings of the present embodiment only show examples of circuit modules and circuit designs related to the core concept of the present invention, and do not indicate that the technical solution of the present invention is limited thereto. Those skilled in the art may reasonably add, delete and modify internal circuit blocks in the control circuit IC according to the prior art and product requirements, while reasonably replacing, modifying and deleting circuit design examples of one or several circuit blocks. For example, a pulse modulation module (not shown) is added to the control circuit IC to increase the required pulse modulation signal PWM.

Based on the same inventive concept, please refer to fig. 3 to 10, an embodiment of the present invention further provides a power supply system, which includes a power switch circuit U3, an output circuit U4, and a control circuit IC according to the present invention. The specific circuit designs of the power switch circuit U3, the output circuit U4 and the control circuit IC may be referred to above, and will not be described herein.

In summary, the control circuit and the power supply circuit system with the control circuit can control the on time of the power switch circuit to be adjustable in the corresponding switch period when the power supply circuit system is in a low-load state, so that the peak value of the on current of the power switch circuit can be adjusted, and therefore, in low-load application, the energy transmitted by the power switch circuit in each switch period can be improved. In addition, the control circuit and the power supply circuit system with the control circuit can automatically adjust the peak value of the on current of the power switch circuit according to different input voltages and output voltages, and the problem of overlarge output voltage ripple is avoided. And can be used in parallel with the existing constant on-time control mode (i.e., the COT mode) as a complementary control of the power circuitry in the low load mode.

Based on the same inventive concept, an embodiment of the present invention also provides a control method of a power supply circuit system, which may be implemented based on the control circuit IC of the present invention or a power supply circuit system having the control circuit IC of the present invention, or may be implemented based on any suitable control circuit IC or a power supply circuit system having the corresponding control circuit IC in the art.

Referring to fig. 3 to 10, taking the control method as an example based on the power supply circuit system of the present invention, the power supply circuit system converts the input voltage V _IN into the output voltage V _OUT by controlling the power switch circuit U3 to be turned on and off, and the control method includes controlling the on time of the power switch circuit U3 to be adjustable in a corresponding switching period when the power supply circuit system is in a low-load state, so as to adjust the peak value of the on current IL of the GIA power switch circuit.

The power switch circuit U3 includes an upper power switch HS and a lower power switch LS, a source of the upper power switch HS is coupled to the input voltage VIN, a drain of the upper power switch HS is coupled to a drain of the lower power switch LS, and a source of the lower power switch LS is grounded. The on time of the power switch circuit U3 refers to the duration of the state in which the upper power switch HS is turned on and the lower power switch LS is turned off in one switching period, and the off time of the power switch circuit U3 refers to the duration of the state in which the upper power switch HS is turned off and the lower power switch LS is turned on in one switching period.

Optionally, when the power supply circuitry is operating in a low load state, the on-time of the upper power switch HS in the power switch circuit U3 is controlled to be prolonged within the corresponding switching period to increase the peak value of the on-current IL.

Obviously, the control method of the power supply circuit system can control the conduction time of the power switch circuit to be adjustable in the corresponding switch period when the power supply circuit system is in a low-load state, so that the peak value of the conduction current of the power switch circuit can be adjusted, and therefore, in low-load application, the energy transmitted by the power switch circuit in each switch period can be improved.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.

Claims

1. A control circuit coupled to a power switching circuit of a power supply circuitry and controlling the turning on and off of the power switching circuit such that the power supply circuitry converts an input voltage to an output voltage, the control circuit comprising:

2. The control circuit of claim 1, wherein the switch control module controls the power switch circuit to extend a conduction time during a corresponding switching period under control of the conduction control signal to increase a peak value of the conduction current when the power supply circuitry is in a low load state.

3. The control circuit of claim 2, wherein the power switch circuit comprises an upper power switch and a lower power switch, a source of the upper power switch coupled to the input voltage, a drain of the upper power switch coupled to a drain of the lower power switch, a source of the lower power switch coupled to ground; in a switching period, when the upper power switch is turned on, the lower power switch is turned off, and when the power supply circuit system is in a low-load state, the switch control module controls the upper power switch to be turned on for a prolonged time in the corresponding switching period.

4. The control circuit of claim 1, wherein the turn-on control module comprises:

5. The control circuit of claim 4, wherein the rollover adjustment module comprises:

6. The control circuit of claim 5, wherein the first input voltage detection circuit comprises a first error amplifier, a first switch, and a first resistor, a first input terminal of the first error amplifier is coupled to the input voltage, an output terminal of the first error amplifier is coupled to a gate of the first switch, a second input terminal of the first error amplifier is coupled to a source of the first switch and one end of the first resistor, the other end of the first resistor is grounded, and a drain of the first switch is coupled to the current mirror superposition circuit.

7. The control circuit of claim 5, wherein the output voltage detection circuit comprises a second error amplifier, a second switch, and a second resistor, a first input terminal of the second error amplifier being coupled to the output voltage, an output terminal of the second error amplifier being coupled to a gate of the second switch, a second input terminal of the second error amplifier being coupled to a source of the second switch and one end of the second resistor, another end of the second resistor being grounded, and a drain of the second switch being coupled to the current mirror superposition circuit.

8. The control circuit of claim 4, wherein the current detection module comprises:

9. The control circuit of any of claims 4-8, further comprising a low load state signal generation module coupled to the current detection module and the switch control module for generating a low load state signal based on the sensed voltage and a corresponding first reference voltage, and wherein the power supply circuitry is in the low load state when the low load state signal is active.

10. The control circuit of claim 9, wherein the low load state signal generation module comprises an RC filter circuit and a second comparator, an input of the RC filter circuit coupled to an output of the current detection module, an output of the RC filter circuit coupled to a first input of the second comparator, a second input of the second comparator coupled to the first reference voltage, and an output of the second comparator outputting the low load state signal.

11. The control circuit of claim 3, wherein the switch control module comprises a trigger module and a logic driving module, a first input terminal of the trigger module is coupled to an output terminal of the turn-on control module, a second input terminal of the trigger module is coupled to the pulse width modulation signal, an output terminal of the trigger module is coupled to a gate of the upper power switch and the logic driving module, and the trigger module is configured to generate a first driving signal for controlling turn-on and turn-off of the upper power switch according to the turn-on control signal and the corresponding pulse width modulation signal; the logic driving module is used for generating a second driving signal for controlling the on and off of the lower power switch according to the first driving signal.

12. The control circuit of claim 1, wherein the constant on-time module comprises:

13. The control circuit of claim 12, wherein the second input voltage detection circuit comprises a third error amplifier, a detection switch, and a detection resistor, a first input terminal of the third error amplifier being coupled to the input voltage, an output terminal of the third error amplifier being coupled to a gate of the detection switch, a second input terminal of the third error amplifier being coupled to a source of the detection switch and one end of the detection resistor, the other end of the detection resistor being grounded, and a drain of the detection switch being coupled to the second current mirror circuit.

14. The control circuit of any one of claims 1-8 or 10-13, further comprising:

15. A power supply system comprising a power switching circuit, an output circuit and a control circuit as claimed in any one of claims 1 to 14.

16. A control method of a power supply circuit system that converts an input voltage into an output voltage by controlling on and off of a power switching circuit thereof, characterized by comprising:

17. The control method of claim 16, wherein when the power circuitry is operating in a low load state, controlling the on-time of the power switching circuit to extend within a corresponding switching period increases the peak value of the on-current.