CN118249807B - A wide range precision delay adjustment circuit - Google Patents
A wide range precision delay adjustment circuit Download PDFInfo
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- CN118249807B CN118249807B CN202410672639.8A CN202410672639A CN118249807B CN 118249807 B CN118249807 B CN 118249807B CN 202410672639 A CN202410672639 A CN 202410672639A CN 118249807 B CN118249807 B CN 118249807B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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Abstract
本发明公开了一种大范围精密延时调节电路，包括粗延时调节电路和细延时调节电路，粗延时调节电路由压控延时链实现，基本延时单元为单控制电压电流饥饿型压控延时单元；压控延时链的起点、终点及各个压控延时单元的中间位置均存在抽头，经过缓冲器后引出至多路选择器的输入端，通过控制多路选择器的码值来控制输出连接的抽头位置；粗延时调节电路的输出作为细延时调节电路的输入，通过无源数字时间转换器实现。上述电路基于粗延时、细延时调节两级结合的调节方式，能够在较小的硬件资源消耗前提下实现大范围的延时调节，同时兼顾了较高的调节精度。
The present invention discloses a large-range precision delay adjustment circuit, including a coarse delay adjustment circuit and a fine delay adjustment circuit. The coarse delay adjustment circuit is implemented by a voltage-controlled delay chain, and the basic delay unit is a single-control voltage and current hungry voltage-controlled delay unit; there are taps at the starting point, the end point and the middle position of each voltage-controlled delay unit of the voltage-controlled delay chain, which are led to the input end of the multiplexer after passing through a buffer, and the tap position of the output connection is controlled by controlling the code value of the multiplexer; the output of the coarse delay adjustment circuit is used as the input of the fine delay adjustment circuit, which is implemented by a passive digital time converter. The above circuit is based on a two-stage combination of coarse delay and fine delay adjustment, which can achieve a large range of delay adjustment under the premise of small hardware resource consumption, while taking into account high adjustment accuracy.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a large-range precise delay adjusting circuit.
Background
The large-scale precise delay adjustment technology plays a vital role in the high-precision synchronous clock distribution process, and for a high-precision clock distribution and synchronization system, the core task is to realize multi-node distribution of high-precision clock signals and realize synchronization of distribution clock phases. However, on the clock distribution path, due to the influence of factors such as cable transmission delay and temperature variation, synchronization of clock phases of master and slave nodes is difficult to achieve in a clock distribution system lacking a feedback mechanism. Therefore, if the loop delay of the clocks between the master node and the slave node in the distribution and feedback paths can be measured in the clock distribution process, and the phase difference value of the clocks between the master node and the slave node can be calculated by combining a proper delay distribution algorithm; and controlling a delay adjusting circuit according to the phase difference value of the master node clock and the slave node clock so as to gradually align and realize synchronization from the slave node clock to the master node clock.
In the existing high-precision synchronous clock distribution system, two main technical schemes are used for realizing precise delay adjustment: firstly, fine delay is realized through a programmable delay ASIC, and secondly, fine delay is realized through a phase interpolation module in the FPGA high-speed serial transceiver. However, the phase interpolation module of the FPGA is used for realizing fine delay adjustment, so that the performance requirement on the FPGA is higher, more resources are occupied, the cost is higher during batch use, and the precision delay adjustment circuit integrated in the ASIC is used, so that the batch cost is low, the integration level is high, and the trend of the front end chip formation of data processing is met. For the large-range precise delay adjusting circuit realized in the ASIC at present, a small enough delay step can be realized by constructing special delay units, but if the large adjusting range is realized by only increasing the number of the delay units, the delay step is unacceptable in terms of hardware resource consumption, so that the structure of the delay circuit needs to be researched, the resource consumption is realized as low as possible, and the requirements of large range and thin delay are met.
Disclosure of Invention
The invention aims to provide a large-range precise delay adjusting circuit, which is based on an adjusting mode of two-stage combination of coarse delay and fine delay adjustment, can realize large-range delay adjustment on the premise of smaller hardware resource consumption, and simultaneously has higher adjusting precision.
The invention aims at realizing the following technical scheme:
a large-scale precision delay adjustment circuit, the adjustment circuit comprising a coarse delay adjustment circuit and a fine delay adjustment circuit, wherein:
The coarse delay adjusting circuit is realized by a voltage-controlled delay chain, the basic delay units of the voltage-controlled delay chain are single control voltage and current starvation type voltage-controlled delay units, and each voltage-controlled delay unit is in an end-to-end connection structure;
The voltage-controlled delay chain, the phase discriminator PD1, the charge pump CP1 and the loop filter LF1 form a delay phase-locked loop circuit, the delay phase-locked loop circuit performs phase discrimination on a start point clock signal and an end point clock signal which are used as a coarse delay chain in the voltage-controlled delay chain, the charge pump CP1 and the loop filter LF1 are controlled to generate proper control voltage which is connected to a control voltage end of each voltage-controlled delay unit in the voltage-controlled delay chain, so that delay step sizes of the voltage-controlled delay units are consistent, and the total delay length of the voltage-controlled delay chain is equal to one clock cycle;
Taps are arranged at the starting point and the ending point of the voltage-controlled delay chain and the middle position of each voltage-controlled delay unit, the taps are led out to the input end of the multiplexer after passing through the buffer, and the tap positions connected with the output of the coarse delay adjusting circuit are controlled by controlling the code value sel_coarse of the multiplexer, so that the coarse delay amount is adjusted;
The output of the coarse delay adjusting circuit is used as the input of the fine delay adjusting circuit, the fine delay adjusting circuit is realized through a passive digital time converter DTC1, the passive digital time converter DTC1 adjusts the size of a capacitor mounted on the load end of the inverter through a digital control signal, and then the size of a discharging current of the load capacitor is controlled through adjusting a bias voltage, so that the delay value of the whole passive digital time converter DTC1 is controlled, and the output of the passive digital time converter DTC1 is the result after fine delay adjustment.
According to the technical scheme provided by the invention, the circuit can realize large-scale delay adjustment on the premise of smaller hardware resource consumption based on the two-stage combined adjustment mode of coarse delay and fine delay adjustment, and meanwhile, higher adjustment precision is considered.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a large-scale precise delay adjusting circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a coarse delay adjustment circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a passive digital-to-time converter according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a fine delay adjustment circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of simulation results of a coarse delay adjustment circuit according to an example of the present invention;
FIG. 6 is a schematic diagram of a fine tuning capacitor step simulation result of the fine delay circuit according to the example of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention, and this is not limiting to the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Fig. 1 is a schematic structural diagram of a large-range precise delay adjusting circuit according to an embodiment of the present invention, where the adjusting circuit includes a coarse delay adjusting circuit and a fine delay adjusting circuit, where:
the coarse delay adjusting circuit is realized by a voltage-controlled delay chain VCDL, the basic delay units of the voltage-controlled delay chain are single control voltage and current starvation type voltage-controlled delay units, and each voltage-controlled delay unit is in an end-to-end connection structure;
As shown in fig. 2, the coarse delay adjusting circuit according to the embodiment of the present invention is a schematic structural diagram, where the voltage-controlled delay chain, the phase discriminator PD1, the charge pump CP1 and the loop filter LF1 form a delay phase-locked loop DLL circuit, and the delay phase-locked loop circuit performs phase discrimination on a start clock signal and an end clock signal used as the coarse delay chain in the voltage-controlled delay chain, and controls the charge pump CP1 and the loop filter LF1 to generate a suitable control voltage to be connected to a control voltage end of each voltage-controlled delay unit in the voltage-controlled delay chain, so that delay steps of each voltage-controlled delay unit are consistent, and a total delay length of the voltage-controlled delay chain is equal to one clock period;
Taps are arranged at the starting point and the ending point of the voltage-controlled delay chain and the middle position of each voltage-controlled delay unit, the taps are led out to the input end of the multiplexer after passing through the buffer, and the tap positions connected with the output of the coarse delay adjusting circuit are controlled by controlling the code value sel_coarse of the multiplexer, so that the coarse delay amount is adjusted;
The output of the coarse delay adjusting circuit is used as the input of the fine delay adjusting circuit, the fine delay adjusting circuit is realized through a passive digital time Converter DTC1 (DIGITAL TIME Converter), the passive digital time Converter DTC1 adjusts the size of a capacitor mounted on the load end of the inverter through a digital control signal, and then the size of a discharging current of the load capacitor is controlled through adjusting a bias voltage, so that the delay value of the whole passive digital time Converter DTC1 is controlled, and the output of the passive digital time Converter DTC1 is the result after fine delay adjustment.
In a specific implementation, a fine delay control code sel_fine for controlling the fine delay adjustment quantity is connected to a selection end of the passive digital time converter DTC1 to select a required fine delay quantity, and the output of the passive digital time converter DTC1 is a result after fine delay adjustment, so that the precise delay adjustment of an input signal in a large range and high precision is finally completed.
Fig. 3 is a schematic structural diagram of a passive digital-to-time converter according to an embodiment of the present invention, wherein the passive digital-to-time converter DTC1 includes PMOS transistors MP1 and MP2, NMOS transistors MN1, MN2 and MN3, and a fine-tuning unit capacitor array, wherein:
the source electrode of the PMOS transistor MP1 is connected to the power supply voltage, and the grid electrode of the PMOS transistor MP1 is connected with the grid electrode of the NMOS transistor MN1 and is used as a clock input end;
the source electrode of the NMOS transistor MN1 is connected with the drain electrode of the NMOS transistor MN3, the grid electrode of the NMOS transistor MN3 is connected with the control voltage end, and the source electrode of the NMOS transistor MN3 is connected to the ground;
the drain electrode of the PMOS transistor MP1 is connected with the drain electrode of the NMOS transistor MN1 and is connected to the fine-adjustment unit capacitor array;
The source electrode of the PMOS transistor MP2 is connected to the power supply voltage, and the grid electrode of the PMOS transistor MP2 is connected with the grid electrode of the NMOS transistor MN2 and is connected to the fine-adjustment unit capacitor array;
the access quantity of the unit capacitors in the fine-adjustment unit capacitor array is controlled by a selection end;
The source of the NMOS transistor MN2 is connected to ground, and the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2 and serves as a clock output terminal.
Fig. 4 is a schematic structural diagram of a fine delay adjustment circuit according to an embodiment of the present invention, where the fine delay adjustment circuit includes a fine delay feedback circuit, and the fine delay feedback circuit includes two passive digital time converters DTC2 and DTC3, a phase detector PD2, a charge pump CP2, and a loop filter LF2, where:
the passive digital time converters DTC2 and DTC3 are the same three modules as the passive digital time converter DTC 1;
The clock input ends of the passive digital time converters DTC2 and DTC3 are respectively connected to the input end and the output end of the same voltage-controlled delay unit in the coarse delay adjusting circuit; the passive digital time converter DTC2 is controlled to mount all the unit capacitors in the unit capacitor load array into a delay circuit, and the unit delay capacitors in the passive digital time converter DTC3 are controlled to be used without mounting;
The clock outputs of the passive digital time converters DTC2 and DTC3 are respectively connected to the input end of the phase discriminator PD2, the output result of the phase discriminator PD2 is connected with the input end of the charge pump CP2, the output of the charge pump CP2 is connected with the input end of the loop filter LF2, and the output of the loop filter LF2 is used as control voltage and is connected with the control voltage ends of the passive digital time converters DTC1, DTC2 and DTC 3;
the selection end of the passive digital time converter DTC1 is led out to be used as the selection end for controlling the size of the fine delay amount, and the clock signal output by the clock output end of the passive digital time converter DTC1 is the output result processed by the coarse and fine two-stage delay architecture.
The fine delay feedback circuit is used for providing bias voltage for the passive digital time converter in the delay link, namely the DTC module, and the bias voltage provided by the fine delay feedback circuit enables the total delay time of the fine delay regulating circuit to be equal to the delay time of one voltage-controlled delay unit in the coarse delay regulating circuit.
The working process of the delay adjusting circuit according to the embodiment of the invention is described in detail below by a specific example, the example adjusts the high-precision delay within a period range according to the 125MHz clock signal, in the embodiment, 36 basic voltage-controlled delay units are connected end to form a voltage-controlled delay chain, two basic delay units are reserved on two sides respectively, so that the middle voltage-controlled delay unit has more similar load conditions.
The method comprises the steps of selecting a voltage-controlled delay chain formed by 32 voltage-controlled delay units in the middle, forming a delay phase-locked loop circuit by the voltage-controlled delay chain, a phase discriminator PD1, a charge pump CP1 and a loop filter LF1, connecting a tap VCDL2 of a2 nd basic voltage-controlled delay unit and a tap VCDL34 of a 34 th basic voltage-controlled delay unit to the input end of the phase discriminator PD1, regulating charge pump CP1 to charge and discharge the loop filter LF1 according to the phase difference of clock signals between the VCDL2 and the VCDL34 by the PD1, and gradually converging the output voltage of the loop filter LF1 to Vctrl1 as the control voltage of each basic delay unit in the voltage-controlled delay chain. At this time, the phase of the clock signal VCDL2 input by the phase discriminator PD1 is the same as the phase of the clock signal VCDL34, the delay interval from the tap VCDL2 to the tap VCDL34 is exactly equal to one clock cycle, and the delay amounts of the basic delay units are the same under the action of the same control voltage, so that the equipartition of the delay chain of one clock cycle is realized. A total of 33 taps from VCDL2 to VCDL34 are connected to the input terminal of the multiplexer through the buffer. The multiplexer is gated by 33-bit single thermal code sel_coarse [32:0], and the coarse delay adjusting circuit controls the magnitude of the adjustment quantity according to different connection tap positions.
The output of the coarse delay adjusting circuit is used as the input of the fine delay adjusting circuit, and the fine delay control is performed in the fine delay adjusting circuit. Referring to fig. 3, the fine delay adjusting circuit is implemented by a passive digital time converter DTC1, and the specific structure of the passive digital time converter DTC1 includes PMOS transistors MP1, MP2, NMOS transistors MN1, MN2, MN3 and a fine adjusting unit capacitor array, and the specific structure is as described in the above embodiments. For the fine-adjustment unit capacitor array, the unit capacitors coexist in 32 unit capacitors, 1 unit capacitor is accessed by a 1-bit single thermal code s0, and the accessing quantity of 31 capacitors is accessed by a 5-bit binary code sel_fine [4:0 ].
The fine delay adjustment circuit includes a passive digital time converter DTC1 and a fine delay feedback circuit, and referring to fig. 4, includes two passive digital time converters DTC2, DTC3, a phase detector PD2, a charge pump CP2, and LF2. Passive digital-to-time converters DTC2 and DTC3 are the same three modules as passive digital-to-time converter DTC 1. The clock input end of the passive digital time converter DTC2 is connected to the buffer output connected with the VCDL3 tap of the basic voltage-controlled delay unit in the coarse delay regulating circuit, and the selecting end controls the DTC2 to mount all unit capacitors in the fine regulating unit capacitor array into the delay circuit; the clock input end of the passive digital time converter DTC3 is connected to the buffer output connected with the VCDL4 tap of the basic voltage-controlled delay unit in the coarse delay adjusting circuit, and the selection end controls the unit delay capacitor in the DTC3 to be used without mounting.
The outputs Clkout and Clkout of the passive digital-to-time converter DTC2 and DTC3 are connected to the input of the phase detector PD2, respectively, and the PD2 adjusts the charge pump CP2 to charge and discharge the loop filter LF2 according to the phase difference of the clock signals between Clkout and Clkout, and the output voltage of the loop filter LF2 gradually converges to Vctrl2 as the control voltages of the three passive digital-to-time converters. At this time, the bias voltage provided by the fine delay feedback circuit makes the delay total time of the fine delay adjusting circuit equal to the delay time of one voltage-controlled delay unit in the coarse delay adjusting circuit.
Therefore, under the control voltage generated by the feedback circuit, the fine delay circuit realizes picosecond fine delay adjustment of the clock signal through the mounting quantity of unit capacitors in the gating DTC module by the fine delay control code sel_fine, and the output of the digital time converter is the result after the fine delay adjustment.
The simulation of the tt process angle is performed under the 180 nm CMOS process, the simulation result diagram of the coarse delay adjustment circuit of the example of the invention is shown in fig. 5, the step simulation result diagram of the fine delay adjustment capacitor of the example of the invention is shown in fig. 6, and reference is made to fig. 5-6: simulation results show that the maximum delay amount which can be provided by 32 basic voltage-controlled delay units in the coarse delay adjusting circuit is 7853.7 ps, and the delay step length of each basic delay unit is about 245.4 ps; the maximum delay amount that can be provided by using 31 fine adjustment unit capacitors in the fine delay adjustment circuit is 237.6 ps, and the adjustment step size is about 7.7ps.
Therefore, the large-range precise delay adjusting circuit provided by the embodiment of the invention can realize the delay coverage range of 8ns, the delay adjusting precision of about 7.7ps, and can realize large-range precise delay adjustment with less hardware resource occupation, and can be applied to a system needing delay adjustment of clock signal phase, such as a high-precision clock distribution system.
It is noted that what is not described in detail in the embodiments of the present invention belongs to the prior art known to those skilled in the art.
In summary, the circuit according to the embodiment of the invention has the following advantages:
1) According to the embodiment of the invention, the coarse delay adjusting circuit and the fine delay adjusting circuit are combined, the coarse delay adjusting circuit enlarges the delay adjusting range, the fine delay adjusting circuit improves the delay precision, and the circuit is suitable for clock signals and carries out picosecond fine delay adjustment in a period range;
2) According to the embodiment of the invention, the passive digital time converter is used for high-precision adjustment of fine delay, the maximum adjustment range of the fine delay adjusting circuit is equal to the adjustment step length of each coarse delay adjusting circuit through the scale of the delay amount of the pressure control delay unit in the coarse delay adjusting circuit, and the precision and coverage of delay adjustment in a period range are improved; meanwhile, the delay range is prevented from being enlarged by increasing the number of the fine delay adjusting units, and the hardware resource consumption in the implementation process is reduced.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.
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Citations (2)
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| JP2008072597A (en) * | 2006-09-15 | 2008-03-27 | Ricoh Co Ltd | Delay locked loop circuit |
| CN114567318A (en) * | 2022-02-21 | 2022-05-31 | 芯思原微电子有限公司 | Binary channels numerical control time delay chip |
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| EP0619653B1 (en) * | 1993-04-05 | 1998-12-23 | Koninklijke Philips Electronics N.V. | Digital phase-locked loop |
| JP3575430B2 (en) * | 2001-02-01 | 2004-10-13 | 日本電気株式会社 | Two-stage variable length delay circuit |
| KR100596428B1 (en) * | 2004-07-30 | 2006-07-06 | 주식회사 하이닉스반도체 | Digital delay locked loop with hierarchical delay control structure |
| US20080211590A1 (en) * | 2007-03-01 | 2008-09-04 | Stephen Wu | Method and system for a varactor-tuned voltage-controlled ring oscillator with frequency and amplitude calibration |
| CN104601166B (en) * | 2015-01-23 | 2017-08-25 | 北京大学 | It is a kind of that there is the delay locked loop circuit for starting control function |
| US10320401B2 (en) * | 2017-10-13 | 2019-06-11 | Xilinx, Inc. | Dual-path digital-to-time converter |
| CN117097330A (en) * | 2023-08-23 | 2023-11-21 | 重庆吉芯科技有限公司 | Delay self-calibration circuit, direct digital frequency synthesizer and delay self-calibration method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2008072597A (en) * | 2006-09-15 | 2008-03-27 | Ricoh Co Ltd | Delay locked loop circuit |
| CN114567318A (en) * | 2022-02-21 | 2022-05-31 | 芯思原微电子有限公司 | Binary channels numerical control time delay chip |
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