CN118246374B - Method and device for predicting voltage-temperature variation of parameters for chip design - Google Patents
Method and device for predicting voltage-temperature variation of parameters for chip design Download PDFInfo
- Publication number
- CN118246374B CN118246374B CN202410670487.8A CN202410670487A CN118246374B CN 118246374 B CN118246374 B CN 118246374B CN 202410670487 A CN202410670487 A CN 202410670487A CN 118246374 B CN118246374 B CN 118246374B
- Authority
- CN
- China
- Prior art keywords
- voltage
- temperature
- region
- function
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 133
- 238000013461 design Methods 0.000 title claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 78
- 238000000611 regression analysis Methods 0.000 claims abstract description 31
- 238000000638 solvent extraction Methods 0.000 claims abstract description 12
- 230000006870 function Effects 0.000 claims description 158
- 238000013507 mapping Methods 0.000 claims description 40
- 230000008859 change Effects 0.000 claims description 15
- 238000012417 linear regression Methods 0.000 claims description 13
- 238000004458 analytical method Methods 0.000 claims description 4
- 238000004590 computer program Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000004044 response Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010801 machine learning Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004422 calculation algorithm Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000000246 remedial effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a method and a device for predicting the variation of parameters of chip design along with voltage and temperature, wherein the method comprises the following steps: based on a voltage threshold of a target type, counting the number of liberty libraries under various process angles to obtain number information; when the number information is judged to be in accordance with a first rule under a target process angle: partitioning a coordinate plane formed by voltage and temperature based on working parameters of a chip to obtain a plurality of areas; based on the target process angle and the values in the liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a first prediction function of each region; and inputting the target voltage and the target temperature into a first prediction function of the region where the target voltage and the target temperature belong to, and obtaining a prediction result of the parameter. Delay and leakage current under various process, voltage and temperature conditions can be obtained quickly and efficiently.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a method and a device for predicting the change of parameters of chip design along with voltage and temperature.
Background
The Liberty library is a standard Electronic Design Automation (EDA) tool library used to describe timing and power consumption characteristics of digital Integrated Circuits (ICs). In the chip design process, engineers may use the models and data provided in the liberty library to evaluate and optimize key metrics such as performance, power consumption, and area of the chip.
The liberty library at present only provides a limited number of parameters such as voltage, temperature, delay and leakage current under process corner conditions, reK (re characterization) or SPICE (Simulation Program WITH INTEGRATED Circuit Emphasis) simulation if other parameters are needed. Delay and leakage current under various process, voltage and temperature conditions are high in cost, and the design period of the chip is prolonged.
Disclosure of Invention
The invention mainly aims to provide a prediction method, a prediction device, an intelligent terminal and a computer readable storage medium for the variation of parameters of chip design along with voltage and temperature, and aims to solve the problem that parameters under various process, voltage and temperature conditions cannot be obtained quickly and efficiently.
In order to achieve the above object, a first aspect of the present invention provides a method for predicting a variation of a parameter of chip design with voltage temperature, the method comprising:
Based on a voltage threshold of a target type, counting the number of liberty libraries under various process angles to obtain number information;
when the number information is judged to be in accordance with a first rule under a target process angle:
partitioning a coordinate plane formed by voltage and temperature based on working parameters of a chip to obtain a plurality of areas;
based on the target process angle and the values in the liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a first prediction function of each region;
and inputting the target voltage and the target temperature into a first prediction function of the region where the target voltage and the target temperature belong to, and obtaining a prediction result of the parameter.
Optionally, based on the target process angle and the values in the liberty library, performing nonlinear regression analysis on each region to obtain a first prediction function of each region, including:
based on the target process angle and the values in liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a regression function of each region;
And carrying out boundary stitching on the regression function to ensure that boundaries are continuous, and obtaining the first prediction function of each region.
Optionally, the stitching the boundaries of the regression function to make the boundaries continuous, to obtain the first prediction function of each region includes:
and based on the boundary of each region, performing boundary stitching on the regression function related to the boundary by adopting a sigmoid function and a Haidelded step function, so as to obtain the first prediction function of each region.
Optionally, the area is divided into a normal working area and a maximum operable area, the maximum operable area is located at the periphery of the normal working area, the border stitching is performed on the regression function related to the border by adopting a sigmoid function and a sea-voiedel step function based on the border of each area, so as to obtain the first prediction function of each area, including:
Stitching the regression function of each maximum operable area with the regression function of the normal working area by adopting a sigmoid function to obtain the first prediction function of each maximum operable area;
and stitching the regression function of the normal working area and the regression functions of all the maximum operable areas by adopting a sigmoid function and a Haidelder step function to obtain the first prediction function of the normal working area.
Optionally, based on the target process angle and the values in the liberty library, performing nonlinear regression analysis on each region to obtain a regression function of each region, including:
based on the target process angle, a plurality of voltage values, temperature values and parameter values are obtained from a liberty library;
Traversing each region, carrying out nonlinear mapping on the voltage value, the temperature value and the parameter value belonging to the current region to obtain a mapped voltage value, a mapped temperature value and a mapped parameter value, and obtaining a regression function of the current region by adopting linear regression according to all the mapped voltage value, the mapped temperature value and the mapped parameter value.
Optionally, the partitioning is performed on a coordinate plane formed by voltage and temperature based on the working parameters of the chip, to obtain a plurality of areas, including:
Constructing a voltage temperature plane by taking voltage as a horizontal axis and temperature as a vertical axis;
acquiring working parameters of a chip, wherein the working parameters comprise: standard power supply voltage, maximum operating voltage, minimum operating voltage, maximum operating temperature, minimum value of normal operating temperature, maximum value of normal operating temperature;
And dividing a transverse axis by adopting the minimum working voltage, the standard power supply voltage of the first preset proportion, the standard power supply voltage of the second preset proportion and the maximum working voltage, and dividing a longitudinal axis by adopting the minimum working temperature, the minimum value of the normal working temperature, the maximum value of the normal working temperature and the maximum working temperature to obtain a plurality of areas.
Optionally, the method further comprises:
and when the number information is judged to accord with a second rule, linear regression analysis is carried out based on liberty libraries to obtain a second prediction function, and a target process angle, a target voltage and a target temperature are input into the second prediction function to obtain a prediction result of the parameter.
A second aspect of the present invention provides a device for predicting a change in a parameter with voltage temperature for chip design, comprising:
the liberty library number module is used for counting the number of liberty libraries under various process angles based on the voltage threshold of the target type to obtain number information;
The rule judging module is used for judging whether the number information accords with a first rule under a target process angle;
The partitioning module is used for partitioning a coordinate plane formed by voltage and temperature based on working parameters of the chip to obtain a plurality of areas;
The regression analysis module is used for respectively carrying out nonlinear regression analysis on each region based on the target process angle and the values in the liberty library to obtain a first prediction function of each region;
And the prediction module is used for inputting the target voltage and the target temperature into a first prediction function of the region where the target voltage and the target temperature belong to, and obtaining a prediction result of the parameter.
The third aspect of the present invention provides an intelligent terminal, where the intelligent terminal includes a memory, a processor, and a prediction program for a parameter of a chip design that is stored in the memory and is capable of running on the processor and changes with voltage and temperature, and when the prediction program for a parameter of a chip design that changes with voltage and temperature is executed by the processor, the method for predicting a parameter of a chip design that changes with voltage and temperature is implemented.
A fourth aspect of the present invention provides a computer-readable storage medium, on which a program for predicting a change in a parameter for chip design with voltage and temperature is stored, which when executed by a processor, implements any one of the steps of the method for predicting a change in a parameter for chip design with voltage and temperature.
From the above, the first prediction function of each region is obtained by partitioning the voltage temperature plane and adopting nonlinear regression analysis fitting, and when the chip is designed, parameters such as delay, leakage current and the like can be obtained by calculating according to the first prediction function corresponding to the target voltage and the target temperature, and parameters under various process, voltage and temperature conditions can be obtained rapidly and efficiently.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for predicting the variation of parameters for chip design with voltage and temperature according to an embodiment of the present invention;
FIG. 2 is a schematic illustration of VT planar segmentation;
FIG. 3 is a flowchart illustrating a first prediction function obtaining process according to an embodiment of the present invention;
FIG. 4 is a schematic flow chart of border stitching according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a stitching principle reference of a sigmoid function;
FIG. 6 is a functional block diagram of a prediction apparatus for parameter variation with voltage and temperature for chip design according to an embodiment of the present invention;
fig. 7 is a schematic block diagram of an internal structure of an intelligent terminal according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted in context as "when …" or "once" or "in response to a determination" or "in response to detection. Similarly, the phrase "if a condition or event described is determined" or "if a condition or event described is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a condition or event described" or "in response to detection of a condition or event described".
The following description of the embodiments of the present invention will be made more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown, it being evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
Aiming at the problem of high cost of delay and leakage current under various process, voltage and temperature conditions, the invention overcomes the limitation that liberty library only provides values under discrete conditions, adopts a zoned nonlinear regression method to obtain a prediction function capable of predicting the trend of delay and leakage current along with the change of voltage and temperature, and flexibly applies a sigmoid function (hereinafter referred to as S function) and a Hai-Vise step function to stitch the prediction functions of different areas so as to ensure that boundaries are continuous. And then predicting delay and leakage current under various process angles, target voltage and target temperature conditions. The method can rapidly and efficiently predict parameters such as delay, leakage current and the like, can control the variation trend of delay and leakage current along with voltage temperature in the early stage of chip design, improves the reliability and manufacturability of the design, and becomes the basis of DTCO (Design Technology Co-optimization: collaborative design optimization).
The embodiment of the invention provides a prediction method for the variation of parameters of chip design along with voltage and temperature, which is operated on a computer terminal or a mobile terminal. Parameters include delay and leakage current, and delay under various conditions can be predicted, and leakage current under various conditions can be predicted.
As shown in fig. 1, the specific steps include:
Step S100: based on a voltage threshold of a target type, counting the number of liberty libraries under various process angles to obtain number information;
Chip delay and leakage current are generally affected by three factors: process, voltage, temperature, collectively referred to as PVT parameters. The current processes are divided into different Process corners, such as TT: TYPICAL N TYPICAL P (typical process corner), FF: FAST N FAST P (fast process corner), SS: slow N Slow P (Slow process corner), FS: fast N Slow P (Fast and Slow process corner), SF: slow N Fast P (Slow Process corner). Wherein N represents NMOS and P represents PMOS.
The types of Voltage Thresholds (VT) include: low Voltage Threshold (LVT), standard Voltage Threshold (SVT) and High Voltage Threshold (HVT).
Typically the liberty library will give a series of values or look-up tables for one VT, one process corner (burner) at different voltages V and temperatures T. The values at voltage temperature form a liberty library.
And under the limitation of a voltage threshold of a target type, counting the number of liberty libraries under various process angles to obtain number information. For example: the 40 nm standard cell library of TSMC, under LVT, there are 3 libraries of SS (different voltage temperatures), 1 library of TT, 3 libraries of FF; under SVT, there are 3 libraries of SS, 1 library of TT, 3 libraries of FF; under HVT, there are 3 libraries of SS, 1 library of TT, 3 libraries of FF.
If the liberty libraries are too small, no predictions can be made. For the voltage threshold of the target category, the following steps S200-S400 are performed when it is determined that the number information meets the first rule at the target process corner. The first rule of this embodiment is: at a certain VT, a certain process corner, liberty libraries of different voltages are greater than 2 and liberty libraries of different temperatures are greater than 2. If at a certain VT, a certain process angle, less than liberty libraries of two different voltages or less than liberty libraries of two different temperatures; or the three process angles (FF, TT and SS) are added up, and if the number of libraries with different voltages and different temperatures is less than 6, the judgment conditions are insufficient, and the prediction cannot be performed.
Step S200: partitioning a coordinate plane formed by voltage and temperature based on working parameters of a chip to obtain a plurality of areas;
Voltage temperature plane (Voltage-Temperature Plane) is commonly used to evaluate the performance and reliability of integrated circuits. The relation between delay and leakage current and voltage temperature is nonlinear, and in order to predict more accurately, the voltage temperature plane is partitioned, regression analysis is carried out on each region, and the prediction function of each region is determined. When predicting, the voltage and the temperature fall in different areas, and the prediction delay and the leakage current are calculated by adopting different prediction functions.
The specific process of dividing the area is as follows: and constructing a voltage temperature plane by taking voltage as a horizontal axis and temperature as a vertical axis. And then according to the working parameters of the chip, such as: the standard power supply voltage, the maximum working voltage, the minimum working voltage, the maximum working temperature, the minimum value of the normal working temperature and the maximum value of the normal working temperature are adopted to divide the transverse axis in sequence by adopting the minimum working voltage, the standard power supply voltage of a first preset proportion, the standard power supply voltage of a second preset proportion and the maximum working voltage, and the longitudinal axis is adopted to divide the longitudinal axis in sequence by adopting the minimum working temperature, the minimum value of the normal working temperature, the maximum value of the normal working temperature and the maximum working temperature, so that a plurality of areas are obtained.
Referring to fig. 2, the present embodiment divides the VT plane into ten regions. The rectangle in the center represents the normal operating region (region I); the rectangle at the periphery represents the maximum operable area (area II to area IX). Wherein the voltage is Vdd, the maximum operating voltage is maxVdd, the minimum operating voltage is minVdd, the standard supply voltage is VDDNOM, the first predetermined ratio of standard supply voltage is 90% VDDNOM, and the second predetermined ratio of standard supply voltage is 110% VDDNOM. The temperature is Temp, the minimum operating temperature is minTemp, typically-40 ℃, and the maximum operating temperature is maxTemp, typically 125 ℃; t1 is the minimum of normal operating temperature, typically 0 ℃; t2 is the highest value for normal operating temperature, typically 85 ℃.
The shaded portion is an inoperable region. If for a certain VT, a certain process angle, voltage V > maxVdd or voltage V < minVdd, temperature T >125 or temperature T < -40, then it is determined that the voltage, temperature is in zone X (non-operational area), no prediction is needed.
Step S300: based on the target process angle and the values in the liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a first prediction function of each region;
Nonlinear regression analysis refers to nonlinear fitting according to the existing values in liberty libraries to obtain a first prediction function of each region; then, the target voltage value and the target temperature value to be predicted can be input into a first prediction function of the area to which the target voltage value and the target temperature value belong, and a parameter prediction result is obtained.
Specifically, under a certain VT and a certain process angle, when delay is required to be predicted, nonlinear regression analysis is performed according to the existing voltage value, temperature value and delay value in liberty library, so as to obtain a delay function of each region; when the leakage current needs to be predicted, nonlinear regression analysis is carried out according to the existing voltage value, temperature value and leakage current value in liberty libraries, so as to obtain the leakage current function of each region. The delay function and the leakage current function are the generic names of the first prediction function in different scenes.
In this embodiment, as shown in fig. 3, the specific steps for obtaining the voltage threshold of the target class and the first prediction function of each region under the target process angle include:
Step S310: based on the target process angle and the values in liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a regression function of each region;
Firstly, under the voltage threshold value of a target type and a target process angle, when the parameter to be predicted is delay, acquiring a plurality of voltage values, temperature values and delay values from a liberty library; when the parameter to be predicted is leakage current, a plurality of voltage values, temperature values and leakage current values are obtained from liberty library. Then traversing each region, screening out voltage values, temperature values and delay values or leakage current values belonging to the current region, carrying out nonlinear mapping on all the values to obtain mapped voltage values, mapped temperature values, mapped delay values or mapped leakage current values (namely mapped parameter values), and then adopting linear regression according to all the mapped voltage values, mapped temperature values, mapped delay values or mapped leakage current values to obtain a regression function of the current region.
Specifically, the mapping method adopted when each region is non-linearly mapped is different. It is necessary to determine how to do the nonlinear mapping based on an empirical formula for each region.
The regression analysis implementation procedure for each region is described in detail below with reference to fig. 2, taking delay as an example:
For zone I, the empirical formula for delay is: d=d0 (V/V0)/((- α) (T/T0)/(β) e (- γ) (vth—vth 0)). Wherein D0 is a reference delay value, V is a voltage value, V0 is a reference voltage value, T is a temperature value, T0 is a reference temperature value, vth is a threshold voltage, the threshold voltage can be obtained from SPICE model, vth0 is a reference threshold voltage, and α, β, γ are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi1 = lnVi, xi2 = lnTi, yi = lnDi. Wherein Vi, ti and Di are the ith voltage value, the ith temperature value and the ith delay value in the liberty library. If liberty libraries have n separate libraries, then i=1, 2,3, …, n; the larger n is, the more reliable the regression analysis results are, and the better the predicted effect is. In the linear regression, sklearn of the Python library (scikit-learn: free open source machine learning library of Python) was used, and the regression function DI was obtained by calling lr.fit (X, Y) to realize the linear regression. The delay of the region I can be predicted after the regression analysis is successful, namely: DI (V, T) =exp (Y (X))=exp (lr. Prediction (X)). Where fit and predict are both functions of Sklearn, representing regression fits and predictions of the model.
Region II differs from region I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for the zone II delay is: d=k=e (Vth/(V-Vth)) (T/T0) ≡β, where V is a voltage value, T is a temperature value, T0 is a reference temperature value, vth is a threshold voltage, and k and β are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi 1=1/(Vi-Vth), xi 2= lnTi, yi= lnDi.
Region III differs from region I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for the III-region delay is: d=k=e (Vth/(V-Vth)) (T/T0)/(n), where V is a voltage value, T is a temperature value, T0 is a reference temperature value, vth is a threshold voltage, and k and n are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi 1=1/(Vi-Vth), xi 2= lnTi, yi= lnDi.
Zone IV differs from zone I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for the zone IV delay is: d=k (V/V0)/(α (- α) (T/T0)/(n), wherein V is a voltage value, V0 is a reference voltage value, T is a temperature value, T0 is a reference temperature value, and k, n, α are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi1 = lnVi, xi2 = lnTi, yi = lnDi.
The V region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for V-zone delay is: d=k1/(V-Vth) × (T/T0)/(n), where V is the voltage value, vth is the threshold voltage, T is the temperature value, T0 is the reference temperature value, and k, n are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi 1=ln (Vi-Vth), xi 2= lnTi, yi= lnDi.
Region VI differs from region I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for VI zone delay is: d=k1/(V-Vth) × (T/T0) ≡β, where V is the voltage value, vth is the threshold voltage, T is the temperature value, T0 is the reference temperature value, and k and β are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi 1=ln (Vi-Vth), xi 2= lnTi, yi= lnDi.
The VII region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for the VII region delay is: d=k1/(V-Vth) ×e (α (T-T0)), where V is a voltage value, vth is a threshold voltage, T is a temperature value, T0 is a reference temperature value, and k and α are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi 1=ln (Vi-Vth), xi 2= lnTi, yi= lnDi.
The VIII region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for the VIII zone delay is: d=k (V/V0)/((- α) ×e (α) (T-T0)), where V is a voltage value, V0 is a reference voltage value, T is a temperature value, T0 is a reference temperature value, and k and α are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi1 = lnVi, xi2 = Ti, yi = lnDi.
The IX region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula for the IX zone delay is: d=k×e (Vth/(V-Vth))×e (α×0)), where V is a voltage value, vth is a threshold voltage value, T is a temperature value, T0 is a reference temperature value, and k and α are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi 1=1/(Vi-Vth), xi 2=ti, yi= lnDi.
The following describes in detail the implementation procedure of regression analysis for each region with reference to fig. 2, taking leakage current as an example:
For region I, the empirical formula for leakage current is: i=i0×e (V/Vth) × (T/T0) ×2×e (δvth/Vth). Wherein I0 is a reference leakage current value, V is a voltage value, vth is a threshold voltage value, T is a temperature value, T0 is a reference temperature value, and δvth may be approximated as a constant. Determining the nonlinear mapping according to an empirical formula is: xi1 = Vi, xi2 = lnTi, yi = lnIi. Wherein Vi, ti and Ii are the ith voltage value, the ith temperature value and the ith leakage current value in the liberty library. In the case of linear regression, sklearn of the Python library (scikit-learn: free open source machine learning library of Python) was used, and linear regression was achieved by calling lr.fit (X, Y). After the regression analysis is successful, the leakage current of the region I can be predicted, and a regression function I_I can be obtained. I_i (V, T) =exp (Y (X))=exp (lr. Prediction (X)). Where fit and predict are both functions of Sklearn, representing regression fits and predictions of the model.
Region II differs from region I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0×e (V/Vth) ×2 (T/T0), where V is a voltage value, T is a temperature value, T0 is a reference temperature value, vth is a threshold voltage, and I0 is a reference leakage current value. Determining the nonlinear mapping according to an empirical formula is: xi1 = Vi, xi2 = lnTi, yi = lnIi.
Region III differs from region I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0×e (V/Vth) ×e (-Ea/kT), where V is a voltage value, T is a temperature value, I0 is a reference leakage current value, vth is a threshold voltage, ea is an activation energy, and k is an adjustable parameter. Determining the nonlinear mapping according to an empirical formula is: xi1 = Vi, xi2 = 1/Ti, yi = lnIi.
Zone IV differs from zone I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0×e (V/Vth) ×e (-Ea/kT), where V is a voltage value, I0 is a reference leakage current value, T is a temperature value, vth is a threshold voltage, ea is an activation energy, and k is an adjustable parameter. Determining the nonlinear mapping according to an empirical formula is: xi1 = Vi, xi2 = 1/Ti, yi = lnIi.
The V region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0 (V/V0)/(n) e (-Ea/kT), where V is a voltage value, T is a temperature value, V0 is a reference voltage value, I0 is a reference leakage current value, ea is an activation energy, and k and n are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi1 = lnVi, xi2 = 1/Ti, yi = lnIi.
Region VI differs from region I only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0 (V/V0)/(n) (T/T0)/(2), wherein V is a voltage value, I0 is a reference leakage current value, V0 is a reference voltage value, T is a temperature value, T0 is a reference temperature value, and n is an adjustable parameter. Determining the nonlinear mapping according to an empirical formula is: xi1 = lnVi, xi2 = lnTi, yi = lnIi.
The VII region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0 (V/V0)/(n x e) (α (T-T0)), where V is a voltage value, V0 is a reference voltage value, T is a temperature value, T0 is a reference temperature value, I0 is a reference leakage current value, and n and α are adjustable parameters. Determining the nonlinear mapping according to an empirical formula is: xi1 = lnVi, xi2 = Ti, yi = lnIi.
The VIII region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0×e (V/Vth) ×e (α×α -T0)), where V is a voltage value, vth is a threshold voltage, T is a temperature value, T0 is a reference temperature value, I0 is a reference leakage current value, and α is an adjustable parameter. Determining the nonlinear mapping according to an empirical formula is: xi1 = Vi, xi2 = Ti, yi = lnIi.
The IX region differs from the I region only in the empirical formula and the nonlinear mapping method. Specifically, the empirical formula of leakage current is: i=i0×e (V/Vth) ×e (α×α -T0)), where V is a voltage value, vth is a threshold voltage value, T is a temperature value, T0 is a reference temperature value, I0 is a reference leakage current value, and α is an adjustable parameter. Determining the nonlinear mapping according to an empirical formula is: xi1 = Vi, xi2 = Ti, yi = lnIi.
In the embodiment, a logarithmic method is adopted when the Xi1, the Xi2 and the Yi are subjected to nonlinear mapping, so that the nonlinear relation can be converted into linear solution, and then a linear regression method can be adopted for fitting.
Step S320: the regression function is edge stitched to make the edges continuous, and a first prediction function of each region is obtained.
The resulting regression functions are also zoned, as a result of the zoned regression analysis, which is discontinuous at the boundaries. To solve this problem, it is necessary to stitch the boundaries of the regression function so that the regression function is continuous at the boundaries. And taking the regression function after stitching each region as a first prediction function of each region. By stitching the boundary after regression analysis, the delay and leakage current are more continuous at the boundary and reflected as continuous changes on the interface.
Specifically, the embodiment divides the voltage temperature plane into a plurality of maximum operable areas and a normal working area, and adopts an S function and a Haifenesin step function to carry out boundary stitching on regression functions related to the same boundary aiming at the divided areas. The expression of the S function is: f (x) =1/(1+exp (-x)), the saturation region is in the x >10 region, and the transition region is in the 0< x <10 region. The expression of the Haifenesin step function is: u (x) =1, x > =0; u (x) =0, x <0.
As shown in fig. 4, the specific steps of the border stitching include:
Step S321: stitching the regression function of each maximum operable area with the regression function of the normal working area by adopting a sigmoid function to obtain a first prediction function of each maximum operable area;
The stitching principle of the sigmoid function is shown with reference to fig. 5. Let S function be used to stitch u (x) f+v (x) (1-f), where u (x), v (x) represent regression functions for different regions and f represents S function. Then the region where x is greater than zero is u (x), the region where x is less than zero is v (x), and both u (x) and v (x) continuously change around zero, so that u (x) and v (x) are stitched and continue at boundary x=0.
Since each maximum operable area is different from the boundary of the normal operation area, the expression at the time of stitching is also different. The following description will be given by taking stitching of the delay functions of the respective regions as an example:
For stitching between region II and region I, the post-stitching regression function (i.e., the first prediction function) DIInew (V, T) for region II is: DIInew (V, T) =dii (V, T) ×f (x) +di (V, T) ×1-f (x)), DII being a regression function of region II, DI being a regression function of region I. The saturation region of the region II is the DII, and functions of the two regions are overlapped in the transition region, so that the transition from one function to the other function is smooth. The variable x between region II and region I is (-v+90%vddnom)/(90%vddnom-minVdd) 100, achieving the effect: so that the region (-V+90%VDDNOM) > (90%VDDNOM-minVdd)/10 is the saturation region, (90%VDDNOM-minVdd) is the width of region II, that is, the 1/10 width of the dividing boundary to the region is the transition region, and the region exceeding 1/10 width is the saturation region. Substituting x into the complete expression of ： DIInew(V,T)=DII(V,T)*f((-V+90%VDDNOM)/(90%VDDNOM-minVdd)*100) +DI(V,T)*(1-f((-V+90%VDDNOM)/(90%VDDNOM-minVdd)*100)).
Similarly, the stitch between region III and region I, variable x is ((-v+90% vddnom)/(90% vddnom-minVdd) +(-t+t1)/(T1-minTemp))x100;
Stitching between region IV and region I, the variable x being (-t+t1)/(T1-minTemp) x 100;
stitching between region V and region I, variable x being ((V-110% vddnom)/(maxVdd-110% vddnom) +(-t+t1)/(T1-minTemp)) ×100);
Stitching between region VI and region I, variable x being (V-110% vddnom)/(maxVdd-110% vddnom) ×100);
Stitching between region VII and region I, variable x being ((V-110% VDDNOM)/(maxVdd-110% VDDNOM) + (T-T2)/(maxTemp-T2)). 100);
Stitching between region VIII and region I, variable x being (T-T2)/(maxTemp-T2) x 100);
The stitch between region IX and region I, the variable x is ((-V+90% VDDNOM)/(90% VDDNOM-minVdd) + (T-T2)/(maxTemp-T2)). Times.100).
When the leakage current function of each area is stitched, the first prediction function for solving the leakage current can be obtained by replacing the delay function with the leakage current function.
Step S322: and stitching the regression function of the normal working area and the regression functions of all the maximum operable areas by adopting a sigmoid function and a Haifenesin step function to obtain a first prediction function of the normal working area.
When stitching the delay function of the normal operating region, stitching with the delay functions of all the maximum operable regions is required to obtain the first prediction function of the normal operating region.
Specifically, a sigmoid function and a sea-Vise step function are adopted for stitching, and the specific expression is: DInew (V, T) =
DI(V,T)*f((V-90%VDDNOM)/(90%VDDNOM-minVdd)*100)*[U((90%VDDNOM-minVdd)/100+90%VDDNOM-V)*U(T2-(maxTemp-T2)/100-T)*U(T-(T1-minTemp)/100-T)+1/8*U(V-(90%VDDNOM-minVdd)/100-90%VDDNOM)]
+DII(V,T)*(1-f((V-90%VDDNOM)/(90%VDDNOM-minVdd)*100))+DI(V,T) *f(((V-90%VDDNOM)/(90%VDDNOM-minVdd)+(T-T1)/(T1-minTemp))*100)*[U((90%VDDNOM-minVdd)/100+90%VDDNOM-V)*U((T1-minTemp)/100+T1-T)+1/8*U(V-(90%VDDNOM-minVdd)/100-90%VDDNOM)*U(T-(T1-minTemp)/100-T1)]
+DIII(V,T)*(1-f(((V-90%VDDNOM)/(90%VDDNOM-minVdd)+(T-T1)/(T1-minTemp))*100))+DI(V,T)*f((T-T1)/(T1-minTemp)*100)*[U(T1+(T1-minTemp)/100-T)*U(V-(90%VDDNOM-minVdd)/100-90%VDDNOM)*U(-(maxVdd-110%VDDNOM)/100+110%VDDNOM-V) + 1/8*U(T-T1-(T1-minTemp)/100)]
+DIV(V,T)*(1-f((T-T1)/(T1-minTemp)*100))+DI(V,T)*f(((-V+110%VDDNOM)/(maxVdd-110%VDDNOM)+(T-T1)/(T1-minTemp))*100)*[U(V-110%VDDNOM+(maxVdd-110%VDDNOM)/100)*U(T1+(T1-minTemp)/100-T)+1/8*U(-(maxVdd-110%VDDNOM)/100+110%VDDNOM-V) * U(T-T1-(T1-minTemp)/100)]
+DV[V,T]*(1-f(((-V+110%VDDNOM)/(maxVdd-110%VDDNOM)+(T-T1)/(T1-minTemp))*100))+DI(V,T)*f((-V+110%VDDNOM)/(maxVdd-110%VDDNOM)*100)*[U(V-110%VDDNOM+(maxVdd-110%VDDNOM)/100)*U(T2-(maxTemp-T2)/100-T)*U(T-(T1-minTemp)/100-T1)+1/8*U(110%VDDNOM-(maxVdd-110%VDDNOM)/100-V)]
+DVI[V,T]*(1-f((-V+110%VDDNOM)/(maxVdd-110%VDDNOM)*100))+ DI(V,T)*f(((110%VDDNOM-V)/(maxVdd-110%VDDNOM)+(T2-T)/(maxTemp-T2))*100)*[U(V+(maxVdd-110%VDDNOM)/100-110%VDDNOM)*U(T-T2+(maxTemp-T2)/100)+1/8*U(-(maxVdd-110%VDDNOM)/100+110%VDDNOM-V)*U(T2-(maxTemp-T2)/100-T)]
+DVII(V,T)*(1-f(((110%VDDNOM-V)/(maxVdd-110%VDDNOM)+(T2-T)/(maxTemp-T2))*100))+DI(V,T)*f((T2-T)/(maxTemp-T2)*100)*[U(T-T2+(maxTemp-T2)/100)*U(V-(90%VDDNOM-minVdd)/100-90%VDDNOM)*U(-(maxVdd-110%VDDNOM)/100+110%VDDNOM-V)+1/8*U(T2-(maxTemp-T2)/100-T)]
+DVIII(V,T)*(1-f((T2-T)/(maxTemp-T2)*100))+DI(V,T)*f(((V-90%VDDNOM)/(90%VDDNOM-minVdd)+(T2-T)/(maxTemp-T2))*100)*[U(90%VDDNOM+(90%VDDNOM-minVdd)/100-V)*U(T-T2+(maxTemp-T2)/100)+1/8*U(V-90%VDDNOM-(90%VDDNOM-minVdd)/100)*U(T2-(maxTemp-T2)/100-T)]
+Dix (V, T) ×1-f (((V-90% vddnom)/(90% vddnom-minVdd) + (T2-T)/(maxTemp-T2)) ×100)). Wherein U (-) is a Haifenesin step function and f (-) is a sigmoid function.
When the leakage current function of the normal working area is stitched, the first prediction function for solving the leakage current of the normal working area can be obtained by replacing the delay function with the leakage current function.
Step S400: inputting the target voltage and the target temperature into a first prediction function of a region to which the target voltage and the target temperature belong, and obtaining a prediction result of the parameters;
after the first prediction function of each region is determined, the chip design can continuously predict each target voltage and each target temperature. Namely: and determining the area according to the target voltage and the target temperature, and then inputting the target voltage and the target temperature into a first prediction function of the area to obtain a prediction result of the parameter. Specifically, when predicting delay, inputting a target voltage and a target temperature into a corresponding delay function to obtain a predicted delay value; when the leakage current is predicted, the target voltage and the target temperature are input into the corresponding leakage current function, and the predicted leakage current value is obtained.
In summary, in this embodiment, the first prediction function of each region is obtained by fitting through nonlinear regression analysis, and then, when the chip is designed, the corresponding first prediction function is determined according to the target voltage and the target temperature, and the parameter values such as delay and leakage current can be obtained by calculation. And in the process of fitting to obtain the first prediction function of each region, the S function and the Haifenesin step function are adopted to carry out boundary stitching, so that the predicted value of the parameter is more accurate and smooth.
In this embodiment, when it is determined that the number information does not meet the first rule but meets the second rule under the target process angle, step S500 is performed: and performing linear regression analysis according to the values in the liberty library to obtain a second prediction function, and inputting the target process angle, the target voltage and the target temperature into the second prediction function to obtain a prediction result of the parameters.
Specifically, in this embodiment, the second rule is: for a certain VT, there are less than two different voltages or less than two different temperature values in the liberty library, but the three process corners (FF, TT or SS) add up, the different voltage different temperature values being greater than 6. When the number information is determined to be in accordance with the second rule, ff= (1, 0), tt= (0, 1, 0), ss= (0, 1); let Dly =a, vdd+b, temp+c, ff+d, tt+e, ss+f; performing lr.fit (X, Y) linear regression, wherein each row Xi of X consists of Vi, ti, FFi, TTi, SSi columns of data in the liberty banks; each row of Y is composed of a corresponding delay or leakage current Yi (Xi). And obtaining a second prediction function after the regression analysis is successful, and inputting the target process angle, the target voltage and the target temperature into the second prediction function to obtain a prediction result of delay or leakage current. The second rule is the lowest threshold that the number of liberty libraries required for prediction needs to meet, which is a remedial measure, unlike the zoned nonlinear regression.
The embodiment also manufactures a ring oscillator, researches the temperature sensitivity and the voltage sensitivity of the ring oscillator, compares the predicted value with SPICE simulation and wafer test values, uses the actual measured value of the wafer to prove the predicted value of the method, and obtains the trend of delay along with the change of voltage or temperature under different oscillation frequencies.
The invention also provides a device for predicting the change of parameters of chip design along with voltage and temperature, as shown in fig. 6, the device comprises:
liberty the database number module 600 is configured to count the number of the liberty databases under various process angles based on the voltage threshold of the target class, so as to obtain number information;
A rule determination module 610, configured to determine whether the number information meets a first rule under a target process corner;
The partitioning module 620 is configured to partition a coordinate plane formed by the voltage and the temperature based on the working parameters of the chip, so as to obtain a plurality of areas;
The regression analysis module 630 is configured to perform nonlinear regression analysis on each region based on the target process angle and the values in the liberty library, to obtain a first prediction function of each region;
and the prediction module 640 is configured to input a target voltage and a target temperature into a first prediction function of a region to which the target voltage and the target temperature belong, so as to obtain a prediction result of the parameter.
In particular, in this embodiment, the specific function of the device for predicting the change of the parameter for chip design with the voltage temperature may refer to the corresponding description in the method for predicting the change of the parameter for chip design with the voltage temperature, which is not described herein again.
Based on the above embodiment, the present invention further provides an intelligent terminal, and a functional block diagram thereof may be shown in fig. 7. The intelligent terminal comprises a processor, a memory, a network interface and a display screen which are connected through a system bus. The processor of the intelligent terminal is used for providing computing and control capabilities. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating system and a prediction program for a change in parameters of chip design with voltage temperature. The internal memory provides an environment for the operation of an operating system and a predictive program for the variation of parameters of chip design with voltage temperature in a non-volatile storage medium. The network interface of the intelligent terminal is used for communicating with an external terminal through network connection. The method for predicting the variation of the parameter for chip design along with the voltage and the temperature comprises the step of realizing the method for predicting the variation of the parameter for chip design along with the voltage and the temperature when the program for predicting the variation of the parameter for chip design along with the voltage and the temperature is executed by a processor. The display of the meter may be a liquid crystal display or an electronic ink display.
It will be appreciated by those skilled in the art that the schematic block diagram shown in fig. 7 is merely a block diagram of a portion of the structure associated with the present inventive arrangements and is not limiting of the smart terminal to which the present inventive arrangements are applied, and that a particular smart terminal may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a prediction program for the variation of the parameters of the chip design along with the voltage and the temperature, and when the prediction program for the variation of the parameters of the chip design along with the voltage and the temperature is executed by a processor, the method for predicting the variation of the parameters of the chip design along with the voltage and the temperature is realized.
It should be understood that the sequence number of each step in the above embodiment does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not be construed as limiting the implementation process of the embodiment of the present invention.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units described above is merely a logical function division, and may be implemented in other manners, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.
The integrated modules/units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer-readable storage medium. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the steps of each method embodiment may be implemented. The computer program comprises computer program code, and the computer program code can be in a source code form, an object code form, an executable file or some intermediate form and the like. The computer readable medium may include: any entity or device capable of carrying the computer program code described above, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. The content of the computer readable storage medium can be appropriately increased or decreased according to the requirements of the legislation and the patent practice in the jurisdiction.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that; the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions are not intended to depart from the spirit and scope of the various embodiments of the invention, which are also within the spirit and scope of the invention.
Claims (9)
1. A method for predicting a change in a parameter with voltage temperature for chip design, comprising:
Based on a voltage threshold of a target type, counting the number of liberty libraries under various process angles to obtain number information;
When the number information is judged to accord with a first rule under a target process angle, wherein the first rule is as follows: at a certain voltage threshold and a certain process angle, liberty libraries of different voltages are more than 2, and liberty libraries of different temperatures are more than 2;
partitioning a coordinate plane formed by voltage and temperature based on working parameters of a chip to obtain a plurality of areas;
based on the target process angle and the values in the liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a first prediction function of each region;
Inputting a target voltage and a target temperature into a first prediction function of a region where the target voltage and the target temperature belong to, and obtaining a prediction result of the parameter;
when the number information is judged to accord with a second rule, linear regression analysis is carried out based on liberty libraries to obtain a second prediction function, and a target process angle, a target voltage and a target temperature are input into the second prediction function to obtain a prediction result of the parameter, wherein the second rule is as follows: for a certain voltage threshold, there are less than two different voltages or less than two different temperatures in the liberty libraries for a certain process corner, but typical process corners, fast process corners, slow process corners add up, the libraries for different voltages and different temperatures are greater than 6.
2. The method for predicting temperature change of parameters for chip design with voltage according to claim 1, wherein the performing nonlinear regression analysis on each region based on the target process corner and the values in liberty library to obtain the first prediction function of each region comprises:
based on the target process angle and the values in liberty library, respectively carrying out nonlinear regression analysis on each region to obtain a regression function of each region;
And carrying out boundary stitching on the regression function to ensure that boundaries are continuous, and obtaining the first prediction function of each region.
3. The method for predicting temperature change of parameters for chip design with voltage according to claim 2, wherein said performing boundary stitching on the regression function to make boundaries continuous, obtaining the first prediction function of each region comprises:
and based on the boundary of each region, performing boundary stitching on the regression function related to the boundary by adopting a sigmoid function and a Haidelded step function, so as to obtain the first prediction function of each region.
4. The method for predicting voltage-temperature variation of parameters for chip design according to claim 3, wherein the area is divided into a normal operation area and a maximum operable area, the maximum operable area is located at the periphery of the normal operation area, the border stitching is performed on the regression function related to the border by using a sigmoid function and a sea-going step function based on the border of each area, respectively, to obtain the first prediction function of each area, and the method comprises:
Stitching the regression function of each maximum operable area with the regression function of the normal working area by adopting a sigmoid function to obtain the first prediction function of each maximum operable area;
and stitching the regression function of the normal working area and the regression functions of all the maximum operable areas by adopting a sigmoid function and a Haidelder step function to obtain the first prediction function of the normal working area.
5. The method for predicting temperature variation of parameters for chip design with voltage according to claim 2, wherein said performing a nonlinear regression analysis on each region based on the target process corner and the values in liberty library, respectively, to obtain a regression function of each region comprises:
based on the target process angle, a plurality of voltage values, temperature values and delay values or leakage current values are obtained from a liberty library;
Traversing each region, carrying out nonlinear mapping on the voltage value, the temperature value and the delay value or the leakage current value belonging to the current region to obtain a mapped voltage value, a mapped temperature value, a mapped delay value or a mapped leakage current value, and obtaining a regression function of the current region by adopting linear regression according to all the mapped voltage value, the mapped temperature value, the mapped delay value or the mapped leakage current value.
6. The method for predicting temperature variation of parameters for chip design according to claim 1, wherein partitioning the coordinate plane formed by the voltage and the temperature based on the operating parameters of the chip to obtain a plurality of areas comprises:
Constructing a voltage temperature plane by taking voltage as a horizontal axis and temperature as a vertical axis;
acquiring working parameters of a chip, wherein the working parameters comprise: standard power supply voltage, maximum operating voltage, minimum operating voltage, maximum operating temperature, minimum value of normal operating temperature, maximum value of normal operating temperature;
And dividing a transverse axis by adopting the minimum working voltage, the standard power supply voltage of the first preset proportion, the standard power supply voltage of the second preset proportion and the maximum working voltage, and dividing a longitudinal axis by adopting the minimum working temperature, the minimum value of the normal working temperature, the maximum value of the normal working temperature and the maximum working temperature to obtain a plurality of areas.
7. A device for predicting a change in a parameter of a chip design with voltage temperature, comprising:
the liberty library number module is used for counting the number of liberty libraries under various process angles based on the voltage threshold of the target type to obtain number information;
The rule judging module is used for judging whether the number information accords with a first rule under a target process angle, wherein the first rule is as follows: at a certain voltage threshold and a certain process angle, liberty libraries of different voltages are more than 2, and liberty libraries of different temperatures are more than 2;
The partitioning module is used for partitioning a coordinate plane formed by voltage and temperature based on working parameters of the chip to obtain a plurality of areas;
The regression analysis module is used for respectively carrying out nonlinear regression analysis on each region based on the target process angle and the values in the liberty library to obtain a first prediction function of each region;
the prediction module is used for inputting the target voltage and the target temperature into a first prediction function of the region where the target voltage and the target temperature belong to, and obtaining a prediction result of the parameter;
when the number information is judged to accord with a second rule, linear regression analysis is carried out based on liberty libraries to obtain a second prediction function, and a target process angle, a target voltage and a target temperature are input into the second prediction function to obtain a prediction result of the parameter, wherein the second rule is as follows: for a certain voltage threshold, there are less than two different voltages or less than two different temperatures in the liberty libraries for a certain process corner, but typical process corners, fast process corners, slow process corners add up, the libraries for different voltages and different temperatures are greater than 6.
8. A smart terminal, characterized in that it comprises a memory, a processor and a prediction program for the variation of parameters of a chip design with voltage temperature stored on the memory and executable on the processor, the prediction program for the variation of parameters of a chip design with voltage temperature implementing the steps of the prediction method for the variation of parameters of a chip design with voltage temperature according to any one of claims 1-6 when executed by the processor.
9. Computer-readable storage medium, characterized in that it has stored thereon a prediction program for the variation of parameters of a chip design with voltage temperature, which, when executed by a processor, implements the steps of the method for predicting the variation of parameters of a chip design with voltage temperature according to any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410670487.8A CN118246374B (en) | 2024-05-28 | 2024-05-28 | Method and device for predicting voltage-temperature variation of parameters for chip design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410670487.8A CN118246374B (en) | 2024-05-28 | 2024-05-28 | Method and device for predicting voltage-temperature variation of parameters for chip design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118246374A CN118246374A (en) | 2024-06-25 |
| CN118246374B true CN118246374B (en) | 2024-08-06 |
Family
ID=91552919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410670487.8A Active CN118246374B (en) | 2024-05-28 | 2024-05-28 | Method and device for predicting voltage-temperature variation of parameters for chip design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118246374B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112257361A (en) * | 2020-10-22 | 2021-01-22 | 东南大学 | Standard unit library construction method based on quadratic fitting model |
| CN116595915A (en) * | 2023-04-06 | 2023-08-15 | 长鑫存储技术有限公司 | System simulation method and device, electronic equipment and storage medium |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8549452B2 (en) * | 2010-05-06 | 2013-10-01 | International Business Machines Corporation | Method for supporting multiple libraries characterized at different process, voltage and temperature points |
| US10380286B2 (en) * | 2017-02-20 | 2019-08-13 | International Business Machines Corporation | Multi-sided variations for creating integrated circuits |
-
2024
- 2024-05-28 CN CN202410670487.8A patent/CN118246374B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112257361A (en) * | 2020-10-22 | 2021-01-22 | 东南大学 | Standard unit library construction method based on quadratic fitting model |
| CN116595915A (en) * | 2023-04-06 | 2023-08-15 | 长鑫存储技术有限公司 | System simulation method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118246374A (en) | 2024-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220012395A1 (en) | Efficient integrated circuit simulation and testing | |
| Fang et al. | Machine-learning-based dynamic IR drop prediction for ECO | |
| US5751593A (en) | Accurate delay prediction based on multi-model analysis | |
| US8036870B2 (en) | Simulation method for efficient characterization of electronic systems under variability effects | |
| CN109426698B (en) | Apparatus for predicting yield of semiconductor integrated circuit and method for manufacturing semiconductor device | |
| US7503020B2 (en) | IC layout optimization to improve yield | |
| TWI716115B (en) | Integrated circuit design method, iintegrated circuit design system and non-transitory computer readable media | |
| US5787008A (en) | Simulation corrected sensitivity | |
| JP2021521646A (en) | Integrated circuit profiling and anomaly detection | |
| Krause et al. | Adaptive voltage over-scaling for resilient applications | |
| US5790415A (en) | Complementary network reduction for load modeling | |
| US5940779A (en) | Architectural power estimation method and apparatus | |
| US7269806B2 (en) | Decoupling capacitance analysis method | |
| JP2002328966A (en) | Method for preparing model for estimating power consumption of circuit and method for estimating power consumption | |
| US20170147727A1 (en) | Temperature-aware integrated circuit design methods and systems | |
| US7933747B2 (en) | Method and system for simulating dynamic behavior of a transistor | |
| US10474774B2 (en) | Power and performance sorting of microprocessors from first interconnect layer to wafer final test | |
| US8606557B2 (en) | Table lookup method for physics based models for SPICE-like simulators | |
| US20170185709A1 (en) | Method and apparatus for adjusting a timing derate for static timing analysis | |
| US7240304B2 (en) | Method for voltage drop analysis in integreted circuits | |
| US6665843B2 (en) | Method and system for quantifying the integrity of an on-chip power supply network | |
| US8813006B1 (en) | Accelerated characterization of circuits for within-die process variations | |
| De Smedt et al. | HOLMES: Capturing the yield-optimized design space boundaries of analog and RF integrated circuits | |
| CN118246374B (en) | Method and device for predicting voltage-temperature variation of parameters for chip design | |
| US9830413B2 (en) | System and method for estimating performance, power, area and cost (PPAC) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |