CN118244594A - Photoetching alignment structure, semiconductor device and forming method of photoetching alignment structure - Google Patents

Abstract

The invention provides a photoetching alignment structure, a semiconductor device and a forming method of the photoetching alignment structure, and belongs to the technical field of semiconductor device manufacturing. The photoetching alignment structure comprises an auxiliary pattern and an alignment mark, wherein the auxiliary pattern is positioned in the first wafer layer, the auxiliary pattern comprises a plurality of first grid bars, and the first grid bars are arranged in parallel along a first direction; the alignment mark is positioned in the second wafer layer, the second wafer layer is positioned above the first wafer layer, the alignment mark comprises a plurality of second grid bars, and the second grid bars are arranged in parallel along a second direction; the first direction is perpendicular to the second direction, the second direction is parallel to the photoetching scanning direction, and the alignment mark and the auxiliary pattern are at least partially overlapped on the projection of the height direction. The photoetching alignment structure is provided with the auxiliary pattern at the bottom layer of the alignment mark, so that the noise interference on the alignment mark can be avoided while the load effect is eliminated.

Description

Photoetching alignment structure, semiconductor device and forming method of photoetching alignment structure

Technical Field

The invention relates to the technical field of semiconductor device manufacturing, in particular to a photoetching alignment structure, a semiconductor device and a forming method of the photoetching alignment structure.

Background

Photolithography is the basis for large scale integrated circuit fabrication techniques, which largely determine the degree of integration of integrated circuits. Photolithography is a process technique in which a pattern on a reticle is transferred onto a photoresist-coated wafer by exposure and, after development, the pattern on the reticle is developed on the wafer.

The critical step in the photolithography process is to align the reticle with the wafer. In the fabrication of integrated circuits, it is often necessary to expose several layers or even tens of layers of mask patterns on a wafer to form a complete circuit structure. In the photolithography process, the mask is aligned to each exposure unit on the wafer before each exposure step, and the alignment accuracy of the photolithography process determines the complexity and functional density of the integrated circuit.

The prior art typically places alignment marks in the front layer of the wafer to achieve exposure alignment when layer lithography is performed on the wafer. For process consideration when designing alignment marks on a wafer, it is generally necessary to keep the bottom layer of the front-layer mark region clean (i.e. without patterns), but the large-area non-pattern region existing in the wafer layer may generate loading effect (loading effect) on other processes (such as photolithography, chemical mechanical polishing, etc.); if dummy pattern structures, such as blind closed-cell marks (close the blind mark, CTB marks), are placed in the bottom layer of the front-layer mark region, the dummy patterns placed in the bottom layer may cause noise interference to the alignment marks in the front layer, resulting in alignment failure, although the loading effect of the wafer during other processes can be eliminated. Therefore, in the prior art, it is difficult to eliminate the noise interference for the photolithography alignment and the loading effect for other processes in the subsequent processes.

Therefore, there is a need to design a lithographic alignment structure, a semiconductor device, and a method of forming a lithographic alignment structure to solve the above-mentioned problems.

Disclosure of Invention

In view of the above drawbacks of the prior art, the present invention provides a lithographic alignment structure, a semiconductor device, and a method for forming the lithographic alignment structure, so as to solve the technical problem that the existing lithographic alignment structure is difficult to eliminate both the load effect and the noise interference effect in the subsequent process.

To achieve the above and other related objects, the present invention provides a lithographic alignment structure comprising an assist pattern and an alignment mark.

The auxiliary pattern is positioned in the first wafer layer and comprises a plurality of first grid bars which are arranged in parallel along a first direction; the alignment mark is positioned in a second wafer layer, the second wafer layer is positioned above the first wafer layer, and the alignment mark comprises a plurality of second grid bars which are arranged in parallel along a second direction; and the first direction is perpendicular to the second direction, the second direction is parallel to the photoetching scanning direction, and the alignment mark and the auxiliary pattern are at least partially overlapped on the projection of the height direction.

In an example of the present invention, the auxiliary pattern forms a background light under an alignment light, and the alignment mark forms a diffraction image in the background light under the alignment light, and the diffraction image is aligned with a reference mark in the mask in a matching manner.

In one example of the present invention, the pitches between the adjacent first bars are equal.

In one example of the present invention, the alignment mark and the auxiliary pattern are located in the same exposure unit on the wafer.

In an example of the present invention, the alignment mark includes a plurality of sets of sub alignment marks, the sub alignment mark includes a plurality of the second bars, and the plurality of second bars in the sub alignment mark are arranged in parallel along the second direction; the plurality of groups of sub-alignment marks are arranged in combination in the first direction and/or the second direction.

In an example of the present invention, among the plurality of sets of sub-alignment marks arranged in the first direction, second bars in at least two sets of sub-alignment marks are staggered in the second direction.

In one example of the present invention, the plurality of sets of sub-alignment marks includes at least two sets of sub-alignment marks having different periods of the second grid arrangement.

In one example of the present invention, the pitches between the adjacent second bars are equal.

The invention also provides a method for forming the photoetching alignment structure, which comprises the following steps:

Providing a substrate;

forming an auxiliary pattern in a first wafer layer of the substrate, wherein the auxiliary pattern comprises a plurality of first grid bars which are arranged in parallel along a first direction;

Forming an alignment mark in a second wafer layer of the substrate, and at least partially overlapping the alignment mark with the auxiliary pattern in a height direction; the alignment mark comprises a plurality of second grid bars which are arranged in parallel along a second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the photoetching scanning direction.

The invention also provides a semiconductor device comprising a plurality of wafer layers, the wafer layers comprising a main chip region and a marking region; wherein the plurality of wafer layers comprises at least one set of selected layers, each set of selected layers comprising a first wafer layer and a second wafer layer, the marking area of each set of selected layers being configured to accommodate a lithographic alignment structure as described in any of the examples above.

The invention provides a photoetching alignment structure, a semiconductor device and a forming method of the photoetching alignment structure, wherein the photoetching alignment structure comprises an auxiliary pattern positioned at a bottom layer and an alignment mark positioned at an upper layer, the auxiliary pattern comprises a plurality of first grid bars which are arranged in parallel along a first direction, the first grid bars in the auxiliary pattern extend along a second direction (namely a photoetching scanning direction), the alignment mark comprises a plurality of second grid bars which are arranged in parallel along the second direction, and the second grid bars in the alignment mark extend along the first direction. The auxiliary pattern placed on the bottom layer of the alignment mark by the photoetching alignment structure can effectively eliminate the load effect in the subsequent process; and because the auxiliary pattern and the alignment mark are mutually orthogonally arranged, when the alignment illumination scans and irradiates the wafer along the photoetching scanning direction in the photoetching exposure process, the alignment illumination is reflected by the alignment mark to form a diffraction image which presents diffraction characteristics in the second direction, and the reflected light of the auxiliary pattern under the alignment illumination can not introduce periodic characteristic information in the second direction, so that the alignment information in the diffraction image can not be disturbed.

In conclusion, the photoetching alignment structure is provided with the auxiliary pattern at the bottom layer of the alignment mark, so that the noise interference to the alignment mark can be avoided while the load effect is eliminated, and the load effect and the noise interference influence can be eliminated in the subsequent process.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art lithographic alignment structure;

FIG. 2 is a schematic diagram of another prior art lithographic alignment structure;

FIG. 3 is a schematic cross-sectional view of a lithographic alignment structure according to an embodiment of the invention;

FIG. 4 is a schematic top view of a lithographic alignment structure according to an embodiment of the invention;

FIG. 5 is a schematic top view of a lithographic alignment structure according to another embodiment of the invention;

FIG. 6 is a schematic top view of another lithographic alignment structure according to another embodiment of the invention;

FIG. 7 is a schematic top view of a further lithographic alignment structure according to another embodiment of the invention;

FIG. 8 is a schematic top view of a lithographic alignment structure according to yet another embodiment of the invention;

FIG. 9 is a schematic top view of another lithographic alignment structure according to yet another embodiment of the invention;

FIG. 10 is a schematic top view of a lithographic alignment structure according to another embodiment of the invention;

FIG. 11 is a schematic top view of another lithographic alignment structure according to yet another embodiment of the invention;

FIG. 12 is a schematic top view of a further lithographic alignment structure according to a further embodiment of the invention;

FIG. 13 is a flow chart of a method for forming a lithographic alignment structure according to an embodiment of the invention;

Fig. 14 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

Description of element reference numerals

10. A substrate; 101. a first wafer layer; 102. a second wafer layer; 103. closed blind holes; 20.a semiconductor device; 21. a main chip region; 22. marking the area; 100. photoetching an alignment structure; 110. an auxiliary pattern; 111. a first grid; 120. an alignment mark; 121. a second grid; 122. sub-alignment marks; 123. a first sub-alignment mark; 124. and a second sub-alignment mark.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.

In the semiconductor manufacturing process, alignment between layout layers is typically achieved using photolithographic alignment marks. In the prior art, for the process consideration of alignment accuracy, the bottom layer of the mark region in the wafer needs to be kept clean, that is, as shown in fig. 1, when the alignment mark 120 is placed in the second wafer layer 102, the first wafer layer 101 below the second wafer layer 102 needs to be kept clean (that is, no pattern structure) however, the large-area non-pattern region in the wafer layer may generate a loading effect on other processes (such as etching, chemical mechanical polishing and the like), and the loading effect may affect the uniformity of the region of the wafer after the wafer is processed by the polishing and etching process, thereby negatively affecting the yield of the chips in the process.

If the loading effect of the wafer in the subsequent process is eliminated, as shown in fig. 2, a dummy pattern structure (such as a closed blind hole 103 mark) is generally placed in the first wafer layer 101, and the placed dummy pattern can stabilize the hierarchical structure of the wafer and eliminate the loading effect of the wafer in the subsequent process, but at the same time, the optical noise is reflected under the alignment illumination to form optical noise, and the optical noise can interfere with the diffraction image formed by the alignment illumination reflected by the alignment mark 120, so that the diffraction image is difficult to match with the reference mark in the mask, and further the alignment failure of the mask and the exposure unit of the wafer is caused.

Therefore, the photoetching alignment structure arranged in the wafer in the prior art is difficult to eliminate noise interference on alignment and load effect of other manufacturing processes in the subsequent manufacturing process. To solve the above-mentioned problems, as shown in fig. 3 to 12, the present invention provides a lithographic alignment structure 100, in which a lithographic alignment mark 120 is placed in a second wafer layer 102 located at an upper layer, and an auxiliary pattern 110 is placed in a first wafer layer 101 located at a lower layer. The photolithographic alignment structure 100 extends the plurality of first bars 111 in the auxiliary pattern 110 arranged in parallel along the first direction in the second direction (photolithographic scanning direction), and the plurality of second bars 121 in the alignment mark 120 are arranged in parallel along the second direction on the projection of the auxiliary pattern 110. The design structure eliminates the loading effect of the wafer in the subsequent process by placing the auxiliary pattern 110 in the first chip layer 101, and eliminates the noise interference of the diffraction image generated by the auxiliary pattern 110 reflected light on the alignment mark 120 by utilizing the orthogonal arrangement relation of the auxiliary pattern 110 and the alignment mark 120 in the projection of the height direction.

As shown in fig. 3 to 12, the photolithographic alignment structure 100 includes an auxiliary pattern 110 and an alignment mark 120. The auxiliary pattern 110 is located in the first wafer layer 101, the auxiliary pattern 110 includes a plurality of first grid bars 111, the plurality of first grid bars 111 are arranged in parallel along a first direction, the first grid bars 111 are arranged in an extending manner in a second direction, and the second direction is a lithography scanning direction, wherein the lithography scanning direction is a moving direction of a lithography beam relative to a wafer during an exposure operation performed on the wafer by a lithography machine. The alignment mark 120 is located in the second wafer layer 102, the second wafer layer 102 is located above the first wafer layer 101 in the wafer, the alignment mark 120 includes a plurality of second grid bars 121, the plurality of second grid bars 121 are arranged in parallel along the second direction, and the second grid bars 121 are arranged in an extending manner in the first direction.

As shown in fig. 3 to 12, the alignment mark 120 at least partially overlaps with the projection of the auxiliary pattern 110 in the height direction. Since the first direction is perpendicular to the second direction, the plurality of second bars 121 in the alignment mark 120 are arranged in parallel in the extending direction of the projection of the first bars 111, and the second bars 121 are arranged orthogonally to the projection of the first bars 111 in the height direction.

As shown in fig. 4, in the photolithography exposure process, when the alignment illumination scans and irradiates the wafer along the photolithography scanning direction, the auxiliary pattern 110 forms a background light under the alignment illumination, the background light has periodic features only in a first direction which is the same as the photolithography scanning direction, the background light is reflected onto the mask plate to form a background image, and only background light spots arranged in the first direction are arranged in the background image; the alignment mark 120 forms a diffraction light in the background light under the alignment light, the diffraction light has a diffraction feature in the second direction, and the diffraction light is reflected onto the mask plate to form a diffraction image, and the diffraction image includes diffraction spots arranged in the second direction. Since the background light has periodic features only in the first direction and does not have any intensity variation features in the second direction, the diffracted light formed in the background light still retains the diffraction features of the alignment mark 120 in the second direction, and the position of the diffraction spot in the second direction in the diffraction image is not disturbed by the background light. The reference mark on the mask is matched with the diffraction image, and the alignment of the mask and the wafer exposure unit is realized by matching the reference mark with the diffraction image in the diffraction characteristic in the second direction; specifically, when the reference mark and the diffraction light spots are arranged in the same direction in the second direction, the reference mark can enable the diffraction light at a plurality of specified positions to simultaneously form alignment images through the mask when the mask is aligned with the exposure unit of the wafer, and the alignment detection unit detects the alignment images above the mask, so that the alignment of the mask and the exposure unit of the wafer can be confirmed. It can be seen that, since the background light formed by the auxiliary pattern 110 under the alignment illumination does not have the intensity feature information in the second direction, the diffraction feature of the diffraction image in the second direction is not affected, and the matching alignment of the diffraction image and the mask is not disturbed.

In addition, the lithographic alignment structure 100 is placed in the mark region 22 of the wafer prior to lithographic exposure for use in the alignment of the reticle with the exposure unit of the wafer. It should be noted that the lithographic alignment structure 100 may be used for single exposure alignment or for multiple exposure alignment.

As shown in fig. 3 to 12, in the lithographic alignment structure 100, the auxiliary pattern 110 located at the bottom layer of the alignment mark 120 can stabilize the wafer layer structure of the wafer, and reduce or even eliminate the loading effect of the wafer in the subsequent process; meanwhile, based on the orthogonal arrangement relation between the auxiliary pattern 110 and the alignment mark 120, the auxiliary pattern 110 cannot introduce noise interference affecting alignment characteristic information into a diffraction image generated by reflection of the alignment mark 120 in the photoetching exposure process.

It should be noted that the plurality of first bars 111 in the auxiliary pattern 110 may be regularly arranged in the first direction or may be irregularly arranged in the first direction. As shown in fig. 4, in some embodiments, the spaces between any two adjacent first grid bars 111 in the auxiliary pattern 110 are equal, and the plurality of first grid bars 111 arranged at equal intervals are beneficial to weaken the interference of the background light on the diffraction image shape. Alternatively, in other embodiments, the pitches between two adjacent first bars 111 in the auxiliary pattern 110 are not equal, for example, the auxiliary pattern 110 is periodically arranged in a bar group including a preset number of first bars 111, the pitch between two adjacent first bars 111 in the two bar groups is a first pitch, the pitch between two adjacent first bars 111 in the bar group is a second pitch, the first pitch is not equal to the second pitch, and the preset number may be 2, 3, 4, 5 or 6.

As shown in fig. 3 and 4, in some embodiments, the auxiliary pattern 110 and the alignment mark 120 are located in the same exposure unit on the wafer. Alternatively, in other embodiments, the auxiliary pattern 110 extends through the mark areas 22 of the plurality of exposure units in the second direction in the first wafer layer 101, and the alignment marks 120 are disposed in the mark areas 22 of the respective corresponding exposure units in the second wafer layer 102, and the projections of the alignment marks 120 in the corresponding mark areas 22 overlap with the projections of the auxiliary pattern 110 in the height direction.

Furthermore, in some embodiments, the auxiliary pattern 110 and the alignment mark 120 in the photo-alignment structure 100 are disposed in dicing lanes of the wafer, and the dicing lanes where the photo-alignment structure 100 is located extend along the second direction, in which embodiment the photo-alignment structure 100 is detached from the semiconductor device 20 divided on the wafer after the dicing process, and the photo-alignment structure 100 does not remain in the finished semiconductor device 20. In other embodiments, the photo-alignment structure 100 is not disposed in the scribe line of the wafer, the photo-alignment structure 100 is disposed in the mark region 22 at the edge of the main chip region 21 in the wafer layer, and the photo-alignment structure 100 remains in the finished semiconductor device 20 after the wafer dicing process.

As shown in fig. 4, in some embodiments, the plurality of second bars 121 in the alignment mark 120 may be regularly arranged in the second direction, for example, in an example, the pitch between any adjacent two second bars 121 in the alignment mark 120 is equal.

As shown in fig. 5 to 12, the alignment mark 120 includes a plurality of sets of sub-alignment marks 122, the sub-alignment marks 122 include a plurality of second bars 121, and the plurality of second bars 121 in the sub-alignment marks 122 are arranged in parallel along the second direction. The arrangement of the plurality of sets of sub-alignment marks 122 in the second wafer layer 102 is not limited, and can be designed according to the diffraction image requirement of alignment matching, and only the second grid bars 121 in the alignment marks 120 and the projection of the first grid bars 111 in the height direction are orthogonally arranged. In some embodiments, multiple sets of sub-alignment marks 122 are arranged in combination in the first direction and/or the second direction. Wherein, the plurality of groups of sub-alignment marks 122 can increase the position features of diffraction spots in the diffraction image reflected by the alignment mark 120, thereby improving the alignment accuracy of the alignment mark 120 and the mask.

As shown in fig. 5 to 7, in an example, a plurality of sets of sub-alignment marks 122 are arranged in combination in a first direction. Within the same exposure unit of the wafer, the plurality of sets of sub-alignment marks 122 are arranged in combination at different positions in the first direction, the plurality of second bars 121 in each set of sub-alignment marks 122 are arranged in parallel in the second direction, for example, the plurality of sets of sub-alignment marks 122 are arranged in combination at different positions in the first direction, and the plurality of sets of sub-alignment marks 122 are all at the same position in the second direction. When the alignment light irradiates the alignment mark 120, the multiple groups of sub-alignment marks 122 in the alignment mark 120 are respectively reflected at the respective positions to form diffraction spots, so that the diffraction image formed by reflection of the alignment mark 120 includes diffraction spots arranged at different positions in the first direction, and when the reference mark of the mask is simultaneously matched with the multiple groups of diffraction spots in the diffraction image (for example, the reference mark of the mask is simultaneously aligned with the ±1-order diffraction spots of each diffraction spot), successful alignment of the mask with the exposure unit of the wafer can be confirmed.

As shown in fig. 8 and 9, in another example, the plurality of sets of sub-alignment marks 122 are arranged in combination in the second direction. Within the same exposure unit of the wafer, the plurality of sets of sub-alignment marks 122 are arranged in combination at different positions in the second direction, and the plurality of second bars 121 in each set of sub-alignment marks 122 are arranged in parallel in the second direction, for example, the plurality of sets of sub-alignment marks 122 are arranged in combination at different positions in the second direction, the plurality of sets of sub-alignment marks 122 are all at the same position in the first direction, and the shortest distance between two adjacent sets of sub-alignment marks 122 is larger than the distance between two adjacent second bars 121 in any set of sub-alignment marks 122. When the alignment light irradiates the alignment mark 120, the plurality of groups of sub-alignment marks 122 in the alignment mark 120 are respectively reflected at the respective positions to form diffraction spots, so that the diffraction image formed by the reflection of the alignment mark 120 contains diffraction spots arranged at different positions in the second direction, and when the reference mark of the mask is matched with the plurality of groups of diffraction spots in the diffraction image at the same time, the successful alignment of the mask and the exposure unit of the wafer can be confirmed.

As shown in fig. 10 to 12, in still another example, a plurality of sets of sub-alignment marks 122 are simultaneously arranged in combination in the first direction and the second direction. In the same exposure unit of the wafer, a plurality of sets of sub-alignment marks 122 are arranged in rows at different positions in the first direction, a plurality of columns of sub-alignment marks 122 are arranged in rows at different positions in the second direction, and a plurality of second bars 121 in each set of sub-alignment marks 122 are arranged in parallel in the second direction. When the alignment light irradiates the alignment mark 120, the plurality of groups of sub-alignment marks 122 in the alignment mark 120 are respectively reflected at the respective positions to form diffraction spots, so that the diffraction image formed by the reflection of the alignment mark 120 contains diffraction spots arranged at different positions in the first direction and the second direction, and when the reference mark of the mask is matched with the plurality of groups of diffraction spots in the diffraction image at the same time, the successful alignment of the mask and the exposure unit of the wafer can be confirmed.

As shown in fig. 5 and 10, in some embodiments, among the plurality of sets of sub-alignment marks 122 arranged in the first direction, the second bars 121 of any two sets of sub-alignment marks 122 are aligned with each other in the second direction. As shown in fig. 7 and 12, in other embodiments, among the plurality of sets of sub-alignment marks 122 arranged in the first direction, the second bars 121 of at least two sets of sub-alignment marks 122 are staggered in the second direction.

It should be noted that, the patterns adopted by each group of the sub-alignment marks 122 in the alignment mark 120 are not limited, and the plurality of groups of the sub-alignment marks 122 may adopt the same grating pattern or may adopt different grating patterns. As shown in fig. 5,8 and 10, in some embodiments, the plurality of sets of sub-alignment marks 122 have the same grating pattern, the widths of the second bars 121 included in the plurality of sets of sub-alignment marks 122 are equal, and the pitches between two adjacent second bars 121 in each set of sub-alignment marks 122 are equal. In addition, as shown in fig. 6, 9 and 11, in other embodiments, the plurality of sets of sub-alignment marks 122 includes at least two sets of sub-alignment marks 122 having different arrangement periods of the second bars 121, the sub-alignment marks 122 having different arrangement periods of the second bars 121 may form different diffraction spots under the alignment light, and the diffraction images having different diffraction spots may effectively improve the alignment accuracy of the wafer and the mask when matching with the reference marks of the mask. For example, as shown in fig. 6, in an example, the plurality of sets of sub-alignment marks 122 include a first sub-alignment mark 123 and a second sub-alignment mark 124, the first sub-alignment mark 123 and the second sub-alignment mark 124 are arranged and combined at different positions in the first direction, the first sub-alignment mark 123 and the second sub-alignment mark 124 are arranged at intervals in the first direction, the widths of the second grid bars 121 included in the first sub-alignment mark 123 and the second sub-alignment mark 124 are equal, and the arrangement period of the second grid bars 121 in the first sub-alignment mark 123 is greater than the arrangement period of the second grid bars 121 in the second sub-alignment mark 124. When the alignment light irradiates the alignment mark 120, a first sub-alignment mark 123 in the alignment mark 120 forms a first diffraction spot with a larger distance under the alignment light, a second sub-alignment mark 124 forms a second diffraction spot with a smaller distance under the alignment light, the diffraction images formed by the alignment mark 120 by reflection under the alignment light have a first diffraction spot and a second diffraction spot which are arranged at intervals at different positions in the first direction, and when the reference mark of the mask is matched with the first diffraction spot and the second diffraction spot at the same time, the successful alignment of the mask and the exposure unit of the wafer can be confirmed.

In addition, the dimensions of the auxiliary pattern 110 and the alignment mark 120 in the lithographic alignment structure 100 may be adjusted according to the lithographic precision (i.e., the diffraction limit of the lithographic laser), for example, in an example, the lithographic machine performs lithography using an argon fluoride (ArF) excimer laser as a light source, when the lithographic laser wavelength is 193nm, the minimum length of the auxiliary pattern 110 may be 200nm, the minimum width of the auxiliary pattern 110 may be 200nm, the minimum length of the alignment mark 120 may be 200nm, and the minimum width of the alignment mark 120 may be 200nm; in another example, the lithography machine performs lithography using the same wavelength laser and processes the wafer using an immersion process, and the wavelength of the lithography laser incident on the wafer is further reduced by the influence of water refraction, which helps to further reduce the size of the set auxiliary pattern 110 and the alignment mark 120, the minimum length of the auxiliary pattern 110 may be 100nm, the minimum width of the auxiliary pattern 110 may be 100nm, the minimum length of the alignment mark 120 may be 100nm, and the minimum width of the alignment mark 120 may be 100nm.

As shown in fig. 13, the present invention further provides a method for forming the lithographic alignment structure 100 according to any one of the above embodiments, where the method at least includes the following steps:

S1, providing a substrate 10;

s2, forming an auxiliary pattern 110 in the first wafer layer 101 of the substrate 10, wherein the auxiliary pattern 110 comprises a plurality of first grid bars 111 which are arranged in parallel along a first direction;

S3, forming an alignment mark 120 in the second wafer layer 102 of the substrate 10, and enabling the alignment mark 120 to be at least partially overlapped with the auxiliary pattern 110 in the height direction; the alignment mark 120 includes a plurality of second bars 121 arranged in parallel along a second direction, the second direction in which the second bars 121 are arranged in parallel is perpendicular to the first direction in which the first bars 111 are arranged in parallel, and the second direction is in phase with the lithographic scanning direction.

In some embodiments, in step S1, the substrate 10 is a wafer to be processed before exposure, and the wafer may be a substrate, or a wafer including a substrate and an epitaxial layer on the substrate. The substrate may be a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, or a silicon-on-insulator substrate. The substrate may be selected by those skilled in the art as desired, and thus the type of substrate should not limit the scope of the present invention. However, the implementation of the present solution on a silicon substrate is less costly than the implementation of the present solution on other substrates as described above.

In some embodiments, in step S2, the auxiliary pattern 110 may be formed in the first wafer layer 101 by a conventional photolithography means. For example, in one example, a photoresist layer is formed on the surface of the substrate 10, the photoresist layer is exposed and developed to form a photoresist pattern, and a first film layer is formed on the photoresist pattern and the surface of the substrate 10; removing the photoresist pattern and the first film layer on top thereof, and reserving the first film layer on the surface of the substrate 10 to form an auxiliary pattern 110; a second film layer is formed on the surfaces of the auxiliary pattern 110 and the substrate 10, a portion of the second film layer on the surfaces of the substrate 10 and the auxiliary pattern 110, which is located on top of the auxiliary pattern 110, is removed to form a first wafer layer 101 on the substrate 10, and the auxiliary pattern 110 is disposed in the first wafer layer 101.

In some embodiments, in step S3, alignment marks 120 may be formed in the second wafer layer 102 by conventional photolithographic means. For example, in one example, a photoresist layer is formed on the surface of the first wafer layer 101, the photoresist layer is exposed and developed to form a photoresist pattern, and a third film layer is formed on the photoresist pattern and the surface of the first wafer layer 101; removing the photoresist pattern and the third film layer on top of the photoresist pattern, and reserving the third film layer on the surface of the first wafer layer 101 to form an alignment mark 120; a fourth film layer is formed on the surfaces of the alignment mark 120 and the first wafer layer 101, a portion of the second film layer on the surfaces of the first wafer layer 101 and the alignment mark 120, which is located on top of the auxiliary pattern 110, is removed to form a second wafer layer 102 on the substrate 10, and the alignment mark 120 is disposed in the second wafer layer 102.

As shown in fig. 14, the present invention also provides a semiconductor device 20, in which the semiconductor device 20 includes a plurality of wafer layers, each of which includes a main chip region 21 and a mark region 22. The plurality of wafer layers includes at least one set of selected layers, each set of selected layers including a first wafer layer 101 and a second wafer layer 102, and the mark region 22 of each set of selected layers is configured to accommodate the lithographic alignment structure 100 according to any of the embodiments described above, wherein the first wafer layer 101 is configured to accommodate the auxiliary pattern 110, the auxiliary pattern 110 is located in the mark region 22 of the first wafer layer 101, the second wafer layer 102 is located above the first wafer layer 101, the second wafer layer 102 is configured to accommodate the alignment mark 120, the alignment mark 120 is located in the mark region 22 of the second wafer layer 102, and the alignment mark 120 overlaps on the projection of the auxiliary pattern 110 in the height direction.

In summary, the invention provides a lithography alignment structure, a semiconductor device and a method for forming the lithography alignment structure, wherein the lithography alignment structure is provided with an auxiliary pattern at the bottom layer of an alignment mark, so that noise interference affecting alignment characteristic information is prevented from being introduced into a diffraction image generated by reflection of the alignment mark while load effect of a wafer in a subsequent process is reduced or even eliminated.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A lithographic alignment structure, comprising:

An auxiliary pattern in the first wafer layer, the auxiliary pattern including a plurality of first bars arranged in parallel along a first direction;

The alignment mark is positioned in the second wafer layer, the second wafer layer is positioned above the first wafer layer, and the alignment mark comprises a plurality of second grid bars which are arranged in parallel along a second direction;

The first direction is perpendicular to the second direction, the second direction is parallel to the photoetching scanning direction, and the alignment mark and the auxiliary pattern are at least partially overlapped on projection in the height direction.

2. The lithographic alignment structure of claim 1, wherein the auxiliary pattern forms a background light under alignment illumination, and the alignment mark forms a diffraction image in the background light under alignment illumination, the diffraction image being cooperatively aligned with a reference mark in a reticle.

3. The lithographic alignment structure of claim 1 wherein the spacing between adjacent first bars is equal.

4. The lithographic alignment structure of claim 1 wherein the alignment mark and the auxiliary pattern are located in the same exposure unit on the wafer.

5. The lithographic alignment structure of claim 1 wherein said alignment marks comprise a plurality of sets of sub-alignment marks, said sub-alignment marks comprising a plurality of said second bars; the plurality of groups of sub-alignment marks are arranged in combination in the first direction and/or the second direction.

6. The lithographic alignment structure of claim 5, wherein among said plurality of sets of sub-alignment marks arranged in said first direction, second bars of at least two sets of said sub-alignment marks are staggered in said second direction.

7. The lithographic alignment structure of claim 5 wherein said plurality of sets of sub-alignment marks comprises at least two sets of sub-alignment marks having different periods of said second grid arrangement.

8. The lithographic alignment structure of claim 1 wherein the spacing between adjacent second bars is equal.

9. A method of forming a lithographic alignment structure, comprising:

Providing a substrate;

forming an auxiliary pattern in a first wafer layer of the substrate, wherein the auxiliary pattern comprises a plurality of first grid bars which are arranged in parallel along a first direction;

Forming an alignment mark in a second wafer layer of the substrate, and at least partially overlapping the alignment mark with the auxiliary pattern in a height direction; the alignment mark comprises a plurality of second grid bars which are arranged in parallel along a second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the photoetching scanning direction.

10. A semiconductor device, comprising:

a plurality of wafer layers, the wafer layers including a main chip region and a marking region;

Wherein the plurality of wafer layers comprises at least one set of selected layers, each set of selected layers comprising a first wafer layer and a second wafer layer, the marking area of each set of selected layers being for accommodating a lithographic alignment structure according to any one of claims 1 to 8.