CN118232875A - Impedance matching device and method for eliminating process deviation - Google Patents
Impedance matching device and method for eliminating process deviation Download PDFInfo
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- CN118232875A CN118232875A CN202410463736.6A CN202410463736A CN118232875A CN 118232875 A CN118232875 A CN 118232875A CN 202410463736 A CN202410463736 A CN 202410463736A CN 118232875 A CN118232875 A CN 118232875A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/28—Impedance matching networks
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Abstract
The invention discloses an impedance matching device and method for eliminating process deviation, wherein the device comprises an impedance matching network, an off-chip precise resistor, an input voltage selection module capable of switching input signals, a comparator and an impedance calibration logic module, wherein the impedance matching network and the off-chip precise resistor are respectively connected with a group of resistors in series, and the resistance ratio of the series resistors connected with the impedance matching network and the off-chip precise resistor is 1: n; the node voltage V_1 of the impedance matching network and the node voltage V_2 corresponding to the branch where the off-chip precision resistor is located are respectively input into an input voltage selection module, the output of the input voltage selection module is connected with the input of a comparator, the output end of the comparator is connected with the input end of an impedance calibration logic module, and the output end of the impedance calibration logic module is connected with the impedance matching network; the invention has the advantages that: the bias caused by the analog circuit can be eliminated, high-precision impedance matching can be realized, and meanwhile, circuit consumption is not increased.
Description
Technical Field
The invention relates to the field of impedance matching, in particular to an impedance matching device and method for eliminating process deviation.
Background
With the acceleration of data transmission rate, high-speed serial interfaces (serdes) are widely used, and high-speed channels bring great high-frequency loss, so that the amplitude of high-frequency components of signals is small, and the reflection is increased due to the mismatching of the impedance of a transmitting end and a receiving end and the impedance of the channels, so that the high-frequency components are further lost. To solve this problem, an impedance matching circuit is required. The impedance matching circuit needs to be implemented by an analog part, and the analog part is greatly affected by process deviation, for example, the process deviation of an input pair tube of a comparator can cause a certain deviation of matched impedance, so that signal loss is caused. Accordingly, there is a need to design an impedance matching apparatus and method that eliminates process variations.
Chinese patent publication No. CN109729295A discloses a transmitting end driving circuit and method, generating a calibration control signal; generating a calibration current based on the calibration control signal to obtain a bias voltage; and amplifying the signal to be output under the action of the bias voltage, and obtaining a stable output signal through impedance matching. Fig. 1 is a schematic diagram of a transmitting-side driving circuit of the patent application, and it can be seen from fig. 1 that the impedance of each driving unit is unchanged, and an adjustable resistor between P and N is used to adjust the amplitude, instead of realizing impedance matching with a channel. Fig. 2 is a schematic structural diagram of the calibration control unit of the patent application, which only realizes 1 between the resistor array and the external resistor: 1, the off-chip precise resistance is generally large, for a typical 50 ohm channel on a PCB, N is required: 1, and the comparator has certain process deviation in actual production, the comparison result and the digital module have certain resistance value deviation in cooperation, the deviation generated by the analog circuit can only be eliminated by the analog circuit, and the successive approximation module cannot be eliminated.
Disclosure of Invention
The invention aims to solve the technical problem that the deviation of an analog circuit in an impedance matching calibration circuit in the prior art cannot be eliminated.
The invention solves the technical problems by the following technical means: the utility model provides an eliminate impedance matching device of technology deviation, includes impedance matching network, off-chip precision resistance, can carry out input voltage selection module, comparator and the impedance calibration logic module of adjusting to the signal of input, impedance matching network, off-chip precision resistance connect a set of series connection resistance respectively and impedance matching network, the resistance ratio of the series connection resistance that off-chip precision resistance connected is 1: n; the node voltage V_1 of the impedance matching network and the node voltage V_2 corresponding to the branch where the off-chip precision resistor is located are respectively input into an input voltage selection module, the output of the input voltage selection module is connected with the input of a comparator, the output end of the comparator is connected with the input end of an impedance calibration logic module, and the output end of the impedance calibration logic module is connected with the impedance matching network.
Further, the impedance matching network is connected in series with a set of resistors and then grounded.
Further, the off-chip precision resistor is connected in series with another set of resistors and then grounded.
Further, the number of the series resistors connected with the impedance matching network and the off-chip precision resistor is the same.
Further, the node voltage v_1 of the impedance matching network and the node voltage v_2 corresponding to the branch where the off-chip precision resistor is located are respectively input to two input ends of the input voltage selection module, two output ends of the input voltage selection module respectively output a voltage VP and a voltage VN, and the voltage VP and the voltage VN are respectively input to the in-phase end and the anti-phase end of the comparator.
Further, the input voltage selection module includes a first transmission gate and a second transmission gate, and the node voltage v_1 and the node voltage v_2 are respectively input to the first transmission gate and the second transmission gate to obtain the voltage VP.
Further, the input voltage selection module includes a third transmission gate and a fourth transmission gate, and the node voltage v_1 and the node voltage v_2 are respectively input to the third transmission gate and the fourth transmission gate to obtain the voltage VN.
The invention also provides a method of an impedance matching device for eliminating process deviation, the method comprising:
The input voltage selection module inputs the node voltage V_1 and the node voltage V_2 into the comparator, the comparator inputs the signals into the impedance calibration logic module to obtain a first control code, the input voltage selection module inputs the position of the node voltage V_1 and the node voltage V_2 into the comparator in a switching mode, the comparator inputs the signals into the impedance calibration logic module to obtain a second control code, the impedance calibration logic module carries out algorithm processing on the first control code and the second control code, offset voltage of the comparator is eliminated, a final control code is obtained, and the final control code is input into the impedance matching network to control impedance matching.
Further, the two output ends of the input voltage selection module respectively output a voltage VP and a voltage VN, the voltage VP and the voltage VN are respectively input into an in-phase end and an opposite-phase end of the comparator, the comparator has offset voltage, the node voltage v_1 and the node voltage v_2 can be exchanged by utilizing the input voltage selection module, before exchanging, the result output by the comparator is the result of adding the offset voltage, after exchanging, the result output by the comparator is the result of subtracting the offset voltage, and the impedance calibration logic module respectively obtains a first control code and a second control code before exchanging operation and after exchanging operation of the input voltage selection module.
Further, the algorithm processing process is as follows:
And the impedance calibration logic module adds the first control code and the second control code, then averages the added control codes, and eliminates the offset voltage of the comparator to obtain the final control code.
The invention has the advantages that:
(1) The input voltage selection module can exchange the input signals, the comparator has offset voltage, the output result of the comparator is the result of adding offset voltage before exchange, the output result of the comparator is the result of subtracting offset voltage after exchange, and the impedance calibration logic module receives the signals of the comparator before and after exchange operation by the input voltage selection module, so that offset voltage can be eliminated, deviation caused by an analog circuit can be eliminated, high-precision impedance matching is realized, and circuit consumption is not increased.
(2) The resistance ratio of the series resistors connected with the impedance matching network and the off-chip precision resistor is 1: n, thus can provide the terminating resistance and any proportion resistance value of the accurate resistance outside the chip, realize the impedance matching network and any impedance matching of the accurate resistance outside the chip.
Drawings
FIG. 1 is a schematic diagram of a prior art transmitter driver circuit;
FIG. 2 is a schematic diagram of a prior art calibration control unit;
fig. 3 is a schematic structural diagram of an impedance matching device for eliminating process deviation according to an embodiment of the present invention;
FIG. 4 is a schematic flow chart of an impedance matching method for eliminating process deviation according to an embodiment of the present invention;
Fig. 5 is a schematic structural diagram of an input voltage selection module in an impedance matching device for eliminating process deviation according to an embodiment of the present invention, wherein fig. 5 (a) is a schematic diagram of an output voltage VP of the input voltage selection module, and fig. 5 (b) is a schematic diagram of an output voltage VN of the input voltage selection module;
fig. 6 is a schematic diagram of a comparator in an impedance matching device for eliminating process deviation according to an embodiment of the present invention, wherein fig. 6 (a) is a schematic diagram of signals of a comparator before the node voltage v_1 and the node voltage v_2 are exchanged, and fig. 6 (b) is a schematic diagram of signals of a comparator after the node voltage v_1 and the node voltage v_2 are exchanged.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 3 and fig. 4, the present invention provides an impedance matching device for eliminating process deviation, which includes an impedance matching network, an off-chip precision resistor, an input voltage selecting module capable of modulating an input signal, a comparator and an impedance calibration logic module, wherein the impedance matching network and the off-chip precision resistor are respectively connected with a group of resistors in series, and the resistance ratio of the series resistors connected with the impedance matching network and the off-chip precision resistor is 1: and N, the number of resistors connected in series between the impedance matching network and the off-chip precision resistor is the same. The node voltage V_1 of the impedance matching network and the node voltage V_2 corresponding to the branch where the off-chip precision resistor is located are respectively input to two input ends of the input voltage selection module, two output ends of the input voltage selection module respectively output voltage VP and voltage VN, and the voltage VP and the voltage VN are respectively input to the in-phase end and the anti-phase end of the comparator. The output end of the comparator is connected with the input end of the impedance calibration logic module, and the output end of the impedance calibration logic module is connected with the impedance matching network. In FIG. 3, control code <6:0> represents a 6-bit impedance control code, RESISTIVE NETWORK represents an impedance matching network or an impedance calibration network, offchip resistor represents an off-chip precision resistor, mux sel represents input voltage selection or input signal selection, and resistor calibration logic represents impedance calibration logic.
As a further improvement of the present invention, as shown in fig. 5 (a), the input voltage selection module includes a first transmission gate and a second transmission gate, and the node voltage v_1 and the node voltage v_2 are respectively input to the first transmission gate and the second transmission gate to obtain the voltage VP. As shown in fig. 5 (b), the input voltage selection module includes a third transmission gate and a fourth transmission gate, and the node voltage v_1 and the node voltage v_2 are respectively input to the third transmission gate and the fourth transmission gate to obtain the voltage VN.
The input voltage selection module inputs the node voltage V_1 and the node voltage V_2 into the comparator, the comparator inputs the signals into the impedance calibration logic module to obtain a first control code, the input voltage selection module inputs the position of the node voltage V_1 and the node voltage V_2 into the comparator in a switching mode, the comparator inputs the signals into the impedance calibration logic module to obtain a second control code, the impedance calibration logic module adds the first control code and the second control code and then averages the first control code and the second control code, offset voltage of the comparator is eliminated, a final control code is obtained, and the final control code is input into the impedance matching network to control impedance matching. As shown in fig. 6 (a) and 6 (b), the principle of eliminating offset voltage is: the comparator has offset voltage, the node voltage V_1 and the node voltage V_2 can be exchanged by the input voltage selection module, the result output by the comparator is the result of adding the offset voltage before the exchange, the result output by the comparator is the result of subtracting the offset voltage after the exchange, and the impedance calibration logic module respectively obtains a first control code and a second control code before the exchange operation and after the exchange operation of the input voltage selection module. Vos in fig. 6 represents offset voltage, compare_out represents comparator output.
Through the technical scheme, the impedance matching network and the off-chip precise resistor are divided into two branches according to 1: n is set in proportion relation, corresponding node voltages are selected from the two branches, V_1 and V_2 are sent to an input voltage selection module, and VP or VN can be respectively corresponding to the two input voltages. The result of VP and VN comparison in the comparator is sent to an impedance calibration logic module to obtain an impedance matching control code <6:0> to control impedance matching. V_1 and V_2 are respectively compared at the P/N N/P end of the comparator for 2 times to obtain control codes related to the offset voltage of the comparator, and the results of the two control codes are the results of adding the offset voltage and subtracting the offset voltage. The impedance calibration logic module performs calibration in the manner of fig. 4, performs two-round calibration, performs impedance matching code calibration by using the results of the forward bias of the comparator and the exchange input of the comparator, and uses the matching code with analog deviation to eliminate the influence of the manufacturing deviation of the comparator through an algorithm, thereby realizing high-precision impedance matching without increasing circuit consumption.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The impedance matching device for eliminating the process deviation is characterized by comprising an impedance matching network, an off-chip precise resistor, an input voltage selection module capable of switching an input signal, a comparator and an impedance calibration logic module, wherein the impedance matching network and the off-chip precise resistor are respectively connected with a group of resistors in series, and the resistance ratio of the series resistors connected with the impedance matching network and the off-chip precise resistor is 1: n; the node voltage V_1 of the impedance matching network and the node voltage V_2 corresponding to the branch where the off-chip precision resistor is located are respectively input into an input voltage selection module, the output of the input voltage selection module is connected with the input of a comparator, the output end of the comparator is connected with the input end of an impedance calibration logic module, and the output end of the impedance calibration logic module is connected with the impedance matching network.
2. An impedance matching device for eliminating process variation according to claim 1, wherein said impedance matching network is connected in series with a set of resistors and then connected to ground.
3. An impedance matching device for eliminating process variation according to claim 1, wherein said off-chip precision resistor is connected in series with another set of resistors and then connected to ground.
4. The apparatus of claim 1, wherein the number of resistors connected in series between the impedance matching network and the off-chip precision resistor is the same.
5. The impedance matching device for eliminating process deviation according to claim 1, wherein the node voltage v_1 of the impedance matching network and the node voltage v_2 corresponding to the branch where the off-chip precision resistor is located are respectively input to two input ends of the input voltage selection module, and the two output ends of the input voltage selection module respectively output a voltage VP and a voltage VN, and the voltage VP and the voltage VN are respectively input to the non-inverting end and the inverting end of the comparator.
6. The apparatus of claim 5, wherein the input voltage selection module includes a first transmission gate and a second transmission gate, and the node voltage v_1 and the node voltage v_2 are respectively input to the first transmission gate and the second transmission gate to obtain the voltage VP.
7. The apparatus of claim 5, wherein the input voltage selection module includes a third transmission gate and a fourth transmission gate, and the node voltage v_1 and the node voltage v_2 are respectively input to the third transmission gate and the fourth transmission gate to obtain the voltage VN.
8. A method of an impedance matching device for eliminating process variation according to any one of claims 1-7, comprising:
The input voltage selection module inputs the node voltage V_1 and the node voltage V_2 into the comparator, the comparator inputs the signals into the impedance calibration logic module to obtain a first control code, the input voltage selection module inputs the position of the node voltage V_1 and the node voltage V_2 into the comparator in a switching mode, the comparator inputs the signals into the impedance calibration logic module to obtain a second control code, the impedance calibration logic module carries out algorithm processing on the first control code and the second control code, offset voltage of the comparator is eliminated, a final control code is obtained, and the final control code is input into the impedance matching network to control impedance matching.
9. The method of claim 8, wherein the two output terminals of the input voltage selection module output voltage VP and voltage VN, respectively, the voltage VP and voltage VN are input to the in-phase terminal and the opposite-phase terminal of the comparator, respectively, the comparator has offset voltage, the node voltage v_1 and the node voltage v_2 can be exchanged by using the input voltage selection module, the result output by the comparator is the result of adding the offset voltage before the exchange, the result output by the comparator is the result of subtracting the offset voltage after the exchange, and the impedance calibration logic module obtains the first control code and the second control code before the exchange operation and after the exchange operation by the input voltage selection module, respectively.
10. The method of an impedance matching device for eliminating process variation according to claim 9, wherein the algorithm processing is as follows:
And the impedance calibration logic module adds the first control code and the second control code, then averages the added control codes, and eliminates the offset voltage of the comparator to obtain the final control code.
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| CN202410463736.6A CN118232875A (en) | 2024-04-17 | 2024-04-17 | Impedance matching device and method for eliminating process deviation |
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| CN202410463736.6A CN118232875A (en) | 2024-04-17 | 2024-04-17 | Impedance matching device and method for eliminating process deviation |
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Country or region after: China Address after: Building 10, Sino German Cooperation and Innovation Demonstration Park, Intersection of Qingtan Road and Zipeng Road, Economic and Technological Development Zone, Hefei City, Anhui Province, 230000 Applicant after: Hefei Institute of innovation and development, Tianjin University Applicant after: Anhui Zhuozhan Electronic Technology Co.,Ltd. Address before: Building 37, Sino German Cooperation Innovation Demonstration Park, the intersection of Qingtan Road and Zipeng Road, Hefei Economic and Technological Development Zone, 230000, Anhui Province Applicant before: Hefei Institute of innovation and development, Tianjin University Country or region before: China Applicant before: Anhui Zhuozhan Electronic Technology Co.,Ltd. |
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