CN211319101U

CN211319101U - Self-adaptive and calibrated ODT (on-die termination) circuit applied to FPGA (field programmable Gate array)

Info

Publication number: CN211319101U
Application number: CN201922442707.9U
Authority: CN
Inventors: 冯晓玲; 姬晶; 孟智凯; 贾红; 陈维新; 韦嶔; 程显志
Original assignee: XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Current assignee: XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-08-21
Anticipated expiration: 2029-12-30

Abstract

The utility model relates to a be applied to self-adaptation correctable ODT circuit of FPGA, include: the device comprises an ODT circuit module, a first calibration module and a second calibration module, wherein the ODT circuit module comprises a first terminal resistance unit and a second terminal resistance unit, and the first terminal resistance unit and the second terminal resistance unit respond to the voltage change of a transmission signal and finish self-adaptive trimming to keep impedance unchanged; the first calibration module is connected with the first terminal resistance unit and used for calibrating the first terminal resistance unit; the second calibration module is connected with the second terminal resistance unit and used for calibrating the second terminal resistance unit. The utility model discloses a be applied to self-adaptation correctable ODT circuit of FPGA, the terminal resistance of the ODT circuit module of setting can the automatically regulated circuit electric current when the signal amplitude of oscillation of transmission changes, makes its terminal matching resistance's impedance keep unchangeable.

Description

Self-adaptive and calibrated ODT (on-die termination) circuit applied to FPGA (field programmable Gate array)

Technical Field

The utility model belongs to the technical field of FPGA's high-speed interface, concretely relates to be applied to FPGA's self-adaptation correctable ODT circuit.

Background

An FPGA is a logic device composed of many logic units, wherein the logic units include gates, lookup tables and flip-flops, and the FPGA has rich hardware resources, strong parallel processing capability and flexible reconfigurable capability, and is increasingly and widely applied in many fields such as data processing, communication, network and the like.

With the development of integrated circuits, the interface transmission speed is higher and higher. When the transmitter and the receiver carry out high-speed communication, because the transmission line has characteristic impedance, a matching resistor with the same value as the characteristic impedance of the transmission line is accessed to the input end of the receiver side, so that signal reflection is reduced, and the signal transmission quality is ensured. The ODT (On Die Termination) circuit integrates an off-chip matching resistor inside a chip to realize impedance matching. The impedance matching has two circuit forms, as shown in fig. 1a-1b, one is that an input terminal is connected with a pull-up resistor to be connected with vccio/2, the other is that the input terminal is connected with a resistor through pull-up and pull-down resistors, the pull-up resistor is connected with a power source vccio, the pull-down resistor is grounded, and finally a thevenin equivalent circuit is used as impedance matching. Generally, matching impedance of the ODT circuit is affected by PVT (process error, applied voltage factor and applied temperature factor in the chip manufacturing process) and voltage variation of the interface transmission signal, so that resistance value of the ODT circuit varies, and how to provide stable and accurate impedance matching becomes a difficulty of ODT.

SUMMERY OF THE UTILITY MODEL

In order to solve the above-mentioned problem that exists among the prior art, the utility model provides a be applied to FPGA's self-adaptation correctable ODT circuit. The to-be-solved technical problem of the utility model is realized through following technical scheme:

the utility model provides a be applied to self-adaptation correctable ODT circuit of FPGA, a serial communication port, include: an ODT circuit module, a first calibration module, and a second calibration module, wherein the ODT circuit module includes a first termination resistance unit and a second termination resistance unit, wherein,

the first terminal resistance unit and the second terminal resistance unit respond to the voltage change of a transmission signal, and self-adaptive trimming is completed to keep impedance unchanged;

the first calibration module is connected with the first terminal resistance unit and is used for calibrating the first terminal resistance unit;

the second calibration module is connected with the second terminal resistance unit and is used for calibrating the second terminal resistance unit;

the first calibration module comprises a first current mirror unit, a reference resistor, a comparator and a control unit, wherein,

the first current mirror unit is used for providing a first current and a second current and connecting the reference resistor and the first terminal resistor unit;

the reference resistor is used for generating a reference voltage according to the first current, and the first terminal resistance unit is used for generating a first terminal resistance voltage according to the second current;

the reference voltage is input to a first input end of the comparator, the first terminal resistance voltage is input to a second input end of the comparator, and a comparison result is output from an output end of the comparator;

the control unit is connected with the output end of the comparator and used for outputting a control signal according to the comparison result, and the first terminal resistance unit responds to the control signal to finish calibration;

the second calibration module comprises a second current mirror unit, the reference resistor, the comparator and the control unit, the connection relation of the second calibration module is the same as that of the first calibration module, and the second terminal resistor unit responds to the control signal to complete calibration.

In one embodiment of the present invention, the first termination resistance unit includes a first PMOS transistor, a first enable portion, and a plurality of first equivalent resistance portions, wherein,

the grid electrode of the first PMOS tube is connected with the signal transmission end, and the drain electrode of the first PMOS tube is connected with the grounding end;

the first enabling part is connected between the power supply voltage end and the source electrode of the first PMOS tube in series;

the first equivalent resistor parts are connected between the signal transmission end and the grounding end in parallel.

In one embodiment of the present invention, the first enabling portion comprises an inverter, an NMOS transistor, a PMOS transistor, and a transmission gate, wherein,

the input end of the phase inverter receives a second enabling signal, and the output end of the phase inverter is connected with the grid electrode of the NMOS tube;

the drain electrode of the NMOS tube is connected with the power supply voltage end, and the source electrode of the NMOS tube is connected with the source electrode of the first PMOS tube;

the source electrode of the PMOS tube is connected with the power supply voltage end, and the drain electrode of the PMOS tube is connected with the source electrode of the first PMOS tube;

the input end of the transmission gate is connected with the grounding end, the output end of the transmission gate is connected with the grid electrode of the PMOS tube, the control end of the transmission gate respectively receives a first enabling signal and a second enabling signal, and the first enabling signal and the second enabling signal are a pair of differential signals.

In one embodiment of the present invention, the first equivalent resistor portion includes an inverter, two NMOS transistors and a transmission gate, wherein,

the input end of the phase inverter receives the control signal, and the output end of the phase inverter is connected with the grid electrode of the NMOS tube;

the drain electrodes of the two NMOS tubes are connected with the signal transmission end, and the source electrodes of the two NMOS tubes are connected with the grounding end;

the input end of the transmission gate is connected with the source electrode of the first PMOS tube, the output end of the transmission gate is connected with the grid electrode of the other NMOS tube, and the control end of the transmission gate receives the control signal.

In one embodiment of the present invention, the second termination resistance unit includes a first NMOS transistor, a second enable portion, and a plurality of second equivalent resistance portions, wherein,

the grid electrode of the first NMOS tube is connected with the signal transmission end, and the drain electrode of the first NMOS tube is connected with the power supply voltage end;

the second enabling part is connected between the source electrode of the first NMOS tube and the grounding end in series;

the second equivalent resistance parts are connected in parallel between the power supply voltage end and the signal transmission end.

In one embodiment of the present invention, the second enabling portion comprises an inverter, an NMOS transistor, a PMOS transistor, and a transmission gate, wherein,

the input end of the phase inverter receives a first enabling signal, and the output end of the phase inverter is connected with the grid electrode of the PMOS tube;

the source electrode of the PMOS tube is connected with the source electrode of the first NMOS tube, and the drain electrode of the PMOS tube is connected with the grounding end;

the drain electrode of the NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the NMOS tube is connected with the grounding end;

the input end of the transmission gate is connected with the power supply voltage end, the output end of the transmission gate is connected with the grid electrode of the NMOS tube, the control end of the transmission gate receives a first enabling signal and a second enabling signal respectively, and the first enabling signal and the second enabling signal are a pair of differential signals.

In one embodiment of the present invention, the second equivalent resistor portion includes an inverter, two PMOS transistors and a transmission gate, wherein,

the input end of the phase inverter receives the control signal, and the output end of the phase inverter is connected with the grid electrode of one PMOS tube;

the source electrodes of the two PMOS tubes are connected with the power supply voltage end, and the drain electrodes of the two PMOS tubes are connected with the signal transmission end;

the input end of the transmission gate is connected with the source electrode of the first NMOS tube, the output end of the transmission gate is connected with the grid electrode of the other PMOS tube, and the control end of the transmission gate receives the control signal.

In one embodiment of the present invention, the first current mirror unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a first switch, a second switch, a third switch, and a current source, wherein,

the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are PMOS transistors;

the source electrodes of the first MOS transistor, the third MOS transistor and the fifth MOS transistor are all connected with the power supply voltage end;

the grid electrode of the first MOS tube is respectively connected with the grid electrode of the third MOS tube, the drain electrode of the second MOS tube and the grid electrode of the fifth MOS tube;

the source electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, the grid electrode of the second MOS tube is respectively connected with the grid electrode of the fourth MOS tube and the grid electrode of the sixth MOS tube, and the grid electrode bias voltage of the second MOS tube is provided by a band gap circuit in the FPGA chip;

the source electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the sixth MOS tube is connected with the drain electrode of the fifth MOS tube;

the first switch and the current source are sequentially connected in series between the drain electrode of the second MOS tube and a grounding end;

the second switch is connected between the drain electrode of the fourth MOS tube and the reference resistor in series;

the third switch is connected in series between the drain of the sixth MOS tube and the first terminal resistance unit.

In an embodiment of the present invention, a first terminal of the reference resistor is connected to the first input terminal of the comparator, and a second terminal of the reference resistor is connected to the ground terminal.

In an embodiment of the present invention, the control unit includes a counter, a temperature decoder, a controller, and a fourth switch connected in sequence, wherein the input terminal of the counter is connected to the output terminal of the comparator, and the fourth switch is connected to the ODT circuit module.

Compared with the prior art, the beneficial effects of the utility model reside in that:

1. the utility model discloses a be applied to self-adaptation correctable ODT circuit of FPGA, the terminal resistance of the ODT circuit module of setting can the automatically regulated circuit electric current when the signal amplitude of oscillation of transmission changes, makes its terminal matching resistance's impedance keep unchangeable.

2. The utility model discloses a be applied to self-adaptation correctable ODT circuit of FPGA is provided with calibration module, can calibrate terminal matching resistance's impedance through calibration module, has reduced the influence of PVT to its impedance.

3. The utility model discloses a be applied to self-adaptation correctable ODT circuit of FPGA, based on FPGA's configurability, can repair and transfer terminal matched resistance and make its adaptation different agreements.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

FIGS. 1a-1b illustrate a prior art impedance matching scheme provided by the present invention;

fig. 2 is a schematic block diagram of an adaptive calibratable ODT circuit applied to an FPGA according to an embodiment of the present invention;

fig. 3 is a circuit diagram of an ODT circuit module according to an embodiment of the present invention;

fig. 4 is a circuit structure diagram of a first calibration module according to an embodiment of the present invention;

fig. 5 is a circuit structure diagram of a second calibration module according to an embodiment of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the objectives of the present invention, the following description will be made in conjunction with the accompanying drawings and the detailed description of the embodiments, so as to explain in detail the adaptive and calibrated ODT circuit applied to the FPGA according to the present invention.

The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention to achieve the predetermined objects can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are only for reference and description and are not intended to limit the technical solution of the present invention.

Example one

Referring to fig. 2, fig. 2 is a block diagram of an adaptive and calibratable ODT circuit applied to an FPGA according to an embodiment of the present invention. As shown in the figure, the adaptive calibratable ODT circuit applied to the FPGA of the present embodiment includes an ODT circuit module 1, a first calibration module 2, and a second calibration module 3, where the ODT circuit module 1 includes a first termination resistance unit 101 and a second termination resistance unit 102, where the first termination resistance unit 101 and the second termination resistance unit 102 perform adaptive trimming to keep impedance unchanged in response to a voltage change of a transmission signal; the first calibration module 2 is connected to the first terminal resistance unit 101, and is configured to calibrate the first terminal resistance unit 101; the second calibration module 3 is connected to the second terminal resistance unit 102, and is configured to calibrate the second terminal resistance unit 102; the first calibration module 2 comprises a first current mirror unit a1, a reference resistor Req, a comparator COMP and a control unit B, wherein the first current mirror unit a1 is configured to provide a first current and a second current, and is connected to the reference resistor Req and the first terminal resistor unit 101; the reference resistor Req is used for generating a reference voltage according to the first current, and the first termination resistor unit 101 is used for generating a first termination resistor voltage according to the second current; a first input end of the comparator COMP inputs a reference voltage, a second input end of the comparator COMP inputs a first terminal resistor voltage, and an output end of the comparator COMP outputs a comparison result; the control unit B is connected with the output end of the comparator COMP and used for outputting a control signal according to the comparison result, and the first terminal resistance unit 101 responds to the control signal to finish calibration; the second calibration module 3 includes a second current mirror unit a2, a reference resistor Req, a comparator COMP, and a control unit B, which are connected in the same relationship as the first calibration module 2, and the second terminal resistance unit 102 completes calibration in response to a control signal.

Referring to fig. 3 in combination, fig. 3 is a circuit structure diagram of an ODT circuit module according to an embodiment of the present invention, and specifically, the first termination resistor unit 101 includes a first PMOS transistor PM1, a first enabling portion and a plurality of first equivalent resistor portions R1, where a gate of the first PMOS transistor PM1 is connected to a signal transmission terminal, and a drain of the first PMOS transistor PM1 is connected to a ground terminal GND; the first enabling part is connected between a power supply voltage end vccio and a source electrode of a first PMOS pipe PM1 in series; the first equivalent resistor portions R1 are connected in parallel between the signal transmission terminal and the ground terminal GND.

In this embodiment, the first enabling part comprises an inverter, an NMOS transistor, a PMOS transistor and a transmission gate, wherein an input terminal of the inverter receives the second enabling signal

The output end is connected with the grid of the NMOS tube; the drain electrode of the NMOS tube is connected with a power supply voltage end vccio, and the source electrode of the NMOS tube is connected with the source electrode of a first PMOS tube PM 1; the source electrode of the PMOS tube is connected with a power voltage end vccio, and the drain electrode of the PMOS tube is connected with the source electrode of the first PMOS tube PM 1; the input end of the transmission gate is connected with a ground end GND, the output end of the transmission gate is connected with the grid electrode of the PMOS tube, and the control end of the transmission gate respectively receives a first enable signal en and a second enable signal en

The first equivalent resistor part R1 comprises a phase inverter, two NMOS tubes and a transmission gate, wherein the input end of the phase inverter receives a control signal, and the output end of the phase inverter is connected with the grid electrode of one NMOS tube; the drain electrodes of the two NMOS tubes are connected with a signal transmission end, and the source electrodes of the two NMOS tubes are connected with a ground end GND; the input end of the transmission gate is connected with the source electrode of the first PMOS pipe PM1, the output end of the transmission gate is connected with the grid electrode of the other NMOS pipe, and the control end of the transmission gate receives a control signal.

In the present embodiment, a first enable signal en and a second enable signal

For a pair of differential signals, the first enabling part controls the opening and closing of the first termination resistance unit 101 according to the received enabling signal, and a plurality of first equivalent resistance parts R1 connected in parallel are opened and closed according to the received control signalAnd the adjustment of the equivalent resistance values of the plurality of first equivalent resistance portions R1 is realized.

Further, the second terminal resistance unit 102 includes a first NMOS transistor NM1, a second enable portion, and a plurality of second equivalent resistance portions R2, wherein a gate of the first NMOS transistor NM1 is connected to the signal transmission terminal, and a drain is connected to the power supply voltage terminal vccio; the second enable part is connected in series between the source of the first NMOS transistor NM1 and the ground GND; a plurality of second equivalent resistance portions R2 are connected in parallel between the power supply voltage terminal vccio and the signal transmission terminal.

In this embodiment, the second enabling portion includes an inverter, an NMOS transistor, a PMOS transistor, and a transmission gate, where an input end of the inverter receives the first enabling signal en, and an output end of the inverter is connected to a gate of the PMOS transistor; the source electrode of the PMOS tube is connected with the source electrode of the first NMOS tube NM1, and the drain electrode of the PMOS tube is connected with the ground end GND; the drain electrode of the NMOS tube is connected with the source electrode of the first NMOS tube NM1, and the source electrode is connected with the ground end GND; the input end of the transmission gate is connected with a power supply voltage end vccio, the output end of the transmission gate is connected with the grid electrode of the NMOS tube, and the control end of the transmission gate respectively receives a first enable signal en and a second enable signal en

The second equivalent resistor part R2 comprises a phase inverter, two PMOS tubes and a transmission gate, wherein the input end of the phase inverter receives a control signal, and the output end of the phase inverter is connected with the grid electrode of one PMOS tube; the source electrodes of the two PMOS tubes are connected with a power supply voltage end vccio, and the drain electrodes of the two PMOS tubes are connected with a signal transmission end; the input end of the transmission gate is connected with the source electrode of the first NMOS transistor NM1, the output end of the transmission gate is connected with the grid electrode of the other PMOS transistor, and the control end of the transmission gate receives a control signal.

In the present embodiment, a first enable signal en and a second enable signal

The second enabling part controls the opening and closing of the second terminal resistance unit 102 according to the received enabling signal, and the second equivalent resistance part R2 opens and closes according to the received control signal, so as to realize the adjustment of the equivalent resistance values of the plurality of second equivalent resistance parts R2.

Further, please refer to fig. 4, fig. 4 is a circuit structure diagram of a first calibration module according to an embodiment of the present invention, and as shown in the figure, the first current mirror unit a1 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a first switch S1, a second switch S2, a third switch S3, and a current source IB, where the current source IB is provided by a bandgap circuit in the FPGA chip, and the current is an ideal current source independent of the power voltage and the temperature.

The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 are all PMOS transistors; the source electrodes of the first MOS transistor M1, the third MOS transistor M3 and the fifth MOS transistor M5 are all connected with a power supply voltage end vccio; the grid electrode of the first MOS transistor M1 is respectively connected with the grid electrode of the third MOS transistor M3, the drain electrode of the second MOS transistor M2 and the grid electrode of the fifth MOS transistor M5; the source electrode of the second MOS transistor M2 is connected with the drain electrode of the first MOS transistor M1, the grid electrodes of the second MOS transistor M2 and the sixth MOS transistor M6 are respectively connected with the grid electrode of the fourth MOS transistor M4 and the grid electrode of the sixth MOS transistor M6, and the grid electrode bias voltage pbias of the second MOS transistor M2 is provided by a band gap circuit in the FPGA chip; the source electrode of the fourth MOS transistor M4 is connected with the drain electrode of the third MOS transistor M3, and the source electrode of the sixth MOS transistor M6 is connected with the drain electrode of the fifth MOS transistor M5; the first switch S1 and the current source IB are sequentially connected in series between the drain of the second MOS transistor M2 and the ground GND; the second switch S2 is connected in series between the drain of the fourth MOS transistor M4 and the reference resistor Req; the third switch S3 is connected in series between the drain of the sixth MOS transistor M6 and the first termination resistor unit 101, and the other end of the first termination resistor unit 101 is connected to the ground GND. The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 form a cascode current mirror structure according to electric connection, and current required by mirror image can be accurately provided.

The first end of the reference resistor Req is connected to the first input terminal of the comparator COMP, and the second end is connected to the ground terminal GND. The control unit B comprises a counter B1, a temperature decoder B2, a controller B3 and a fourth switch S4 which are sequentially connected, wherein the input end of the counter B1 is connected with the output end of the comparator COMP, and the fourth switch S4 is connected with the input ends of inverters of the first equivalent resistor parts R1 and the control end of the transmission gate.

Further, please refer to fig. 5, fig. 5 is a circuit structure diagram of a second calibration module according to an embodiment of the present invention, and as shown in the figure, it is noted that the second current mirror unit a2 further includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, and a fifth switch S5, compared with the first current source unit a 1. The seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all NMOS transistors.

The third switch S3 is connected in series between the drain of the sixth MOS transistor M6 and the drain of the seventh MOS transistor M7; the gate of the seventh MOS transistor M7 is connected to the gate of the ninth MOS transistor M9, and the source is connected to the drain of the eighth MOS transistor M8; the gate of the eighth MOS transistor M8 is connected to the drain of the seventh MOS transistor M7 and the gate of the tenth MOS transistor M10, respectively, and the source of the eighth MOS transistor M8 and the source of the tenth MOS transistor M10 are both connected to the ground GND; the source electrode of the ninth MOS transistor M9 is connected with the drain electrode of the tenth MOS transistor M10; the fifth switch S5 is connected in series between the drain of the ninth MOS transistor M9 and the second terminal resistance unit 102, and the other end of the second terminal resistance unit 102 is connected to the power supply voltage terminal vccio; the fourth switch S4 is connected to the inverter input terminals of the second equivalent resistor units R2 and the control terminal of the transmission gate. The gate bias voltage nbias of the seventh MOS transistor M7 is provided by a bandgap circuit inside the FPGA chip. In this embodiment, since the source terminal of the second equivalent resistor R2 is connected to the power supply terminal in the ODT circuit module 1, a mirror current source formed by electrically connecting the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10 needs to be added to provide a current required for mirroring, and the mirror ratio is 1: 1.

the adaptive calibratable ODT circuit applied to the FPGA of this embodiment may automatically adjust a circuit current when a terminal resistance of the set ODT circuit module changes a swing of a signal transmitted, so that an impedance of a terminal matching resistance of the ODT circuit module remains unchanged. Moreover, the calibration module is arranged, so that the impedance of the terminal matching resistor can be calibrated through the calibration module, and the influence of PVT on the impedance is reduced. In addition, the adaptive calibratable ODT circuit applied to the FPGA of this embodiment may modify the terminal matching resistance to adapt to different protocols based on the configurability of the FPGA.

Further, a specific operation process of the adaptively calibratable ODT circuit applied to the FPGA of the present embodiment, which includes an ODT calibration circuit, i.e., the first calibration module 2 and the second calibration module 3, and an ODT circuit, i.e., the ODT circuit module 1, will be described as follows. The operation of the ODT calibration circuit will be described by taking the first calibration module 2 as an example.

The first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are closed, and the first calibration module 2 forms a current I2 and a current I3 through the first current mirror unit a1 based on the current I1 formed by the current source IB, wherein the current I2 and the current I3 are proportional mirror currents of the current I1, wherein I2 is I1, I3 is I2, and in this embodiment, the current I2 is used as the first current and the current I3 is used as the second current. As shown in fig. 4, the reference resistor Req and the current I2 generate a reference voltage Vref ═ vccio/2; the first termination resistance unit 101 and the current I3 generate a voltage V1. Wherein, the proportional relationship between the resistance value of the reference resistor Req and the equivalent resistance value of the first termination resistor unit 101 is I3/I2. For example, if the equivalent resistance value of the first termination resistor unit 101 is 100 Ω according to the protocol requirement, the resistance value of the reference resistor Req is 1000 Ω. The reference resistor Req is an internal trimmable resistor that can be trimmed according to protocol specifications, such as 800 Ω/1000 Ω/1200 Ω. The protocol of the trimming thereof is the same as that of the trimming of the first termination resistance unit 101.

As shown in fig. 4, the voltage V1 is compared with the reference voltage vref, if the output of the comparator COMP is low, the counter B1 is incremented by 1, the temperature decoder B2 converts the binary count into a temperature code, the controller B3 outputs a control signal according to the temperature code to lower the impedance of the first termination resistance unit 101, and the first termination resistance unit 101 increases the number of on-state number of the first equivalent resistance parts R1 connected in parallel according to the received control signal, thereby reducing the impedance of the first termination resistance unit 101. Until the comparator COMP outputs high for the first time, the counter B1 latches, storing the control signal of the controller B3, at which time the calibration of the first terminal resistance unit 101 is completed, and then the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are turned off.

The voltage V1 is compared with the reference voltage vref, if the output of the comparator COMP is high, the counter B1 is decremented by 1, the temperature decoder B2 converts the binary count into a temperature code, the controller B3 outputs a control signal according to the temperature code to increase the impedance of the first termination resistance unit 101, and the first termination resistance unit 101 decreases the number of on-state of the first equivalent resistance parts R1 connected in parallel according to the received control signal, thereby increasing the impedance of the first termination resistance unit 101. Until the comparator COMP outputs low for the first time, the counter B1 latches, storing the control signal of the controller B3, at which time the calibration of the first terminal resistance unit 101 is completed, and then the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are turned off. In the present embodiment, the initial value of the counter B1 is given by the protocol, and is used to roughly adjust the impedance of the first termination resistance unit 101 under different protocols.

The calibration of the second calibration module 3 is the same as the calibration principle of the first calibration module 2, and is not described herein again.

Further, specifically describing the adaptive modulation process of the ODT circuit module of the present embodiment, as shown in fig. 3, the ODT circuit module 1 includes a first equivalent resistance portion R1 and a second equivalent resistance portion R2, each of the first equivalent resistance portion R1 and the second equivalent resistance portion R2 forms an impedance by a diode and a saturation region MOS transistor, and the first equivalent resistance portion R1 and the second equivalent resistance portion R2 can implement adaptive adjustment for the voltage change of the transmission signal so that the impedance thereof remains unchanged.

The second equivalent resistor R2 is used as a pull-up resistor, when the voltage vih of the transmission signal becomes high, the conductivity of the first NMOS transistor NM1 becomes large, and the voltage at the source P _ gate thereof becomes high, so that the conductivity of the PMOS transistor (P1 in the figure) at the second equivalent resistor R2 becomes small, the current I2 flowing through the PMOS transistor becomes small, and finally the impedance R2 thereof is kept substantially constant (vccio-vih)/I2. Conversely, when the voltage vih of the transmission signal becomes lower, the on-capability of the first NMOS transistor NM1 becomes smaller, and the voltage at the source P _ gate thereof decreases, so that the on-capability of the PMOS transistor (P1 in the figure) at the second equivalent resistor R2 becomes larger, the current I2 flowing through the PMOS transistor becomes larger, and finally the impedance R2 ═ vccio-vih)/I2 remains substantially unchanged.

The first equivalent resistance portion R1 acts as a pull-down resistor, and when the voltage vih of the transmission signal becomes high, the conductivity of the first PMOS transistor PM1 becomes small, and the voltage at the source N _ gate thereof rises, so that the conductivity of the NMOS transistor (N1 in the drawing) at the first equivalent resistance portion R1 becomes large, the current I1 flowing through the NMOS transistor becomes large, and finally the resistance R1 is kept substantially constant at vih/I1. On the contrary, when the voltage vih of the transmission signal becomes low, the conduction capability of the first PMOS transistor PM1 becomes high, and the voltage at the source N _ gate thereof decreases, so that the conduction capability of the NMOS transistor (N1 in the figure) at the first equivalent resistor R1 becomes low, and the flowing current I1 becomes low. Finally, the resistance R1 is vih/I1 and is kept basically unchanged. Thereby solving the problem that the impedance of the ODT circuit module 1 is affected by the voltage variation of the transmission signal.

Specifically, under the condition that the power supply voltage vccio is 1.5v, the voltage of the transmission signal changes from 0.2 × vccio to 0.8 × vccio, and the impedance differs by less than 1 Ω at maximum. Under the condition that the power supply voltage vccio is 1.35v, the voltage of the transmission signal changes from 0.2 to 0.8, and the impedance difference is at most 3 omega.

The adaptive and calibratable ODT circuit applied to the FPGA of this embodiment is used as follows, first, the plurality of first equivalent resistor portions R1 connected in parallel are turned on or off by a control signal of the controller B3 of the first calibration module 2, so as to implement trimming of the pull-down resistor impedance, and make it meet the impedance required by the protocol, the trimming is performed by the protocol, the protocol is fixed, the value of the counter B1 is fixed, the number of switches of the plurality of first equivalent resistor portions R1 connected in parallel is fixed, and for coarse tuning and for the same reason, the pull-up resistor impedance can also be trimmed in the same manner. Secondly, fine tuning is performed on the basis of the trimming, that is, the impedances of the first and second terminating

resistor units

101 and 102 are calibrated using the first and second calibration modules 2 and 3. In the working process, the impedance values of the first termination resistance unit 101 and the second termination resistance unit 102 can be adaptively adjusted according to the voltage change of the transmission signal. In the embodiment, the impedance value of each parallel first equivalent resistor R1 is proportional, the impedance value of each parallel second equivalent resistor R2 is proportional, and the controller B circuit modifies the impedance values through control signals (pen 1/nen1, pen2/nen2, pen3/nen3 … … in fig. 3).

The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.

Claims

1. An adaptively calibratable ODT circuit applied to an FPGA, comprising: an ODT circuit module (1), a first calibration module (2) and a second calibration module (3), wherein,

the ODT circuit module (1) includes a first termination resistance unit (101) and a second termination resistance unit (102), wherein,

the first terminal resistance unit (101) and the second terminal resistance unit (102) respond to the voltage change of a transmission signal and finish self-adaptive trimming to keep the impedance unchanged;

the first calibration module (2) is connected with the first terminal resistance unit (101) and is used for calibrating the first terminal resistance unit (101);

the second calibration module (3) is connected with the second terminal resistance unit (102) and is used for calibrating the second terminal resistance unit (102);

the first calibration module (2) comprises a first current mirror unit (A1), a reference resistor (Req), a Comparator (COMP) and a control unit (B), wherein,

the first current mirror unit (A1) is used for providing a first current and a second current, and is connected with the reference resistor (Req) and the first terminal resistor unit (101);

the reference resistor (Req) is used for generating a reference voltage according to the first current, and the first terminal resistor unit (101) is used for generating a first terminal resistor voltage according to the second current;

the reference voltage is input to a first input end of the Comparator (COMP), the first terminal resistor voltage is input to a second input end of the Comparator (COMP), and a comparison result is output from an output end of the Comparator (COMP);

the control unit (B) is connected with an output end of the Comparator (COMP) and used for outputting a control signal according to the comparison result, and the first terminal resistance unit (101) responds to the control signal to finish calibration;

the second calibration module (3) comprises a second current mirror unit (A2), the reference resistor (Req), the Comparator (COMP) and the control unit (B), the connection relation of the second calibration module (3) is the same as that of the first calibration module (2), and the second terminal resistor unit (102) completes calibration in response to the control signal.

2. The adaptively calibratable ODT circuit applied to an FPGA according to claim 1, wherein the first termination resistance unit (101) comprises a first PMOS transistor (PM1), a first enable section, and a number of first equivalent resistance sections (R1), wherein,

the grid electrode of the first PMOS tube (PM1) is connected with a signal transmission end, and the drain electrode of the first PMOS tube (PM1) is connected with a ground end (GND);

the first enabling part is connected between a power supply voltage end (vccio) and a source electrode of the first PMOS pipe (PM1) in series;

a plurality of the first equivalent resistance parts (R1) are connected in parallel between the signal transmission terminal and the ground terminal (GND).

3. The adaptively calibratable ODT circuit applied to an FPGA of claim 2, wherein the first enabling part comprises an inverter, an NMOS transistor, a PMOS transistor, and a transmission gate, wherein,

the input end of the phase inverter receives a second enabling signal

The output end of the NMOS transistor is connected with the grid electrode of the NMOS transistor;

the drain electrode of the NMOS tube is connected with the power supply voltage end (vccio), and the source electrode of the NMOS tube is connected with the source electrode of the first PMOS tube (PM 1);

the source electrode of the PMOS tube is connected with the power supply voltage end (vccio), and the drain electrode of the PMOS tube is connected with the source electrode of the first PMOS tube (PM 1);

the input end of the transmission gate is connected with the grounding end (GND), the output end of the transmission gate is connected with the grid electrode of the PMOS tube, and the control end of the transmission gate respectively receives a first enable signal (en) and a second enable signal (en)

The first enable signal (en) and the second enable signal (en)

Is a pair of differential signals.

4. The adaptively calibratable ODT circuit applied to an FPGA of claim 2, wherein the first equivalent resistance section (R1) comprises an inverter, two NMOS transistors and a transmission gate, wherein,

the drain electrodes of the two NMOS tubes are connected with the signal transmission end, and the source electrodes of the two NMOS tubes are connected with the grounding end (GND);

the input end of the transmission gate is connected with the source electrode of the first PMOS tube (PM1), the output end of the transmission gate is connected with the grid electrode of the other NMOS tube, and the control end of the transmission gate receives the control signal.

5. The adaptively calibratable ODT circuit applied to an FPGA according to claim 1, wherein the second termination resistance unit (102) includes a first NMOS transistor (NM1), a second enable section, and a plurality of second equivalent resistance sections (R2), wherein,

the grid electrode of the first NMOS tube (NM1) is connected with a signal transmission end, and the drain electrode of the first NMOS tube (NM1) is connected with a power supply voltage end (vccio);

the second enabling part is connected between the source of the first NMOS transistor (NM1) and a ground terminal (GND) in series;

a plurality of the second equivalent resistance portions (R2) are connected in parallel between the power supply voltage terminal (vccio) and the signal transmission terminal.

6. The adaptively calibratable ODT circuit applied to an FPGA of claim 5, wherein the second enabling part comprises an inverter, an NMOS transistor, a PMOS transistor, and a transmission gate, wherein,

the input end of the phase inverter receives a first enabling signal (en), and the output end of the phase inverter is connected with the grid electrode of the PMOS tube;

the source electrode of the PMOS tube is connected with the source electrode of the first NMOS tube (NM1), and the drain electrode of the PMOS tube is connected with the ground terminal (GND);

the drain electrode of the NMOS tube is connected with the source electrode of the first NMOS tube (NM1), and the source electrode of the NMOS tube is connected with the ground terminal (GND);

the input end of the transmission gate is connected with the power supply voltage end (vccio), the output end of the transmission gate is connected with the grid electrode of the NMOS tube, and the control end of the transmission gate respectively receives a first enabling signal (en) and a second enabling signal (en)

The first enable signal (en) and the second enable signal (en)

Is a pair of differential signals.

7. The adaptively calibratable ODT circuit applied to an FPGA of claim 5, wherein the second equivalent resistance section (R2) comprises an inverter, two PMOS tubes and a transmission gate, wherein,

the source electrodes of the two PMOS tubes are connected with the power supply voltage end (vccio), and the drain electrodes of the two PMOS tubes are connected with the signal transmission end;

the input end of the transmission gate is connected with the source electrode of the first NMOS transistor (NM1), the output end of the transmission gate is connected with the grid electrode of the other PMOS transistor, and the control end of the transmission gate receives the control signal.

8. The adaptively calibratable ODT circuit applied to the FPGA of claim 2, wherein the first current mirror unit (A1) comprises a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), a fourth MOS transistor (M4), a fifth MOS transistor (M5), a sixth MOS transistor (M6), a first switch (S1), a second switch (S2), a third switch (S3) and a current source (IB),

the first MOS transistor (M1), the second MOS transistor (M2), the third MOS transistor (M3), the fourth MOS transistor (M4), the fifth MOS transistor (M5) and the sixth MOS transistor (M6) are all PMOS transistors;

the sources of the first MOS transistor (M1), the third MOS transistor (M3) and the fifth MOS transistor (M5) are all connected with the power supply voltage terminal (vccio);

the grid electrode of the first MOS tube (M1) is respectively connected with the grid electrode of the third MOS tube (M3), the drain electrode of the second MOS tube (M2) and the grid electrode of the fifth MOS tube (M5);

the source electrode of the second MOS transistor (M2) is connected with the drain electrode of the first MOS transistor (M1), the grid electrodes of the second MOS transistor (M2) are respectively connected with the grid electrode of the fourth MOS transistor (M4) and the grid electrode of the sixth MOS transistor (M6), and the grid electrode bias voltage (pbias) of the second MOS transistor (M2) is provided by a band gap circuit inside the FPGA chip;

the source electrode of the fourth MOS tube (M4) is connected with the drain electrode of the third MOS tube (M3), and the source electrode of the sixth MOS tube (M6) is connected with the drain electrode of the fifth MOS tube (M5);

the first switch (S1) and the current source (IB) are sequentially connected in series between the drain of the second MOS transistor (M2) and a ground terminal (GND);

the second switch (S2) is connected in series between the drain of the fourth MOS transistor (M4) and the reference resistor (Req);

the third switch (S3) is connected in series between the drain of the sixth MOS transistor (M6) and the first termination resistance unit (101).

9. The adaptively calibratable ODT circuit applied to FPGA according to claim 1, characterized in that, a first terminal of the reference resistor (Req) is connected to a first input terminal of the Comparator (COMP), and a second terminal is connected to Ground (GND).

10. The adaptively calibratable ODT circuit applied to FPGA according to claim 1, characterized in that, the control unit (B) comprises a counter (B1), a temperature decoder (B2), a controller (B3) and a fourth switch (S4) which are connected in sequence, wherein, the input end of the counter (B1) is connected with the output end of the Comparator (COMP), and the fourth switch (S4) is connected with the ODT circuit module (1).