CN118231498A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN118231498A CN118231498A CN202211660352.0A CN202211660352A CN118231498A CN 118231498 A CN118231498 A CN 118231498A CN 202211660352 A CN202211660352 A CN 202211660352A CN 118231498 A CN118231498 A CN 118231498A
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Abstract
The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: an epitaxial layer comprising opposing first and second faces; a first doped region extending from a portion of the first surface of the epitaxial layer into the epitaxial layer; the second doped region is positioned in the epitaxial layer, is stacked and distributed with the first doped region, and is different from the doping type of the first doped region; the isolation structures are positioned on two sides of the first doped region and extend from part of the second surface of the epitaxial layer to the first surface; the first lead structure is used for leading out the first doped region on the first surface of the epitaxial layer; and the second lead structure is used for leading out the second doped region on the second surface of the epitaxial layer. The semiconductor structure can effectively improve the photosensitive property of the small-size SPAD.
Description
Technical Field
The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The photon time-of-flight technique (Photon Time of Flight) is a method for measuring distance by utilizing time difference (d-TOF) or phase difference (i-TOF) between light signal emission and light signal reception, and a core pixel photosensitive single photon avalanche diode (Single photon avalanche diode, SPAD) of the d-TOF is a diode working in a reverse avalanche breakdown region, photon can generate photon-generated carriers in a semiconductor, and the photon-generated carriers drift into a strong electric field in a reverse bias PN junction depletion region of the SPAD to trigger avalanche breakdown to generate a high-current signal, so that detection of the single photon signal is realized.
When the SPAD structure is designed, if the SPAD size is larger, the area proportion occupied by the effective photosensitive area is larger, so that the photon detection efficiency (Photon detection efficiency, PDE) can be better improved, but the SPAD distribution density is lower and the Dark Count Rate (DCR) is lower. The size of the SPAD is reduced, so that the distribution density (integration efficiency) and DCR performance of the SPAD are improved, but the area of the effective photosensitive area is extruded by the electrical path, so that the PDE is greatly reduced, and the minimum size of the SPAD is not excessively small in order to ensure that lateral breakdown does not occur.
In the process of reducing the size of the SPAD, since the pick-up end (pick up) on the outer side needs to occupy a certain area, and meanwhile, in order to ensure that no lateral abnormal breakdown is caused, a certain distance is needed between two poles, and the required area greatly extrudes the area of the photosensitive area of the SPAD, so that the photosensitive area is too small, PDE is greatly reduced, meanwhile, the uniformity of an electric field in the reverse bias PN junction is poor, and the breakdown performance is deteriorated. When SPAD is scaled down to a certain size (< 4 μm by 4 μm), the photosensitive area has not been designed. Therefore, improvement of the existing structure is needed, so that the photosensitive characteristic of the small-size SPAD is effectively improved.
Disclosure of Invention
The application aims to provide a semiconductor structure and a forming method thereof, which can effectively improve the photosensitive characteristic of small-size SPAD.
In order to solve the above technical problems, the present application provides a semiconductor structure, including: an epitaxial layer comprising opposing first and second faces; a first doped region extending from a portion of the first surface of the epitaxial layer into the epitaxial layer; the second doped region is positioned in the epitaxial layer, is stacked and distributed with the first doped region, and is different from the doping type of the first doped region; the isolation structures are positioned on two sides of the first doped region and extend from part of the second surface of the epitaxial layer to the first surface; the first lead structure is used for leading out the first doped region on the first surface of the epitaxial layer; and the second lead structure is used for leading out the second doped region on the second surface of the epitaxial layer.
In some embodiments of the present application, a third doped region for ohmic contact is further included in the first doped region, and the third doped region is connected to the first lead structure.
In some embodiments of the application, the first lead structure comprises: the first through hole connecting line is connected with the third doped region; and the first conductive layer is connected with the first through hole connecting line.
In some embodiments of the present application, the semiconductor structure further comprises: the first dielectric layer is positioned on the first surface of the epitaxial layer, the bottom of the isolation structure, the first doped region and the third doped region, and the first lead structure is positioned in the first dielectric layer.
In some embodiments of the present application, a fourth doped region for ohmic contact is further included in the second doped region, and the fourth doped region is connected to the second lead structure.
In some embodiments of the application, the second lead structure comprises: a trench filling lead extending from a portion of the second face of the epitaxial layer into the fourth doped region; and the second interconnection lead is connected with the groove filling lead.
In some embodiments of the present application, the trench-filled lead includes: a trench extending from a portion of the second side of the epitaxial layer into the fourth doped region; an insulating layer located on the side wall of the groove in the epitaxial layer; and conductive material filling the trench.
In some embodiments of the application, the second interconnect lead comprises: the second through hole connecting line is connected with the groove filling lead; and the second conductive layer is connected with the second through hole connecting line.
In some embodiments of the present application, the semiconductor structure further comprises: and a second dielectric layer on a portion of the second face of the epitaxial layer, on top of the isolation structure, and on top of the trench fill lead, wherein the second lead structure is located in the second dielectric layer.
The application also provides a method for forming the semiconductor structure, which comprises the following steps: providing an epitaxial layer comprising opposing first and second faces; forming a first doped region and a second doped region which are different in doping type and distributed in a stacking manner in the epitaxial layer, wherein the first doped region extends from part of a first surface of the epitaxial layer to the epitaxial layer; forming a first lead structure, wherein the first lead structure is used for leading out the first doped region on the first surface of the epitaxial layer; forming isolation structures extending from a part of the second surface of the epitaxial layer to the first surface on two sides of the first doped region; a second lead structure is formed and is used to lead out the second doped region at a second face of the epitaxial layer.
In some embodiments of the present application, after forming the first doped region, a third doped region for ohmic contact is also formed in the first doped region.
In some embodiments of the present application, a method of forming the first lead structure includes: forming a first portion of a first dielectric layer on the first side of the epitaxial layer, the first doped region, and the third doped region; forming a first through hole connecting line connected with the third doped region in a first part of the first dielectric layer; forming a first conductive layer connected with the first through hole connection line; a second portion of the first dielectric layer is formed and a surface of the second portion of the first dielectric layer is coplanar with a top surface of the first conductive layer.
In some embodiments of the present application, after forming the second doped region, a fourth doped region for ohmic contact is also formed in the second doped region.
In some embodiments of the present application, a method of forming the second lead structure includes: forming a trench filling lead, wherein the trench filling lead extends from a part of the second face of the epitaxial layer into the fourth doping region; the second interconnect lead is formed and connected with the trench fill lead.
In some embodiments of the present application, the method for forming the trench-fill lead includes: etching from part of the second surface of the epitaxial layer and stopping in the fourth doped region to form a groove; forming an insulating layer on the side wall of the groove in the epitaxial layer; and filling conductive materials into the grooves.
In some embodiments of the present application, a method of forming the second interconnect lead includes: forming a first portion of a second dielectric layer on the second side of the epitaxial layer, the isolation structure and the trench filling lead; forming a second through hole connecting line connected with the groove filling lead in the first part of the second dielectric layer; forming a second conductive layer connected with the second through hole connecting line; a second portion of a second dielectric layer is formed, and a surface of the second portion of the second dielectric layer and a top surface of the second conductive layer are coplanar.
In some embodiments of the application, the second side of the epitaxial layer is located on a substrate prior to forming the isolation structures, and the substrate is removed when the isolation structures are formed.
Compared with the prior art, the semiconductor structure and the forming method thereof have the following beneficial effects:
The semiconductor structure leads out the first doped region on the first surface of the epitaxial layer, and leads out the second doped region on the second surface of the epitaxial layer, so that the photosensitive area can be greatly increased, and meanwhile, the isolation of the SPAD is not affected, so that the PDE performance of the SPAD is greatly improved while other performances are not obviously deteriorated. Meanwhile, as the leading-out structure of the second doped region is changed, the isolation structure can be further close to the first doped region and the second doped region, the size of the SPAD is further reduced, and the integration level of the SPAD is improved. Further, the second doped region is led out from the second face of the epitaxial layer through a second lead structure formed by the groove filling lead and the second interconnection lead, and the influence on other photoelectric properties of the SPAD is small.
The method for forming the semiconductor structure does not need to carry out new high-cost process development, does not need to additionally increase a new photomask, has higher compatibility with the existing working procedure, and has the advantages of no complicated manufacturing flow and easy control.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a BSI SPAD structure;
FIG. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present application;
fig. 3 to 8 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Referring to fig. 1, a back-illuminated (Back side illumination, BSI) SPAD structure includes an epitaxial layer 10, an N-type doped region 20 and a P-type doped region 30 are formed in the epitaxial layer 10, the N-type doped region 20 and the P-type doped region 30 form a PN junction region, an ohmic contact region 21 is formed in the N-type doped region 20, and the ohmic contact region 21 is connected with an interconnection structure 41. A deep P-well region 31 is formed below the P-type doped region 30, P-well regions 32 are formed at two end positions of the deep P-well region 31, an ohmic contact region 33 is formed in the P-well region 32, and the ohmic contact region 33 is connected with an interconnection structure 42. The SPADs also need to be isolated by a backside deep trench structure (Back SIDE DEEP TRENCH isolation, BDTI) 11. The metal layers of the interconnection structure 41 and the interconnection structure 42 are two ends of the SPAD with voltage, wherein the interconnection structure 42 is used for leading out the lower part of the PN junction of the SPAD from two sides, which needs to occupy a certain area, and meanwhile, the P-well region 32 needs to keep a certain distance from the PN junction region to prevent lateral breakdown, and the required area greatly extrudes the photosensitive area of the SPAD, so that PDE is greatly reduced, the uniformity of the electric field inside the PN junction is deteriorated, and the breakdown performance is poor.
In order to solve the problems, the embodiment of the application improves the structure of the BSI SPAD, effectively increases the occupation ratio of the area of the photosensitive area of the BSI SPAD, greatly improves the PDE performance of the SPAD while ensuring that other performances are not remarkably deteriorated, and simultaneously can reduce the size of the SPAD.
Referring to fig. 2, a semiconductor structure of an embodiment of the present application can be used for BSI SPAD, and includes: epitaxial layer 110, first doped region 300, second doped region 400, isolation structure 700, first lead structure 600, and second lead structure. Wherein the epitaxial layer 110 is formed by epitaxial growth on a substrate. The material of the epitaxial layer 110 may include, for example, silicon germanium, and the like. The epitaxial layer 110 includes opposing first and second faces 111, 112, the first face 111 being a front surface and the second face 112 being a back surface. Thus, the BSI SPAD receives light from the side of the second side 112.
The first doped region 300 extends from a portion of the first side 111 of the epitaxial layer 110 into the epitaxial layer 110. The doping type of the first doped region 300 may be N-type or P-type, and the N-type is taken as an example for illustration of the embodiment of the present application. The surface doping concentration of the first doped region 300 may be 1E10cm -2～1E16cm-2 (i.e., 1×10 10cm-2～1×1016cm-2). The depth of the first doped region 300 may be 0.1nm to 10 μm. In some embodiments, the first doped region 300 further includes a third doped region 310, the doping types of the third doped region 310 and the first doped region 300 are the same, and the surface doping concentration of the third doped region 310 is greater than the surface doping concentration of the first doped region 300. For example, the surface doping concentration of the third doped region 310 may be 1E10cm -2～1E16cm-2. The surface of the third doped region 310 is coplanar with the top surface of the first doped region 300. The third doped region 310 may be used for ohmic contact of the third doped region 310, leading out the third doped region 310.
The second doped region 400 is located in the epitaxial layer 110 and below the first doped region 300, and is stacked with the first doped region 300. The second doped region 400 has a doping type different from that of the first doped region 300, and forms a PN junction with the first doped region 300. In the embodiment of the present application, the second doped region 400 is P-type doped. The surface doping concentration of the second doped region 400 may be 1E10cm -2～1E16cm-2. The distance from the surface to the bottom of the second doped region 400 may be 0.1nm to 10 μm. The relative widths of the second doped region 400 and the first doped region 300 are not required, and are adjusted according to practical situations, and the embodiment of the application is illustrated by taking the case that the width of the first doped region 300 is larger than the width of the second doped region 400.
The second doped region 400 further includes a fourth doped region 410, the doping types of the fourth doped region 410 and the second doped region 400 are the same, and the surface doping concentration of the fourth doped region 410 is greater than the surface doping concentration of the second doped region 400. For example, the surface doping concentration of the fourth doped region 410 may be 1E10cm -2～1E16cm-2. The bottom surface of the fourth doped region 410 and the bottom surface of the second doped region 400 are coplanar. The fourth doped region 410 may be used for ohmic contact of the second doped region 400 to draw the second doped region 400 out.
Compared with the structure shown in fig. 1, the embodiment of the present application improves the extraction structure of the second doped region 400, completely removes the P-type electrode region around the original SPAD, and sets the fourth doped region 410 in the second doped region 400 as the pick up end (pick up). The original P-type electrode area is omitted, so that the photosensitive area of the SPAD can be greatly increased.
The isolation structures 700 are located on both sides of the first doped region 300 and are used to isolate adjacent SPADs. The isolation structure 700 extends from a portion of the second side 112 of the epitaxial layer 110 to the first side 111. The isolation structure 700 may be a deep trench structure.
The first lead structure 600 is used to lead out the first doped region 300 at the first side 111 of the epitaxial layer 110. The first lead structure 600 is connected to the third doped region 310 as an ohmic contact to induce the first doped region 300. In some embodiments, the first lead structure 600 may include a first via connection 610 and a first conductive layer 620, wherein the first via connection 610 is connected to the third doped region 310, and the first conductive layer 620 is connected to the first via connection 610. The first lead structure 600 may include at least one layer of a first via connection 610 and a first conductive layer 620, and embodiments of the present application are described by way of example only. The first lead structure 600 may be located in a first dielectric layer 510, where the first dielectric layer 510 is located on a portion of the first surface 111 of the epitaxial layer 110, the bottom of the isolation structure 700, the first doped region 300, and the third doped region 310. The material of the first dielectric layer 510 may include one or more of silicon dioxide, silicon nitride, silicon oxynitride, and the like.
The second lead structure is used to lead out the second doped region 400 at the second side 112 of the epitaxial layer 110. The second lead structure is connected to the fourth doped region 410 as an ohmic contact to induce the second doped region 400. In some embodiments, the second lead structure may include a trench-filled lead 810 and a second interconnect lead 820, wherein the trench-filled lead 810 is connected to the fourth doped region 410 and extends from a portion of the second face 112 of the epitaxial layer 110 into the fourth doped region 410. The trench fill lead 810 may include a trench extending from a portion of the second side 112 of the epitaxial layer 110 into the fourth doped region 410, an insulating layer 811 located at a sidewall of the trench in the epitaxial layer 110, and a conductive material 812 filling the trench. Wherein the insulating layer 811 functions as an electrical insulator, and the conductive material 812 is connected to the fourth doped region 410 to function as a conductive line. The second interconnection lead 820 is connected to the trench filling lead 810, and may include a second via connection line 821 and a second conductive layer 822, wherein the second via connection line 821 is connected to the trench filling lead 810, and the second conductive layer 822 is connected to the second via connection line 821. The second lead structure may include at least one layer of second via connection 821 and second conductive layer 822, and the embodiment of the present application is illustrated by taking one layer as an example.
The second lead structure may be located in a second dielectric layer 520, the second dielectric layer 520 being located on a portion of the second side 112 of the epitaxial layer 110, on top of the isolation structure 700, and on top of the trench-filled lead 810. The material of the second dielectric layer 520 may include one or more of silicon dioxide, silicon nitride, silicon oxynitride, and the like.
The semiconductor structure of the embodiment of the application abandons the previous mode of picking up the N doped region and the P doped region for forming the PN junction on the same surface of the epitaxial layer, but picks up the two doped regions for forming the PN junction on the first surface and the second surface of the epitaxial layer respectively, and although one doped region needs to be picked up on the second surface, a groove filling lead needs to be introduced, so that a part of photosensitive area is lost, and compared with the photosensitive area saved by omitting the original P-type electrode region (shown in figure 1), the photosensitive area of the lost part is smaller, and the photosensitive area of BSI SPAD is also increased as a whole. Meanwhile, the isolation structure among the SPADs is not affected, and the performance of the SPADs is not negatively affected. In addition, the original P-type electrode area is omitted, so that the isolation structure can be close to the PN junction, the size of the SPAD is reduced, and the integration level is improved.
The embodiment of the application also provides a forming method of the semiconductor structure, which comprises the following steps:
Step S1: providing an epitaxial layer comprising opposing first and second faces;
Step S2: forming a first doped region and a second doped region which are different in doping type and distributed in a stacking manner in the epitaxial layer, wherein the first doped region extends from part of a first surface of the epitaxial layer to the epitaxial layer;
step S3: forming a first lead structure, wherein the first lead structure is used for leading out the first doped region on the first surface of the epitaxial layer;
step S4: forming isolation structures extending from a part of the second surface of the epitaxial layer to the first surface on two sides of the first doped region;
step S5: a second lead structure is formed and is used to lead out the second doped region at the first and second sides of the epitaxial layer.
A method of forming the semiconductor structure is described in detail below with reference to fig. 3 through 8.
Referring to fig. 3, an epitaxial layer 110 is provided. The epitaxial layer 110 may be formed by performing epitaxial growth on the substrate 100, and the material of the epitaxial layer 110 may include at least one of silicon, silicon germanium, and the like. The epitaxial layer 110 includes a first surface 111 and a second surface 112 opposite to each other, wherein the first surface 111 serves as a backlight surface of the BSI SPAD, and the second surface 112 serves as a light receiving surface of the BSI SPAD.
Then, a first doped region and a second doped region are formed in the epitaxial layer 110. The second doped region is formed first and then the first doped region is formed according to the principle that the deeper doped region is formed preferentially. With continued reference to fig. 3, the second doped region 400 is formed at a specific depth from the surface of the epitaxial layer 110 using an ion implantation process, the specific depth being determined according to the depth of the first doped region, and the doping type of the second doped region 400 being selected according to requirements. After forming the second doped region 400 and before forming the first doped region, a fourth doped region 410 is also formed in the second doped region 400, the doping types of the fourth doped region 410 and the second doped region 400 are the same, and the surface doping concentration of the fourth doped region 410 is greater. Since the fourth doped region 410 functions as an ohmic contact, the bottom surface of the fourth doped region 410 is coplanar with the bottom surface of the second doped region 400.
Referring to fig. 4, a first doped region 300 is formed in the epitaxial layer 110 using an ion implantation process, the first doped region 300 extending from a portion of the first side 111 of the epitaxial layer 110 into the epitaxial layer 110. The first doped region 300 and the second doped region 400 are stacked. Specifically, the first doped region 300 extends from a portion of the first side 111 of the epitaxial layer 110 onto the second doped region 400. The doping types of the first doping region 300 and the second doping region 400 are different. After the first doped region 300 is formed, a third doped region 310 for ohmic contact is also formed in the first doped region 300. The doping types of the third doped region 310 and the first doped region 300 are the same, and the surface doping concentration of the third doped region 310 is greater than the surface doping concentration of the first doped region 300. The surface of the third doped region 310 is coplanar with the top surface of the first doped region 300.
Referring to fig. 5, a first lead structure 600 is formed, and the first lead structure 600 is used to lead out the first doped region 300 at the first face 111 of the epitaxial layer 110. The method of forming the first lead structure 600 may include: the first portion 511 of the first dielectric layer 510 is formed on the first surface 111 of the epitaxial layer 110, the first doped region 300, and the third doped region 310, for example, by a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Then, a first via line 610 connecting the third doped region 310 is formed in the first portion 511 of the first dielectric layer 510, the first via line 610 may be formed by etching and via filling steps, and the first via line 610 and the surface of the first portion 511 of the first dielectric layer 510 are coplanar. Next, a first conductive layer 620 is formed to connect the first via connection line 610, and a process of forming the first conductive layer 620 may include deposition and etching of the conductive layer. The material of the first conductive layer 620 and the first via connection line 610 may include a metal, such as Al, W, cu, ti, co, ni, or may be a transition metal material used as an adhesion layer. Finally, a second portion 512 of the first dielectric layer 510 is formed, and a surface of the second portion 512 of the first dielectric layer 510 and a top surface of the first conductive layer 620 are coplanar. The material of the first dielectric layer 510 may include at least one of silicon dioxide, silicon nitride, silicon oxynitride, high K material (dielectric constant K is greater than or equal to 3), and the like.
Referring to fig. 6, isolation structures 700 are formed. In forming the isolation structure 700, the structure shown in fig. 5 needs to be inverted so that the substrate 100 faces upward, the first lead structure 600 faces downward, and then the substrate 100 is removed to expose the second face 112 of the epitaxial layer 110. And etching from the second surface 112 of the epitaxial layer 110 and stopping to form a trench on the first dielectric layer 500, filling an insulating material into the formed trench, making the surface of the insulating material and the second surface 112 coplanar, and forming isolation structures 700 extending from part of the second surface 112 of the epitaxial layer 110 to the first surface 111 at two sides of the first doped region 300. The insulating material may include at least one of silicon dioxide, silicon nitride, silicon oxynitride, and the like.
Then, a second lead structure is formed and is used to lead out the second doped region 400 at the second face 112 of the epitaxial layer 110. The method of forming the second lead structure may include: forming a trench filling lead extending from a portion of the second face 112 of the epitaxial layer 110 into the fourth doped region 410; and forming the second interconnection lead, wherein the second interconnection lead is connected with the groove filling lead.
Referring to fig. 7, a method of forming the trench-filled lead 810 may include: etching from a portion of the second side 112 of the epitaxial layer 110 and stopping in the fourth doped region 410 to form a trench; forming an insulating layer 811 on sidewalls of the trench in the epitaxial layer 110; the trench is filled with a conductive material 812, a surface of the conductive material 812 being coplanar with the second face 112 of the epitaxial layer 110. When the conductive material 812 is filled, an electroplating process may be used, and a suitable annealing process may be performed, so that a metal silicide (silicide) may be formed on the contact surface between the fourth doped region 410 and the conductive material 812, so as to reduce the contact resistance. The insulating layer 811 may be made of at least one of insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, and High K material. The conductive material 812 may include at least one of copper, aluminum, tungsten, and the like.
Referring to fig. 8, a method of forming the second interconnect lead 820 may include: a first portion 521 of the second dielectric layer 520 is formed on the second side 112 of the epitaxial layer 110, the isolation structure 700, and the trench-fill lead 810. A second via connection line 821 connecting the trench filling lead 810 is formed in the first portion 521 of the second dielectric layer 520, and the forming process of the second via connection line 821 may include an etching process and a deposition process. And then forming a second conductive layer 822 connected to the second via connection line 821, wherein the forming process of the second conductive layer 822 may include deposition and etching of the conductive layer. The materials of the second conductive layer 822 and the second via hole connection 821 may include metals such as Al, W, cu, ti, co, ni, or may be transition metal materials used as an adhesion layer, or the like. Finally, a second portion 522 of the second dielectric layer 520 is formed, and a surface of the second portion 522 of the second dielectric layer 520 and a top surface of the second conductive layer 822 are coplanar. The material of the second dielectric layer 520 may include at least one of silicon dioxide, silicon nitride, silicon oxynitride, and the like.
The method for forming the semiconductor structure does not need to develop a new high-cost process, does not need to add an additional photomask, has simple flow and easy realization, can effectively increase the occupation ratio of the area of the photosensitive area of the SPAD, greatly improves the PDE performance of the SPAD while ensuring other performances not to be remarkably deteriorated, and can realize the design and processing of the SPAD with small size and high performance.
In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be appreciated that when a member such as a layer, region or substrate
When an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present 5. In contrast, the term "directly" means without intermediate elements. It should also be understood that the procedure
The terms "comprises," "comprising," "includes," "including," or "includes" when used in this document, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
0 It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements
Parts, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
5 Furthermore, the description of the application refers to idealized exemplary sectional and/or plan views and +.
Or perspective views to describe exemplary embodiments. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. 0 thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Claims (17)
1. A semiconductor structure, comprising:
an epitaxial layer comprising opposing first and second faces;
A first doped region extending from a portion of the first surface of the epitaxial layer into the epitaxial layer;
the second doped region is positioned in the epitaxial layer, is stacked and distributed with the first doped region, and is different from the doping type of the first doped region;
The isolation structures are positioned on two sides of the first doped region and extend from part of the second surface of the epitaxial layer to the first surface;
The first lead structure is used for leading out the first doped region on the first surface of the epitaxial layer;
And the second lead structure is used for leading out the second doped region on the second surface of the epitaxial layer.
2. The semiconductor structure of claim 1, wherein the first doped region further comprises a third doped region for ohmic contact, and wherein the third doped region is connected to the first lead structure.
3. The semiconductor structure of claim 2, wherein the first lead structure comprises:
The first through hole connecting line is connected with the third doped region;
and the first conductive layer is connected with the first through hole connecting line.
4. The semiconductor structure of claim 3, wherein the semiconductor structure further comprises: the first dielectric layer is positioned on the first surface of the epitaxial layer, the bottom of the isolation structure, the first doped region and the third doped region, and the first lead structure is positioned in the first dielectric layer.
5. The semiconductor structure of claim 1, wherein a fourth doped region for ohmic contact is further included in the second doped region, and wherein the fourth doped region is connected to the second lead structure.
6. The semiconductor structure of claim 5, wherein the second lead structure comprises:
a trench filling lead extending from a portion of the second face of the epitaxial layer into the fourth doped region;
And the second interconnection lead is connected with the groove filling lead.
7. The semiconductor structure of claim 6, wherein the trench fill lead comprises: a trench extending from a portion of the second side of the epitaxial layer into the fourth doped region;
An insulating layer located on the side wall of the groove in the epitaxial layer;
And conductive material filling the trench.
8. The semiconductor structure of claim 6, wherein the second interconnect lead comprises: the second through hole connecting line is connected with the groove filling lead;
and the second conductive layer is connected with the second through hole connecting line.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises: and a second dielectric layer on a portion of the second face of the epitaxial layer, on top of the isolation structure, and on top of the trench fill lead, wherein the second lead structure is located in the second dielectric layer.
10. A method of forming a semiconductor structure, comprising:
providing an epitaxial layer comprising opposing first and second faces;
Forming a first doped region and a second doped region which are different in doping type and distributed in a stacking manner in the epitaxial layer, wherein the first doped region extends from part of a first surface of the epitaxial layer to the epitaxial layer;
forming a first lead structure, wherein the first lead structure is used for leading out the first doped region on the first surface of the epitaxial layer;
Forming isolation structures extending from a part of the second surface of the epitaxial layer to the first surface on two sides of the first doped region;
A second lead structure is formed and is used to lead out the second doped region at a second face of the epitaxial layer.
11. The method of claim 10, further comprising forming a third doped region for ohmic contact in the first doped region after forming the first doped region.
12. The method of forming a semiconductor structure of claim 11, wherein the method of forming the first lead structure comprises:
forming a first portion of a first dielectric layer on the first side of the epitaxial layer, the first doped region, and the third doped region;
Forming a first through hole connecting line connected with the third doped region in a first part of the first dielectric layer;
Forming a first conductive layer connected with the first through hole connection line;
A second portion of the first dielectric layer is formed and a surface of the second portion of the first dielectric layer is coplanar with a top surface of the first conductive layer.
13. The method of claim 10, further comprising forming a fourth doped region for ohmic contact in the second doped region after forming the second doped region.
14. The method of forming a semiconductor structure of claim 13, wherein the method of forming the second lead structure comprises:
Forming a trench filling lead, wherein the trench filling lead extends from a part of the second face of the epitaxial layer into the fourth doping region;
The second interconnect lead is formed and connected with the trench fill lead.
15. The method of forming a semiconductor structure of claim 14, wherein the method of forming a trench-filled lead comprises:
Etching from part of the second surface of the epitaxial layer and stopping in the fourth doped region to form a groove;
forming an insulating layer on the side wall of the groove in the epitaxial layer;
and filling conductive materials into the grooves.
16. The method of forming a semiconductor structure of claim 14, wherein the method of forming the second interconnect lead comprises:
Forming a first portion of a second dielectric layer on the second side of the epitaxial layer, the isolation structure and the trench filling lead;
Forming a second through hole connecting line connected with the groove filling lead in the first part of the second dielectric layer;
Forming a second conductive layer connected with the second through hole connecting line;
A second portion of a second dielectric layer is formed, and a surface of the second portion of the second dielectric layer and a top surface of the second conductive layer are coplanar.
17. The method of claim 10, wherein the second side of the epitaxial layer is located on a substrate prior to forming the isolation structure, and wherein the substrate is removed when forming the isolation structure.
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