CN118231255A

CN118231255A - Semiconductor structure and forming method thereof

Info

Publication number: CN118231255A
Application number: CN202410215873.8A
Authority: CN
Inventors: 范韵如; 谌俊元; 苏焕杰; 王志豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-02-27
Filing date: 2024-02-27
Publication date: 2024-06-21

Abstract

Embodiments of the present application disclose semiconductor structures and methods of forming the same. The method of forming a semiconductor structure includes forming a fin on a semiconductor layer, depositing an isolation feature on a sidewall of the fin, recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer, forming a sacrificial feature in the first trench, forming an epitaxial feature on the sacrificial feature, exposing a bottom surface of the sacrificial feature, removing the sacrificial feature to form a second trench exposing a bottom surface of the epitaxial feature, and forming a conductive feature in the second trench. The conductive member is electrically coupled to the epitaxial member.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in integrated circuit materials and design have resulted in several generations of integrated circuits, each generation being smaller, more complex circuits than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. Such a scaling down process generally provides benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

Integrated circuits have evolved into advanced technologies with smaller feature sizes, such as 7nm, 5nm, and 3nm. In these advanced techniques, the gate pitch (pitch) is continuously reduced, thus causing a problem of contact with the gate bridge. In addition, to enhance device performance, multiple gate transistors, such as those formed on the fin active region, are often required. Those three-dimensional Field Effect Transistors (FETs) formed on the fin active region are also known as finfets. Other three-dimensional field effect transistors include full gate-all-around (GAA) FETs. For short channel control, these FETs require a narrow fin width, which results in smaller source/drain regions than planar FETs. This will reduce the alignment margin and lead to problems with further shrinking the device pitch and increasing the packing density. As device dimensions shrink, power lines are formed on the backside of the substrate. However, existing backside power rails still face various challenges including shorts, leakage, wiring resistance, alignment margin, layout flexibility, and packing density. Accordingly, there is a need for a structure and method for a multi-gate transistor with backside power rails and vias to address these issues to enhance circuit performance and reliability.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a method of forming a semiconductor structure, comprising: forming a fin over the semiconductor layer; depositing isolation features on the sidewalls of the fins; recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer; forming a sacrificial member in the first trench; forming an epitaxial feature over the sacrificial feature; exposing the bottom surface of the sacrificial member; removing the sacrificial member to form a second trench exposing a bottom surface of the epitaxial member; and forming a conductive feature in the second trench, wherein the conductive feature is electrically coupled to the epitaxial feature.

According to another aspect of an embodiment of the present application, there is provided a method of forming a semiconductor structure, comprising: providing a structure having a front side and a back side, the structure comprising a substrate at the back side of the structure and a fin at the front side of the structure, wherein the fin comprises a plurality of sacrificial layers and a plurality of channel layers arranged alternately; recessing the fin from a front side of the structure in source/drain (S/D) regions, thereby exposing a top surface of the substrate; epitaxially growing a semiconductor component from a top surface of the substrate; forming an S/D epitaxial feature over the semiconductor feature; thinning the structure from the backside of the structure until the semiconductor component is exposed; etching the semiconductor component from the backside of the structure to form a backside trench exposing the bottom surface of the S/D epitaxial component; depositing a conductive feature in the backside trench; and forming a metal wiring layer on the backside of the structure, wherein the metal wiring layer is electrically coupled to the S/D epitaxial component through the conductive component.

According to yet another aspect of an embodiment of the present application, there is provided a semiconductor structure including: a first source/drain (S/D) epitaxial feature and a second S/D epitaxial feature; one or more nanostructures connecting the first S/D epitaxial component and the second S/D epitaxial component; a gate structure joining the one or more nanostructures, wherein the first and second S/D epitaxial components, the one or more nanostructures, and the gate structure are located at a front side of the semiconductor structure; a metal wiring layer located at a back side of the semiconductor structure; a conductive member located directly under the first S/D epitaxial member and connecting the metal wiring layer and the first S/D epitaxial member; and a semiconductor component located directly under the second S/D epitaxial component.

Drawings

The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A and 1B illustrate a flowchart of an example method of manufacturing a semiconductor device, according to some embodiments of the present disclosure.

Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, and 25A illustrate perspective views of a semiconductor device manufactured according to the methods of fig. 1A and 1B, according to some embodiments.

Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, and 25B illustrate cross-sectional views of portions of a semiconductor device in a Y-Z plane during fabrication according to the methods of fig. 1A and 1B in accordance with some embodiments of the present disclosure.

Fig. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, 23C, 24C, and 25C illustrate cross-sectional views of portions of a semiconductor device in an X-Z plane during fabrication of a method according to fig. 1A and 1B in accordance with some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the present disclosure below, the formation of a feature over, connected to, and/or coupled to another feature may include embodiments in which the feature is formed in direct contact, and may also include embodiments in which additional components may be formed as intervening features, such that the feature may not be in direct contact. Further, for example, "lower," "upper," "horizontal," "vertical," "above," "below," "upward," "downward," "top," "bottom," and the like, and derivatives thereof (e.g., "horizontally," "downward," "upward," etc.) are used to simplify the relationship of one feature to another feature of the disclosure. Spatially relative terms are intended to encompass different orientations of the device including the feature. Furthermore, when a number or a series of numbers is described by "about," "approximately," etc., the term is intended to include numbers within a reasonable range including the number described, e.g., within +/-10% of the number described or other values as understood by one of skill in the art. For example, the term "about 5nm" includes the size range from 4.5nm to 5.5 nm.

The present disclosure provides a semiconductor structure having a backside power rail and a method of manufacturing the same. The semiconductor structure also includes a backside via (also referred to as a backside contact) feature disposed on the backside of the substrate and interposed between the semiconductor active region (e.g., fin active region) and the backside power rail, and a device feature (e.g., source feature of a Field Effect Transistor (FET)) that electrically connects the backside power rail to the semiconductor active region. In particular, the backside via feature is self-aligned with the device feature (e.g., source feature) to be electrically connected, thereby providing a connection without overlap offset and eliminating shorting problems, such as shorting between the corresponding metal gate electrode and the backside power rail connected to the source/drain feature through the via feature.

The semiconductor structure further includes an interconnect structure formed on the front side of the substrate. The interconnect structure also includes front side contact features electrically connected to the FET, such as landing on and connecting to the drain features of the transistor, thereby distributing the power rails to the front and back sides of the substrate, reducing the number of power lines from the front side, and providing more space for metal routing and process margin on the front side of the substrate. The semiconductor structure thus formed comprises a backside power rail on the backside and an interconnect structure on the front side to commonly route the power lines, e.g. the drain component is connected to the respective power line through the interconnect structure and the source component is connected to the respective power line through the backside power rail. In some embodiments, both the front side and back side contact features include silicide to reduce contact resistance. The disclosed structure and method of fabricating the same may be applied to semiconductor structures having FETs of three-dimensional structure, such as fin FETs (finfets) formed over fin active regions, and FETs having multiple channels in a vertical stack, such as a full gate-all-around (GAA) structure. For simplicity, the present disclosure uses GAA transistors as examples. Those of ordinary skill in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures (e.g., finfets and/or planar FETs) to achieve the same purposes and/or achieve the same advantages of the embodiments described herein.

Fig. 1A and 1B illustrate a flow chart of a method 100 for fabricating a semiconductor device according to various embodiments of the present disclosure. The present disclosure contemplates additional processing. Additional operations may be provided before, during, and after the method 100, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 100. Fig. 1A and 1B are described below in conjunction with fig. 2A-25C, with fig. 2A-25C showing various perspective and cross-sectional views of a semiconductor device (or device) 200 at various steps of fabrication according to method 100, in accordance with some embodiments. In some embodiments, device 200 is an IC chip, a system on a chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), finfets, nanoflake FETs, nanowire FETs, other types of multi-gate FETs, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. Fig. 2A through 25C are simplified for clarity to better understand the inventive concepts of the present disclosure. Additional components may be added to the device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 200.

In operation 102, the method 100 (fig. 1A) provides a device 200 having a substrate 202, a buried layer 206 disposed on the substrate 202, and a semiconductor layer 208 disposed on the buried layer 206, as shown in fig. 2A-2C. Fig. 2A shows a perspective view of the device 200, and fig. 2B and 2C show cross-sectional views of portions of the device 200 along lines A-A and B-B in fig. 2A, respectively. Specifically, the A-A line is a cross section along the length direction (direction "Y" or Y direction) of the gate structure to be formed, and the B-B line is a cross section along the length direction (direction "X" or X direction) of the semiconductor fin to be formed. The A-A and B-B lines in fig. 3A to 25C are of similar structure. Some of fig. 3A-25C (e.g., fig. 7B) also partially illustrate cross-sectional views of device 200 along line C-C, which is parallel to line A-A and taken in the source/drain (S/D) regions of device 200.

In some embodiments, the substrate 202 is a silicon-on-insulator (SOI) substrate. The semiconductor on insulator substrate may be fabricated by separation by oxygen implantation (SIMOX), wafer bonding, and/or other suitable methods. In an alternative embodiment, substrate 202 is a bulk silicon substrate (i.e., comprising bulk monocrystalline silicon). In various embodiments, the substrate 202 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, siGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or combinations thereof. The device 200 further includes a buried layer 206 disposed on the substrate 202. The buried layer 206 may be an oxide layer such as silicon oxide, or a semiconductor layer such as GaAs. The device 200 further includes a semiconductor layer 208 disposed on the buried layer 206. In some embodiments, both the substrate 202 and the semiconductor layer 208 may comprise bulk monocrystalline silicon, and the buried layer 206 comprises GaAs. The concentration (molar ratio) of Ga in buried layer 206 may range from about 20% to about 55%. Or buried layer 206 may be a buried oxide layer. Further, in some embodiments, the substrate 202 and the semiconductor layer 208 may comprise different semiconductor compositions, such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, inP or combinations thereof. Furthermore, in some alternative embodiments, formation of the buried layer 206 may be selectively skipped such that the semiconductor layer 208 may be disposed on the top surface of the substrate 202.

At operation 104, the method 100 (fig. 1A) forms an epitaxial stack 212 on the semiconductor layer 208, as shown in fig. 3A-3C. The epitaxial stack 212 includes an epitaxial layer 214 having a first composition, the first composition epitaxial layer 214 being interposed by an epitaxial layer 216 having a second composition. The first and second components may be different. In one embodiment, epitaxial layer 214 is a SiGe layer and epitaxial layer 216 is a Si layer. However, other embodiments are possible, including those that provide the first and second compositions with different oxidation rates and/or etch selectivities. Epitaxial layer 216, or portions thereof, form the channel region of device 200, as described further below. In the depicted embodiment, epitaxial stack 212 includes three epitaxial layers 214 and three epitaxial layers 216 configured to form three semiconductor layer pairs disposed on substrate 202, each semiconductor layer pair having a respective first epitaxial layer 214 and a respective second epitaxial layer 216. This configuration will result in device 200 having three channel layers after undergoing subsequent processing. However, the present disclosure contemplates embodiments in which epitaxial stack 212 includes more or fewer semiconductor layers, depending, for example, on the number of channels required for device 200 (e.g., GAA transistor) and/or the design requirements of device 200. For example, epitaxial stack 212 may include two to ten epitaxial layers 214 and two to ten epitaxial layers 216. In an alternative embodiment where device 200 is a FinFET device, epitaxial stack 212 is only one layer of semiconductor material, such as one layer of Si. As will be discussed, the method 100 will process layers on both sides of the substrate 202. In the present disclosure, the side of the substrate 202 on which the epitaxial stack 212 is located is referred to as the front side, and the side opposite the front side is referred to as the back side.

For example, epitaxial growth of epitaxial stack 212 may be performed by a Molecular Beam Epitaxy (MBE) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as epitaxial layer 216, comprises the same material as the overlying semiconductor layer 208, such as Si. In some embodiments, either of epitaxial layers 214 and 216 may comprise a different material than semiconductor layer 208 above. In further embodiments of the embodiments, either of epitaxial layers 214 and 216 may comprise other materials, such as germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors such as SiGe, gaAsP, alInAs, alGaAs, inGaAs, gaInP and/or GaInAsP; or a combination thereof. As discussed, the materials of epitaxial layers 214 and 216 may be selected based on providing different oxidation and etch selectivity characteristics. In some embodiments, epitaxial layer 214 has a first etch rate to the etchant and epitaxial layer 216 has a second etch rate to the etchant, wherein the second etch rate is less than the first etch rate. In some embodiments, epitaxial layer 214 has a first oxidation rate and epitaxial layer 216 has a second oxidation rate, wherein the second oxidation rate is less than the first oxidation rate. In the depicted embodiment, epitaxial layer 214 and epitaxial layer 216 comprise different materials, atomic percentages of compositions, weight percentages of compositions, thicknesses, and/or characteristics to achieve a desired etch selectivity during an etching process, such as performing an etching process to form a floating channel layer in a channel region of device 200. For example, where epitaxial layer 214 comprises silicon germanium and epitaxial layer 216 comprises silicon, the silicon etch rate of epitaxial layer 216 is less than the silicon germanium etch rate of epitaxial layer 214 for a given etchant. In some embodiments, epitaxial layer 214 and epitaxial layer 216 may comprise the same material, but have different atomic percentages of the composition to achieve etch selectivity and/or different oxidation rates. For example, epitaxial layer 214 and epitaxial layer 216 may include silicon germanium, wherein epitaxial layer 214 has a first atomic percent of silicon and/or a first atomic percent of germanium, and epitaxial layer 216 has a second, different atomic percent of silicon and/or a second, different atomic percent of germanium. The present disclosure contemplates that epitaxial layer 214 and epitaxial layer 216 comprise any combination of semiconductor materials that may provide a desired etch selectivity, a desired oxidation rate differential, and/or a desired performance characteristic (e.g., a material that maximizes current flow), including any of the semiconductor materials disclosed herein.

In some embodiments, the thickness of epitaxial layer 214 ranges from about 3nm to about 6nm. In further embodiments, the thickness of the epitaxial layer 214 in the epitaxial stack 212 may be substantially uniform. In still other alternative embodiments, the bottommost epitaxial layer 214 may be thicker than the other upper epitaxial layers 214, for example, about 20% to about 50% thicker. In some embodiments, epitaxial layer 216 has a thickness ranging from about 4nm to about 12 nm. In a further embodiment, the thickness of the epitaxial layer 216 in the epitaxial stack 212 is substantially uniform. As described in more detail below, in the illustrated embodiment, the epitaxial layer 216 serves as a channel layer for the GAA transistor and the thickness is selected based on device performance considerations. The epitaxial layer 214 is used to preserve the spacing (or referred to as the gap) between adjacent channel structures for GAA transistors, and the thickness is also selected based on device performance considerations. Thus, the epitaxial layer 214 is also referred to as a sacrificial layer 214, and the epitaxial layer 216 is also referred to as a channel layer 216 or nanostructure 216.

Further, in operation 104, a mask layer 218 is formed over the epitaxial stack 212. In some embodiments, the mask layer 218 includes a first mask layer 218A and a second mask layer 218B. The first mask layer 218A is a pad oxide layer made of silicon oxide, which may be formed by a thermal oxidation process. The second mask layer 218B is made of silicon nitride (SiN), which is formed by Chemical Vapor Deposition (CVD), including Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other suitable process.

In operation 106, the method 100 (fig. 1A) patterns the epitaxial stack 212 to form a semiconductor fin 220 (also referred to as fin 220), as shown in fig. 4A-4C. In various embodiments, each fin 220 includes a top of alternating epitaxial layers 214 and 216 and a bottom formed by patterning the top of semiconductor layer 208, buried layer 206, and substrate 202. The bottom of the fin 220 is also referred to as the fin base or mesa. That is, in the illustrated embodiment, the fin base or mesa includes the semiconductor layer 208, the buried layer 206, and the top of the substrate 202. The mask layer 218 is patterned into a mask pattern by using a patterning operation including photolithography and etching. In some embodiments, operation 106 patterns epitaxial stack 212 using an appropriate process including a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process combines lithography and a self-aligned process, allowing creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithography process. For example, in one embodiment, a layer of material is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the epitaxial stack 212 may then be patterned using the remaining spacers or mandrels in an etching process, such as a dry etch (e.g., reactive ion etch), a wet etch, and/or other suitable process, for example, through openings defined by the patterned mask layer 218. Trenches 222 are defined between opposing sidewalls of adjacent fins 220. In the depicted embodiment, the trench 222 extends through the buried layer 206 and exposes a recessed top surface of the substrate 202.

Referring still to fig. 4A-4C, each fin 220 protrudes upward in the Z-direction above the substrate 202 and extends longitudinally in the X-direction. In fig. 4A-4C, three (3) fins 220 are spaced apart along the Y-direction. The number of fins is not limited to three, but may be one, two, or more than three. The fin 220 may have a uniform fin width along the Y direction. Notably, in fig. 4B, for simplicity of illustration, the portion of device 200 having two fin pitches spanned in the Y-direction is shown, so that leftmost and rightmost fins 220 each have only half of the fin width shown in fig. 4B. In some embodiments, one or more dielectric fins (not shown) are formed on both sides of each fin 220 to improve fin density and fin structure fidelity.

In operation 108, the method 100 (fig. 1A) deposits a dielectric material in the trenches 222 between adjacent fins 220 to form isolation features 224, as shown in fig. 5A-5C. The isolation member 224 may include one or more dielectric layers. Suitable dielectric materials for isolation feature 224 may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low K dielectric materials, and/or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique, including thermal growth, CVD, HDP-CVD, PVD, ALD, and/or spin-on techniques. Then, a planarization operation such as a CMP process is performed such that the upper surface of the topmost epitaxial layer 216 is exposed from the isolation feature 224. The isolation features 224 are then recessed to form Shallow Trench Isolation (STI) features (hence also referred to as STI features 224). Isolation feature 224 may be recessed using any suitable etching technique, including dry etching, wet etching, RIE, and/or other etching methods, and in an exemplary embodiment, anisotropic dry etching is used to selectively remove dielectric material of isolation feature 224 without etching fin 220. In some embodiments, the mask layer 218 is removed by a CMP process performed prior to recessing the isolation feature 224. In some embodiments, the mask layer 218 is removed by an etchant used to recess the isolation feature 224. In the illustrated embodiment as shown in fig. 5B, the top surface of STI feature 224 may be below the bottom surface of epitaxial stack 212 (also the top surface of semiconductor layer 208) and above the top surface of buried layer 206. Alternatively, according to some other embodiments, the top surfaces of STI features 224 may be coplanar with the bottom surfaces of epitaxial stack 212.

In operation 110, the method 100 (fig. 1A) forms a sacrificial (dummy) gate structure 226, as shown in fig. 6A-6C. In the illustrated embodiment, two (2) sacrificial gate structures 226 are formed, but the number of sacrificial gate structures is not limited to one, two, or more sacrificial gate structures arranged in the X-direction. A sacrificial gate structure 226 is formed over a portion of fin 220 that will become the channel region. The sacrificial gate structure 226 defines the channel region of the GAA transistor to be formed. Each sacrificial gate structure 226 includes a sacrificial gate dielectric layer 228 and a sacrificial gate electrode layer 230. Sacrificial gate structure 226 is formed by first blanket depositing a sacrificial gate dielectric layer 228 over fin 220. Sacrificial gate electrode layer 230 is then deposited over sacrificial gate dielectric layer 228 and over fin 220. The sacrificial gate electrode layer 230 includes silicon such as polysilicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer 230 is planarized. Sacrificial gate dielectric layer 228 and sacrificial gate electrode layer 230 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. Subsequently, a mask layer 232 is formed over the sacrificial gate electrode layer 230. The mask layer 232 may include a pad silicon oxide layer 232A and a silicon nitride mask layer 232B. Subsequently, a patterning operation is performed on the mask layer 232 and the sacrificial gate dielectric and electrode layer are patterned into the sacrificial gate structure 226. By patterning the sacrificial gate structure 226, the fin 220 is partially exposed on opposite sides of the sacrificial gate structure, thereby defining source/drain (S/D) regions.

Still referring to fig. 6A-6C, the method 100 (fig. 1A) at operation 110 also forms gate spacers 234 on sidewalls of the sacrificial gate structure 226. The gate spacer 234 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, siCN film, silicon oxycarbide, siOCN film, and/or combinations thereof. In some embodiments, the gate spacer layer 234 includes multiple layers, such as a main spacer wall, a liner layer, and the like. For example, the gate spacers 234 may be formed by blanket depositing a layer of dielectric material over the sacrificial gate structure 226 in a conformal manner using a process such as a CVD process, sub-atmospheric pressure CVD (SACVD) process, flowable CVD process, ALD process, PVD process, or other suitable process. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch back (e.g., anisotropic) process to remove the dielectric material from the horizontal surfaces and expose the top surfaces of the sacrificial gate structures 226 and the top surfaces (e.g., S/D regions) of the fins 220 adjacent to the sacrificial gate structures 226 but not covered by the sacrificial gate structures 226. The dielectric material layer may remain on the sidewalls of the sacrificial gate structure 226 as gate spacers 234 (and/or on the sidewalls of the fin 220 as fin spacers). Due to the limited etch contrast between the dielectric material of gate spacer 234 and STI feature 224, the etch back process may also recess the top of STI feature 224 when recess 235 is formed (as shown in fig. 7B). In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multi-step etch process, and/or combinations thereof.

In operation 112, the method 100 (fig. 1A) recesses portions of the fins 220 to form S/D trenches (or S/D recesses) 236 in the S/D regions, as shown in fig. 7A-7C. The stacked epitaxial layers 214 and 216 are etched down at the S/D regions. In many embodiments, operation 112 forms S/D trenches 236 by a suitable etching process, such as a dry etching process, a wet etching process, or a RIE process. The etching process at operation 112 may implement a dry etching process using an etchant that includes a bromine-containing gas (e.g., HBr and/or CHBR ₃), a fluorine-containing gas (e.g., CF ₄、SF₆、CH₂F₂、CHF₃ and/or C ₂F₆), other suitable gases, or a combination thereof. The etchant is selected such that the top of the semiconductor layer 208 is recessed and the sidewalls of the STI features 224 are exposed in the S/D trenches 236. In the embodiment shown in fig. 7B, the S/D trench 236 may extend to a position below the bottom surface of the recess 235 formed in the top of the STI feature 224.

At operation 114, the method 100 (fig. 1A) forms an inner spacer 240 adjacent an end of the epitaxial layer 214, as shown in fig. 8A-8C. Operation 114 may first laterally etch the ends of epitaxial layer 214 to form cavities filled with dielectric material as internal spacers 240. The epitaxial layer 214 may be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH ₄ OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Or operation 114 may first selectively oxidize the lateral ends of epitaxial layer 214 exposed in S/D trenches 236 to increase the etch selectivity between epitaxial layers 214 and 216. In some examples, the oxidation process may be performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. Next, operation 114 forms an inner spacer 240 on the recessed lateral end of the upper epitaxial layer 214. For example, operation 114 may include blanket depositing an inner spacer material layer in S/D trenches 236. In particular, an inner spacer material layer is deposited on the recessed lateral ends of the upper epitaxial layer 214 exposed in the cavity and on the sidewalls of the epitaxial layer 216 exposed in the S/D trenches 236. The inner spacer material layer may include oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and/or other suitable dielectric materials. In some embodiments, the inner spacer material layer is deposited as a conformal layer having a substantially uniform thickness over the different surfaces. The inner spacer material layer may be formed by ALD or any other suitable method. By conformally forming the inner spacer material layer, the volume of the cavity is reduced or completely filled. After depositing the inner spacer material layer, an etching operation is performed to partially remove the inner spacer material layer from the S/D trenches 236. In particular, the inner spacer material layer is removed from the sidewalls of epitaxial layer 216. By this etching, the inner spacer material layer remains substantially within the cavity due to the smaller volume of the cavity. In general, plasma dry etching etches the layer faster in wide and flat areas than in recessed (e.g., hole, groove, and/or slot) portions. Thus, the inner spacer material layer may remain inside the cavity. The remaining portion of the inner spacer material layer within the cavity, referred to as inner spacer 240, provides isolation between the metal gate structure to be formed and the S/D epitaxial feature to be formed.

At operation 116, the method 100 (fig. 1A) forms a semiconductor layer 242 in the S/D trench 236, as shown in fig. 9A-9C. Semiconductor layer 242 may be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of semiconductor layer 242 is achieved by a Molecular Beam Epitaxy (MBE) process, a Chemical Vapor Deposition (CVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, or other suitable epitaxial growth process, or a combination thereof. Semiconductor layer 242 includes a semiconductor material that is different from the semiconductor material included in semiconductor layer 208 to achieve etch selectivity during subsequent processing. For example, semiconductor layers 242 and 208 may include different materials, different atomic percentages of components, different weight percentages of components, and/or other characteristics to achieve a desired etch selectivity during an etching process. In one embodiment, semiconductor layer 242 comprises silicon germanium, such as undoped silicon germanium, and semiconductor layer 208 comprises silicon. The present disclosure contemplates that semiconductor layers 242 and 208 comprise any combination of semiconductor materials capable of providing a desired etch selectivity, including any of the semiconductor materials disclosed herein. As will be discussed in further detail below, the semiconductor layer 242 formed in some of the source regions will be removed in a backside process to form backside vias. It is noted that at operation 116, semiconductor layer 242 may be formed in the drain and source regions, while semiconductor layer 242 that is not removed in the back-side process will remain in the final device, including in the drain region.

The semiconductor layer 242 is deposited to a thickness such that it extends up to the bottommost inner spacers 240 (fig. 9C) and over the top surfaces of the STI features 224 (fig. 9B). In the embodiment shown in fig. 9C, the top surface of semiconductor layer 242 is above the bottom surface of bottommost inner spacer 240 and below the top surface of bottommost outer spacer 240. In some other embodiments, the top surface of semiconductor layer 242 is substantially flush with the bottom surface of the bottommost interior spacer. In various embodiments, the top surface of semiconductor layer 242 is below the top surface of bottommost inner spacer 240 to avoid physical contact between epitaxial layer 216 and semiconductor layer 242. Otherwise, the backside via, which replaces semiconductor layer 242 in subsequent processes, may be electrically shorted to epitaxial layer 216. In some embodiments, the thickness H1 of the semiconductor layer 242 is in a range from about 5nm to about 20 nm. In the embodiment shown in fig. 9B, the width W1 of the top of the semiconductor layer 242 is greater than the width W2 of the bottom of the semiconductor layer 242. In some embodiments, width W2 ranges from about 5nm to about 30nm, and width W1 ranges from about 25nm to about 50nm. Due to epitaxial growth, the top of semiconductor layer 242 may have crystalline facets, and the edges of the crystalline facets may extend laterally to a position directly above STI features 224.

At operation 118, the method 100 (fig. 1A) forms a cap layer 244 that covers at least a top surface of the semiconductor layer 242, as shown in fig. 10A-10C. The cap layer 244 may include silicon oxide (SiO ₂), aluminum oxide (AlO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon carbonitride (SiCON). According to some embodiments, cap layer 244 may comprise the same or different composition of dielectric material as inner spacer 240. In general, the composition of cap layer 244 and semiconductor layer 242 are selected such that there is a high etch selectivity therebetween. As will be discussed in further detail below, cap layer 244 is used as an etch stop layer during the etching process to protect S/D epitaxial features formed in S/D trenches 236 during later removal of semiconductor layer 242. Thus, if cap layer 244 completely covers the bottom surface of the S/D epitaxial feature to be formed thereon, cap layer 244 may be sufficient to protect the S/D epitaxial structure and not necessarily completely cover semiconductor layer 242. For example, edge portions of semiconductor layer 242 (e.g., edges of crystalline facets) may extend laterally outward and not be covered by cap layer 244. In the embodiment shown in fig. 10C, the top surface of cap layer 244 is substantially flush with the bottom surface of bottommost epitaxial layer 216. Or the top surface of cap layer 244 may be above or below the bottom surface of bottommost epitaxial layer 216. In various embodiments, the top surface of cap layer 244 is below the top surface of bottommost epitaxial layer 216. In some embodiments, cap layer 244 is first deposited in S/D trench 236, covering the top surface of semiconductor layer 242 and over the sidewalls of the S/D trench, using CVD, PVD, ALD or other suitable process. Subsequently, an etch back process is performed to remove portions of the cap layer 244 from the sidewalls of the S/D trenches 236 while leaving other portions of the cap layer 244 covering the top surface of the semiconductor layer 242. Any suitable etching technique may be used to partially remove cap layer 244 from S/D trenches 236, including dry etching, wet etching, RIE, and/or other etching methods, and in the exemplary embodiment, anisotropic dry etching is used.

At operation 120, the method 100 (FIG. 1A) forms an S/D epitaxial feature 246 in the S/D trench 236, as shown in FIGS. 11A-11C. In some embodiments, S/D epitaxial feature 246 comprises an epitaxially grown semiconductor material, such as epitaxially grown silicon, germanium, or silicon germanium. The S/D epitaxial features 246 may be formed by any epitaxial process, including Chemical Vapor Deposition (CVD) techniques (e.g., vapor phase epitaxy and/or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S/D epitaxial feature 246 may be doped with n-type dopants and/or p-type dopants. In some embodiments, for n-type transistors, the S/D epitaxial feature 246 comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si: C S/D epitaxial feature, si: P S/D epitaxial feature, or Si: C: P S/D epitaxial feature). In some embodiments, for p-type transistors, the S/D epitaxial feature 246 comprises silicon germanium or germanium, and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si: ge: B S/D epitaxial feature). The S/D epitaxial feature 246 may include a plurality of epitaxial semiconductor layers having different doping density levels. In some embodiments, an annealing process (e.g., rapid Thermal Annealing (RTA) and/or laser annealing) is performed to activate dopants in the S/D epitaxial components 246. The bottom surface of S/D epitaxial feature 246 is located entirely on the top surface of cap layer 244.

At operation 122, the method 100 (fig. 1A) forms a Contact Etch Stop Layer (CESL) 248 over the S/D epitaxial feature 246, and forms an interlayer dielectric (ILD) layer 250 over the CESL layer 248, as shown in fig. 12A-12C. CESL layer 248 may include silicon nitride, silicon oxynitride, silicon nitride with elemental oxygen (O) or carbon (C), and/or other materials; and may be formed by CVD, PVD (physical vapor deposition), ALD or other suitable methods. ILD layer 250 may comprise tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass, boron doped silicate glass (BSG), and/or other suitable dielectric materials. ILD layer 250 may be formed by PECVD or FCVD (flowable CVD) or other suitable methods. In some embodiments, forming ILD layer 250 further comprises performing a CMP process to planarize the top surface of device 200 such that mask layer 232 on top of sacrificial gate structure 226 is removed. Cap layer 244 may separate semiconductor layer 242 from contact CESL 248 and ILD layer 250. As described above, in some embodiments, an edge portion of semiconductor layer 242 may extend beyond cap layer 244, and an edge portion of semiconductor layer 242 may be in contact with CESL 248 or ILD layer 250 (if CESL 248 is not present).

At operation 124, the method 100 (fig. 1B) removes the sacrificial gate structure 226 to form a gate trench 252 in an etching process (e.g., plasma dry etching and/or wet etching). The gate trench 252 exposes the epitaxial layers 214 and 216 in the channel region. Operation 124 then releases the channel structure from the channel region. The resulting structure at the end of operation 124 is shown in fig. 13A-13C. In the illustrated embodiment, the channel layer is an epitaxial layer 216 in the form of nanostructures (e.g., nanoplates or nanowires). In this embodiment, epitaxial layer 216 comprises silicon and epitaxial layer 214 comprises silicon germanium. The epitaxial layer 214 is selectively removed. In some embodiments, the selective removal process includes oxidizing epitaxial layer 214 using a suitable oxidizing agent (e.g., ozone). Thereafter, the oxidized epitaxial layer 214 may be selectively removed from the gate trench 252. To further implement this embodiment, operation 124 includes a dry etching process to selectively remove epitaxial layer 214, for example, by applying HCl gas at a temperature of about 500 ℃ to about 700 ℃, or applying a gas mixture of CF ₄、SF₆ and CHF ₃. For simplicity and clarity, after the channel structure is released, epitaxial layer 216 is shown as channel layer 216.

At operation 126, the method 100 (fig. 1B) forms a metal gate structure 254 in the gate trench 252, as shown in fig. 14A-14C. A metal gate structure 254 surrounds each channel layer 216 in the channel region. The internal spacers 240 separate the metal gate structure 254 from the contact of the S/D epitaxial feature 246. The bottommost inner spacer 240 also separates the metal gate structure 254 from the contact of the semiconductor layer 242 and cap layer 244.

The metal gate structure 254 includes a gate dielectric layer 256 surrounding each channel structure 216 in the channel region, and a gate electrode layer 258 formed on the gate dielectric layer 256. In some embodiments, gate dielectric layer 256 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and/or combinations thereof. Examples of high-k dielectric materials include HfO ₂、HfSiO、HfSiO₂, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnium oxide-alumina (HfO ₂-Al₂O₃) alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, gate dielectric layer 256 includes an interfacial layer formed between the channel structure and the high-k dielectric material. Gate dielectric layer 256 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 256 is formed using a highly conformal deposition process, such as ALD, to ensure that a gate dielectric layer of uniform thickness is formed around each channel layer. A gate electrode layer 258 is formed on the gate dielectric layer 256 to surround each channel structure 216. The gate electrode layer 258 includes one or more layers of conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, tiN, WN, tiAl, tiAlN, taCN, taC, taSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode layer 258 may be formed by CVD, ALD, electroplating, or other suitable methods. In certain embodiments of the present disclosure, one or more work function adjustment layers are interposed between the gate dielectric layer and the gate electrode layer. The work function adjusting layer is made of a conductive material such as a single layer of TiN, taN, taAlC, tiC, taC, co, al, tiAl, hfTi, tiSi, taSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FETs, one or more of TaN, taAlC, tiN, tiC, co, tiAl, hfTi, tiSi, and TaSi are used as work function tuning layers, and for p-channel FETs, one or more of TiAlC, al, tiAl, taN, taAlC, tiN, tiC, and Co are used as function tuning layers. The work function tuning layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Further, the work function adjusting layer may be formed separately for an n-type transistor and a p-type transistor, which may use different metal layers.

Operation 126 may further include an etch back process to recess metal gate structure 254. The metal gate structure 254 is recessed below the upper surface of the gate spacer 234 by dry and/or wet etching operations. After recessing the metal gate structure 254, a gate cap insulating layer 260 is formed over the recessed metal gate structure 254 (as shown in fig. 15C). The gate cap insulating layer 260 may include a dielectric material selected from one or more of SiC, siON, siOCN, siCN and SiN. A planarization operation, such as a CMP process, is performed to remove excess dielectric material of the gate cap insulating layer 260.

At operation 128, the method 100 (FIG. 1B) forms front side S/D contact features 264 that land on some of the S/D features 246, as shown in FIGS. 15A-15C. Operation 128 may include a photolithographic process and etching to form S/D contact holes for a subset of the S/D features. Operation 128 includes one or more etching processes that selectively tune the material of ILD layer 250 to form contact holes. In addition, operation 128 may also include additional etches, such as wet etches, to open CESL 248 such that those S/D features 246 are exposed within the contact holes. In some embodiments, the S/D feature 246 may be partially etched. The etching process may be a dry etch, a wet etch, a reactive ion etch, or other etching method.

Operation 128 may also include forming silicide features 262 over S/D features 246 and forming S/D contacts (or vias) 264 over silicide features 262. Since the silicide features 262 and the S/D contacts 264 are formed on the front side of the device 200, they are also referred to as front side silicide features 262 and S/D contacts 264, respectively.

The process of forming silicide features 262 in operation 128 includes depositing one or more metals into the contact holes, performing an annealing process on device 200 to cause a reaction between the one or more metals and S/D features 246 to produce silicide features 262, and removing unreacted portions of the one or more metals, leaving silicide features 262 in the contact holes. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or combinations thereof (e.g., alloys of two or more metals), and may be deposited using CVD, PVD, ALD or other suitable methods. Silicide features 262 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (nipesi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

The S/D contact 264 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer functions to prevent the metal material of the metal fill layer from diffusing into the dielectric layer adjacent to the S/D contact feature 354. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD and/or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S/D contact 264. Operation 128 may perform a CMP process to remove excess material of S/D contacts 264.

At operation 132, the method 100 (fig. 1B) forms one or more interconnect layers 266 in which contacts, vias, and wires are embedded in a dielectric layer, as shown in fig. 15A-15C. One or more interconnect layers 266 connect the gates, sources, and drains of the various transistors and other circuitry in device 200 to form, in part or in whole, an integrated circuit. In some embodiments, operation 132 includes performing one or more intermediate process (MEOL) and back-end-of-line (BEOL) processes. This may include forming gate contact vias and source/drain contact vias, inter-metal dielectric (IMD) layers, metal lines embedded in IMD layers, contact pads, and the like. The device 200 may also include passivation layers and/or other layers built on the front side of the device 200. These layers and one or more interconnect layers are collectively referred to by numeral 266.

At operation 134, the method 100 (fig. 1B) attaches the front side of the device 200 to the carrier 268, as shown in fig. 15A-15C. In some embodiments, the carrier 268 may be a silicon wafer. Operation 134 may use any suitable attachment process, such as direct bonding, hybrid bonding, use of an adhesive, or other bonding method. In the illustrated embodiment, an adhesive layer (not shown) is formed on the front side of the device 200 and the carrier 268 is adjacent to the front side of the device 200. Operation 134 may further include alignment, annealing, and/or other processes. Attachment of the carrier 268 allows the device 200 to be flipped upside down. This allows access to the device 200 from the backside of the device 200 for further processing. It should be noted that, starting from the following figures, the device 200 is inverted.

At operation 136, the method 100 (fig. 1B) flips the device 200 up and down so that the device 200 can be accessed from the backside of the device 200 for further processing, as shown in fig. 16A-16C. From fig. 16A-16C, the "Z" direction points from the back side of device 200 to the front side of device 200, while the "-Z" direction points from the front side of device 200 to the back side of device 200.

Still referring to fig. 16A-16C, operation 136 also thins device 200 from the back side of device 200 until semiconductor layer 242 is exposed from the back side of device 200. The thinning process may include a mechanical grinding process and/or a chemical thinning process. The substrate 202 may first be removed in a chemical thinning process, wherein the buried layer 206 acts as an etch stop layer. Thereafter, a mechanical polishing process may be applied to completely remove the buried layer 206 and the bulk of the semiconductor layer 208 and the STI feature 224, wherein the semiconductor layer 242 acts as a planarization stop layer.

At operation 138, the method 100 (fig. 1B) forms a hard mask layer 270 on the backside of the device 200, as shown in fig. 17A-17C. The hard mask layer 270 may include SiO, hfSi, siOC, alO, zrSi, alON, zrO, hfO, tiO, zrAlO, znO, taO, laO, YO, taCN, siN, siOCN, si, siOCN, zrN, siCN, or other suitable materials. The thickness of the hard mask layer 270 may range from about 5nm to about 30 nm. A photolithographic patterning and etching process is performed to pattern the hard mask layer 270. In particular, a photolithography process forms a patterned photoresist layer having openings, and an etching process is applied to transfer the openings to the hard mask layer 270 as openings 272. The opening 272 is larger than the bottom surface of the semiconductor layer 242 such that the bottom surface of the semiconductor layer 242 is completely exposed in the opening 272. Portions of STI features 224 are also exposed in openings 272 (fig. 17B), and portions of semiconductor layer 208 are also exposed in openings 272 (fig. 17C).

At operation 140, the method 100 (fig. 1B) selectively etches the semiconductor layer 242 to extend the opening 272 to the cap layer 244, as shown in fig. 18A-18C. The opening 272 is also referred to as a backside trench 272. The backside trench 272 exposes the surfaces of the semiconductor layer 208, the cap layer 244, and the STI feature 224. In some embodiments, operation 140 applies an etching process that is tuned to be selective to the material (e.g., siGe) in semiconductor layer 242 and that does not (or minimally) etch semiconductor layer 208, STI feature 224, and cap layer 244. The bottommost inner spacer 240 may also be exposed in the backside trench 272 (fig. 18C).

At operation 142, the method 100 (FIG. 1B) performs an additional etch to open the cap layer 244, thereby exposing the bottom surface of the S/D feature 246, as shown in FIGS. 19A-19C. In the illustrated embodiment, CESL 248 is also exposed in backside trench 272 (fig. 19B). In some alternative embodiments, formation of cap layer 244 at operation 118 is optionally skipped and S/D feature 246 is formed directly on semiconductor layer 242. Thus, at the end of operation 140, s/D feature 246 has been exposed in backside trench 272 by selectively etching semiconductor layer 242, and operation 142 may be skipped. In the illustrated embodiment, the bottom surface of one S/D feature 246 exposed in the backside trench 272 is substantially level with the bottom surface of an adjacent S/D feature that is still covered. In an alternative embodiment, the etching process also etches the S/D epitaxial features 246 to recess the exposed surfaces to a level below the bottom surface of an adjacent S/D feature 246.

At operation 144, the method 100 (fig. 1B) forms a spacer layer 274 on sidewalls of the backside trench 272, as shown in fig. 20A-20C. The spacer layer 274 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, siCN film, silicon oxycarbide, siOCN film, and/or combinations thereof. For example, the spacer layer 274 may be formed by blanket depositing a layer of dielectric material on the backside of the device 200 in a conformal manner using a process such as a CVD process, SACVD process, ALD process, PVD process, or other suitable process. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch back (e.g., anisotropic) process to remove the dielectric material from the horizontal surfaces and expose the bottom surfaces of the S/D features 246. A layer of dielectric material may remain on the sidewalls of the backside trench 272 as a spacer layer 274. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multi-step etch process, and/or combinations thereof. In some embodiments, the thickness of the spacer layer 274 is in the range from about 3nm to about 10 nm. If the thickness of the spacer layer 274 is less than about 3nm, the spacer layer 274 may be removed during a subsequent cleaning process for forming the backside silicide features. If the thickness of the spacer layer 274 is greater than about 10nm, the spacer layer 274 may become difficult to etch through to expose the S/D feature 246.

At operation 146, the method 100 (fig. 1B) forms a backside conductive contact (or backside via) 282 in the backside trench 272 formed by removing the semiconductor layer 242 and the cap layer 244, as shown in fig. 21A-21C. The backside conductive contacts 282 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. The spacer layer 274 acts as a diffusion barrier to prevent metal elements in the backside conductive contacts 282 from diffusing into the semiconductor layer 208 and surrounding dielectric features, such as the STI feature 224 and ILD layer 250. In one embodiment, the backside conductive contacts 282 directly contact the S/D epitaxial components 246. Alternatively, in one embodiment, operation 146 optionally forms silicide features 280 between the S/D epi feature 246 and the backside conductive contact 282 to further reduce contact resistance. In a further implementation of the embodiment, operation 146 first deposits one or more metals into the backside trench 272, performs an annealing process on the device 200 to cause a reaction between the one or more metals and the S/D epitaxial feature 246 to produce a silicide feature, and removes unreacted portions of the one or more metals, leaving the silicide feature in the backside trench 272. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or combinations thereof (e.g., alloys of two or more metals), and may be deposited using CVD, PVD, ALD or other suitable methods. Silicide feature 280 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (Ni Ge si), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. A planarization operation, such as a CMP process, is performed to remove excess conductive material of the backside conductive contacts 282 and further thin the hard mask layer 270. The remaining thickness of the hard mask layer 270 may be in the range from about 3nm to about 40 nm. As shown in fig. 21B, the backside conductive contact 282 has a base portion extending over the STI feature 224 and a post portion between the base portion and the S/D feature 246. The base portion has a greater width than the post portion. Since the pillar portion is formed by a self-alignment process, even though an overlap shift occurs during the formation of the opening 272, the base may shift slightly to the left or right of the pillar portion without the position of the pillar portion changing.

At operation 148, the method 100 (fig. 1B) forms one or more backside interconnect layers 290 with backside power rails embedded in a dielectric layer on the backside of the device 200. The resulting structure according to one embodiment is shown in fig. 22A-22C. The backside power rail is electrically connected to backside conductive contacts 282. In embodiments, the backside power rail may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable process. The backside power rail may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, electroplating, or other suitable processes. Although not shown in fig. 22A-22C, the backside power rail may include contacts, vias, wires, and/or other conductive features. Having backside power rails advantageously increases the number of metal tracks available in device 200 for direct connection to source/drain contacts and vias, including backside conductive contacts 282. The backside power rail may have a wider dimension than the first level metal (M0) rail on the front side of the device 200, which advantageously reduces the backside power rail resistance.

By forming the sacrificial semiconductor layer 242 prior to forming the S/D features 246, a relatively large contact area may be maintained between the S/D epitaxial features and the power rails, thereby effectively further reducing contact resistance and improving device performance. Furthermore, the relatively large contact area provides better coverage control between the via and the contact structure. In some embodiments, source features in S/D epitaxial features 246 are connected to respective power lines through backside power rails and drain features in S/D epitaxial features 246 are connected to respective power lines through interconnect structures on the front side of device 200.

Reference is now made to fig. 23A-23C. Fig. 23A-23C illustrate an alternative embodiment of the resulting structure after operation 148. Some of the processes and materials used to form device 200 may be similar or identical to those previously described in connection with fig. 1A-22C and are not repeated here. One difference is that the bottom surface of the S/D epitaxial feature 246 is recessed during operation 142 so as to be lower than the adjacent S/D epitaxial feature 246. The spacer layer 274 may extend further downward and contact the bottommost channel layer 216 (fig. 23C).

Reference is now made to fig. 24A-24C. Fig. 24A-24C illustrate an alternative embodiment of the resulting structure after operation 148. Some of the processes and materials used to form device 200 may be similar or identical to those previously described in connection with fig. 1A-22C and are not repeated here. One difference is that the formation of cap layer 244 may be skipped and semiconductor layer 242 is in contact with S/D epitaxial feature 246. To selectively remove the semiconductor layer 242 to form the backside trench 272, the material compositions of the semiconductor layer 242 and the S/D epitaxial feature 246 are different from each other to exhibit sufficient etching contrast. For example, if both include SiGe, semiconductor layer 242 may have a greater Ge concentration than S/D epitaxial feature 246.

Reference is now made to fig. 25A-25C. Fig. 25A-25C illustrate an alternative embodiment of the resulting structure after operation 148. Some of the processes and materials used to form device 200 may be similar or identical to those previously described in connection with fig. 1A-22C and are not repeated here. One difference is that the hard mask layer 270 is completely removed from the backside of the device 200 during the planarization process. STI features 224 are exposed after hard mask layer 270 is removed.

At operation 150, the method 100 (fig. 1B) performs a further manufacturing process on the device 200. For example, one or more interconnect layers may be formed on the back side of the device 200, a passivation layer formed on the back side of the device 200, other BEOL processes performed, and the carrier 268 removed.

Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form backside contacts on the backside of the wafer in a self-aligned manner. This advantageously preserves a relatively large backside contact area to form an interconnect structure for the backside power rail having a relatively low contact resistance. Further, embodiments of the present disclosure form backside wiring layers, such as backside power rails, to increase the number of metal tracks available in the integrated circuit and to increase gate density for greater device integration. Embodiments of the present disclosure may be readily integrated into existing semiconductor manufacturing processes.

In one exemplary aspect, the present disclosure is directed to a method of forming a semiconductor structure. The method comprises the following steps: forming a fin over the semiconductor layer; depositing an isolation feature on a sidewall of the fin; recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer; forming a sacrificial member in the first trench; forming an epitaxial feature over the sacrificial feature; exposing a bottom surface of the sacrificial member; removing the sacrificial component to form a second trench exposing the bottom surface of the epitaxial component; and forming a conductive feature in the second trench, wherein the conductive feature is electrically coupled to the epitaxial feature. In some embodiments, the method further comprises depositing a cap layer over the sacrificial member prior to forming the epitaxial member, wherein the epitaxial structure is over the cap layer. In some embodiments, the method further comprises removing a portion of the cap layer from the second trench after removing the sacrificial member. In some embodiments, the cap layer separates the epitaxial component from the sacrificial component. In some embodiments, the cover layer covers a top surface of the spacer member. In some embodiments, the sacrificial member comprises a semiconductor material. In some embodiments, the sacrificial component comprises SiGe. In some embodiments, the method further comprises depositing a spacer layer on sidewalls of the second trench prior to forming the conductive feature. In some embodiments, the second trench exposes a sidewall of the isolation feature. In some embodiments, the method further comprises forming a hard mask layer on a bottom surface of the sacrificial member, wherein the hard mask layer comprises an opening on the bottom surface of the sacrificial member, and removing the sacrificial member comprises etching the sacrificial member through the opening.

In another exemplary aspect, the present disclosure is directed to a method of forming a semiconductor structure. The method comprises the following steps: providing a structure having a front side and a back side, the structure comprising a substrate at the back side of the structure and a fin at the front side of the structure, wherein the fin comprises a plurality of sacrificial layers and a plurality of channel layers arranged alternately; recessing the fin from the front side of the structure in source/drain (S/D) regions, thereby exposing a top surface of the substrate; epitaxially growing a semiconductor component from the top surface of the substrate; forming an S/D epitaxial feature over the semiconductor feature; thinning the structure from the backside of the structure until the semiconductor component is exposed; etching the semiconductor feature from the backside of the structure to form a backside trench exposing a bottom surface of the S/D epitaxial feature; depositing a conductive feature in the backside trench; and forming a metal wiring layer on the backside of the structure, wherein the metal wiring layer is electrically coupled to the S/D epitaxial component through the conductive component. In some embodiments, a top surface of the semiconductor component is below a bottom surface of a bottom-most one of the channel layers. In some embodiments, the method further comprises: an inner spacer is formed adjacent to an end portion of the sacrificial layer, wherein the semiconductor component is in physical contact with a bottommost one of the inner spacers. In some embodiments, the method further comprises: depositing a dielectric layer between the semiconductor component and the S/D epitaxial component; and removing the dielectric layer from the backside trench. In some embodiments, an edge portion of the semiconductor component is not covered by the dielectric layer. In some embodiments, the method further comprises: removing the sacrificial layer; forming a metal gate structure, wherein the metal gate structure wraps around each channel layer; and forming a dielectric member interposed between the metal gate structure and the conductive member. In some embodiments, the method further comprises: an isolation feature is formed, the isolation feature being disposed on a sidewall of the fin, wherein the semiconductor feature extends upwardly through the isolation feature and a portion of the semiconductor feature is located directly above the isolation feature.

In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes: a first source/drain (S/D) epitaxial feature and a second S/D epitaxial feature; one or more nanostructures connecting the first S/D epitaxial component and the second S/D epitaxial component; a gate structure joining the one or more nanostructures, wherein the first and second S/D epitaxial components, the one or more nanostructures, and the gate structure are located at a front side of the semiconductor structure; a metal wiring layer located at a back side of the semiconductor structure; a conductive member located directly under the first S/D epitaxial member and connecting the metal wiring layer and the first S/D epitaxial member; and a semiconductor component directly under the second S/D epitaxial component. In some embodiments, the semiconductor structure further includes a dielectric layer interposed between the semiconductor component and the second S/D epitaxial component. In some embodiments, the conductive member extends to a position directly below the one or more nanostructures.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

Forming a fin over the semiconductor layer;

Depositing an isolation feature on a sidewall of the fin;

recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer;

Forming a sacrificial member in the first trench;

Forming an epitaxial feature over the sacrificial feature;

exposing a bottom surface of the sacrificial member;

Removing the sacrificial component to form a second trench exposing the bottom surface of the epitaxial component; and

A conductive feature is formed in the second trench, wherein the conductive feature is electrically coupled to the epitaxial feature.

2. The method of claim 1, further comprising:

A cap layer is deposited over the sacrificial feature prior to forming the epitaxial feature, wherein the epitaxial structure is over the cap layer.

3. The method of claim 2, further comprising:

after removing the sacrificial member, a portion of the cap layer is removed from the second trench.

4. The method of claim 2, wherein the cap layer separates the epitaxial component from the sacrificial component.

5. The method of claim 2, wherein the cap layer covers a top surface of the isolation feature.

6. The method of claim 1, further comprising:

a spacer layer is deposited on sidewalls of the second trench prior to forming the conductive feature.

7. A method of forming a semiconductor structure, comprising:

providing a structure having a front side and a back side, the structure comprising a substrate at the back side of the structure and a fin at the front side of the structure, wherein the fin comprises a plurality of sacrificial layers and a plurality of channel layers arranged alternately;

Recessing the fin from the front side of the structure in source/drain regions, thereby exposing a top surface of the substrate;

epitaxially growing a semiconductor component from the top surface of the substrate;

Forming source/drain epitaxial features over the semiconductor features;

Thinning the structure from the backside of the structure until the semiconductor component is exposed;

etching the semiconductor feature from the backside of the structure to form a backside trench exposing a bottom surface of the source/drain epitaxial feature;

depositing a conductive feature in the backside trench; and

A metal wiring layer is formed on the backside of the structure, wherein the metal wiring layer is electrically coupled to the source/drain epitaxial feature through the conductive feature.

8. The method of claim 7, wherein a top surface of the semiconductor component is below a bottom surface of a bottommost one of the channel layers.

9. The method of claim 7, further comprising:

Forming an inner spacer adjacent to an end of the sacrificial layer,

Wherein the semiconductor component is in physical contact with a bottommost one of the internal spacers.

10. A semiconductor structure, comprising:

A first source/drain epitaxial feature and a second source/drain epitaxial feature;

one or more nanostructures connecting the first source/drain epitaxial feature and the second source/drain epitaxial feature;

A gate structure joining the one or more nanostructures, wherein the first and second source/drain epitaxial features, the one or more nanostructures, and the gate structure are located at a front side of the semiconductor structure;

a metal wiring layer located at a back side of the semiconductor structure;

A conductive member located directly under the first source/drain epitaxial member and connecting the metal wiring layer and the first source/drain epitaxial member; and

And a semiconductor component located directly below the second source/drain epitaxial component.