CN117096099A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117096099A
CN117096099A CN202310942561.2A CN202310942561A CN117096099A CN 117096099 A CN117096099 A CN 117096099A CN 202310942561 A CN202310942561 A CN 202310942561A CN 117096099 A CN117096099 A CN 117096099A
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China
Prior art keywords
layer
dielectric
metal layer
forming
trench
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CN202310942561.2A
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Chinese (zh)
Inventor
蔡忠浩
王朝勋
姚佳贤
薛婉容
黄谚钧
杨复凯
王美匀
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US18/298,629 external-priority patent/US20240038855A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN117096099A publication Critical patent/CN117096099A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

The method of forming a semiconductor structure includes providing a semiconductor substrate having source/drain features and a gate structure formed thereon; forming an interlayer dielectric layer on a semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the groove; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling the dielectric material layer in the grooves. Embodiments of the present invention also provide a semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to semiconductor structures and methods of forming the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs.
This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. For example, as IC component sizes continue to shrink, multilayer interconnect (MLI) components become more compact, and the interconnects of the MLI components exhibit increased contact resistance and misalignment between the various conductive layers, which presents challenges for performance, yield, and cost. It is observed that the higher contact resistance exhibited by interconnects in advanced IC technology nodes significantly delays (and in some cases prevents) the efficient routing of signals to and from IC devices (such as transistors), thereby counteracting any improvement in performance of such IC devices in advanced technology nodes. Accordingly, while existing interconnects are generally adequate for their intended purpose, they are not entirely satisfactory in all respects.
Disclosure of Invention
Some embodiments of the present invention provide a method of forming a semiconductor structure, the method comprising: providing a semiconductor substrate having source/drain features and gate structures formed thereon; forming an interlayer dielectric layer on a semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the groove; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling the dielectric material layer in the grooves.
Further embodiments of the present invention provide a method of forming a semiconductor structure, the method comprising: providing a semiconductor substrate having source/drain features and gate structures formed thereon; forming an interlayer dielectric layer on a semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a silicide layer on the source/drain feature; filling a metal layer on the silicide layer in the groove; forming a patterned mask having an opening, wherein a first portion of the metal layer is exposed within the opening and a second portion of the metal layer is covered by the patterned mask, and wherein the second portion extends to the second portion in the trench; and etching the metal layer through the openings of the patterned mask such that a first portion of the metal layer is recessed and a second portion of the metal layer remains.
Still further embodiments of the present invention provide a semiconductor structure comprising: source/drain features and a gate structure disposed on the semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; a metal component of metal embedded in the interlayer dielectric layer and positioned on the source/drain component, wherein the metal component comprises a lower portion and an upper portion of elongated shape, and wherein the upper portion is disposed above a first lengthwise end of the lower portion and the upper portion is remote from a second lengthwise end of the lower portion; a dielectric material member disposed over the second longitudinal end of the lower portion; and a dielectric liner disposed on sidewalls of the metal layer and the dielectric material member, wherein the dielectric liner is compositionally different from the interlayer dielectric layer and the dielectric material member, and wherein the dielectric liner surrounds the metal member and the dielectric material member in a top view.
Drawings
Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a perspective view of a semiconductor structure constructed in accordance with various aspects of the present disclosure.
Fig. 2 is a flow chart of a method of fabricating the semiconductor structure of fig. 1 in accordance with various aspects of the present disclosure.
Fig. 3A, 14 and 15 are top views of a semiconductor structure at various stages of fabrication constructed in accordance with various aspects of the disclosure.
Fig. 3B, 3C, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, and 13B are cross-sectional views of a semiconductor structure at various stages of fabrication in accordance with various aspects of the present disclosure.
Detailed Description
The present disclosure relates generally to Integrated Circuit (IC) devices, and more particularly to multilayer interconnect features for IC devices.
The following disclosure provides many different embodiments, or examples, of the different components used to implement the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact.
In addition, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, in the present disclosure below, forming an element on, connected to, and/or coupled to another element may include embodiments in which the elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the elements such that the elements may not be in direct contact. In addition, to facilitate describing the relationship between one component of the present disclosure and another component, spatially relative terms are used, such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upper," "lower," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," and the like). Spatially relative terms are intended to encompass different orientations of the device in which the component is included. Still further, when a value or range of values is recited using "about," "approximately," etc., the term is intended to encompass values within a reasonable range of the recited value, such as values within +/-10% of the recited value or other values understood by those of skill in the art. For example, the term "about 5nm" encompasses a size range from 4.5nm to 5.5 nm.
IC fabrication process flows are generally divided into three categories: front end of line (FEOL), middle of line (MEOL), and back end of line (BEOL). FEOL generally encompasses processes related to the fabrication of IC devices, such as transistors. For example, FEOL processes may include forming isolation features, gate structures, and source and drain features (commonly referred to as source/drain features). MEOLs typically encompass processes related to manufacturing contacts to conductive features (or conductive regions) of an IC device, such as contacts to gate structures and/or source/drain features. BEOL generally encompasses processes related to the fabrication of multi-layer interconnect (MLI) features that interconnect IC features fabricated by FEOL and MEOL (referred to herein as FEOL features or structures and MEOL features or structures, respectively) to ensure operation of the IC device.
As IC technology advances to smaller technology nodes, MEOL processes and BEOL processes are experiencing significant challenges. For example, advanced IC technology nodes require more compact MLI components, which require significantly reduced critical dimensions of the interconnects (e.g., widths and/or heights of the vias and/or wires of the interconnects) of the MLI components. The reduced critical dimensions have resulted in a significant increase in interconnect resistance, which may impair IC device performance (e.g., by increasing resistance-capacitance (RC) delay).
The present disclosure describes self-aligned interconnect architecture formed on source/drain features. Specifically, the MLI structure includes metal lines distributed among a plurality of metal layers to provide horizontal wiring and vias to provide vertical wiring of metal lines to adjacent metal layers. For example, the MLI structure includes a first metal line of a first metal layer, a second metal line of a second metal layer over the first metal layer, … …, an (n-1) th metal line of an (n-1) th metal layer, … …, an n-th metal line of an n-th metal layer over the (n-1) th metal layer, … …, and a top metal line of a top metal layer. In addition, the MLI structure includes contacts and vias located below the first metal layer. Specifically, contacts are positioned on the source/drain features, and vias are self-aligned with and positioned on the contacts. The self-aligned architecture can reduce capacitance at minimum pitch and reduce leakage. The self-aligned architecture may also use time dependent dielectric breakdown Test (TDDB) margin to manage low resistance and low capacitance, reduce power consumption, and increase speed. Different embodiments may have different advantages and no particular advantage is required for any embodiment.
The present disclosure provides structures and methods of making the same to address issues related to interconnects. Fig. 1 is a perspective view of a semiconductor structure 50 constructed in accordance with some embodiments. The semiconductor structure 50 may have a planar structure; a multi-gate structure, such as a fin structure; or a multi-channel structure having multiple channels vertically stacked, such as a full-gate-all-around (GAA) structure. The following description uses fin structures as examples, but is not intended to be limiting, and may be applied to any suitable structure without departing from the present disclosure.
The semiconductor structure 50 includes a semiconductor substrate 52 on which individual Field Effect Transistors (FETs) are formed. Specifically, the semiconductor structure 50 includes a first region 52A having a p-type FET (PFET) formed thereon and a second region 52B having an n-type FET (NFET) formed thereon. The semiconductor structure 50 includes various isolation features 54, such as Shallow Trench Isolation (STI) features. Semiconductor structure 50 also includes respective fin active regions 56 formed on semiconductor substrate 52. The fin active regions 56 protrude above the isolation members 54, and the fin active regions 56 are surrounded by the isolation members 54 and isolated from each other by the isolation members 54. Individual fin field effect transistors are formed on fin active region 56. In this embodiment, the PFET is disposed on the fin active region 56 within the first region 52A and the NFET is disposed on the fin active region 56 within the second region 52B. In some embodiments, a silicon germanium (SiGe) layer is epitaxially grown on semiconductor substrate 52 within first region 52A to enhance carrier mobility and device speed. Source and drain electrodes 58 are formed on the fin active region 56, and a gate stack 60 is formed on the fin active region 56 and disposed between the corresponding source and drain electrodes 58. Each gate stack 60 includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Dielectric spacers 62 may also be formed on sidewalls of gate stack 60 and on sidewalls of fin active region 56. The channel 64 is a portion of the fin active region 56 under the corresponding gate stack 60. Corresponding source and drain electrodes 58; a gate stack 60; and channel 64 is coupled to a field effect transistor. In the present example shown in fig. 1, the first region 52A includes two PFETs and the second region 52B includes two NFETs. Since the fin active region 56 protrudes above the isolation feature 54, the gate stack 60 is more effectively coupled to the corresponding channel 64 through the sidewalls and top surface of the fin active region 56, thus enhancing device performance.
Semiconductor structure 50 also includes an interlayer dielectric (ILD) layer 66 disposed over fin active region 56 and surrounding gate stack 60. ILD layer 66 is drawn in dashed lines and ILD layer 66 is shown as transparent to better view various components, such as gate stack 60 and fin active region 56.ILD layer 66 comprises one or more films of dielectric material. The MLI structure is formed in ILD layer 66 and is configured to couple individual devices into an integrated circuit. In fig. 1, the metal lines of the MLI structure are not illustrated, and an exemplary conductive structure is shown that includes contacts 68 positioned on the source/drain features 58 and vias 70 positioned on the contacts 68. Specifically, the via 70 and the contact 68 are self-aligned without an overlay shift problem (e.g., a short or open circuit). In addition, the through hole 70 and the contact 68 have the same composition without an interface between the through hole 70 and the contact 68, which reduces contact resistance. Although only one pair of exemplary contacts 68 and vias 70 are shown, there may be more pairs of contacts 68 and vias 80 depending on the various applications and layouts of the semiconductor structure 50. The following focuses on semiconductor structure 50 and a method of making the same.
Fig. 2 illustrates a flow chart of a method 100 of fabricating a semiconductor structure 50 in accordance with aspects of the present disclosure. The method may include the method 100. Fig. 3A, 14, and 15 are top views of a semiconductor structure 200 at various stages of fabrication, and fig. 3B-3C, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, and 13A-13B are cross-sectional views of the semiconductor structure 200 at various stages of fabrication, according to various embodiments of the method 100 of the present disclosure. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 100. Additional components may be added to the semiconductor structure depicted in fig. 3A-3C, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13B, 14 and 15, and some components described below may be replaced, modified or eliminated in other embodiments of the semiconductor structure depicted in fig. 3A-3C, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13B, 14 and 15. According to various embodiments, semiconductor structure 200 is part of semiconductor structure 50.
Fig. 2 is a flow chart illustrating a method 100 of fabricating a semiconductor structure 200 in accordance with various aspects of the present disclosure. Semiconductor structure 200 may be included in a microprocessor, memory, and/or other IC device. In some embodiments, semiconductor structure 200 may be part of an IC chip, a system on a chip (SoC), or portions thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The transistor may be a planar transistor or a multi-gate transistor, such as a fin FET (FinFET) or a multi-channel transistor, such as a GAA FET. Fig. 3A to 3C, 4A to 4B, 5A to 5B, 6A to 6B, 7A to 7B, 8A to 8B, 9A to 9B, 10A to 10B, 11A to 11B, 12A to 12B, 13A to 13B, 14 and 15 are simplified for clarity in understanding the inventive concepts of the present disclosure. Additional components may be added to semiconductor structure 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of semiconductor structure 200.
The semiconductor structure 200 may be electrically coupled to various devices (e.g., transistors, resistors, capacitors, and/or inductors) and/or components (e.g., gate structures and/or source/drain features) such that the various devices and/or components may operate in a manner dictated by design requirements of the semiconductor structure 200. The semiconductor structure 200 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form respective interconnect structures. The conductive layer is configured to form vertical interconnect features (e.g., to provide vertical connections and/or vertical electrical wiring between features), such as contacts and/or vias, and/or to form horizontal interconnect features (e.g., to provide horizontal electrical wiring), such as wires (or metal lines). The vertical interconnect typically connects horizontal interconnects in different layers of the semiconductor structure 200. During operation, the interconnect component is configured to route signals between and/or distribute signals (e.g., clock signals, voltage signals, and/or ground signals) to devices and/or components of the semiconductor device. Although semiconductor structure 200 is depicted as having a given number of dielectric and conductive layers, the present disclosure contemplates semiconductor structure 200 having any number of dielectric and/or conductive layers.
Referring collectively to fig. 2, 3A, 3B, and 3C, a method 100 of fabricating a semiconductor structure 200 includes a block 102, at which 102 a semiconductor substrate or wafer 202 is provided. In some embodiments, the semiconductor substrate 202 may comprise silicon. In some embodiments, the substrate 202 may include another elemental semiconductor, such as germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors such as silicon germanium (SiGe), gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination thereof. In some embodiments, the substrate 202 may include one or more group III-V materials, one or more group II-IV materials, or a combination thereof. In some embodiments, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The substrate 202 may include various doped regions (not shown), such as p-type doped regions, n-type doped regions, or combinations thereof, configured according to the design requirements of the semiconductor device. The P-type doped region (e.g., P-type well) includes a P-type dopant such as boron, indium, other P-type dopants, or combinations thereof. The N-type doped region (e.g., N-well) includes an N-type dopant, such as phosphorus, arsenic, other N-type dopants, or a combination thereof. In some implementations, the substrate 202 can include doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions may be formed directly on the substrate 202 and/or in the substrate 202 to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and/or other suitable doping processes may be performed to form the respective doped regions.
In some embodiments, the substrate 202 may include an isolation feature 204. Isolation features 204 may be formed over the substrate 202 and/or in the substrate 202 to isolate individual device regions 206. Those device regions 206 comprise a semiconductor layer so that various doped features, such as source/drain features, may be formed thereon. Accordingly, those device regions 206 are also referred to as active regions (or active regions) 206. In the disclosed embodiment, the active region 206 is a fin-shaped active region protruding above the isolation feature 204. For example, the isolation feature 204 defines active regions and electrically isolates the active regions from each other. The isolation feature 204 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material, or a combination thereof. The isolation features may include different structures such as Shallow Trench Isolation (STI) structures, deep Trench Isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. In some embodiments, the isolation feature 204 comprises an STI feature. For example, the STI feature may be formed by etching a trench in the substrate 202 (e.g., by using a dry etching process and/or a wet etching process) and filling the trench with an insulating material (e.g., by using a Chemical Vapor Deposition (CVD) process or a spin-on-glass process). A Chemical Mechanical Polishing (CMP) process may be performed to remove excess insulator material and/or planarize the top surface of the isolation features. In some embodiments, the STI feature includes a multi-layer structure filling the trench, such as a silicon nitride layer disposed over an oxide liner layer.
Semiconductor structure 200 also includes a respective gate structure 208. A gate structure 208 may be disposed over the substrate 202 and one or more gate structures may be interposed between the source and the gateBetween the drains, the source and drain are collectively referred to as source/drain features having the numeral 210, with a channel region defined between the source and drain 210. Source/drain features may refer to either source or drain, either individually or collectively depending on the context. One or more gate structures 208 engage the channel region such that current may flow between the source/drain regions during operation. In some implementations, the gate structure formation may be over the fin structure such that the gate structure wraps around portions of the fin structure. For example, one or more gate structures wrap around the channel region of the fin structure, thereby being interposed between the source region and the drain region of the fin structure. In some embodiments, the gate structure includes a Metal Gate (MG) stack configured to achieve a desired function according to design requirements of the semiconductor device. In some embodiments, the metal gate stack may include a gate dielectric and a gate electrode over the gate dielectric. The gate dielectric comprises a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric material, or a combination thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant, such as a dielectric constant greater than silicon oxide (k≡3.9). Exemplary high-k dielectric materials may include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable compositions, or combinations thereof. In some embodiments, the gate dielectric may include a multi-layer structure, such as an interfacial layer including, for example, silicon oxide, and a high-k dielectric layer including, for example, hfO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO 2 、Al 2 O 3 、HfO 2 -Al 2 O 3 、TiO 2 、Ta 2 O 5 、La 2 O 3 、Y 2 O 3 Other suitable high-k dielectric materials, or combinations thereof. The gate electrode comprises a conductive material. In some embodiments, the gate electrode may include multiple layers, such as one or more capping layers, work function layers, glue/barrier layers, and/or metal filled (or bulk) layers. The capping layer may include a material that prevents or eliminates diffusion and/or reaction of components between the gate dielectric and other layers of the gate electrode. In one placeIn some embodiments, the capping layer may include a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W 2 N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof. The work function layer includes a conductive material, such as an n-type work function material and/or a p-type work function material, tuned to have a desired work function, such as an n-type work function or a p-type work function. The P-type work function material may include TiN, taN, ru, mo, al, WN, zrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 WN, other p-type work function materials, or combinations thereof. The N-type work function material may include Ti, al, ag, mn, zr, tiAl, tiAlC, taC, taCN, taSiN, taAl, taAlC, tiAlN, other N-type work function materials, or combinations thereof. The glue/barrier layer may include a material that promotes adhesion between adjacent layers, such as a work function layer and a metal fill layer, and/or a material that blocks and/or reduces diffusion between gate layers, such as a work function layer and a metal fill layer. For example, the glue/barrier layer may include a metal (e.g., W, al, ta, ti, ni, cu, co, other suitable metals or combinations thereof), a metal oxide, a metal nitride (e.g., tiN), or combinations thereof. The metal fill layer may include a suitable conductive material such as Al, W, and/or Cu. In the disclosed embodiments, the gate structure further includes gate spacers disposed on sidewalls of the metal gate stack.
The source/drain features 210 may be formed by epitaxial growth with the same or a different semiconductor material as the substrate 202. For example, source/drain features 210 of PFETs are epitaxially grown with silicon germanium and source/drain features 210 of NFETs are epitaxially grown with silicon or silicon carbide for strain effects to enhance carrier mobility. Forming epitaxial source/drain features 210 may include etching to recess the source/drain regions and epitaxially growing one or more semiconductor materials in the recessed source/drain regions of active region 206. The gate structure 208 and the epitaxial source/drain features 210 form part of a field effect transistor. Thus, the gate structure and/or the epitaxial source/drain features are alternatively referred to as device features. In some embodiments, the epitaxial source/drain features wrap around source/drain regions of the fin structure. The epitaxial process may implement CVD deposition techniques (e.g., vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable Selective Epitaxial Growth (SEG) processes, or combinations thereof. The epitaxial source/drain features may be doped with n-type dopants and/or p-type dopants. In some embodiments where the transistor is configured as an n-type device (e.g., having an n-channel), the epitaxial source/drain feature may be a silicon-containing epitaxial layer or a silicon-containing carbon epitaxial layer doped with phosphorus, other n-type dopants, or a combination thereof (e.g., forming a Si: P-epitaxial layer or a Si: C: P-epitaxial layer). In some embodiments where the transistor is configured as a p-type device (e.g., having a p-channel), the epitaxial source/drain features may be a silicon and germanium-containing epitaxial layer doped with boron, other p-type dopants, or a combination thereof (e.g., forming a Si: ge: B epitaxial layer). In some embodiments, an annealing process may be performed to activate dopants in the epitaxial source/drain features.
An interlayer dielectric (ILD) layer 212 may be formed on the substrate 202. In some embodiments, ILD layer 212 may be formed of any suitable dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS) formed oxide, phosphosilicate glass (PSG), boron doped phosphosilicate glass (BPSG)), a low-k dielectric material, other suitable dielectric material, or a combination thereof. Exemplary low-k dielectric materials may include Fluorinated Silicate Glass (FSG), carbon doped silicon oxide,(applied materials of Santa Clara, calif.), xerogels, aerogels, amorphous carbon fluorides, parylene, siLK (Dow chemical company of Midland, mich.), polyimides, or combinations thereof. In some embodiments, the first ILD layer 212 may be formed by a deposition process (such as CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, other suitable methods, or a combination thereof). After depositing the first ILD layer 212, a CMP process and/or other planarization process may be performedThe process is such that the first ILD layer 212 has a substantially planar surface to enhance the formation of the overlying layers. ILD layer 212 is not illustrated in fig. 3A, so other underlying components may be shown in fig. 3A.
Referring to fig. 4A and 4B, the method 100 proceeds to form various material layers, including an etch stop layer 214 and an ILD layer 216, on the substrate 202. In some embodiments, the deposited material layer further includes a first hard mask layer 218, a dielectric layer 220, such as a silicon oxide layer, and a second hard mask 222, which will be described in detail below.
In particular, referring to fig. 2, 4A, and 4B, the method 100 proceeds to block 104 to deposit a first Etch Stop Layer (ESL) 214 and another ILD layer 216 over the semiconductor substrate 202. In some embodiments, the first ESL 214 may comprise silicon nitride. In some embodiments, the first ESL 214 comprises any suitable dielectric material of a composition different from that of the ILD layer in order to achieve etch selectivity and etch stop, such as silicon oxycarbide (SiOC), silicon nitride (e.g., siCN, siN, siON), silicon carbide (e.g., siC), metal oxide, other suitable materials, or combinations thereof. In some embodiments, the first ESL 214 may be formed by a suitable deposition process, such as CVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, other suitable methods, or combinations thereof. An ILD layer 216 is deposited on the first ESL 214. ILD layer 216 is similar in formation and composition to ILD layer 212. After depositing the first ESL 214 and ILD layer 216, a CMP process and/or other planarization process may be performed such that the ILD layer 216 has a substantially planar surface to enhance the formation of an overlying layer.
Still referring to fig. 2, 4A, and 4B, the method 100 proceeds to block 106 to form a first hard mask layer 218 and a dielectric layer 220 over the ILD layer 216. The first hard mask layer 218 may comprise any suitable material of different composition than the upper and lower materials in order to achieve etch selectivity. In some embodiments, the first hard mask layer 218 includes a metal oxide (such as aluminum oxide, hafnium oxide, or titanium oxide), a metal nitride (such as titanium nitride or aluminum nitride), other suitable dielectric layers (such as silicon oxynitride), or combinations thereof. In some embodiments, the first hard mask layer 218 may be deposited using PVD, CVD, ALD, other suitable deposition processes, or a combination thereof.
A layer of dielectric material 220 is formed on the first hard mask layer 218. In some embodiments, the dielectric material layer 220 comprises silicon oxide, and the dielectric material layer 220 may be formed by a suitable deposition technique, such as CVD, flowable CVD, other deposition methods, or combinations thereof. The layer of dielectric material 220 may include other suitable dielectric materials, such as silicon oxynitride.
Still referring to fig. 2, 4A and 4B, the method 100 proceeds to block 108 where a second hard mask layer 222 patterned with openings 224 is formed to define regions for positioning contacts 68 on the source/drain features 210. The operation of forming the patterned hard mask layer 222 includes suitable processes, such as processes further including depositing the hard mask layer 222; forming a patterned photoresist layer by photolithography; and etching the hard mask layer 222 using the patterned photoresist layer as an etch mask, thereby transferring the openings of the patterned photoresist layer to the hard mask layer 222.
Exemplary lithographic processes may include photoresist coating, exposure to Ultraviolet (UV) radiation, post-exposure baking, developing the photoresist, and hard baking. After etching the hard mask layer 222, the patterned photoresist layer may be removed by a suitable method such as wet stripping or plasma ashing. The photolithographic patterning may also be implemented or replaced by other suitable methods such as maskless lithography, electron beam writing, ion beam writing, and molecular imprinting. The etching process applied to the hard mask layer 222 may include dry etching, wet etching, or a combination thereof.
Referring to fig. 2, 5A and 5B, the method 100 proceeds to block 110 where the dielectric layer 220 and the first hard mask layer 218 are patterned to extend the openings 224 into the dielectric layer 220 and the first hard mask layer 218. The extended opening 224 is also referred to as a trench 224. In some embodiments, patterning the dielectric layer 220 and the first hard mask layer 218 includes one or more etching processes using respective etchants to effectively remove respective materials within the trenches 224. In some embodiments, the etching process is performed in a single etching process. In one placeIn some embodiments, the etching process includes applying hydrofluoric acid to etch the dielectric layer 220 comprising silicon oxide. In some embodiments, the etching process includes applying phosphoric acid (H 3 PO 4 ) The solution is used to etch the hard mask layer 218 comprising silicon nitride. Thereafter, the second hard mask layer 222 may be removed by an etching process using an appropriate etchant to selectively remove the second hard mask layer 222.
Referring to fig. 2, 6A and 6B, the method 100 proceeds to block 112 to pattern the ILD layers 212, 216 and the ESL 214 to further extend the trenches 224 therein such that the source/drain features 210 are exposed within the trenches 224. Patterning the ILD layer 216 and the ESL 214 includes an etching process, such as a dry etch, a wet etch, or a combination thereof, using the patterned dielectric layer 220 and the hard mask layer 218 as an etch mask. In some embodiments, patterning ILD layer 216 comprises two etching steps: a first etch process using a first etchant to selectively etch ILD layer 216 until it stops at ESL 214; and a second etching process using a second etchant to selectively remove ESL 214 within trench 224, thereby exposing source/drain feature 210 within trench 224. Thus, trenches 224 for contacts 68 are formed in ILD layer 216. The formation of trench 224 employs various layers of material and various patterning and etching processes. For example, ESL 214 provides an etch stop function, enabling an etch process applied to ILD layer 216 to etch completely through ILD layer 216 without damaging substrate 202, and in particular without damaging source/drain features 210. In another example, the hard mask layer 218 and the dielectric layer 220 are further employed along with additional etching processes to adjust the profile of the trench 224 as the patterning process transfers the trench 224 to the ILD layer 216. When the individual etching steps are applied to the hard mask 222, dielectric layer 220, hard mask 218, ILD layer 216, ESL 214, and ILD layer 212, respectively, the multiple etching steps use an appropriate combination of wet and dry etches with respective etchants, each of which has a significantly greater etch rate. In particular, multiple etching steps may freely use an appropriate combination of wet and dry etches with respective etchants, each having a different lateral etch rate/vertical etch rate ratio, thereby modifying the profile of trench 224.
For example, the etching step applied to ILD layer 216 comprises a dry etch to etch ILD layer 216 substantially vertically, and the etching step applied to ESL 214 comprises a wet etch to open ESL 214, such as with hot phosphoric acid when ESL 214 is silicon nitride; and the etching step applied to ILD layer 212 includes a wet etch with a significant lateral etch to substantially widen trench 224 in ILD layer 212. After forming the trenches 224 in the ILD layer 216, the dielectric layer 220 and the hard mask layer 218 are removed by one or more etching processes.
Referring to fig. 2, 7A and 7B, the method 100 proceeds to block 114 with forming a dielectric liner 226 on the sidewalls of the trench 224. The dielectric liner 226 includes one or more suitable dielectric materials to enhance integration of the contact 68 and the ILD layer 216 to be formed, such as to function to increase adhesion therebetween and to prevent diffusion of the contact 68 into the ILD layer 216. In some embodiments, the dielectric liner 226 comprises silicon nitride, silicon oxynitride, other suitable dielectric material, or a combination thereof. The dielectric liner 226 may be formed by deposition such as CVD and anisotropic etching such as plasma etching to remove a bottom portion of the dielectric liner 226.
Referring to fig. 2, 8A, and 8B, the method 100 may proceed to block 116 to form a silicide layer 228 on the epitaxial source/drain features 210. The silicide layer 228 serves as part of the source/drain features to reduce contact resistance between the overlying contacts (to be formed) and the epitaxial source/drain features 210. In some embodiments, the silicide layer may be formed by a self-aligned silicide (salicide) process that includes depositing a metal layer over the epitaxial source/drain features 210; annealing to react the metal with silicon; and etching to remove unreacted metal to form silicide layer 228 that is self-aligned to source/drain feature 210. The metal layer comprises any material suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The semiconductor structure 200 is then heated (e.g., subjected to an annealing process) to react the composition of the epitaxial source/drain features (e.g., silicon and/or germanium) with the metal. Thus, the silicide layer includes a metal and a composition of epitaxial source/drain features (e.g., silicon and/or germanium). In some embodiments, the silicide layer may include nickel silicide, titanium silicide, or cobalt silicide. Any unreacted metal, such as the remainder of the metal layer, is selectively removed by any suitable process, such as an etching process.
Referring to fig. 2, 9A, and 9B, the method 100B proceeds to block 118 where the trench 224 is filled with a metal layer 230. The forming may include deposition and Chemical Mechanical Polishing (CMP) processes to remove the excess metal layer and planarize the top surface. In some embodiments, the metal layer 230 includes tungsten (W), ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), or a combination thereof. In some other embodiments, the metal layer 230 includes any suitable conductive material, such as Cu, co, ru, W, mo, ni, cr, ir, pt, rh, ta, ti, al, taN, tiN, a compound, or other suitable conductive material. In some embodiments, the metal layer 230 may be deposited using PVD, CVD, ALD, electroplating, or other suitable deposition process, or a combination thereof.
Referring to fig. 2, 10A, and 10B, the method 100 proceeds to block 120 where one or more material layers 232 are deposited as a hard mask. The material layer 232 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In the disclosed embodiment, the material layer 232 includes a silicon oxide layer and a silicon nitride layer disposed on the silicon oxide layer. In some embodiments, the material layer 232 may be deposited using CVD or other suitable deposition process or combinations thereof.
Referring to fig. 2, 11A, and 11B, the method 100 proceeds to block 122 to pattern the material layer 232. The patterning process is similar to the other patterning processes described above. For example, patterning processes include photolithography processes and etching. The patterned material layer 232 includes openings. The patterned material layer 232 and ILD layer 216 are used together as an etch hard mask to define the areas to be etched.
Referring to fig. 2, 12A and 12B, the method 100 proceeds to block 124 by etching through the openings of the common hard mask including the material layer 232 and the ILD layer 216 to form metal layer 230 are recessed to form a channel 234. An etching process applied to the metal layer 230 forms the patterned metal structure 230 and the trenches 234 therein. In some embodiments, patterning metal layer 230 includes a reactive ion etch, a dry etch process, a wet etch process, other etch processes, or a combination thereof. In some embodiments, the etching gas comprises a chlorine-based etching gas (such as SiCl, for example) depending on the metal scheme in the first metal layer and the second metal layer 2 、SiCl 4 Or combinations thereof), fluorine-based (such as CF 4 、CF 3 、C 4 F 8 、NF 3 Or a combination thereof) etching gas, N 2 、O 2 Or a combination thereof. In some embodiments, the etching process is controlled such that the recessed surface is below the top surface of ESL 214. In some embodiments, the etching process is controlled such that the recessed surface is flush with the top surface of ILD layer 212 or below the top surface of ILD layer 212. Accordingly, the bottom surface of the via 70 is flush with the bottom surface of the ESL 214 or below the bottom surface of the ESL 214. This may be controlled by checking the endpoint by a suitable technique, such as detecting the etching exhaust composition or etching time or other suitable method. The metal structure 230 thus formed includes a top portion that is a via 70 and a bottom portion that is a contact 68, as will be described further below.
Referring to fig. 2, 13A and 13B, the method 100 proceeds to block 126 to refill the dielectric layer 236 into the trench 234. Dielectric layer 236 includes silicon carbide (SiC), silicon oxide (SiO), silicon oxynitride (SiCON), other suitable dielectric material, or combinations thereof. According to some embodiments, dielectric layer 236 is compositionally different from ILD layer 212 and dielectric liner 226. According to some embodiments, forming the dielectric layer 236 includes depositing a dielectric material and performing a CMP process to planarize the top surface. Deposition includes CVD, flowable CVD, PECVD, other suitable deposition, or combinations thereof.
The metal structure 230 thus formed includes a bottom portion that is the contact 68 and a top portion that is the via. The pair of contacts 68 and vias 70 are self-aligned with each other and have the same composition, there being no interface between the contacts 68 and vias 70 to reduce wiring resistance. In some embodiments, the height Hv of the via 70 is less than the height Hc of the contact 68. In a further embodiment, the height ratio Hv/Hc is in the range between 1.2 and 11.
Fig. 14 illustrates, in part, a top view of a semiconductor structure 200 in accordance with some embodiments. For example, the ILD layer is not illustrated in fig. 14 so that other components can be clearly seen. Specifically, the via 70 and the refilled dielectric member 236 are surrounded by the dielectric liner 226. The contacts 68 extend continuously from the vias 70 to the source/drain features 210, and the contacts 68 are also surrounded by dielectric pads 226. In top view, the contact 68 completely overlaps the via 70 and the refilled dielectric member 236. The dielectric liner 226, the refilled dielectric component 236, and the ILD layers 212/216 are compositionally different from one another. For example, dielectric liner 226 comprises silicon nitride, refill dielectric feature 236 comprises silicon oxide, and ILD layers 212/216 comprise a low-k dielectric material. Accordingly, in top view, the contact 68 is not visible in fig. 14. Specifically, the contact 68 spans lengthwise along the Y-direction between the first and second ends. The through hole 70 spans along the Y-direction between the first edge and the second edge. The first edge is aligned with the first end. The second edge is remote from the second end and is located between the first end and the second end. In top view, the via 70 is disposed directly above the STI structure 204 and away from the active area 206.
Although one set of contacts 68, vias 70, refill dielectric members 236, and dielectric pads 226 are described above, semiconductor structure 200 includes multiple sets of contacts 68, vias 70, refill dielectric members 236, and dielectric pads 226, as shown in fig. 14. For example, a first set is formed on the first active region 206 and a second set is formed on the second active region. The first and second sets are aligned along the Y-direction and corresponding through holes 70 are formed on the adjacent ends of the corresponding contacts 68. The vias 70 and contacts 68 of the semiconductor structure 200 may have other configurations, such as the one shown in fig. 15, depending on the design and circuit layout.
The present disclosure provides many different embodiments. In one embodiment, a semiconductor structure and a method of forming a semiconductor structure are provided. The method includes providing a semiconductor substrate; forming a trench to expose the source/drain feature; forming a dielectric liner on sidewalls of the trench; forming a metal layer in the trench; patterning the metal layer to recess portions of the metal layer to form grooves in the metal layer; and refilling the recess with dielectric material, thereby forming a pair of contacts and vias self-aligned to each other, and electrically connecting the source/drain feature to the overlying interconnect structure through the pair of contacts and vias. The contact and via pairs so formed are self-aligned and comprise the same composition, with no interface between the contact and via to reduce resistance.
In one exemplary aspect, the present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate having source/drain features and gate structures formed thereon; forming an interlayer dielectric layer on a semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the groove; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling the dielectric material layer in the grooves.
In some embodiments, recessing portions of the metal layer includes etching portions of the metal layer to form contacts and vias that are self-aligned with the contacts.
In some embodiments, the layer of dielectric material is compositionally different from the dielectric liner and the interlayer dielectric layer.
In some embodiments, the layer of dielectric material comprises silicon nitride; the dielectric liner includes at least one of silicon oxide and silicon oxynitride; and the interlayer dielectric layer comprises a low-k dielectric material.
In some embodiments, forming the dielectric liner includes depositing a dielectric film on a surface of the trench and applying an anisotropic etch to the dielectric film.
In some embodiments, forming the interlayer dielectric layer further comprises forming an etch stop layer disposed below the interlayer dielectric layer.
In some embodiments, recessing portions of the metal layer in the trench includes: forming a patterned dielectric layer through a photolithography process and an etching process; and recessing the metal layer using the interlayer dielectric layer and the patterned dielectric layer as a common etch mask.
In some embodiments, recessing the portion of the metal layer in the trench includes recessing the portion of the metal layer such that a top surface of the recessed portion of the metal layer is below a bottom surface of the etch stop layer.
In some embodiments, refilling the dielectric material layer in the recess includes depositing the dielectric material layer in the recess; and performing a chemical mechanical polishing process on the dielectric material layer.
In some embodiments, the dielectric liner surrounds the dielectric material layer and the metal layer in a top view.
In some embodiments, the contacts overlap the dielectric material layer and the vias in a top view.
In another exemplary aspect, the present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate having source/drain features and gate structures formed thereon; forming an interlayer dielectric layer on a semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a silicide layer on the source/drain feature; filling a metal layer on the silicide layer in the groove; forming a patterned mask having an opening, wherein a first portion of the metal layer is exposed within the opening and a second portion of the metal layer is covered by the patterned mask, and wherein the second portion extends to the second portion in the trench; and etching the metal layer through the openings of the patterned mask such that a first portion of the metal layer is recessed and a second portion of the metal layer remains.
In some embodiments, the method of forming a semiconductor structure further comprises forming a dielectric liner on sidewalls of the trench prior to filling the metal layer in the trench; and refilling the dielectric material layer in the groove after etching the metal layer.
In some embodiments, the dielectric liner surrounds the dielectric material layer and the metal layer in a top view; and in a top view, the contact fully overlaps the dielectric material layer and the via.
In some embodiments, the layer of dielectric material is compositionally different from the dielectric liner and the interlayer dielectric layer; and the dielectric liner extends continuously from the sidewall of the second portion of the metal layer from top to bottom.
In some embodiments, forming the dielectric liner includes depositing a dielectric film on a surface of the trench and applying an anisotropic etch to the dielectric film.
In some embodiments, the method of forming a semiconductor structure further includes forming an etch stop layer disposed below the interlayer dielectric layer, wherein etching the metal layer includes recessing the first portion of the metal layer such that a top surface of the recessed first portion of the metal layer is below a top surface of the etch stop layer.
In yet another exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure comprises a source/drain component and a gate structure, and is arranged on the semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; a metal component of metal embedded in the interlayer dielectric layer and positioned on the source/drain component, wherein the metal component comprises a lower portion and an upper portion of an elongated shape, and wherein the upper portion is disposed above a first elongated end of the lower portion and away from a second elongated end of the lower portion; a dielectric material member disposed over the second longitudinal end of the lower portion; and a dielectric liner disposed on sidewalls of the metal layer and the dielectric material member. The dielectric liner is compositionally different from the interlayer dielectric layer and the dielectric material component. In a top view, the dielectric liner surrounds the metal component and the dielectric material component.
In some embodiments, the semiconductor structure further comprises an etch stop layer disposed below the interlayer dielectric layer, wherein a top surface of the lower portion of the metal feature is below a top surface of the etch stop layer, and wherein a bottom surface of the upper portion of the metal feature is below a top surface of the etch stop layer.
In some embodiments, the lower portion of the metal component completely overlaps the upper portion of the metal component and the dielectric material component.
The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate having source/drain features and gate structures formed thereon;
Forming an interlayer dielectric layer on the semiconductor substrate;
patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench;
forming a dielectric liner on sidewalls of the trench;
filling a metal layer in the groove;
recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and
and refilling the dielectric material layer in the grooves.
2. The method of claim 1, wherein recessing the portion of the metal layer comprises etching the portion of the metal layer to form a contact and a via self-aligned with the contact.
3. The method of claim 2, wherein the layer of dielectric material is compositionally different from the dielectric liner and the interlayer dielectric layer.
4. The method of claim 3, wherein,
the dielectric material layer comprises silicon nitride;
the dielectric liner includes at least one of silicon oxide and silicon oxynitride; and
the interlayer dielectric layer includes a low-k dielectric material.
5. The method of claim 1, wherein forming the dielectric liner comprises depositing a dielectric film on a surface of the trench and applying an anisotropic etch to the dielectric film.
6. The method of claim 1, wherein forming the interlayer dielectric layer further comprises forming an etch stop layer disposed below the interlayer dielectric layer.
7. The method of claim 6, wherein recessing the portion of the metal layer in the trench comprises:
forming a patterned dielectric layer through the photolithography process and the etching process; and
the metal layer is recessed using the interlayer dielectric layer and the patterned dielectric layer as a common etch mask.
8. The method of claim 7, wherein recessing the portion of the metal layer in the trench comprises recessing the portion of the metal layer such that a top surface of the recessed portion of the metal layer is below a bottom surface of the etch stop layer.
9. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate having source/drain features and gate structures formed thereon;
forming an interlayer dielectric layer on the semiconductor substrate;
patterning the interlayer dielectric layer to form a trench to expose the source/drain features within the trench;
forming a silicide layer on the source/drain features;
Filling a metal layer on the silicide layer in the groove;
forming a patterned mask having an opening, wherein a first portion of the metal layer is exposed within the opening and a second portion of the metal layer is covered by the patterned mask, and wherein the second portion extends to the second portion in the trench; and
the metal layer is etched through the openings of the patterned mask such that the first portion of the metal layer is recessed and the second portion of the metal layer remains.
10. A semiconductor structure, comprising:
source/drain features and a gate structure disposed on the semiconductor substrate;
an interlayer dielectric layer disposed on the semiconductor substrate;
a metal component of metal embedded in the interlayer dielectric layer and positioned on the source/drain component, wherein the metal component comprises a lower portion and an upper portion of elongated shape, and wherein the upper portion is disposed above a first lengthwise end of the lower portion and the upper portion is remote from a second lengthwise end of the lower portion;
a dielectric material member disposed over said second longitudinal end of said lower portion; and
A dielectric liner disposed on sidewalls of the metal layer and the dielectric material component, wherein the dielectric liner is compositionally different from the interlayer dielectric layer and the dielectric material component, and wherein the dielectric liner surrounds the metal component and the dielectric material component in a top view.
CN202310942561.2A 2022-07-28 2023-07-28 Semiconductor structure and forming method thereof Pending CN117096099A (en)

Applications Claiming Priority (3)

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US63/393,109 2022-07-28
US18/298,629 2023-04-11
US18/298,629 US20240038855A1 (en) 2022-07-28 2023-04-11 Semiconductor structure with self-aligned conductive features

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