CN118230785A

CN118230785A - Control circuit, control method and memory

Info

Publication number: CN118230785A
Application number: CN202211610632.0A
Authority: CN
Inventors: 高恩鹏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-12-14
Filing date: 2022-12-14
Publication date: 2024-06-21
Also published as: WO2024124678A1

Abstract

The present disclosure provides a control circuit, a method thereof, and a memory, the control circuit including: the clock generation module is used for generating a first clock signal, a second clock signal and a third clock signal according to an external clock signal; the command decoding module is used for decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to a third clock signal to obtain a read command signal; the command processing module is used for carrying out delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal; and the command control module is used for sampling and pulse widening the read control signal according to the first clock signal and the second clock signal to obtain a target control signal. Thus, the interval time between the command address signal and the target control signal satisfies the preset time sequence condition, so that the energy loss and reflection in the transmission process can be reduced and the signal integrity can be improved when the on/off of the NT ODT function is controlled.

Description

Control circuit, control method and memory

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular relates to a control circuit, a control method and a memory.

Background

With the continuous development of semiconductor technology, higher and higher requirements are being placed on the data transmission speed when manufacturing and using devices such as computers. In order to obtain a faster Data transmission speed, a series of devices such as a memory capable of transmitting Data at Double Data Rate (DDR) have been developed.

In a dynamic random access memory (Dynamic Random Access Memory, DRAM) chip, for an on-die termination (On Die Termination, ODT) function of the chip, impedance matching of termination resistors needs to satisfy a preset timing condition, but due to different delay times on transmission lines, there is a deviation in timing, thereby affecting the ODT function of DQ modules and reducing signal integrity (SIGNAL INTEGRITY, SI).

Disclosure of Invention

The embodiment of the disclosure provides a control circuit, a control method and a memory.

In a first aspect, an embodiment of the present disclosure provides a control circuit, where the control circuit includes a clock generating module, a command decoding module, a command processing module, and a command control module, the clock generating module is connected to the command decoding module, the command processing module, and the command control module, and the command processing module is further connected to the command control module, where:

the clock generation module is used for receiving an external clock signal and generating a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, which is earlier than the third clock signal;

The command decoding module is used for receiving the command address signal and the third clock signal, decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to the third clock signal to obtain a read command signal;

The command processing module is used for receiving the third clock signal, the read command signal and the read delay signal, and carrying out delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal comprises read delay (READ LATENCY, RL) information;

The command control module is used for receiving the first clock signal, the second clock signal and the read control signal, and carrying out sampling and pulse widening processing on the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; the interval time between the command address signal and the target control signal meets a preset time sequence condition, and the target control signal is used for controlling the conduction state of the terminal resistor.

In some embodiments, the control circuit further comprises a mode register module coupled to the command processing module, wherein:

And the mode register module is used for setting the RL information, generating a read delay signal comprising the RL information and providing the read delay signal to the command processing module.

In some embodiments, the clock generation module is configured to divide the external clock signal and perform a first clock delay process to obtain a first clock Zhong Ji signal and a first clock Zhong Ou signal, where clock periods of the first clock signal and the first clock Zhong Ou signal are two times of clock periods of the external clock signal, and the first clock signal is composed of the first clock signal and the first clock Zhong Ou signal, and a phase difference between the first clock signal and the first clock Zhong Ou signal is 180 degrees; and

The clock generation module is further used for carrying out frequency division and second clock delay processing on the external clock signal to obtain a second clock odd signal and a second clock even signal, wherein the clock periods of the second clock odd signal and the second clock even signal are two times of the clock period of the external clock signal, the second clock signal consists of the second clock odd signal and the second clock even signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees;

The clock generation module is further used for carrying out frequency division and third clock delay processing on the external clock signal to obtain a third clock odd signal and a third clock even signal, wherein the clock periods of the third clock odd signal and the third clock even signal are two times of the clock period of the external clock signal, the third clock signal consists of the third clock odd signal and the third clock even signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

In some embodiments, the delay time corresponding to the first clock delay process is less than the delay time corresponding to the second clock delay process; the delay time corresponding to the second clock delay process is smaller than the delay time corresponding to the third clock delay process.

In some embodiments, the command decoding module is configured to decode the command address signal to obtain a decoded odd signal and a decoded even signal; sampling the decoding odd signal according to the third clock odd signal to obtain a reading command odd signal; sampling the decoding even signal according to the third clock even signal to obtain a read command even signal;

The command processing module is used for carrying out delay processing on the read command odd signal according to the third clock odd signal and the read delay signal to obtain a read control odd signal; performing delay processing on the read command even signal according to the third clock even signal and the read delay signal to obtain a read control even signal;

The decoding signal is composed of a decoding odd signal and a decoding even signal, the reading command signal is composed of a reading command odd signal and a reading command even signal, and the reading control signal is composed of a reading control odd signal and a reading control even signal.

In some embodiments, the command control module includes a first control module, a second control module, a logic module, and a delay adjustable module, wherein:

the first control module is used for receiving the first time Zhong Ji signal, the second clock odd signal and the read control odd signal, and carrying out sampling and pulse widening processing on the read control odd signal according to the first clock odd signal and the second clock odd signal to obtain a first control signal;

The second control module is used for receiving the first time Zhong Ou signal, the second clock even signal and the read control even signal, and carrying out sampling and pulse widening processing on the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal;

The logic module is used for carrying out logic operation on the first control signal and the second control signal to obtain an initial control signal;

And the delay adjustable module is used for receiving the mode control signal and the initial control signal, and carrying out delay processing on the initial control signal according to the mode control signal to obtain a target control signal.

In some embodiments, the logic module comprises a first or gate, wherein:

the first input end of the first OR gate is connected with the output end of the first control module and is used for receiving a first control signal; the second input end of the first OR gate is connected with the output end of the second control module and is used for receiving a second control signal;

the output end of the first OR gate is connected with the input end of the delay adjustable module and is used for outputting an initial control signal.

In some embodiments, the delay adjustable module comprises K delay units, K being an integer greater than 0, wherein:

And the delay adjustable module is used for determining a target number of delay units from the K delay units according to the mode control signals, and carrying out delay processing on the initial control signals through the target number of delay units to obtain target control signals.

In some embodiments, the first control module includes a first sampling module, a second sampling module, and a third sampling module, wherein:

The first sampling module is used for sampling the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal;

the second sampling module is used for sampling the first sampling odd signal according to the first time Zhong Ji signal to obtain a second sampling odd signal;

the third sampling module is used for sampling and pulse widening the second sampling odd signal according to the first time Zhong Ji signal to obtain a first control signal;

The second control module comprises a fourth sampling module, a fifth sampling module and a sixth sampling module, wherein:

the fourth sampling module is used for sampling the read control even signal according to the second clock even signal to obtain a first sampling even signal;

The fifth sampling module is used for sampling the first sampling even signal according to the first time Zhong Ou signal to obtain a second sampling even signal;

And the sixth sampling module is used for sampling and pulse widening the second sampling even signal according to the first time Zhong Ou signal to obtain a second control signal.

In some embodiments, the third sampling module comprises a first sampling sub-module and at least one second sampling sub-module, wherein:

The first sampling submodule is used for sampling the second sampling odd signal according to the first time Zhong Ji signal to obtain a third sampling odd signal;

The at least one second sampling submodule is used for carrying out logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and carrying out sampling processing on the fourth sampling odd signal according to the first clock odd signal to obtain a first control signal;

the sixth sampling module comprises a third sampling sub-module and at least one fourth sampling sub-module, wherein:

the third sampling submodule is used for carrying out sampling processing on the second sampling even signal according to the first time Zhong Ou signal to obtain a third sampling even signal;

And the at least one fourth sampling sub-module is used for carrying out logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and carrying out sampling processing on the fourth sampling even signal according to the first clock even signal to obtain a second control signal.

In some embodiments, the first sampling module includes a first flip-flop, wherein an input of the first flip-flop is configured to receive the read control odd signal, a clock of the first flip-flop is configured to receive the second clock odd signal, and an output of the first flip-flop is configured to output the first sampling odd signal;

The second sampling module comprises a second trigger, wherein the input end of the second trigger is used for receiving the first sampling odd signal, the clock end of the second trigger is used for receiving the first time Zhong Ji signal, and the output end of the second trigger is used for outputting the second sampling odd signal.

In some embodiments, the first sampling submodule includes a third flip-flop, wherein an input of the third flip-flop is configured to receive the second sampling odd signal, a clock of the third flip-flop is configured to receive the first time Zhong Ji signal, and an output of the third flip-flop is configured to output the third sampling odd signal;

The second sampling submodule comprises a second or gate and a fourth trigger, wherein a first input end of the second or gate is used as a first input end of the second sampling submodule to be connected with a second sampling odd signal, a second input end of the second or gate is used as a second input end of the second sampling submodule to be connected with an output end of a previous second sampling submodule, an output end of the second or gate is connected with an input end of the fourth trigger, a clock end of the fourth trigger is used as a clock end of the second sampling submodule to be connected with a first time Zhong Ji signal, and an output end of the fourth trigger is used as an output end of the second sampling submodule to be used for outputting an intermediate signal.

In some embodiments, when the number of the at least one second sampling submodule is N, the first input terminal of the ith second sampling submodule is connected with the second sampling odd signal, the second input terminal of the ith second sampling submodule is connected with the ith input signal, the clock terminal of the ith second sampling submodule is connected with the first time Zhong Ji signal, and the output terminal of the ith second sampling submodule is used for outputting the ith intermediate signal;

when i is equal to 1, the ith input signal is a third sampling odd signal; when i is greater than 1, the ith input signal is the ith-1 intermediate signal; and when i is equal to N, the ith intermediate signal is a first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

In some embodiments, the fourth sampling module includes a fifth flip-flop, wherein an input of the fifth flip-flop is configured to receive the read control even signal, a clock of the fifth flip-flop is configured to receive the second clock even signal, and an output of the fifth flip-flop is configured to output the first sampling even signal;

The fifth sampling module comprises a sixth trigger, wherein the input end of the sixth trigger is used for receiving the first sampling even signal, the clock end of the sixth trigger is used for receiving the first time Zhong Ou signal, and the output end of the sixth trigger is used for outputting the second sampling even signal.

In some embodiments, the third sampling submodule includes a seventh flip-flop, wherein an input of the seventh flip-flop is configured to receive the second sampling even signal, a clock of the seventh flip-flop is configured to receive the first time Zhong Ou signal, and an output of the seventh flip-flop is configured to output the third sampling even signal;

The fourth sampling submodule comprises a second or gate and an eighth trigger, wherein the first input end of the second or gate is used as the first input end of the fourth sampling submodule to be connected with a second sampling even signal, the second input end of the second or gate is used as the second input end of the fourth sampling submodule to be connected with the output end of the previous fourth sampling submodule, the output end of the second or gate is connected with the input end of the eighth trigger, the clock end of the eighth trigger is used as the clock end of the fourth sampling submodule to be connected with the first time Zhong Ou signal, and the output end of the eighth trigger is used as the output end of the fourth sampling submodule to be used for outputting an intermediate signal.

In some embodiments, when the number of the at least one fourth sampling submodule is M, the first input end of the ith fourth sampling submodule is connected with the second sampling even signal, the second input end of the ith fourth sampling submodule is connected with the ith input signal, the clock end of the ith fourth sampling submodule is connected with the first time Zhong Ou signal, and the output end of the ith fourth sampling submodule is used for outputting the ith intermediate signal; when i is equal to 1, the ith input signal is a third sampling even signal; when i is greater than 1, the ith input signal is the ith-1 intermediate signal; and when i is equal to M, the ith intermediate signal is a second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

In a second aspect, embodiments of the present disclosure provide a control method, including:

Receiving an external clock signal through a clock generation module, and generating a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, which is earlier than the third clock signal;

Receiving a command address signal and a third clock signal through a command decoding module, decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to the third clock signal to obtain a read command signal;

Receiving a third clock signal, a read command signal and a read delay signal through a command processing module, and carrying out delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal comprises RL information;

Receiving a first clock signal, a second clock signal and a read control signal through a command control module, and sampling and pulse widening the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; the interval time between the command address signal and the target control signal meets a preset time sequence condition, and the target control signal is used for controlling the conduction state of the terminal resistor.

In a third aspect, embodiments of the present disclosure provide a memory comprising at least a control circuit as set forth in any one of the first aspects.

The embodiment of the disclosure provides a control circuit, a method thereof and a memory, wherein in the control circuit, a clock generation module is respectively connected with a command decoding module, a command processing module and a command control module, and the command processing module is also connected with the command control module. Specifically, the clock generation module is used for receiving an external clock signal and generating a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, which is earlier than the third clock signal; the command decoding module is used for receiving the command address signal and the third clock signal, decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to the third clock signal to obtain a read command signal; the command processing module is used for receiving the third clock signal, the read command signal and the read delay signal, and carrying out delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal; the command control module is used for receiving the first clock signal, the second clock signal and the read control signal, and carrying out sampling and pulse widening processing on the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; the target control signal is used for controlling the conduction state of the terminal resistor. In this way, the read delay signal comprises the RL information, and the association relationship exists between the RL information and the preset time sequence condition, so that the resistance value of the terminal resistor can be timely changed within the specified time conforming to the technical standard when the interval time between the command address signal and the target control signal meets the preset time sequence condition, thereby not only avoiding signal collision in the transmission process, but also reducing the energy loss and reflection of the signal in the transmission process and further improving the signal integrity; in addition, after the command control module receives the first clock signal and the second clock signal, the processing speed can be increased due to the fact that the relatively fast first clock signal is used for sending out the relatively slow second clock signal to sample in signals, and finally the performance of the memory can be improved.

Drawings

FIG. 1 is a schematic diagram of an ODT function circuit;

FIG. 2A is a schematic diagram of an ODT function circuit for a read operation;

FIG. 2B is a schematic diagram of an ODT function circuit for a write operation;

FIG. 3 is a schematic diagram of the control timing of ODT function during a read operation of a non-target chip;

Fig. 4 is a schematic diagram of a composition structure of a control circuit according to an embodiment of the disclosure;

Fig. 5 is a schematic diagram of a composition structure of another control circuit according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a composition structure of a command control module according to an embodiment of the disclosure;

fig. 7A is a schematic diagram of a composition structure of a delay adjustable module according to an embodiment of the disclosure;

FIG. 7B is a schematic diagram of a delay adjustable module according to an embodiment of the disclosure;

Fig. 8A is a schematic structural diagram of a first control module according to an embodiment of the disclosure;

fig. 8B is a schematic structural diagram of a second control module according to an embodiment of the disclosure;

Fig. 9 is a detailed schematic diagram of a control circuit according to an embodiment of the disclosure;

FIG. 10 is a schematic diagram of an operation timing of a control circuit according to an embodiment of the disclosure;

FIG. 11 is a schematic flow chart of a control method according to an embodiment of the disclosure;

Fig. 12 is a schematic diagram of a composition structure of a memory according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first/second/third" in relation to embodiments of the present disclosure is used merely to distinguish similar objects and does not represent a particular ordering of the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if permitted, to enable embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described herein.

It should also be noted that the high and low levels used with respect to signals according to embodiments of the present disclosure refer to the logic levels of the signals. The signal has a high level unlike when it has a low level. For example, a high level may correspond to a signal having a first voltage and a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. Furthermore, the logic levels of the signals may be different or opposite to those described. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

With the rapid development of semiconductor processes, the transmission rate of signals is faster and faster, resulting in increasingly outstanding signal integrity problems. In order to better improve the signal integrity of Data in the propagation process of high-speed signals, in the third-generation Double Data Rate (Double Data Rate 3, ddr 3) and fourth-generation Double Data Rate 4, ddr4 designs, on-die termination (On Die Termination, ODT) resistors are independently added, that is, in a mode of performing impedance matching on a transmission line by using the ODT resistors, the energy loss and reflection of signals in the transmission process are reduced, so that the signal integrity of a receiving end can be ensured.

Taking DDR4 DRAM as an example, DDR4 DRAM supports an ODT function that may adjust the termination resistance (also referred to as "termination resistance") of the DQ, DQS_t/c, DM_n, and TDQS _t/c ports of each device by ODT pin control, write command, or mode register setting a default resistance value. In addition, the purpose of the ODT function is to reduce reflections, effectively improving signal integrity on the memory interface by the controller independently controlling the termination resistance of all or any of the DRAMs. As shown in fig. 1, a schematic diagram of a related art ODT functional circuit is shown. In fig. 1, the ODT function circuit may include at least a switch S1, a termination resistor RTT, and a power supply VDDQ. One end of the switch S1 is connected to one end of the termination resistor RTT, the other end of the termination resistor RTT is connected to the power supply VDDQ, and the other end of the switch S1 is connected to the other circuit (To other circuity like) and the DQ, DQS, DM, TDQS port. Note that DQS may be a pair of differential data strobe signals dqs_t and dqs_c, TDQS may be a pair of differential data strobe signals TDQS _t and TDQS _c; in other words, the DDR4 DRAM supports only the data strobe signal as a differential signal, and does not support the data strobe signal of a single signal.

In addition, switch S1 in FIG. 1 is controlled by ODT control logic. ODT control logic includes external ODT pin inputs, mode register configurations, and other control information. The value of RTT is controlled by configuration information within a mode register. In addition, if rtt_nom is disabled after self-refresh mode or MR1{ a10, A9, A8} = {0, 0}, control of the ODT pin is ignored.

Specifically, the ODT function is turned on when the configuration bits MR1{ A10, A9, A8} or MR2{ A10: A9} or MR5{ A8: A6} are not all zero. In this case, the actual resistance of the ODT resistance is determined by the configuration bits. After entering self-refresh mode, DDR4 DRAM automatically disables the ODT function, at which point the termination resistance is set to a high resistance state (Hi-Z) to discard all mode register settings.

Illustratively, in the application scenario of the fourth generation low power double rate (Low Power Double Data Rate, LPDDR 4) DRAM, the SI performance of the write operation in the high speed application scenario may be improved for the Non-Target On-Die Termination (NT ODT) function. For a dual Rank (Two Rank) system, the NT ODT function is turned off for read/write access of the target Rank (TARGET RANK), while the ODT function of the Non-target Rank (Non-TARGET RANK) is turned on to improve SI performance.

Taking NT-ODT function On/Off (On/Off) as an example at the time of a read operation in a Two Rank system, fig. 2A shows a schematic structure of an ODT function circuit in the case of a read operation, and fig. 2B shows a schematic structure of an ODT function circuit in the case of a write operation. Where R0 represents a Target Chip (Target), R1 represents a Non-Target Chip (Non-Target), and AP represents a System On Chip (SOC). For the target chip, in fig. 2A, ODT _T is in an off state because the target chip transmits data outwards during a read operation, and no termination resistor is required to eliminate reflection; in fig. 2B, ODT _T is in an on state because a termination resistor is required to cancel reflection since the target chip receives data at the time of a write operation.

Further, fig. 3 shows a schematic diagram of control timing of ODT function at the time of read operation of a non-target chip. As shown in fig. 3, t1 represents ODTLon _rd, t2 represents tcodton.max, and t3 represents tcodton.min; t4 represents ODTLoff _rd, t5 represents tcodtoff.max, and t6 represents tcodtoff.min. When the resistance value of the terminal resistor is switched from the ODT high resistance state to the ODT on state, ODTLon _rd clock cycles are required to be waited at the moment; considering that there is a time jitter value at the time of state switching, the maximum value and the minimum value of the time jitter value may be set here as follows: to ton.max and to ton.min. Correspondingly, when the resistance value of the terminal resistor is switched from the ODT on state to the ODT high resistance state, ODTLoff _rd clock cycles are required to be waited at the moment; considering that there is a time jitter value at the time of state switching, the maximum value and the minimum value of the time jitter value may be set here as follows: toff.max and totoff.min.

Illustratively, table 1 shows the correspondence between ODTLon _rd delay time (ODTLon _ RD LATENCY), ODTLoff _rd delay time (ODTLoff _ RD LATENCY) and the lower limit value (Lower Clock Frequency Limit) and upper limit value (Upper Clock Frequency Limit) of the operating clock frequency of the DRAM, and table 2 shows the timing requirements that ODT on and ODT off need to satisfy at the time of state switching.

TABLE 1

TABLE 2

Parameter (Parameter)	800～2133MHz	Unit (Unit)
			tODTon.Min	1.5	Nanoseconds (ns)
tODTon.Max	3.5	Nanoseconds (ns)
			tODToff.Min	1.5	Nanoseconds (ns)
tODToff.Max	3.5	Nanoseconds (ns)

In short, the resistance of the termination resistor is switchable, but how to switch needs to follow a certain Timing (Timing) requirement. However, due to different delay time on the transmission line, time sequence deviation exists, so that abnormal resistance state switching occurs, the NT ODT function of the DQ module is affected, the energy loss and the reflection effect of signals in the transmission process are poor, even signal collision can occur, and the SI performance is reduced.

Based on this, the embodiments of the present disclosure provide a control circuit, in which the read delay signal includes RL information, and the RL information has an association relationship with a predetermined timing condition. After passing through the command decoding module, the command processing module and the command control module, the interval time between the obtained target control signal and the command address signal meets the preset time sequence condition so as to timely change the resistance value of the terminal resistor within the specified time conforming to the technical standard; therefore, signal collision in the transmission process can be avoided, energy loss and reflection of signals in the transmission process can be reduced, and signal integrity is improved; in addition, the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal, so that the processing speed can be further increased, and finally, the performance of the memory can be improved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, referring to fig. 4, a schematic diagram of a composition structure of a control circuit provided in an embodiment of the present disclosure is shown. As shown in fig. 4, the control circuit 40 may include a clock generation module 401, a command decoding module 402, a command processing module 403, and a command control module 404, the clock generation module 401 being connected to the command decoding module 402, the command processing module 403, and the command control module 404, respectively, and the command processing module 403 being further connected to the command control module 404, wherein:

A clock generation module 401, configured to receive an external clock signal, and generate a first clock signal, a second clock signal, and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, which is earlier than the third clock signal;

The command decoding module 402 is configured to receive the command address signal and the third clock signal, decode the command address signal to obtain a decoded signal, and sample the decoded signal according to the third clock signal to obtain a read command signal;

the command processing module 403 is configured to receive the third clock signal, the read command signal, and the read delay signal, and perform delay processing on the read command signal according to the third clock signal and the read delay signal, so as to obtain a read control signal, where the read delay signal includes RL information;

The command control module 404 is configured to receive the first clock signal, the second clock signal, and the read control signal, and sample and pulse broaden the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; the interval time between the command address signal and the target control signal meets a preset time sequence condition, and the target control signal is used for controlling the conduction state of the terminal resistor.

It should be noted that, in the embodiment of the present disclosure, the control circuit 40 may be applied to a memory. The memory may be, for example, static random access memory (Static Random Access Memory, SRAM), dynamic random access memory (Dynamic Random Access Memory, DRAM), synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), double data rate synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR SDRAM), etc., which is not particularly limited herein.

It should be further noted that, in the embodiment of the present disclosure, the control circuit 40 may be specifically a control circuit applied to ODT on/off timing (ODT on/off timing), and is mainly implemented for timing control of NT ODT on/off under a Read Operation. Specifically, the total delay time for the command address signal to be transmitted to the receiving end (DQ module) of the non-target chip for NT ODT function control after passing through the command decoding module 402, the command processing module 403, and the command control module 404 needs to satisfy a preset timing condition. Wherein, there is an association relationship between the preset time sequence condition and the RL information. Illustratively, the ODT latency is equal to (RL-n) clock cycles, where n may typically have a value of 2, 3, etc., but is not specifically limited.

That is, in the embodiment of the present disclosure, the interval time between the command address signal and the target control signal satisfies the preset timing condition. Specifically, the target control signal is a pulse signal with high level and effective, wherein the interval time between the rising edge of the command address signal and the rising edge of the target control signal needs to meet the ODT on time sequence requirement, and the interval time between the falling edge of the command address signal and the falling edge of the target control signal needs to meet the ODT off time sequence requirement. Here, the ODT on timing requirement may be determined by the sum of ODTLon _rd and tODTon, and the ODT off timing requirement may be determined by the sum of ODTLoff _rd and tODToff.

In the embodiment of the present disclosure, tODTon is required to be within the range of tcodton.min and tcodton.max, and tODToff is required to be within the range of tcodtoff.min and tcodtoff.max. Wherein, the values of the tODTON.Min and the tODTON.Max and the values of the tODToff.Min and the tODToff.Max are shown in the table 2. Illustratively, tODTon may have a value of 2.5ns and the value of tcodtoff may have a value of 2.5ns, but is not particularly limited thereto.

It should also be noted that in the disclosed embodiment, the read delay signal is not a mere delayed signal, but a signal including RL information. In addition, the read delay signal may be one signal or a set of signals, which is not limited in any way.

In some embodiments, based on the control circuit 40 shown in fig. 4, referring to fig. 5, the control circuit 40 may further include a mode register module 405, where the mode register module 405 is connected to the command processing module 403, and where:

the mode register block 405 is configured to set RL information, generate a read delay signal including RL information, and provide the read delay signal to the command processing block 403.

It should be noted that in the embodiments of the present disclosure, the RL information may be set by a Mode Register module (Mode Register), and the read delay signal generated by the Mode Register includes the RL information. Thus, depending on the RL information set by the mode register block 405, the read control signal generated by the command processing block 403 may also be controlled to have different timings; that is, command processing module 403 may generate read control signals of different timing based on different RL information.

In the embodiment of the present disclosure, the clock generation module 401 has a clock frequency division function, and the clock generation module 401 also has a clock delay function to generate clock signals having different delay times. In some embodiments, the clock generation module 401 is configured to divide the external clock signal and perform a first clock delay process to obtain a first clock Zhong Ji signal and a first clock Zhong Ou signal; and

The clock generation module 401 is further configured to divide the frequency of the external clock signal and perform a second clock delay process to obtain a second clock odd signal and a second clock even signal; and

The clock generation module 402 is further configured to divide the external clock signal and perform a third clock delay process to obtain a third clock odd signal and a third clock even signal.

It should be noted that, in the embodiment of the present disclosure, the first clock signal may be composed of the first time Zhong Ji signal and the first time Zhong Ou signal. Wherein the frequency of the external clock signal is twice the frequency of the first time Zhong Ji signal, and the frequency of the external clock signal is also twice the frequency of the first time Zhong Ou signal. That is, the clock periods of the first clock odd signal and the first clock Zhong Ou signal are each twice the clock period of the external clock signal, and the phase difference between the first clock Zhong Ji signal and the first clock Zhong Ou signal is 180 degrees.

It should also be noted that in the embodiments of the present disclosure, the second clock signal may be composed of a second clock odd signal and a second clock even signal. Wherein the frequency of the external clock signal is twice the frequency of the second clock signal and the frequency of the external clock signal is also twice the frequency of the second clock signal. That is, the clock periods of the second clock odd signal and the second clock even signal are each twice the clock period of the external clock signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees.

It should also be noted that in the embodiments of the present disclosure, the third clock signal may be composed of a third clock odd signal and a third clock even signal. Wherein the frequency of the external clock signal is twice the frequency of the third clock signal and the frequency of the external clock signal is also twice the frequency of the third clock signal. That is, the clock periods of the third clock odd signal and the third clock even signal are each twice the clock period of the external clock signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

It is appreciated that in the disclosed embodiments, the external Clock signal may be considered a Clock Source (Clock Source) that sends data to the inside of the DQ pad. The first clock signal, the second clock signal, and the third clock signal having different phases are generated by the clock generation module 401 and then provided to different modules for use. Wherein the first clock signal and the second clock signal are used as clock sources for the command control module 404 to perform ODT on/off timing, and the third clock signal is used as clock sources for the command decoding module 402 and the command processing module 403 to perform command parsing and processing on RL.

It will also be appreciated that in embodiments of the present disclosure, the first clock delay process, the second clock delay process, and the third clock delay process may be different from one another, i.e., the first clock signal, the second clock signal, and the third clock signal are temporally sequential. In some embodiments, the delay time corresponding to the first clock delay process is less than the delay time corresponding to the second clock delay process; the delay time corresponding to the second clock delay process is smaller than the delay time corresponding to the third clock delay process.

It should be noted that, in the embodiment of the present disclosure, the first clock signal and the second clock signal are faster than the third clock signal, that is, the first clock signal and the second clock signal are clock sources for accelerating ODT on/off timing of the command control module 404; in addition, the first clock signal is faster than the second clock signal for the first clock signal and the second clock signal, and the relatively fast first clock signal is used to send out the relatively slow second clock signal for sampling the incoming signal, so that the speed can be further increased.

It should be further noted that, in the embodiment of the present disclosure, the first clock signal is earlier than the second clock signal (i.e., the first clock signal is faster than the second clock signal), which is also referred to as the first Zhong Ji signal being earlier than the second clock signal, and the first Zhong Ou signal being earlier than the second clock even signal; the second clock signal is earlier than the third clock signal (i.e. the second clock signal is faster than the third clock signal), which can be said to be the second clock signal is earlier than the third clock signal, and the second clock even signal is earlier than the third clock even signal.

Further, in some embodiments, the command decoding module 402 is configured to decode the command address signal to obtain a decoded odd signal and a decoded even signal; sampling the decoding odd signal according to the third clock odd signal to obtain a reading command odd signal; sampling the decoding even signal according to the third clock even signal to obtain a read command even signal;

A command processing module 403, configured to delay the read command odd signal according to the third clock odd signal and the read delay signal, to obtain a read control odd signal; and carrying out delay processing on the read command even signal according to the third clock even signal and the read delay signal to obtain a read control even signal.

It should be noted that, in the embodiment of the present disclosure, the decoding signal may be composed of a decoding odd signal and a decoding even signal, the read command signal may be composed of a read command odd signal and a read command even signal, and the read control signal may be composed of a read control odd signal and a read control even signal.

It will be appreciated that for the first clock signal, the first time Zhong Ji signal may be represented by ClkRd O and the first time Zhong Ou signal may be represented by ClkRd E; for the second clock signal, the second clock odd signal may be denoted by ClkRdO and the second clock even signal may be denoted by ClkRdE; for the third clock signal, the third clock odd signal may be denoted by ClkO and the third clock even signal may be denoted by ClkE. Wherein ClkRd E/O signals are earlier than ClkRdE/O signals and ClkRdE/O signals are earlier than ClkE/O signals; that is, clkRd E/O signals are faster than ClkRdE/O signals, and ClkRd E/O signals and ClkRdE/O signals are both faster than ClkE/O signals.

It will also be appreciated that the command address signal may also consist of a command address odd signal and a command address even signal. The command decoding module 402 decodes the command address odd signal to obtain a decoded odd signal, and then decodes the decoded odd signal according to ClkO signals to obtain a read command odd signal; and sampling the command address even signal according to the command decoding module 402 to obtain a decoded even signal, and then sampling the decoded even signal according to ClkE signals to obtain a read command even signal. Here, the read command odd signal may be denoted by RdCmdO and the read command even signal may be denoted by RdCmdE.

It is also noted that in the disclosed embodiment, the command address signals may be represented by CA <5:0 >. It should be noted that CA <5:0> is not a single signal, but represents a set of command address signals, namely CA <0>, CA <1>, CA <2>, CA <3>, CA <4>, CA <5> for a total of six signals. Here, command address odd signals may be represented by CA <5:0> _O, specifically representing a set of signals CA <0> _ O, CA <1> _ O, CA <2> _ O, CA <3> _ O, CA <4> _ O, CA <5> _O, etc.; the command address even signal may be represented by CA <5:0> _E, specifically representing a set of signals such as CA <0> _ E, CA <1> _ E, CA <2> _ E, CA <3> _ E, CA <4> _ E, CA <5> _E, etc.

Thus, for the command processing module 403, the signal RdCmdO is delayed according to the signal ClkO and the RL information included in the read delay signal, so as to obtain a read control odd signal, which may be denoted by Rd 1O; and delaying the RdCmdE signal according to the ClkE signal and the RL information included in the read delay signal, so as to obtain a read control even signal, which can be represented by Rd 1E.

In short, the command address signal is decoded and analyzed by the command decoding module 402, and then calculated by the command processing module 403 according to different RL information, and the obtained Rd1E/O signal is output to the command control module 404; and the command processing module 403 can generate Rd1E/O signals with different time sequences according to different RL information settings, so that the time sequence control of NT ODT on/off of the control circuit 40 can meet the preset time sequence condition, reduce the energy loss and reflection of the signals in the transmission process, and further improve SI performance.

In some embodiments, for the command control module 404, referring to fig. 6, the command control module 404 may include a first control module 411, a second control module 412, a logic module 413, and a delay adjustable module 414, wherein:

The first control module 411 is configured to receive a first time Zhong Ji signal, a second clock odd signal, and a read control odd signal, sample and pulse broaden the read control odd signal according to the first clock odd signal and the second clock odd signal, and obtain a first control signal;

The second control module 412 is configured to receive the first time Zhong Ou signal, the second clock even signal, and the read control even signal, sample and pulse broaden the read control even signal according to the first clock even signal and the second clock even signal, and obtain a second control signal;

The logic module 413 is configured to perform a logic operation on the first control signal and the second control signal to obtain an initial control signal;

The delay adjustable module 414 is configured to receive the mode control signal and the initial control signal, and perform delay processing on the initial control signal according to the mode control signal to obtain a target control signal.

Further, in some embodiments, as shown in fig. 6, the logic module 413 may include a first or gate a, wherein: a first input end of the first or gate a is connected with an output end of the first control module 411 and is used for receiving a first control signal; the second input end of the first or gate a is connected with the output end of the second control module 412 and is used for receiving a second control signal; the output of the first or gate a is connected to the input of the delay adjustable module 414 for outputting an initial control signal.

In the embodiment of the disclosure, for the first control signal and the second control signal, if the first control signal is a valid pulse signal, the second control signal is a low level signal, and the initial control signal at this time is the first control signal; or if the second control signal is a valid pulse signal, the first control signal is a low level signal, and the initial control signal at this time is the second control signal.

It should also be noted that in embodiments of the present disclosure, command control module 404 may be used to generate a target control signal to control the on and off of the NT ODT function on the DQ module. The inputs of the first control module 411 are a first time Zhong Ji signal, a second clock odd signal and a read control odd signal, and the inputs are output as a first control signal; the second control module 412 has inputs of a first clock Zhong Ou signal, a second clock even signal, and a read control even signal, and outputs a second control signal; and the output end of the first control module 411 is connected to the first input end of the first or gate a, the output end of the second control module 412 is connected to the second input end of the first or gate a, the output end of the first or gate a is connected to the input end of the delay adjustable module 414, and the output end of the delay adjustable module 414 is used for outputting a target control signal.

Specifically, in fig. 6, the mode control signal may be represented by TrimAdj < n:0>, and the target control signal may be represented by RdOdtEn. In addition, the first clock Zhong Ji signal may be represented by ClkRd O, the second clock odd signal may be represented by ClkRdO, the read control odd signal may be represented by Rd1O, and the first control signal may be represented by RdOdtO 1; the first time Zhong Ou signal may be denoted ClkRd E, the second clock even signal may be denoted ClkRdE, the read control even signal may be denoted Rd1E, and the second control signal may be denoted RdOdtE 1.

Further, in some embodiments, referring to fig. 7A, the delay adjustable module 414 may include K delay units, where K is an integer greater than 0:

the delay adjustable module 414 is configured to determine a target number of delay units from the K delay units according to the mode control signal, and perform delay processing on the initial control signal by using the target number of delay units to obtain a target control signal.

Note that, in the embodiment of the present disclosure, for the mode control signal TrimAdj < n:0>, trim herein may refer to a test mode, which is controlled by a Fuse (Fuse). In other words, the Mode control signal TrimAdj < n:0> may be generated by the fuse unit in the test Mode or may be generated by the user by setting the Mode register (Mode REGISTER SETTING, MRS), which is not limited in any way.

It should also be noted that in the embodiments of the present disclosure, since the clocks of the first clock signal and the second clock signal are faster than the third clock signal, the delay is adjustable when the process changes faster can be readjusted with the test mode. In addition, it should be noted that for the mode control signal TrimAdj < n:0>, it is not one signal, but represents a set of signals, namely TrimAdj <0>, trimAdj <1>, trimAdj <2>, …, trimAdj < n >.

In a specific embodiment, referring to fig. 7B, the mode control signal may include a K-bit sub-control signal, where j is an integer greater than or equal to 0 and less than K, and a j-th delay unit has a correspondence with the j-th sub-control signal:

The delay adjustable module 414 is configured to determine the jth to kth delay units as a target number of delay units when the level value of the jth sub-control signal is the first value, and perform delay processing on the initial control signal through the jth to kth delay units to obtain the target control signal.

In the embodiment of the present disclosure, there is an association relationship between the target number and the mode control signal. In particular, the mode control signal characterizes a control code from which it can be determined how many delay elements delay the initial control signal. Wherein the control codes are different, and the target number of the delay units is different.

It is understood that in the mode control signal, the j-th sub control signal may be represented by TrimAdj < j >. If the level value of the j-th sub-control signal is the first value, determining that the level values of other sub-control signals except the j-th sub-control signal are all second values; wherein the first value is different from the second value.

Illustratively, assuming that the first value is set to a logic 1 and the second value is set to a logic 0, taking the example that the mode control signal includes an eight-bit sub-control signal, the control code may be 0000 0001, 0000 0010, 0000 0100, 0000 1000, 0001 0000, 0010 0000, 0100 0000, 1000 0000, or the like. Here, if the control code is 0000 0100, at this time j is equal to 5, the 5 th delay unit, the 6 th delay unit, and the 7 th delay unit are taken as a target number of delay units in total; if the control code is 0001 0000, j at this time is equal to 3, five delay units from the 3 rd delay unit to the 7 th delay unit are taken as target number of delay units; if the control code is 1000 0000, at this time j is equal to 0, then eight delay units from the 0 th delay unit to the 7 th delay unit are taken as the target number of delay units.

Thus, when the value of j is different for the mode control signal, the corresponding control code is different, and the target number of delay units is also different.

In some embodiments, for the first control module 411, referring to fig. 8A, the first control module 411 may include a first sampling module 511, a second sampling module 512, and a third sampling module 513, wherein:

A first sampling module 511, configured to sample the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal;

a second sampling module 512, configured to sample the first sampling odd signal according to the first time Zhong Ji signal to obtain a second sampling odd signal;

The third sampling module 513 is configured to sample and pulse-broaden the second sampled odd signal according to the first time Zhong Ji signal to obtain a first control signal.

It should be noted that, in the command control module, for the first control module 411, the second clock signal is sampled into the first control module 411, and when the signal is output from the first control module 411, the first clock Zhong Ji signal is used at this time; the processing speed may be increased by sampling the incoming signal with a relatively fast first clock Zhong Ji signal and a relatively slow second clock signal.

Further, in some embodiments, as shown in fig. 8A, the third sampling module 513 may include a first sampling sub-module A1 and at least one second sampling sub-module B1, wherein:

the first sampling submodule A1 is used for sampling the second sampling odd signal according to the first time Zhong Ji signal to obtain a third sampling odd signal;

and the at least one second sampling submodule B1 is used for carrying out logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and carrying out sampling processing on the fourth sampling odd signal according to the first clock odd signal to obtain a first control signal.

It should be noted that, in the embodiment of the present disclosure, as shown in fig. 8A, at least one second sampling submodule B1 may include one or more second sampling submodules, denoted by C1, C2, C3, …, CN, respectively, where N is a positive integer. Wherein, the value of N has an association relationship with the pulse width of the first control signal. Specifically, the smaller the value of N, the smaller the pulse width of the first control signal; the larger the value of N, the larger the pulse width of the first control signal (i.e., the wider the pulse is widened).

Further, in some embodiments, as shown in fig. 8A, the first sampling module 511 may include a first flip-flop a1, where an input terminal of the first flip-flop a1 is configured to receive the read control odd signal, a clock terminal of the first flip-flop a1 is configured to receive the second clock odd signal, and an output terminal of the first flip-flop a1 is configured to output the first sampling odd signal;

The second sampling module 512 may include a second flip-flop a2, where an input terminal of the second flip-flop a2 is configured to receive the first sampling odd signal, a clock terminal of the second flip-flop a2 is configured to receive the first time Zhong Ji signal, and an output terminal of the second flip-flop a2 is configured to output the second sampling odd signal.

Further, in some embodiments, as shown in fig. 8A, the first sampling sub-module A1 may include a third flip-flop a3, where an input terminal of the third flip-flop a3 is configured to receive the second sampling odd signal, a clock terminal of the third flip-flop a3 is configured to receive the first time Zhong Ji signal, and an output terminal of the third flip-flop a3 is configured to output the third sampling odd signal.

Taking the ith second sampling sub-module Ci as an example, the second sampling sub-module Ci may include a second or gate Ui and a fourth flip-flop Qi, where a first input end of the second or gate Ui (as a first input end of the second sampling sub-module Ci) is connected to a second sampling odd signal, a second input end of the second or gate Ui (as a second input end of the second sampling sub-module Ci) is connected to an output end of a previous second sampling sub-module Ci-1, an output end of the second or gate Ui is connected to an input end of the fourth flip-flop Qi, a clock end of the fourth flip-flop Qi (as a clock end of the second sampling sub-module Ci) is connected to the first clock Zhong Ji signal, and an output end of the fourth flip-flop Qi (as an output end of the second sampling sub-module Ci) is used to output an intermediate signal.

The first Flip-Flop, the second Flip-Flop, the third Flip-Flop, or the fourth Flip-Flop may be a D-type Flip-Flop (DFF) or DELAY FLIP-Flop.

The D-type trigger is an information storage device with a memory function and two stable states, is the most basic logic unit for forming various time sequence circuits, and is also an important unit circuit in a digital logic circuit. Here, the D-type flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to the other under the influence of a clock signal.

It should also be noted that, in the embodiment of the present disclosure, the first flip-flop, the second flip-flop, the third flip-flop, or the fourth flip-flop may include a clock terminal (CK), an input terminal (D), and an output terminal (Q); in addition, a SET terminal (SET), a reset terminal (RST), etc. may be included, but are not shown in the drawing.

It should be further noted that, in the embodiment of the present disclosure, the first sampling module 511 uses the second clock signal as a clock source, the second sampling module 512 uses the first clock Zhong Ji signal as a clock source, and the third sampling module 513 (including the first sampling sub-module and at least one second sampling sub-module) also uses the first clock Zhong Ji signal as a clock source. Thus, since the first clock signal is faster than the second clock signal, the relatively slow second clock signal is sent out by the relatively fast first clock Zhong Ji signal to sample the incoming signal, which can increase the speed, and the pulse widening process of the first control signal can be realized by the at least one second sampling sub-module.

For at least one second sampling sub-module, in some embodiments, as shown in fig. 8A, when the number of at least one second sampling sub-module is N, taking the ith second sampling sub-module Ci as an example, the first input terminal of the ith second sampling sub-module Ci is connected to the second sampling odd signal, the second input terminal of the ith second sampling sub-module Ci is connected to the ith input signal, the clock terminal of the ith second sampling sub-module Ci is connected to the first time Zhong Ji signal, and the output terminal of the ith second sampling sub-module Ci is used for outputting the ith intermediate signal.

In an embodiment of the disclosure, when i is equal to 1, the i-th input signal is a third sampling odd signal; when i is greater than 1, the ith input signal is the ith-1 intermediate signal; and when i is equal to N, the ith intermediate signal is a first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

It should also be noted that, in the embodiment of the present disclosure, the value of N is fixed. Since the command processing module 403 has already processed the requirements of different RLs, the output Rd1O signal already includes RL information, and only the second sampling submodule with a fixed number of stages is needed to obtain the first control signal RdOdtO.

In some embodiments, for the second control module 412, referring to fig. 8B, the second control module 412 may include a fourth sampling module 521, a fifth sampling module 522, and a sixth sampling module 523, wherein:

A fourth sampling module 521, configured to sample the read control even signal according to the second clock even signal to obtain a first sampling even signal;

A fifth sampling module 522, configured to sample the first sampled even signal according to the first time Zhong Ou signal to obtain a second sampled even signal;

the sixth sampling module 523 is configured to sample and pulse-broaden the second sampled even signal according to the first time Zhong Ou signal to obtain a second control signal.

It should be noted that, in the command control module, for the second control module 412, the second clock even signal is sampled into the second control module 412, and when the signal is output from the second control module 412, the first clock Zhong Ou signal is used at this time; so that the processing speed can be increased by sampling the incoming signal with the relatively fast first clock Zhong Ou signal and the relatively slow second clock even signal.

Further, in some embodiments, as shown in fig. 8B, the sixth sampling module 523 may include a third sampling sub-module A2 and at least one fourth sampling sub-module B2, wherein:

The third sampling submodule A2 is used for carrying out sampling processing on the second sampling even signal according to the first time Zhong Ou signal to obtain a third sampling even signal;

and the at least one fourth sampling submodule B2 is used for carrying out logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and carrying out sampling processing on the fourth sampling even signal according to the first clock even signal to obtain a second control signal.

It should be noted that, in the embodiment of the present disclosure, as shown in fig. 8B, at least one fourth sampling submodule B2 may include one or more fourth sampling submodules, denoted by D1, D2, D3, …, DM, respectively, where M is a positive integer. Wherein, the value of M has an association relationship with the pulse width of the second control signal. Specifically, the smaller the value of M, the smaller the pulse width of the second control signal; the larger the value of M, the larger the pulse width of the second control signal (i.e., the wider the pulse is widened).

Further, in some embodiments, as shown in fig. 8B, the fourth sampling module 521 may include a fifth flip-flop B1, where an input terminal of the fifth flip-flop B1 is configured to receive the read control even signal, a clock terminal of the fifth flip-flop B1 is configured to receive the second clock even signal, and an output terminal of the fifth flip-flop B1 is configured to output the first sampling even signal;

The fifth sampling module 522 may include a sixth flip-flop b2, where an input terminal of the sixth flip-flop b2 is configured to receive the first sampling even signal, a clock terminal of the sixth flip-flop b2 is configured to receive the first time Zhong Ou signal, and an output terminal of the sixth flip-flop b2 is configured to output the second sampling even signal.

Further, in some embodiments, as shown in fig. 8B, the third sampling sub-module A2 may include a seventh flip-flop B3, where an input terminal of the seventh flip-flop B3 is configured to receive the second sampling even signal, a clock terminal of the seventh flip-flop B3 is configured to receive the first time Zhong Ou signal, and an output terminal of the seventh flip-flop B3 is configured to output the third sampling even signal.

Taking the ith fourth sampling submodule Di as an example, the fourth sampling submodule Di may include a second or gate Ui and an eighth flip-flop Qi, wherein a first input end (as a first input end of the fourth sampling submodule Di) of the second or gate Ui is connected with a second sampling even signal, a second input end (as a second input end of the fourth sampling submodule Di) of the second or gate Ui is connected with an output end of a previous fourth sampling submodule Di-1, an output end of the second or gate Ui is connected with an input end of the eighth flip-flop Qi, a clock end (as a clock end of the fourth sampling submodule Di) of the eighth flip-flop Qi is connected with a first time Zhong Ou signal, and an output end (as an output end of the fourth sampling submodule Di) of the eighth flip-flop Qi is used for outputting an intermediate signal.

The fifth flip-flop, the sixth flip-flop, the seventh flip-flop, or the eighth flip-flop may be a D-type flip-flop.

It should be further noted that, in the embodiment of the present disclosure, the fourth sampling module 521 uses the second clock even signal as the clock source, the fifth sampling module 522 uses the first clock Zhong Ou signal as the clock source, and the sixth sampling module 523 (including the third sampling sub-module and at least one fourth sampling sub-module) also uses the first clock Zhong Ou signal as the clock source. Thus, since the first clock even signal is faster than the second clock even signal, the relatively slow second clock even signal is sent out by the relatively fast first clock Zhong Ou signal, which can increase the speed, and the pulse widening process of the second control signal can be realized by the at least one fourth sampling sub-module.

For at least one fourth sampling submodule, in some embodiments, as shown in fig. 8B, when the number of at least one fourth sampling submodule is M, taking the ith fourth sampling submodule Di as an example, the first input end of the ith fourth sampling submodule Di is connected with the second sampling even signal, the second input end of the ith fourth sampling submodule Di is connected with the ith input signal, the clock end of the ith fourth sampling submodule Di is connected with the first time Zhong Ou signal, and the output end of the ith fourth sampling submodule Di is used for outputting the ith intermediate signal.

In an embodiment of the disclosure, when i is equal to 1, the i-th input signal is a third sampling even signal; when i is greater than 1, the ith input signal is the ith-1 intermediate signal; and when i is equal to M, the ith intermediate signal is a second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

It should also be noted that in the embodiment of the present disclosure, the value of M is fixed. Since the command processing module 403 has already processed the requirements of different RLs, the output Rd1E signal already includes RL information, and only the fourth sampling submodule with a fixed number of stages is needed to obtain the first control signal RdOdtE.

It should also be noted that in the embodiments of the present disclosure, the values of M and N may be the same. That is, the hardware configuration of the first control module 411 and the second control module 412 may be the same, except that the input signal and the output signal are different. When the ClkRd O signal and the ClkRdO signal are valid pulse signals and the ClkRd E signal and the ClkRdE signal are low level signals, only the first control signal output by the first control module 411 is valid at this time, and the initial control signal at this time is the first control signal; when ClkRd E signal and ClkRdE signal are valid pulse signals and ClkRd O signal and ClkRdO signal are low level signals, only the second control signal output by the second control module 412 is valid at this time, and the initial control signal at this time is the second control signal. The initial control signal is then adjustably delayed by a delay adjustable module 414 to obtain a final target control signal.

The disclosed embodiments provide a control circuit in which a read delay signal includes RL information with an association relationship with a preset timing condition. After passing through the command decoding module, the command processing module and the command control module, the interval time between the obtained target control signal and the command address signal meets the preset time sequence condition so as to timely change the resistance value of the terminal resistor within the specified time conforming to the technical standard; therefore, signal collision in the transmission process can be avoided, energy loss and reflection of signals in the transmission process can be reduced, and SI performance is improved; in addition, since the first clock signal is earlier than the second clock signal, and the second clock signal is sampled by the incoming command control module for the command control module, the first clock signal is used for outputting the signal from the command control module, and the relatively slow second clock signal is sent out by the relatively fast first clock signal to sample the incoming signal, so that the processing speed can be further increased, and finally the performance of the memory can be improved.

In another embodiment of the present disclosure, based on the control circuit 40 described in the foregoing embodiment, referring to fig. 9, a detailed structural schematic diagram of one control circuit 40 provided in the embodiment of the present disclosure is shown. As shown in fig. 9, the control circuit 40 may include a clock receiving module 901, a clock generating (ClkGen) module 902, a command decoding (CmdDec) module 903, a command processing (RdRLCal) module 904, a command control (RdNTOdtCtrl) module 905, a Mode Register (Mode Register) module 906, a first DQ module 907, and a second DQ module 908. The clock receiving module 901 is configured to receive an external clock signal, and the clock receiving module 901 may be a receiver (denoted by Recevier) or may be a Buffer (denoted by Buffer).

It should be noted that, in the embodiment of the present disclosure, the input end of the clock receiving module 901 is a Clk signal, the output end of the clock receiving module 901 is connected to the input end of the clock generating module 902, the first output end of the clock generating module 902 is used for outputting ClkRd E/O signals, the second output end of the clock generating module 902 is used for outputting ClkRdE/O signals, and the first output end and the second output end of the clock generating module 902 are both connected to the input end of the command controlling module 905; in addition, the third output end of the clock generation module 902 is used for outputting ClkE/O signals, the input end of the command decoding module 903 is used for receiving CA <5:0> signals, the output end of the command decoding module 903 is used for outputting RdCmdE/O signals, the output end of the command decoding module 903 is connected with the input end of the command processing module 904, and clock sources of the command decoding module 903 and the command processing module 904 are ClkE/O signals; for the command processing module 904, it is further required to receive RL information set by the mode register module 906, where an output terminal of the command processing module 904 is used for outputting Rd1E/O signals; the input of the command control module 905 is then also connected to the output of the command processing module 905, the output of the command control module 905 being used to output RdOdtEn signals.

It should be further noted that, in the embodiment of the present disclosure, assuming that, for RL information included in the read delay signal, the delay time of the command decoding module 903 is a, the delay time of the command processing module 904 is b, the delay time of the command control module 905 is c, and the path delay time of the command control module 905 to the first DQ module 907 or the second DQ module 908 is d, the sum of a, b, c, and d is (RL-n) clock cycles, where n may be generally set to 2, 3, or may be other positive integers, which is not particularly limited herein. That is, the delay time of the command processing module 904 is b= (RL-n) -a-c-d, where c may be calculated as the smallest RL; then b increases accordingly as RL increases.

It will be appreciated that embodiments of the present disclosure are generally directed to control circuit implementations of NT ODT on/off timing in a read mode of operation. The circuit control of NT ODT in the read operation mode is specifically as follows:

(1) The Clk signal is a clock source that sends data to the inside of the first DQ module 907 and/or the second DQ module 908;

(2) The ClkE/O signals are generated from the clock generation module 902 to be used as a clock source for command parsing and calculation with respect to the RL;

(3) ClkRd1E/O signals and ClkRdE/O signals are provided to command control module 905, which are clock sources used to speed up the ODT on/off timing;

(4) ClkRd1E/O signals are faster than ClkRdE/O signals;

(5) The read command is decoded and parsed by the command decoding module 903, calculated by the command processing module 904 according to different RL information, and output to the command control module 905;

(6) RL information may be output to command processing module 904 according to mode register module 906 settings;

(7) The command processing module 904 may generate read control Rd1E/O signals of different timing based on different RL information settings.

It should be further noted that, in the embodiment of the present disclosure, for the command control module 905, a specific circuit structure thereof may be shown in fig. 6, 7A, 7B, 8A and 8B. The RdOdtEn signal generated by command control module 905 can control NT ODT on/off on DQ modules (e.g., first DQ module 907 and/or second DQ module 908).

Further, based on the control circuit 40 shown in fig. 9, fig. 10 is a schematic diagram of the operation timing of the control circuit. As shown in fig. 10, clk is a clock signal, CS is a chip select signal, and is used to characterize a signal selected by a target chip; the ClkE/O signal, clkRdE/O signal, and ClkRd E/O signal each have a clock period twice that of the Clk signal, and in addition, the ClkRd E/O signal is faster than the ClkRdE/O signal, the ClkRdE/O signal is faster than the ClkE/O signal, i.e., the ClkRd E/O signal has a delay time of t1 compared to the Clk signal, the ClkRdE/O signal has a delay time of t2 compared to the Clk signal, the ClkE/O signal has a delay time of t3 compared to the Clk signal, and t3 is greater than t2, and t2 is greater than t1. Therefore, the processing speed can be increased, the delay of the clock is adjustable, and if the delay of the input of the previous command address signal is overlarge, the module can output the previous delay by sampling with a faster clock, so that the total delay reaches a preset value.

It should be further noted that, referring specifically to fig. 10, for a command address signal (specifically, a read command), after the read command, the RL is required to output data through the DQ port; and for NT ODT on/off, its control logic needs to follow a preset timing condition. Specifically, for RdOdtEn signals, which are active high pulse signals, the interval between the rising edges of the CA <5:0> signals and the RdOdtEn signals needs to meet the ODT on timing requirement (i.e., the sum of ODTLon _rd and tODTon), and the interval between the falling edges of the CA <5:0> signals and the RdOdtEn signals needs to meet the ODT off timing requirement (i.e., the sum of ODTLoff _rd and tODToff), so that the interval between the command address signals and the target control signals meets the preset timing condition.

The embodiment of the present disclosure provides a control circuit, and the specific implementation of the foregoing embodiment is described in detail through the foregoing embodiment, where it can be seen that the read delay signal includes RL information, and the RL information has an association relationship with a preset timing condition. When the interval time between the command address signal and the target control signal meets the preset time sequence condition, the resistance value of the terminal resistor can be changed in time within the specified time conforming to the technical standard; therefore, signal collision in the transmission process can be avoided, energy loss and reflection of signals in the transmission process can be reduced, SI performance is improved, processing speed can be increased, and performance of a memory can be improved finally.

In yet another embodiment of the present disclosure, reference is made to fig. 11, which shows a schematic flow chart of a control method provided by an embodiment of the present disclosure. As shown in fig. 11, the method may include:

s1101: the clock generation module receives the external clock signal and generates a first clock signal, a second clock signal and a third clock signal according to the external clock signal.

S1102: and receiving the command address signal and the third clock signal through the command decoding module, decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to the third clock signal to obtain a read command signal.

S1103: and receiving the third clock signal, the read command signal and the read delay signal through the command processing module, and carrying out delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal.

S1104: and receiving the first clock signal, the second clock signal and the read control signal through the command control module, and sampling and pulse widening the read control signal according to the first clock signal and the second clock signal to obtain a target control signal.

It should be noted that, in the embodiment of the present disclosure, the control method is applied to the control circuit 40 described in the foregoing embodiment. The control circuit 40 may include a clock generation module, a command decoding module, a command processing module, and a command control module, where the clock generation module is connected to the command decoding module, the command processing module, and the command control module, and the command processing module is also connected to the command control module.

It should also be noted that in embodiments of the present disclosure, the first clock signal is earlier than the second clock signal, which is earlier than the third clock signal. In this way, the command control module, after receiving the first clock signal and the second clock signal, can also increase the processing speed by using the relatively fast first clock signal to send out a relatively slow second clock signal sampled in.

It is also noted that in the disclosed embodiments, the read delay signal includes RL information; and the interval time between the command address signal and the target control signal meets a preset time sequence condition, and the target control signal is used for controlling the conduction state of the terminal resistor. Therefore, the resistance value of the terminal resistor can be changed in time within the stipulated time conforming to the technical standard, signal collision in the transmission process is avoided, and SI performance is improved.

Specifically, in the embodiments of the present disclosure, the control method may be applied to a timing control circuit for on/off of an ODT function, mainly implemented for timing control of on/off of an NT ODT under a Read Operation. More specifically, the total delay time for the command address signal to be transmitted to the DQ module of the non-target chip for NT ODT function control after passing through the command decoding module, the command processing module, and the command control module needs to satisfy a preset timing condition. In addition, the preset time sequence condition and the RL information have an association relation.

In some embodiments, the control circuit may further include a mode register module. Wherein the mode register block may set the RL information and then generate a read delay signal including the RL information and provide the read delay signal to the command processing block.

In some embodiments, the method may further comprise: transmitting a target control signal to the DQ module; and controlling the conduction state of the terminal resistor of the DQ module according to the target control signal.

In some embodiments, controlling the on state of the termination resistors of the DQ modules according to the target control signal may include:

when the target control signal is in a first level state, setting the resistance value of the terminal resistor according to a preset mode register;

And when the target control signal is in the second level state, controlling the terminal resistor to be in a high-resistance state according to the target control signal.

In the embodiment of the disclosure, taking DDR4 DRAM as an example, the first level state is high, and the second level state is low. Illustratively, the preset mode register may refer to MR1{ A10, A9, A8} or MR2{ A10: A9} or MR5{ A8: A6}. Wherein, when the configuration bits of MR1{ A10, A9, A8} or MR2{ A10: A9} or MR5{ A8: A6} are not all zero, the actual resistance value of the termination resistor is determined by the configuration bits.

In some embodiments, for the clock generation module, the method may further comprise: dividing the frequency of the external clock signal and performing first clock delay processing to obtain a first time Zhong Ji signal and a first time Zhong Ou signal; and performing frequency division and second clock delay processing on the external clock signal to obtain a second clock odd signal and a second clock even signal; and frequency dividing and third clock delay processing are carried out on the external clock signal to obtain a third clock odd signal and a third clock even signal.

The first clock signal is composed of a first clock odd signal and a first clock Zhong Ou signal, and the clock period of the first clock Zhong Ji signal and the clock period of the first clock Zhong Ou signal are two times of the clock period of the external clock signal, and the phase difference between the first clock Zhong Ji signal and the first clock Zhong Ou signal is 180 degrees.

The second clock signal is composed of a second clock odd signal and a second clock even signal, the clock periods of the second clock odd signal and the second clock even signal are two times of the clock period of the external clock signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees.

The third clock signal is composed of a third clock odd signal and a third clock even signal, the clock periods of the third clock odd signal and the third clock even signal are two times of the clock period of the external clock signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

In the embodiment of the disclosure, the delay time corresponding to the first clock delay process is smaller than the delay time corresponding to the second clock delay process; the delay time corresponding to the second clock delay process is smaller than the delay time corresponding to the third clock delay process.

In some embodiments, for the command decoding module, the method further comprises: decoding the command address signal to obtain a decoding odd signal and a decoding even signal; sampling the decoding odd signal according to the third clock odd signal to obtain a reading command odd signal; and sampling the decoded even signal according to the third clock even signal to obtain a read command even signal.

In some embodiments, for the command processing module, the method may further comprise: performing delay processing on the read command odd signal according to the third clock odd signal and the read delay signal to obtain a read control odd signal; and carrying out delay processing on the read command even signal according to the third clock even signal and the read delay signal to obtain a read control even signal.

In some embodiments, for the command control module, the method may further comprise: receiving a first clock odd signal, a second clock odd signal and a read control odd signal through a first control module, and carrying out sampling and pulse widening processing on the read control odd signal according to the first clock odd signal and the second clock odd signal to obtain a first control signal; receiving a first clock even signal, a second clock even signal and a read control even signal through a second control module, and performing sampling and pulse widening processing on the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal; performing logic operation on the first control signal and the second control signal through a logic module to obtain an initial control signal; and receiving the mode control signal and the initial control signal through the delay adjustable module, and carrying out delay processing on the initial control signal according to the mode control signal to obtain a target control signal.

In some embodiments, the delay adjustable module includes K delay units, K being an integer greater than 0. Accordingly, the method may further comprise: and determining a target number of delay units from the K delay units according to the mode control signals, and carrying out delay processing on the initial control signals through the target number of delay units to obtain target control signals.

It is appreciated that in embodiments of the present disclosure, the first control module includes a first sampling module, a second sampling module, and a third sampling module. Accordingly, in some embodiments, the method may further comprise: in the first sampling module, sampling the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal; in a second sampling module, sampling the first sampling odd signal according to the first time Zhong Ji signal to obtain a second sampling odd signal; and in the third sampling module, sampling and pulse widening processing are carried out on the second sampling odd signal according to the first time Zhong Ji signal, so as to obtain a first control signal.

Further, in some embodiments, the third sampling module includes a first sampling sub-module and at least one second sampling sub-module. Accordingly, the method may further comprise: in the first sampling submodule, sampling the second sampling odd signal according to the first time Zhong Ji signal to obtain a third sampling odd signal; and in at least one second sampling submodule, carrying out logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and carrying out sampling processing on the fourth sampling odd signal according to the first clock odd signal to obtain a first control signal.

Here, when the number of the at least one second sampling submodule is N, the first input end of the ith second sampling submodule is connected with the second sampling odd signal, the second input end of the ith second sampling submodule is connected with the ith input signal, the clock end of the ith second sampling submodule is connected with the first time Zhong Ji signal, and the output end of the ith second sampling submodule is used for outputting the ith intermediate signal; when i is equal to 1, the ith input signal is a third sampling odd signal; when i is greater than 1, the ith input signal is the ith-1 intermediate signal; and when i is equal to N, the ith intermediate signal is a first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

It is also understood that in an embodiment of the present disclosure, the second control module includes a fourth sampling module, a fifth sampling module, and a sixth sampling module. Accordingly, in some embodiments, the method may further comprise: in a fourth sampling module, sampling the read control even signal according to the second clock even signal to obtain a first sampling even signal; in a fifth sampling module, sampling the first sampling even signal according to the first time Zhong Ou signal to obtain a second sampling even signal; and in the sixth sampling module, sampling and pulse widening processing are carried out on the second sampling even signal according to the first time Zhong Ou signal, so as to obtain a second control signal.

Further, in some embodiments, the sixth sampling module includes a third sampling sub-module and at least one fourth sampling sub-module. Accordingly, the method may further comprise: in the third sampling submodule, sampling the second sampling even signal according to the first time Zhong Ou signal to obtain a third sampling even signal; and in at least one fourth sampling sub-module, performing logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and performing sampling processing on the fourth sampling even signal according to the first clock even signal to obtain a second control signal.

Here, when the number of the at least one fourth sampling submodule is M, the first input end of the ith fourth sampling submodule is connected with the second sampling even signal, the second input end of the ith fourth sampling submodule is connected with the ith input signal, the clock end of the ith fourth sampling submodule is connected with the first time Zhong Ou signal, and the output end of the ith fourth sampling submodule is used for outputting the ith intermediate signal; when i is equal to 1, the ith input signal is a third sampling even signal; when i is greater than 1, the ith input signal is the ith-1 intermediate signal; and when i is equal to M, the ith intermediate signal is a second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

The embodiment of the disclosure provides a control method, because a read delay signal comprises RL information, and the interval time between a command address signal and a target control signal meets a preset time sequence condition, the resistance value of a terminal resistor can be timely changed within a specified time conforming to a technical standard, so that signal collision in a transmission process can be avoided, energy loss and reflection of the signal in the transmission process can be reduced, and further, the signal integrity is improved; in addition, since the first clock signal is earlier than the second clock signal, and the second clock signal is sampled by the incoming command control module for the command control module, the first clock signal is used for outputting the signal from the command control module, and the relatively slow second clock signal is sent out by the relatively fast first clock signal to sample the incoming signal, so that the processing speed can be further increased, and finally the performance of the memory can be improved.

In yet another embodiment of the present disclosure, reference is made to fig. 12, which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. As shown in fig. 12, the memory 120 includes at least the control circuit 40 according to any of the previous embodiments.

In some embodiments, memory 120 may include a DRAM chip. The DRAM chip may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, and may also conform to memory specifications such as LPDDR2, LPDDR3, LPDDR4, and LPDDR5, and is not limited herein.

In the embodiments of the present disclosure, the memory 120 is mainly related to semiconductor technology, and in particular, to pulse width design of signals inside a circuit, and better design performance is achieved by using a combination of factors of an external clock and internal independent delay characteristics. In addition, the control circuit of the embodiment of the present disclosure may be applied to various memories.

Thus, for the memory 120, the read delay signal includes RL information, and there is an association between the RL information and the predetermined timing conditions. After passing through the command decoding module, the command processing module and the command control module, the interval time between the obtained target control signal and the command address signal meets the preset time sequence condition, so that the resistance value of the terminal resistor can be changed in time within the specified time conforming to the technical standard; therefore, signal collision in the transmission process can be avoided, energy loss and reflection of signals in the transmission process can be reduced, and SI performance is improved; at the same time, the processing speed can be increased due to the fact that the relatively fast first clock signal is used for sending out the relatively slow second clock signal to sample the incoming signal, and finally the performance of the memory can be improved.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. The control circuit is characterized by comprising a clock generation module, a command decoding module, a command processing module and a command control module, wherein the clock generation module is respectively connected with the command decoding module, the command processing module and the command control module, and the command processing module is also connected with the command control module, wherein:

The command decoding module is used for receiving a command address signal and the third clock signal, decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to the third clock signal to obtain a read command signal;

the command processing module is configured to receive the third clock signal, the read command signal, and a read delay signal, and perform delay processing on the read command signal according to the third clock signal and the read delay signal, so as to obtain a read control signal, where the read delay signal includes RL information;

2. The control circuit of claim 1, further comprising a mode register module coupled to the command processing module, wherein:

The mode register module is used for setting RL information, generating the read delay signal comprising the RL information and providing the read delay signal to the command processing module.

3. The control circuit of claim 1, wherein,

The clock generation module is configured to divide the frequency of the external clock signal and perform first clock delay processing to obtain a first clock Zhong Ji signal and a first clock Zhong Ou signal, where clock periods of the first clock odd signal and the first clock even signal are two times of clock periods of the external clock signal, the first clock signal is composed of the first clock odd signal and the first clock Zhong Ou signal, and a phase difference between the first clock odd signal and the first clock Zhong Ou signal is 180 degrees; and

The clock generation module is further configured to divide the frequency of the external clock signal and perform a second clock delay process to obtain a second clock odd signal and a second clock even signal, where clock periods of the second clock odd signal and the second clock even signal are two times of clock periods of the external clock signal, the second clock signal is composed of the second clock odd signal and the second clock even signal, and a phase difference between the second clock odd signal and the second clock even signal is 180 degrees; and

The clock generation module is further configured to divide the frequency of the external clock signal and perform a third clock delay process to obtain a third clock odd signal and a third clock even signal, where clock periods of the third clock odd signal and the third clock even signal are two times of clock periods of the external clock signal, the third clock signal is composed of the third clock odd signal and the third clock even signal, and a phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

4. The control circuit of claim 3, wherein,

The delay time corresponding to the first clock delay processing is smaller than the delay time corresponding to the second clock delay processing;

And the delay time corresponding to the second clock delay processing is smaller than the delay time corresponding to the third clock delay processing.

5. The control circuit of claim 3, wherein,

The command decoding module is used for decoding the command address signals to obtain decoding odd signals and decoding even signals; sampling the decoding odd signal according to the third clock odd signal to obtain a reading command odd signal; sampling the decoding even signal according to the third clock even signal to obtain a reading command even signal;

The decoding signal is composed of the decoding odd signal and the decoding even signal, the reading command signal is composed of the reading command odd signal and the reading command even signal, and the reading control signal is composed of the reading control odd signal and the reading control even signal.

6. The control circuit of claim 5, wherein the command control module comprises a first control module, a second control module, a logic module, and a delay adjustable module, wherein:

the first control module is configured to receive the first clock signal, the second clock signal and the read control signal, and sample and pulse broaden the read control signal according to the first clock signal and the second clock signal to obtain a first control signal;

The second control module is configured to receive the first clock even signal, the second clock even signal, and the read control even signal, and sample and pulse broaden the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal;

The delay adjustable module is used for receiving the mode control signal and the initial control signal, and carrying out delay processing on the initial control signal according to the mode control signal to obtain the target control signal.

7. The control circuit of claim 6, wherein the logic module comprises a first or gate, wherein:

the first input end of the first OR gate is connected with the output end of the first control module and is used for receiving the first control signal; the second input end of the first OR gate is connected with the output end of the second control module and is used for receiving the second control signal;

the output end of the first OR gate is connected with the input end of the delay adjustable module and is used for outputting the initial control signal.

8. The control circuit of claim 6, wherein the delay adjustable module comprises K delay cells, K being an integer greater than 0, wherein:

the delay adjustable module is configured to determine a target number of delay units from the K delay units according to the mode control signal, and perform delay processing on the initial control signal by using the target number of delay units to obtain the target control signal.

9. The control circuit of claim 6, wherein the first control module comprises a first sampling module, a second sampling module, and a third sampling module, wherein:

the second sampling module is used for sampling the first sampling odd signal according to the first clock odd signal to obtain a second sampling odd signal;

the third sampling module is configured to sample and pulse-broaden the second sampling odd signal according to the first clock odd signal, so as to obtain the first control signal;

the fourth sampling module is configured to sample the read control even signal according to the second clock even signal to obtain a first sampling even signal;

The fifth sampling module is configured to perform sampling processing on the first sampling even signal according to the first clock even signal to obtain a second sampling even signal;

And the sixth sampling module is used for sampling and pulse widening the second sampling even signal according to the first clock even signal to obtain the second control signal.

10. The control circuit of claim 9, wherein the third sampling module comprises a first sampling sub-module and at least one second sampling sub-module, wherein:

the first sampling submodule is used for sampling the second sampling odd signal according to the first clock odd signal to obtain a third sampling odd signal;

The at least one second sampling submodule is used for carrying out logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and carrying out sampling processing on the fourth sampling odd signal according to the first clock odd signal to obtain the first control signal;

The third sampling submodule is used for sampling the second sampling even signal according to the first clock even signal to obtain a third sampling even signal;

The at least one fourth sampling sub-module is configured to perform logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and perform sampling processing on the fourth sampling even signal according to the first clock even signal to obtain the second control signal.

11. The control circuit of claim 9, wherein the control circuit is configured to control the operation of the control circuit,

The first sampling module comprises a first trigger, wherein the input end of the first trigger is used for receiving the read control odd signal, the clock end of the first trigger is used for receiving the second clock odd signal, and the output end of the first trigger is used for outputting the first sampling odd signal;

The second sampling module comprises a second trigger, wherein the input end of the second trigger is used for receiving the first sampling odd signal, the clock end of the second trigger is used for receiving the first clock odd signal, and the output end of the second trigger is used for outputting the second sampling odd signal.

12. The control circuit of claim 10, wherein the control circuit is configured to control the operation of the control circuit,

The first sampling submodule comprises a third trigger, wherein the input end of the third trigger is used for receiving the second sampling odd signal, the clock end of the third trigger is used for receiving the first clock odd signal, and the output end of the third trigger is used for outputting the third sampling odd signal;

the second sampling submodule comprises a second or gate and a fourth trigger, wherein a first input end of the second or gate is used as a first input end of the second sampling submodule to be connected with the second sampling odd signal, a second input end of the second or gate is used as a second input end of the second sampling submodule to be connected with an output end of a previous second sampling submodule, an output end of the second or gate is connected with an input end of the fourth trigger, a clock end of the fourth trigger is used as a clock end of the second sampling submodule to be connected with the first time Zhong Ji signal, and an output end of the fourth trigger is used as an output end of the second sampling submodule to be used for outputting an intermediate signal.

13. The control circuit of claim 12, wherein the control circuit is configured to control the operation of the control circuit,

When the number of the at least one second sampling submodule is N, the first input end of the ith second sampling submodule is connected with the second sampling odd signal, the second input end of the ith second sampling submodule is connected with the ith input signal, the clock end of the ith second sampling submodule is connected with the first time Zhong Ji in a signal mode, and the output end of the ith second sampling submodule is used for outputting an ith intermediate signal;

When i is equal to 1, the ith input signal is the third sampling odd signal; when i is greater than 1, the i input signal is an i-1 intermediate signal; and when i is equal to N, the ith intermediate signal is the first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

14. The control circuit of claim 9, wherein the control circuit is configured to control the operation of the control circuit,

The fourth sampling module comprises a fifth trigger, wherein the input end of the fifth trigger is used for receiving the read control even signal, the clock end of the fifth trigger is used for receiving the second clock even signal, and the output end of the fifth trigger is used for outputting the first sampling even signal;

The fifth sampling module comprises a sixth trigger, wherein the input end of the sixth trigger is used for receiving the first sampling even signal, the clock end of the sixth trigger is used for receiving the first clock even signal, and the output end of the sixth trigger is used for outputting the second sampling even signal.

15. The control circuit of claim 10, wherein the control circuit is configured to control the operation of the control circuit,

The third sampling submodule comprises a seventh trigger, wherein the input end of the seventh trigger is used for receiving the second sampling even signal, the clock end of the seventh trigger is used for receiving the first clock even signal, and the output end of the seventh trigger is used for outputting the third sampling even signal;

The fourth sampling submodule comprises a second or gate and an eighth trigger, wherein a first input end of the second or gate is used as a first input end of the fourth sampling submodule to be connected with the second sampling even signal, a second input end of the second or gate is used as a second input end of the fourth sampling submodule to be connected with an output end of a previous fourth sampling submodule, an output end of the second or gate is connected with an input end of the eighth trigger, a clock end of the eighth trigger is used as a clock end of the fourth sampling submodule to be connected with the first time Zhong Ou signal, and an output end of the eighth trigger is used as an output end of the fourth sampling submodule to be used for outputting an intermediate signal.

16. The control circuit of claim 15, wherein the control circuit is configured to control the operation of the control circuit,

When the number of the at least one fourth sampling submodule is M, a first input end of an ith fourth sampling submodule is connected with the second sampling even signal, a second input end of the ith fourth sampling submodule is connected with an ith input signal, a clock end of the ith fourth sampling submodule is connected with the first time Zhong Ou in a signal mode, and an output end of the ith fourth sampling submodule is used for outputting an ith intermediate signal;

wherein, when i is equal to 1, the i-th input signal is the third sampling even signal; when i is greater than 1, the i input signal is an i-1 intermediate signal; and when i is equal to M, the ith intermediate signal is the second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

17. A control method, characterized in that the method comprises:

receiving a command address signal and the third clock signal through a command decoding module, decoding the command address signal to obtain a decoded signal, and sampling the decoded signal according to the third clock signal to obtain a read command signal;

Receiving the third clock signal, the read command signal and a read delay signal through a command processing module, and carrying out delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal comprises RL information;

receiving the first clock signal, the second clock signal and the read control signal through a command control module, and sampling and pulse widening the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; the interval time between the command address signal and the target control signal meets a preset time sequence condition, and the target control signal is used for controlling the conduction state of the terminal resistor.

18. A memory comprising at least a control circuit according to any one of claims 1-16.