CN118230677B - Data processing method and circuit, chip, display panel and display - Google Patents
Data processing method and circuit, chip, display panel and display Download PDFInfo
- Publication number
- CN118230677B CN118230677B CN202410649332.6A CN202410649332A CN118230677B CN 118230677 B CN118230677 B CN 118230677B CN 202410649332 A CN202410649332 A CN 202410649332A CN 118230677 B CN118230677 B CN 118230677B
- Authority
- CN
- China
- Prior art keywords
- information
- data
- display panel
- transmission
- data processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 32
- 230000005540 biological transmission Effects 0.000 claims abstract description 77
- 238000012545 processing Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims description 4
- 239000002096 quantum dot Substances 0.000 claims description 4
- 238000012800 visualization Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 16
- 238000012549 training Methods 0.000 description 9
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/348—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on the deformation of a fluid drop, e.g. electrowetting
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Dc Digital Transmission (AREA)
Abstract
The invention discloses a data processing method, a circuit, a chip, a display panel and a display. The data processing method according to the embodiment of the invention comprises the steps of acquiring data information; acquiring a plurality of clock information corresponding to the data information; and inserting the plurality of clock information into the data information to generate transmission information of serial transmission, wherein the plurality of clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the plurality of clock information. According to the data processing method, the circuit, the chip, the display panel and the display, transmission of various associated information can be realized through only a single channel, and transmission requirements and circuit structures are simplified.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a data processing method, a circuit, a chip, a display panel, and a display.
Background
With the continuous development of the display industry, the requirements of video definition and frame rate are rapidly advancing, and the requirements on data transmission bandwidth are higher and higher.
In the prior art, in order to achieve high-speed transmission, in a display system, an lvds (Low-Voltage DIFFERENTIAL SIGNALING ) protocol is often used to transmit video data and configuration information. But the lvds protocol transfers outside the data line, at least a pair of differential line transfer clocks is required. This places a relatively large physical wiring burden on the in-board interconnects and the inter-board interconnects in the display system.
Accordingly, it is desirable to have a new data processing method and circuit, chip, display panel and display that overcomes the above-described problems.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a data processing method and circuit, a chip, a display panel and a display, so as to achieve transmission of a plurality of associated information through only a single channel, simplifying transmission requirements and circuit structure.
According to an aspect of the present invention, there is provided a data processing method including:
acquiring data information;
Acquiring a plurality of clock information corresponding to the data information;
inserting the plurality of clock information into the data information to generate transmission information for serial transmission,
The clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the clock information.
Optionally, the data processing method further includes:
and 8b/9b encoding the data information.
Optionally, the encoded 9b data contains 8b valid information, wherein the number of signal level changes is between 1 and 9 times;
the data processing method further comprises the following steps:
Acquiring configuration information, and performing 8b/9b coding on the configuration information; the encoded 9b data contains 2b effective information, wherein the number of times the effective data signal level changes is 3;
Acquiring filling information, and performing 8b/9b coding on the filling information; the encoded 9b data does not contain significant information, wherein the number of times the significant data signal level is changed is 2.
Optionally, the transmission information includes a plurality of data packets;
And idle information is arranged between the adjacent data information packets.
Optionally, the data information in the transmission information is transmitted in the form of a data information packet;
the data information packet includes a synchronization header and at least a portion of the data information.
Optionally, the data processing method further includes:
Acquiring configuration information;
8b/9b encoding the configuration information,
Wherein, the configuration information is coded by 3 times, 8bit data of each byte is split into 4 parts, each part is 2bit, and each 2bit is coded into 9bit transmission;
idle data is inserted between the effective configuration data of the configuration information.
Optionally, the transmission information is a plurality of; a plurality of transmission information are output in series;
at least one group of adjacent transmission information is inserted with filling information.
According to another aspect of the present invention, there is provided a data processing circuit comprising:
the first acquisition unit is used for acquiring data information;
A second acquisition unit configured to acquire a plurality of clock information corresponding to the data information;
A processing unit for inserting the plurality of clock information in the data information to generate transmission information for serial transmission,
The clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the clock information.
According to still another aspect of the present invention, there is provided a chip including:
A data processing circuit as described above.
According to still another aspect of the present invention, there is provided a display panel including:
A developing unit; and
The data processing circuit as described above is connected to the display unit to provide the transmission information to the display unit.
According to still another aspect of the present invention, there is provided a display including:
A display panel; and
The data processing circuit as described above is connected to the display panel to drive the display panel.
Optionally, the display panel includes at least one selected from a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.
According to the data processing method, the circuit, the chip, the display panel and the display, the clock information is respectively inserted into different positions of the data information, the serial transmission information is generated, the transmission of the related information can be realized through a single channel, and the transmission requirement and the circuit structure are simplified.
Furthermore, the data information adopts 8b/9b coding, the information effective rate can reach 8/9 at the highest, and higher data bandwidth can be transmitted.
Further, video data, configuration information and filling information in the data information adopt different coding modes according to different bandwidth requirements, and the anti-interference capability and the transmission bandwidth of the information transmission are balanced.
Further, the continuous transmission length of the data information is adjustable, idle information is inserted between the data information, and the idle information enables the transmission of the data information to adapt to the frequency difference of the transmitting side and the receiving side, so that the fault tolerance rate is high.
Furthermore, idle data can be inserted in any position in the process of sending the configuration information, and the idle data enables the transmission of the configuration information to adapt to the frequency difference of the two sending parties, so that the fault tolerance rate is improved.
Furthermore, the filling information does not contain effective data and does not limit the number, the fault tolerance rate is improved by inserting the filling information, and the frequency difference between the transmitting side and the receiving side can be adapted.
Furthermore, the transmission of data information can be realized by only one pair of differential lines, and the scheme can adapt to the frequency difference of the transmitting and receiving parties, so that the physical connection line is saved, the complexity of a physical system is simplified, and the cost is saved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a method flow diagram of a data processing method according to an embodiment of the invention;
FIG. 2 is a schematic diagram showing an insertion structure of clock information according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing an encoding structure of data information according to an embodiment of the present invention;
fig. 4 is a schematic diagram showing a structure of transmitting information according to an embodiment of the present invention;
FIG. 5 illustrates a schematic diagram of an encoding format of configuration information according to an embodiment of the present invention;
FIG. 6 is a diagram showing a packet format structure of configuration information according to an embodiment of the present invention;
FIG. 7 shows a schematic diagram of the structure of padding information according to an embodiment of the present invention;
Fig. 8 shows a schematic diagram of a data processing circuit according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.
Fig. 1 shows a method flow diagram of a data processing method according to an embodiment of the invention. As shown in fig. 1, the data processing method according to an embodiment of the present invention includes the steps of:
In step S101, data information is acquired;
And acquiring data information. The acquired data information is, for example, information to be transferred. Optionally, the data information comprises display data information. The display data information may be data in binary form. The display data information is processed and finally displayed on a display device (a display screen, a projector and the like) so as to convey specific information or content (in the form of characters, images, videos and the like) to a user.
In step S102, a plurality of clock information corresponding to the data information is acquired;
a plurality of clock information corresponding to the data information is acquired. Multiple clock information is used for matching and synchronizing with the data information to ensure that the data information can be accurately transmitted and received.
In step S103, the plurality of clock information is inserted in the data information to generate transmission information of serial transmission.
A plurality of clock information is inserted into the data information to generate transmission data for serial transmission. The clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the clock information. The serial transmission data can be transmitted through a single transmission channel, and the insertion of clock information ensures that the data information can be accurately received and identified.
A transmission protocol (e.g., a high-speed transmission p2p protocol) may be set corresponding to the data processing method of the present application; data conforming to the protocol may be transmitted by a data processing method as described above, i.e. data information embedded with clock information is transmitted via only one data channel.
In an alternative embodiment of the invention, the data processing method further comprises 8b/9b encoding the data information. Of course, other coding schemes (e.g., 8b/10b coding, etc.) may be used for coding. The data information in the transmission information of the serial transmission exists in an encoded form.
In particular, 8b/9b coding is a line coding technique for converting a data stream into a signal stream with better performance characteristics. In 8b/9b encoding, every 8 bits of data are mapped into a 9-bit encoding, which includes 8 bits of data and 1 control bit. The coding technology is mainly used in high-speed serial communication, and can improve the reliability and anti-interference capability of data transmission.
The 8b/9b coding mode increases the reliability of data transmission; by adding the control bit, errors in transmission can be detected and corrected, and the reliability of data transmission is improved. The 8b/9b coding can reduce direct current components in the signals, and is beneficial to the transmission and analysis of the signals. The 8b/9b code can help the receiving end recover the clock signal of the data through adding the control bit, so that the data stream can be more easily analyzed.
Optionally, the data to be transmitted includes configuration information and padding information (training information) in addition to the data information. The data information is 8b/9b encoded, and the encoded 9b data contains 8b effective information, wherein the number of times (toggle number) of signal level changes is between 1 time and 9 times. The configuration information is 8b/9b encoded, and the encoded 9b data contains 2b effective information, wherein the number of times (toggle number) that the effective data signal level changes is 3. The padding information is 8b/9b encoded, and the encoded 9b data does not contain valid information, wherein the number of times (toggle number) that the valid data signal level changes is 2. The data information is, for example, display data information (video data information). The bandwidth requirement of the data information is greater than the bandwidth requirement of the configuration information, which is greater than the bandwidth requirement of the padding information. Different coding modes are adopted corresponding to different bandwidth requirements. The data information is encoded, the data 9b contains 8b effective information, and the toggle number in the data 9b is 1 to 9 times. The data 9b contains 2b valid data when the configuration information is encoded, the number of the valid data is S1 toggle 4 times, and the number of the valid data is 3 times. The padding information has no effective information, and the effective data toggle in 9b is 2 times. In the case of at least one toggle per 9b, the fewer the number of toggle times, the stronger the interference resistance. Of course, it can be said that the data information includes display data information, configuration information, and padding information.
Fig. 2 shows a schematic diagram of an insertion structure (encoding structure) of clock information according to an embodiment of the present invention. As shown in fig. 2, for example, the clock information is inserted by 8b/9b encoding. According to the data processing method of the embodiment of the invention, clock information is embedded into data information, a receiver can recover the clock information according to the data information, and then effective data is obtained by sampling the recovered clock.
Fig. 3 shows a schematic diagram of a coding structure of data information according to an embodiment of the present invention. As shown in fig. 3, the data information (video data information) is directly encoded in 8b/9b, and video data of each byte is encoded into 9b data. The video data information is, for example, valid image data for display.
Further, the inventors have found that there is usually a frequency difference between the two parties of data transmission and reception due to a certain frequency error existing in the crystal oscillator, the phase-locked loop, etc. The inventors have desired to provide a data processing method that addresses frequency differences at the same time.
In an alternative embodiment of the invention, the transmission information comprises a plurality of data packets. Idle information is arranged between adjacent data information packets.
Optionally, the data information in the transmission information is transmitted in the form of data information packets, the data information packets including at least a portion of the synchronization header and the data information.
Fig. 4 shows a schematic diagram of a structure of transmitting information according to an embodiment of the present invention. As shown in fig. 4, the transmission information includes a plurality of video packets (data packets). Between any adjacent video packets, idle information (f 0 shown in the figure) can be inserted; the setting of the idle information can adapt to frequency jitter between different nodes. The format, length, location, etc. of the idle information may be set according to the need. The data packet includes at least a part of the synchronization header and the data information, the data information in the data packet needs to be transmitted with the synchronization header v_head (the synchronization header is, for example, f0_0f_0f_f0 shown in the drawing) before being transmitted, and then the data information (video data, byther0_byther2_byther3_byther4 shown in the drawing) is continuously transmitted, and the data size can be flexibly configured according to the actual physical bandwidth. The format of the data information (data) and the like can be set according to the actual situation.
Fig. 5 shows a schematic diagram of an encoding format of configuration information according to an embodiment of the present invention. In an alternative embodiment of the present invention, the data processing method further includes obtaining configuration information; and 8b/9b encoding the configuration information. Wherein, the configuration information is coded by 3 times, 8bit data of each byte is split into 4 parts, each part is 2bit, and each 2bit code is transmitted by 9 bit. Idle data is inserted between the valid configuration data of the configuration information.
In a specific embodiment of the present invention, the encoding format of the configuration information (data) is shown in fig. 5, the configuration data is 3 times encoded, 8bit data of each byte is split into 4 parts, each part is 2 bits, and each 2bit is encoded into 9bit for transmission. Wherein S1 has two choices, cc can be selected, and 33 can be selected; whether cc or 33 is selected depends on the last bit value of the previous 9bit data.
Configuration information (configuration data) is responsible for carrying display system control information, typically used to configure registers. The configuration information refers to, for example, parameters and settings for controlling and configuring the display panel. The configuration information may include screen resolution, brightness, contrast, color settings, refresh rate, display mode, and the like. Through setting and adjusting the configuration information, a user can optimize the display effect according to own requirements and preferences, so that the display effect is more in line with personal preference or the requirements of specific application scenes. The adjustment of the configuration information may be typically performed through a menu of a display panel, a control panel, or software. According to the data processing method provided by the embodiment of the invention, idle data can be inserted between (effective configuration data of) configuration information, so that the transmission of the configuration information can adapt to (tolerate) the frequency difference of the two parties.
Fig. 6 is a diagram illustrating a packet format structure of configuration information according to an embodiment of the present invention. As shown in fig. 6, in the configuration information (data) packet format, 4S 1 are used as configuration packet start flags, and any S1 may be inserted in the following. The packet length of the configuration information is unlimited, and S1 can be inserted as blank (blank) data between (middle valid configuration data in) the configuration information, but not more than 3S 1 can be inserted consecutively. The configuration packet of the configuration information ends with 4S 1, and the number of subsequent insertions S1 must not be more than 3.
The packet format of the configuration information is only one specific embodiment, and the packet format of the configuration information and the like can be set according to actual requirements. According to the data processing method provided by the embodiment of the invention, blank data S1 can be inserted in any position in the process of sending the configuration information (data), so that the transmission of the configuration data can adapt to the frequency difference of the sending party and the receiving party.
In an alternative embodiment of the present invention, the transmission information is a plurality of, and the plurality of transmission information is serially output. At least one group of adjacent transmission information is inserted with filling information. The filling information is used for establishing a stable data path, for example, the phase-locked loop is enabled to work in a stable locking state, and the cascaded chips are enabled to be in an on state.
Fig. 7 shows a schematic structural diagram of padding information according to an embodiment of the present invention. The padding information comprises training data, the coding format of the padding information (training data) is shown in fig. 7, and 8b/9b coding is adopted. The training data may use a simple f0, or other form.
The training data is used, for example, to train the link to establish a stable data path. During idle periods of the link, training data may be selected to be sent all the time, thereby leaving the link in a steady state (e.g., a locked state that stabilizes phase locked loop operation, a cascaded chip in an on state, etc.).
In a specific embodiment of the application, the data information comprises video data, configuration data and training data. The bandwidth requirement of the video data is high, the number of effective bits in 9b is 8b, and the number of toggle in 9b is 1-9; the tamper resistance of video data is low. The bandwidth requirement of the configuration data is medium, the effective bit number in 9b is 2b, the toggle number in 9b is divided into two types, namely S1 and ctrl_data, wherein S1 corresponds to 4 toggle numbers, and ctrl_data corresponds to 3 toggle numbers; the interference-free capability of the configuration data, etc. The bandwidth requirement of the training data is low, the number of effective bits in 9b is 0b (none), and the number of toggle in 9b is 2; the anti-interference capability of the training data is high. In the above embodiment, different types of data in the data information adopt different codes, so that various performances in the data information transmission process are considered.
Fig. 8 shows a schematic diagram of a data processing circuit according to an embodiment of the invention. As shown in fig. 8, the data processing circuit according to the embodiment of the present invention is for implementing the data processing method as described above, and includes a first acquisition unit 100, a second acquisition unit 200, and a processing unit 300.
Specifically, the first acquisition unit 100 is configured to acquire data information. The acquired data information is, for example, display data information.
The second acquisition unit 200 is configured to acquire a plurality of clock information corresponding to the data information.
The processing unit 300 is configured to insert a plurality of clock information into the data information to generate transmission information for serial transmission. The clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the clock information. The transmission of the serial transmission information can be completed in one transmission channel.
According to the data processing circuit provided by the embodiment of the invention, the clock information is inserted into the data information for transmission, and the transmission of the data information which needs additional information (clock information and the like) such as the display data information can be realized by only needing a pair of differential lines (for example, two signal lines with relatively complementary voltages), so that the circuit connection structure is simplified.
According to yet another aspect of the invention, a chip is provided. The chip comprises a data processing circuit as described above.
According to another aspect of the present invention, a display panel is provided. The display panel includes a display unit and a data processing circuit as described above; the data processing circuit is connected with the display unit to provide the transmission information to the display unit. The display panel may be a liquid crystal display panel, an Organic Light Emitting Diode (OLED) panel, an electronic ink panel, or the like. The display unit converts (displays) the electrical signal into a visible image/text based on the received transmission information.
According to yet another aspect of the present invention, a display is provided. The display comprises a display panel and a data processing circuit (chip) as described above, which is connected to the display panel to drive the display panel. The display may be for televisions, computers, smartphones, etc. Optionally, the display is at least one selected from the group consisting of a sub-millimeter diode light emitting display, a micro diode light emitting display, a quantum dot diode light emitting display, and the like. The display is for example a complete display device comprising a display panel, a housing, a stand, a circuit board, etc. The display may include one or more display panels, as well as other necessary components (e.g., power adapter, interface ports, control buttons, etc.).
Optionally, the display panel includes at least one selected from a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, a small-pitch display panel, and the like.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A method of data processing, comprising:
Acquiring data information, wherein the data information comprises display data information and configuration information;
Acquiring a plurality of clock information corresponding to the data information;
inserting the plurality of clock information into the data information to generate transmission information for serial transmission,
The clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the clock information; the plurality of clock information is used for matching and synchronizing with the data information;
The transmission information comprises a plurality of data information packets; idle information is arranged between the adjacent data information packets;
the transmission information is a plurality of pieces; a plurality of transmission information are output in series; filling information is inserted between at least one group of adjacent transmission information;
idle data is inserted between the effective configuration data of the configuration information.
2. The data processing method according to claim 1, characterized in that the data processing method further comprises:
and 8b/9b encoding the data information.
3. The data processing method according to claim 2, wherein the encoded 9b data contains 8b valid information, and wherein the number of signal level changes is between 1 and 9 times;
the data processing method further comprises the following steps:
8b/9b encoding the configuration information; the encoded 9b data contains 2b effective information, wherein the number of times the effective data signal level changes is 3;
8b/9b encoding the padding information; the encoded 9b data does not contain significant information, wherein the number of times the significant data signal level is changed is 2.
4. The data processing method according to claim 1, wherein the data information in the transmission information is transmitted in the form of data information packets;
the data information packet includes a synchronization header and at least a portion of the data information.
5. The data processing method according to claim 1, characterized in that the data processing method further comprises:
8b/9b encoding the configuration information,
And the configuration information is subjected to 8b/9b coding by 3 times, 8bit data of each byte is split into 4 parts, each part is 2 bits, and each 2bit code is transmitted into 9 bits.
6. A data processing circuit, comprising:
a first acquisition unit configured to acquire data information including display data information and configuration information;
A second acquisition unit configured to acquire a plurality of clock information corresponding to the data information;
A processing unit for inserting the plurality of clock information in the data information to generate transmission information for serial transmission,
The clock information is respectively inserted into different positions of the data information to represent the corresponding relation between the data information and the clock information; the plurality of clock information is used for matching and synchronizing with the data information;
The transmission information comprises a plurality of data information packets; idle information is arranged between the adjacent data information packets;
the transmission information is a plurality of pieces; a plurality of transmission information are output in series; filling information is inserted between at least one group of adjacent transmission information;
idle data is inserted between the effective configuration data of the configuration information.
7. A chip, comprising:
the data processing circuit of claim 6.
8. A display panel, comprising:
A developing unit; and
The data processing circuit of claim 6, wherein the data processing circuit is coupled to the visualization unit to provide the transmission information to the visualization unit.
9. A display device, which is used for a display, characterized by comprising the following steps:
A display panel; and
The data processing circuit of claim 6, the data processing circuit coupled to the display panel to drive the display panel.
10. The display of claim 9, wherein the display panel comprises at least one selected from the group consisting of a liquid crystal display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small pitch display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410649332.6A CN118230677B (en) | 2024-05-24 | 2024-05-24 | Data processing method and circuit, chip, display panel and display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410649332.6A CN118230677B (en) | 2024-05-24 | 2024-05-24 | Data processing method and circuit, chip, display panel and display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118230677A CN118230677A (en) | 2024-06-21 |
| CN118230677B true CN118230677B (en) | 2024-09-13 |
Family
ID=91513722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410649332.6A Active CN118230677B (en) | 2024-05-24 | 2024-05-24 | Data processing method and circuit, chip, display panel and display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118230677B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101365130A (en) * | 2007-08-08 | 2009-02-11 | 联咏科技股份有限公司 | Clock and data codependent high transmission rate interface |
| CN108694918A (en) * | 2017-06-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Coding method and device, coding/decoding method and device and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3073098B2 (en) * | 1992-06-11 | 2000-08-07 | アンリツ株式会社 | ISDN line connection polarity inspection device |
| JP4131284B2 (en) * | 2006-07-14 | 2008-08-13 | ソニー株式会社 | Video signal processing apparatus and video signal processing method |
| TWI364219B (en) * | 2007-08-20 | 2012-05-11 | Novatek Microelectronics Corp | High transmission rate interface for storing both clock and data signals |
| CN102497527B (en) * | 2011-12-16 | 2013-11-27 | 杭州海康威视数字技术股份有限公司 | Multi-processor video processing system and video image synchronous transmission and display method thereof |
-
2024
- 2024-05-24 CN CN202410649332.6A patent/CN118230677B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101365130A (en) * | 2007-08-08 | 2009-02-11 | 联咏科技股份有限公司 | Clock and data codependent high transmission rate interface |
| CN108694918A (en) * | 2017-06-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Coding method and device, coding/decoding method and device and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118230677A (en) | 2024-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10593256B2 (en) | LED display device and method for operating the same | |
| JP3341845B2 (en) | Block coding for digital video transmission | |
| US7440702B2 (en) | Method for transmitting digital image signal, digital image transmitting device, digital image sending device and digital image receiver | |
| US20070279408A1 (en) | Method and system for data transmission and recovery | |
| JP5945812B2 (en) | System for transmitting and receiving video digital signals for "LVDS" type links | |
| KR100666603B1 (en) | A multi display driving circuit and method of operating the same | |
| US20050094676A1 (en) | Signal transmitting apparatus and method | |
| US20140310425A1 (en) | Methods and apparatus for harmonization of interface profiles | |
| CN107087132B (en) | Receiver and signal transmission method | |
| GB2339653A (en) | Multiple synchronous data stream format for an optical data link | |
| CN111327858B (en) | Method, system and device for converting LVDS (Low Voltage differential Signaling) video signal into HDMI (high-definition multimedia interface) signal | |
| US8279747B2 (en) | Information processing apparatus and signal transmission method | |
| US20170084253A1 (en) | Led display device and method for operating the same | |
| CA2416052A1 (en) | Methods and systems for sending side-channel data during data inactive period | |
| US7102629B2 (en) | System and method for digital video signal transmission | |
| US7889763B2 (en) | Data transmission apparatus and data transmission method | |
| JP2009065399A (en) | Digital data transmitter, digital data receiver, digital data transmitting-receiving system, method for transmitting digital data, method for receiving digital data, method for transmitting-receiving digital data, and electronic information device | |
| JP2006191161A (en) | Optical transmission system | |
| CN118230677B (en) | Data processing method and circuit, chip, display panel and display | |
| US20180338063A1 (en) | High speed serial link for video interfaces | |
| CN1636342A (en) | Apparatus and method for passing large bitwidth data over a low bitwidth datapath | |
| JP2004072344A (en) | Data transmission system provided with multiplexed lvds interface | |
| CN112637673B (en) | Decoding method and decoding system of iSP (information processing system) signal | |
| CN112702608B (en) | 2Lane LVDS video coding method and system | |
| CN107995452B (en) | Double-screen synchronous display method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |