CN118214428A - Low delay, average input current cancellation for differential input, voltage sensing, switched capacitance, sigma-delta modulator - Google Patents

Abstract

An analog-to-digital converter circuit useful for measuring voltages with large common mode voltages includes two input voltage nodes, a voltage sensing circuit (the voltage sensing circuit including a sigma-delta modulator), a digital filter and an input current cancellation circuit, the voltage sensing circuit sensing the voltage between the nodes, the digital filter outputting a multi-bit digital value, the input current cancellation circuit-supplying/drawing a cancellation current to/from the nodes to compensate for the current the voltage sensing circuit draws/supplies from/to the nodes. The input current cancellation circuit comprises a digital programmable digital processing circuit and a current cancellation circuit. In one example, the digital processing circuit includes a sigma-delta modulator that converts a single-bit digital signal output by the voltage sensing circuit to a single-bit digital signal that drives the current cancellation circuit. By loading the digital trim values into the circuit, the transfer function of the current compensation loop is programmable and adjustable.

Description

Low delay, average input current cancellation for differential input, voltage sensing, switched capacitance, sigma-delta modulator

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional application No.63/542,463 under 35u.s.c. ≡119 (e) filed on 10 month 04 of 2023 entitled "low delay, average input current cancellation (Low-Latency,Average Input Current Cancellation For Differential Input,Voltage-Sensing,Switched-Capacitor,Sigma-Delta Modulators)" for differential input, voltage sensing, switched capacitor, sigma-delta modulator. The disclosures of the foregoing documents are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to voltage sensing circuits including voltage sensing circuits that measure differential voltages between high impedance nodes. The present disclosure relates in particular to circuits in which the voltage to be sensed has a high common mode voltage, and in which the sensing circuit comprises an input stage of a sigma-delta modulator for high resolution measurement.

Background

Accurately sensing the differential voltage between two nodes with a high common mode voltage is a difficult task. The challenge involves isolating the high common mode voltage from the measurement circuitry as much as possible. This isolation removes the high common mode voltage and allows the majority of the circuit to operate with only low voltages corresponding to differential voltage magnitudes. Operating with these lower voltages allows the physical size of the overall circuit to be minimized, lower operating power, and higher operating speeds.

In addition, it is highly desirable to maximize the input impedance presented by the differential voltage sensing circuit. The high input impedance will minimize any error introduced by the interaction of the source impedance with the finite input impedance of the sensing circuit. A typical source impedance may be an RC filter that may be used to provide filtering of high frequency electrical noise and to provide both anti-aliasing and input protection functions.

Switched capacitor circuits, particularly sigma-delta converters, are commonly used to provide high precision voltage sensing. When using a suitable differential input sampling circuit configuration, a high voltage tolerant capacitor can be used as both an isolation barrier element and as an input sampling capacitor for the converter. Such an arrangement limits the high common mode voltage to one side of the potential barrier that contains one plate in each high voltage sampling capacitor and a small number of associated switches that operate at closely related voltages. All circuitry (including the second plate of the high voltage input sampling capacitor) remaining may be included on the low voltage side of the isolation barrier.

The charging and discharging of the sampling/isolation capacitor causes a signal dependent differential charge transfer between the input terminal pair. If the sampling rate is low and the time constant of the input network is small enough compared to the sampling period, almost complete charge redistribution can occur during each sampling period and the remaining current and associated IR voltage drop will be small. In this case, the smallest sampling-related error occurs, and the input impedance appears to be very high.

Typically, this is not the case. The presence of an RC filter in the input signal path results in a time constant that is much longer than the sampling period of the switched capacitor network. In this case, the RC filter causes a residual current to continue to flow throughout the sampling interval and after the sampling interval ends. When the input signal frequency is low and the associated anti-aliasing filter time constant is correspondingly long compared to the sampling period, the error associated with this residual current is captured, typically in the form of a time-averaged IR voltage drop across the source resistance of the RC filter.

Counteracting the charge transfer associated with the input signal during one or a small number of input sampling events may reduce the redistribution current that must flow in R of the RC filter. This may be used to substantially reduce or even completely eliminate associated measurement errors, thereby significantly improving voltage sensing accuracy.

Whether it is necessary to cancel the sampled charge transfer during one sampling event or whether it is sufficient to cancel during multiple sampling events will depend on the nature of the circuitry following the sampling circuit. For example, using a Nyquist rate ADC converter would require cancellation of the sampled charge during a single sampling period. The use of a nyquist rate ADC converter with additional averaging or an ADC converter with oversampling would relax the requirements, instead allowing the average charge transfer to be cancelled out during several input sampling events. The residual error will depend on the exact time and frequency domain characteristics of the filtering involved.

Disclosure of Invention

An integrated circuit includes a first node and a second node. The voltage sensing circuit of the integrated circuit senses a differential voltage between two nodes having a high non-zero common mode voltage. The differential inputs form an input sampling capacitor and switching network for the sigma-delta converter such that the sigma-delta converter produces a single bit digital bit stream output, wherein the average value of the digital bit stream is proportional to the differential input voltage, but the digital bit stream may also contain offsets, gain factors and time delays, all depending on the specific characteristics of the sigma-delta modulator. The sigma-delta input sampling network, as a result of the attendant generation of its sampling operation, generates a signal-dependent, time-averaged input current that forms an associated error voltage across any finite resistance of the source RC filter.

The charge injection circuit of the input current cancellation circuit of the integrated circuit compensates for charge transfer in accordance with the modulated single bit digital bit stream signal injection. The input current cancellation circuit may be arranged such that it injects a charge sequence over time at the analog input sampling rate that substantially cancels the signal dependent differential input current caused by the input sampling network of the modulator. With respect to the input node of the voltage sensing circuit, the term offset means that the average current supplied to the node from the input current offset circuit or the average current drawn into the input current offset circuit from the node matches the average current drawn into the voltage sensing circuit from the node or the current output to the node from the voltage sensing circuit. The input current cancellation circuit supplies current onto the node if the voltage sensing circuit is drawing current from the node, and receives current from the node if the voltage sensing circuit is outputting current onto the node.

The modulated single bit digital bit stream signal controlling the compensation charge injection is directly output from the single bit digital bit stream of the analog sigma-delta modulator using a compensation circuit capable of correcting the offset and gain factor of the analog sigma-delta modulator and is advantageously derived at a high sampling rate of the modulator. In one example, a simple digital sigma-delta modulator receives a single-bit digital bit stream from an output of an analog sigma-delta modulator and generates a modulated single-bit digital bit stream signal.

Unlike previous charge compensation schemes that use additional parallel sampling paths to determine the necessary compensation signal level, the disclosed invention can directly reuse the digital output stream of a preexisting analog modulator-whatever the order of the modulator and in the presence of intentional conversion to input offsets or otherwise. This means that there is no additional sampling capacitance that would further increase both the error and the necessary compensation level.

Furthermore, considering that the charge compensation control signal is generated from a digital stream that is related to the input voltage, in the digital domain, it is much easier to make small changes to the exact desired offset and gain correction factors in order to accurately tailor the compensation level to the ideal value. The trimming is achieved by simply changing the coefficients of the digital modulator while using fixed element values in the analog domain. This can significantly relax the exact component value matching and area expensive trimming network requirements necessary for existing compensation schemes.

In a first novel aspect, an integrated circuit includes a first node, a second node, and an analog-to-digital conversion circuit. The analog-to-digital conversion circuit sequentially comprises a differential input voltage sensing circuit and an input current counteracting circuit. The differential input voltage sensing circuit senses a voltage between the first node and the second node and outputs a multi-bit digital output value indicative of the voltage. When the analog-to-digital conversion circuit performs analog-to-digital conversion, the voltage sensing circuit introduces a first current into the voltage sensing circuit from the first node (or outputs the first current from the voltage sensing circuit to the first node). When the analog-to-digital conversion circuit performs the analog-to-digital conversion, the voltage sensing circuit introduces a second current into the voltage sensing circuit from the second node (or outputs the second current from the voltage sensing circuit to the second node). The voltage sensing circuit in one example includes an analog sigma-delta modulator circuit that outputs a single bit digital bit stream signal.

An input current cancellation circuit is coupled to the first node and the second node. The input current cancellation circuit supplies a third current onto (or draws a third current from) the first node to substantially cancel the first current, and the input current cancellation circuit supplies a fourth current onto (or draws a fourth current from) the second node to substantially cancel the second current. Importantly, the input current cancellation circuit includes a digital sigma-delta modulator circuit that receives the single bit digital bit stream signal from the voltage sensing circuit. In one example, the input current cancellation circuit further comprises a switched capacitor, serial data modulated charge injector circuit. The digital sigma-delta modulator circuit output of the input current cancellation circuit is used as an input to control the charge injector circuit. The charge injector circuit then outputs a third current and a fourth current onto the first node and the second node.

In a second novel aspect, an analog-to-digital converter integrated circuit includes a voltage sensing circuit, an input current cancellation circuit, and a digital interface circuit. The digital interface circuit may be operable to load a multi-bit digital input gain trim value, a multi-bit digital input offset trim value, and a multi-bit digital feedback gain trim value onto the integrated circuit. Three multi-bit digital trim values are used as input values to configure and control the input current cancellation circuit. Three multi-bit digital trim values are stored in one or more first digital registers. Circuitry external to the integrated circuit may use the digital interface circuit to load three multi-bit digital trim values onto the integrated circuit and into one or more first digital registers.

In some examples, the analog-to-digital converter integrated circuit further includes one or more second digital registers and a compensation voltage generator circuit. One or more second digital registers store multi-bit compensation voltage values. The compensation voltage generator circuit receives the multi-bit compensation voltage value and outputs a corresponding compensation voltage to the input current cancellation circuit. Circuitry external to the integrated circuit may use the digital interface circuit to load the compensation voltage value onto the integrated circuit and into one or more second digital registers.

Further details and implementations and methods and techniques are described in the detailed description that follows. This summary is not intended to limit the invention. The invention is defined by the claims.

Drawings

The accompanying drawings, in which like numerals indicate like elements, illustrate embodiments of the invention.

Fig. 1 illustrates an example of a prior art for sensing a differential voltage between two nodes, which have differential signals and may have a non-zero common mode voltage, which may be high. The common mode voltage is limited by the electrical breakdown voltage of the capacitor's dielectric.

Fig. 2 illustrates quadrature (2-phase) non-overlapping clock signals used to control the operation and timing of the prior art switched and switched capacitor circuit of fig. 1.

Fig. 3 illustrates an additional example of the prior art that is capable of sensing differential voltages in the presence of a high non-zero common mode voltage.

Fig. 4 illustrates an additional example of the prior art that is capable of sensing differential voltages in the presence of a high non-zero common mode voltage.

Fig. 5 illustrates an example of the prior art in which the differential signal may integrate over time in the presence of a high non-zero common mode voltage while still maintaining a fully differential output signal. This prior art example is commonly used as the first stage of a sigma-delta modulator that constitutes the key element of a sigma-delta analog-to-digital converter.

Fig. 6 illustrates a flow for charging voltage sensing capacitors (C1P and C1N) inherent in the operation of the circuit of fig. 5.

Fig. 7 illustrates how the time-averaged charging current shown in fig. 6 interacts with any low-pass input filter to cause errors in the sensing of the true voltage at the battery terminals and to derive an approximation of the finite input impedance of the sensing circuit.

Fig. 8 illustrates an example of the prior art in which a switched capacitor network is used to generate a compensating reverse current at the input terminal. With the correction capacitor and the compensation voltage value, the differential input charging current can be completely cancelled.

Fig. 9 illustrates a prior art technique in which a parallel input sampling path is used to sense an input voltage and then present the input voltage to the compensation circuit of fig. 8 so that conditions for input current cancellation can be implemented over a wide range of input voltage values. This causes an infinite differential input impedance to appear for the entire circuit at nodes N1 and N2.

Fig. 10 illustrates a prior art in which the sensing circuit includes a switched capacitor, 1-order sigma-delta modulator. The digital bit stream of the modulator is used in combination with the cancellation switched capacitor network, voltage reversing switch and appropriate timing control of fig. 8 to cancel the input current and create a high differential input impedance.

Fig. 11 illustrates the prior art showing an alternative approach to achieving high differential input impedance when the sensing circuit is a switched capacitor, 1-order sigma-delta modulator. In this case, the modulator bit stream uses a series of current mirrors to achieve differential input current injection and cancellation.

Fig. 12 illustrates a modification of the compensation circuit compared to fig. 8 such that the injected charge can be directly modulated by the synchronized serial data stream such that the time averaged compensation current is proportional to the average pulse density of the serial data during a finite time interval comprising a plurality of sampling periods.

Fig. 13 illustrates how the improved circuit of fig. 12 can be used to directly compensate for the differential input impedance of a voltage sensing circuit when the sensing circuit includes a switched capacitor, 1-order sigma-delta modulator with a unipolar input signal range implemented using a switched capacitor signal path that generates an offset.

Fig. 14 is a schematic diagram of a circuit 1, the circuit 1 comprising a stack of eighteen batteries in series, a set of filter resistors and filter capacitors, and an analog-to-digital converter integrated circuit 3.

Fig. 15 is a simplified schematic diagram of one example of the circuitry of VCOMP generator 25 of fig. 14.

Fig. 16 is a schematic diagram of a portion of an analog to digital converter integrated circuit 3 according to one embodiment of the invention. The analog-to-digital converter integrated circuit 3 comprises two input voltage terminals and corresponding nodes N1 and N2, a voltage sensing circuit 18, a digital filter 19, a digital processing circuit (digital sigma-delta modulator) 21 and an average current cancellation circuit 22. The digital sigma-delta modulator 21 transforms the data stream DOUT of the analog modulator into a second data stream DCOMP whose pulse density is more properly optimized for counteracting the average differential input current of the analog modulator over the desired operating area.

Fig. 17 is a more detailed schematic diagram of the average current cancellation circuit 22 of fig. 16.

Fig. 18 is a more detailed schematic diagram of the digital sigma-delta modulator circuit 21 of fig. 16.

Fig. 19 is a graph illustrating an input-to-output data stream pulse density transformation implemented by the digital sigma-delta modulator of fig. 18 with a selected set of coefficients suitable for an analog modulator that produces 12.5% pulse density at a differential input voltage of 0V and 87.5% pulse density at a desired full scale input voltage. Such characteristics are common to single pole input, range optimized 2-order analog modulators.

Fig. 20 shows typical waveforms observed at nodes N1 and N2 of the prior art circuit of fig. 9.

Fig. 21, 22 and 23 are schematic diagrams illustrating typical waveforms observed at nodes N1 and N2 of the novel circuit of fig. 16 for different differential input voltages relative to the available input range.

Detailed Description

Reference will now be made in detail to background examples and some embodiments of the invention, examples of which are illustrated in the accompanying drawings.

It is often necessary to sense and measure small differential voltages between nodes having large common mode voltages. For example, it may be necessary to measure the voltage of one battery cell connected in a large-scale series of battery cells. Large common mode voltages do not allow significant errors to be made in the measurement of differential voltages.

Fig. 1 illustrates an example of a prior art for sensing a differential voltage between two nodes, which have differential signals and may have a non-zero common mode voltage, which may be high. The circuit includes electronic switches, capacitors C1 and C2, and inverting amplifiers operating in phases a and B.

Fig. 2 illustrates an example of a prior art quadrature (2-phase) non-overlapping clock signal used to control the operation and timing of the prior art switch of fig. 1. The electronic switch labeled a in fig. 1 is arranged to be closed when CLK a in fig. 2 is high and open when CLK a is low. The electronic switch labeled B in fig. 1 is arranged to be closed when CLK B in fig. 2 is high and open when CLK B is low. Because CLK a is allowed to go high only after CLK B is low and CLK B is allowed to go high only after CLK a is low, the switch labeled a will never be closed at the same time as the switch labeled B.

Periodically sequentially opening and closing sets of switches a and B causes charge to be transferred between the battery cell and the capacitor. When averaged over a period time equal to one or more full clock cycles (T), the charge transfer is similar to a current of the order i=Δq/Δt. This charge transfer is the basic principle of operation of switched capacitor circuits.

The charge transfer equation now presented illustrates how the circuit of fig. 1 amplifies the battery voltage VBAT while suppressing the common mode voltage (vp+vn)/2.

During phase a, the charge on capacitors C1 and C2 is given by the following equation:

Qc1a=c1 x (V _P -0) (equation 1A);

qc2a=c2×0-0 (equation 1B).

During phase B, the charge on the capacitor becomes:

qc1b=c1 x (V _N -V-) (equation 2A);

Qc2b=c2 (V _OUT B-V-) (equation 2B).

The inverting amplifier is arranged to have a very high gain and the signal V-at the inverting terminal of the amplifier is forced very close to ground via negative feedback through C2. If the gain is sufficiently high, V- =0v. In this case, we can simplify equations 2A and 2B as follows:

Qc1b=c1 x (V _N -0) (equation 3A);

Qc2b=c2 x (V _OUT B-0) (equation 3B).

The principle of conservation of charge requires that the sum of the change in charge on C1 and the change in charge on C2 be zero-so that the charge is not created or destroyed.

(QC 1A-QC 1B) + (QC 2A-Q2 CB) =0 (equation 4).

Substituting equations 1A, 1B, 3A and 3B into equation 4 yields:

C1× (V _P-V_N)+C2*(0-V_OUT B) =0 (equation 5).

Rearranging to solve for V _OUT B:

V _OUTB＝C1/C2*(V_P-V_N) (equation 6).

It is apparent that the output voltage of the amplifier is a differential input voltage (V _P-V_N) or more generally an amplified version of V _BAT. The common mode voltage of (V _P+V_N)/2 has been completely suppressed.

In the circuit of fig. 1, capacitor C1 forms a voltage isolation barrier across the dielectric layer of the capacitor—illustrated with dashed lines. The switch and connected capacitor plate to the left of the isolation barrier are exposed to high voltages. All elements to the right of the barrier, the majority of the circuit, are only subjected to low voltages of the order of magnitude similar to the differential voltage signal. The common mode voltage that can be suppressed is limited by the electrical breakdown voltage of the capacitor for C1. The breakdown voltage may be controlled by the physical spacing between the capacitor plates and by the particular materials used to form the dielectric.

Those skilled in the art will recognize that the circuit of fig. 1 is not limited to performing only an amplification function, and that the circuit may be further enhanced to achieve many important functions with small changes to the circuitry on the low voltage side of the isolation barrier. Examples include input stages such as may be used in a successive approximation or cyclic ADC or may be used to form the sample and hold function of a first stage fully differential integrator of an analog sigma-delta modulator as shown in fig. 5. Standard error correction techniques such as auto-zeroing (to remove input stage offset errors and flicker noise), which are common in equivalent low voltage circuits, can be equally well applied to the circuits in fig. 1 and 5, although the capacitor(s) C1 are used as isolation barriers.

Furthermore, as long as C1 is fabricated using standard semiconductor fabrication techniques, the nature of tight parameter matching allows for the same ratio metric accuracy to be achieved on a semiconductor chip along with similar capacitors as is typically achieved in standard low voltage circuits.

It is highly advantageous to constrain the high common mode voltage to a small area of the circuit that is limited to the switch and capacitor plates, allowing a large portion of the circuit to be constructed with smaller spacing and thus physically smaller and operate at higher speeds and lower power.

Fig. 3 and 4 illustrate additional prior art circuits that have been used to suppress common mode voltages. When the common mode voltage is high, both circuits expose more of the active circuitry to high voltages. In the example of fig. 3, both plates of capacitor C1 and all input switches will be subjected to high voltages. The inputs of the amplifier and switch B for capacitor C2 will also experience a short period of time when a high voltage is present. In the example of fig. 4, the input current is minimized because capacitor C1 is never discharged and does not need to be fully recharged every clock cycle. However, the amplifier, the capacitor and most of the switches experience high voltages. As a result, the circuits of fig. 3 and 4 are difficult to protect from high voltage damage and are not suitable for applications in which high common mode voltages are present. The term "high common mode voltage" is used herein as a term to refer to a common mode voltage of 5 volts to 90 volts or more.

Fig. 5 illustrates a fully differential input, fully differential output integrator circuit that retains all of the isolation advantages of fig. 1. Those skilled in the art will recognize the advantages of fully differential input and output structures for achieving good suppression of power supply disturbances and other common mode signal corruption. With the addition of a low voltage switched capacitor (matched to C1) to form a reference feedback network path, the circuit may form an analog 1-order sigma-delta modulator. Adding an additional pure low voltage integrator inside the feedback loop allows to implement a higher order sigma-delta modulator with the addition of an appropriate compensation path. Higher order modulators allow significantly reduced quantization noise at a given oversampling factor, which results in faster, higher resolution ADC conversion results at the same input sampling rate. 1-order modulators are rarely used in modern designs. 2-order modulators are much more common, providing a good compromise between improved performance and convenience in achieving unconditional modulator loop stability.

Fig. 6 illustrates the charge path and the change in charge through the input sampling capacitor in a 2-phase sampling network as used in fig. 5, with the clock phase as shown in fig. 2. Unlike the circuit of fig. 1, the circuit of fig. 5 uses two input sampling capacitors. The capacitors are switched in opposite phase so that during each phase of the clock signal, while one capacitor is charging from V _N to V _P, the other capacitor is discharging from V _P to V _N. The result is that for fig. 5, the transferred input charge and thus the average current observed during the whole clock cycle is doubled compared to fig. 1.

Consider CLK a:

Δq=qc1pa=c1p for C1P (V _P-V_CM)-C1P*(V_N-V_CM)＝C1P*(V_P-V_N) (equation 7A); Δq=qc1na=c1n×v _N-V_CM)-C1N*(V_P-V_CM)＝-C1N*(V_P-V_N for C1N (equation 7B).

Consider CLK B:

Δq=qc1pb=c1p for C1P (V _N-V_CM)-C1P*(V_P-V_CM)＝-C1P*(V_P-V_N) (equation 7C); Δq=qc1nb=c1n×v _P-V_CM)-C1N*(V_N-V_CM)＝C1N*(V_P-V_N for C1N (equation 7D).

Consider the total charge flowing from V _P, from V _N, and from V _CM during one clock cycle:

Total q=qc1pa+qc1nb= (c1p+c1n) ×v _P-V_N from V _P (equation 8A);

Total q=qc1na+qc1pb= - (c1n+c1p) from V _N (V _P-V_N) (equation 8B);

Total q= - (qc1pa+q1na) = - (C1P (V _P-V_N)-C1N*(V_P-V_N)) from V _CM (equation 8C).

Because c1p=c1n=c1, equations 8A to 8C are simplified as:

Total q=2×c1×from V _P (V _P-V_N) (equation 9A);

Total q= -2×c1×v _P-V_N from V _N (equation 9B);

total q=0 from V _CM (equation 9C).

Equivalent current = charge change/time and F _SAMPLE = 1/T, so:

I_(V_P)＝2*C1*(V_P-V_N)/T＝2*C1*(V_P-V_N)*F_SAMPLE＝2*C1*V_BAT*F_SAMPLE( Equation 10A);

I_(V_N)＝-2*C1*(V_P-V_N)/T＝2*C1*(V_P-V_N)*F_SAMPLE＝-2*C1*V_BAT*F_SAMPLE( Equation 10B);

I_ (V _CM) =0 (equation 10C).

The equivalent input resistance R _IN of the sampling network is given by the following equation:

R _IN＝V/I＝V_BAT/2*C1*V_BAT*F_SAMPLE＝1/(2*C1*F_SAMPLE) (equation 11).

Fig. 7 shows a prior art technique of introducing a differential RC low pass filter between the battery to be sensed and the switched capacitor sampling input network. This filter may be desirable for a number of practical reasons. The battery cell to be measured may be part of a large stack of batteries connected to a load device that generates significant electrical noise. A common load device is a motor that generates electrical noise when the motor current is switched electronically or mechanically. The filter helps reduce high frequency noise components that may interfere with the voltage sensing process and introduce errors in the measurement. RC filters may also be used to help reduce the initial "surge" current flowing into the pins of the semiconductor device when a charged or partially charged battery is initially connected to the measurement circuit. In the case of very high voltages present in large battery arrays, these surge currents can be very large, even though the filter resistance is relatively large. RC filters now present significant source impedance to the sampling network.

The finite input impedance of the voltage sensing circuit will now interact with the source impedance of the RC filter. The interaction is complex, especially in the common case where the voltage sensing circuit is shared between several battery cells in a time interleaved manner using multiplexing circuitry, or alternatively when sensing the voltage of a single cell in an intermittent manner. In both cases, there are steady state errors and short term transient errors when sampling begins and ends.

In the specific case where the invention is applicable we only concern steady state errors. Transient errors will typically dissipate before the voltage sensing process actually begins. We can further assume that: for the filter to be effective, the filter capacitor C _FILT is larger than the input sampling capacitor C1 and the filter time constant R _FILT*C_FILT is larger than the sampling period t=1/F _SAMPLE. Under these conditions, a reasonable simplification is to consider the load of the sampling network as its equivalent switched capacitor resistance given by equation 11.

The measurement error of V _BAT is a direct result of the filtered switched capacitor input current flowing through the filter resistor R _FILT and can be shown as:

V _ERROR＝V_BAT*(4*R_FILT*C1*F_SAMPLE)/(1+4*R_FILT*C1*F_SAMPLE) (equation 12).

And if the error is smaller than V _BAT, we can reduce this to:

V _ERROR＝V_BAT*(4*R_FILT*C1*F_SAMPLE) (equation 13).

If we want to minimize the error term we have three options. First, we can decrease the value of R _FILT. However, this will reduce the effectiveness of R _FILT for providing in-rush current protection, and will require a corresponding increase in the value of C _FILT to maintain the same level of source electrical noise suppression. For C _FILT, this can result in a value that may not be practical and physically large. Second, we can reduce the value of C1. Those skilled in the art will recognize that this will cause higher thermal noise of the input reference to be captured in the modulator, reducing the available signal-to-noise ratio and reducing measurement accuracy. Finally, we can reduce the sampling frequency. This may require the input filter to cut off at a lower frequency, requiring a larger value of C _FILT, and will also reduce the oversampling factor available for a given measurement rate, increasing quantization noise and rapidly decreasing measurement accuracy. None of these options is attractive.

If we can generate a current at the junction of the input filter and the voltage sensing circuit that counteracts the dynamic input current of the voltage sensing circuit, we can avoid all these detrimental variations. The compensation current must track and cancel the input current over the entire input voltage operating range of the voltage sensing circuit. The prior art illustrated in fig. 9 shows an example of how this may be achieved. Here, the switched capacitor charge injection circuit (as shown in the lower part of fig. 8) is driven to generate a parallel negative input current (I _COMP), which counteracts the total positive input current (I _{SAMP_TOT}＝I_SAMP+I_SAMPX) at the sensed node (I _COMP). To allow this cancellation to be maintained over the desired input operating range, secondary inputs forming switched capacitor level shifters and buffers are added. This gives the compensation charge injection circuit a reference input (V _{BAT_REP}), which tracks the original input voltage (V _{BAT_REP}), and appropriately modulates the charge injection and thus the negative cancellation input current.

A significant disadvantage of the method of fig. 9 is that it adds a second input sample path along with the original input sample path. The cancellation circuit now has to provide additional negative compensation to cancel the desired positive contribution of the primary sampling network (I _SAMP) and the positive contribution of the secondary sampling network (I _SAMPX) used by the buffers in the compensation loop. The sampling capacitors in the secondary input network may be significantly smaller than those in the primary sampler in order to limit the increase in total compensation necessary. This and other circuit non-idealities (component mismatch, buffer offset, etc.) can place some limitations on the final accuracy of current cancellation. We can show that the charge transfer generated by the compensation circuit over two phases (1 operation cycle) is given by the following equation:

Q _COMP＝C_COMP*(V_BAT-2*V_{BAT_REP}) (equation 14);

i _COMP＝F_SAMPLE*C_COMP*(V_BAT*-2*V_{BAT_REP}) (equation 15).

We can observe from equation 15 that the compensation circuit also initially adds an additional positive input current V _BAT(C_COMP)*F_SAMPLE to the source and then subtracts a value that is linearly related to V _{BAT_REP} and is 2*V _{BAT_REP}*C_COMP. If we arrange for V _{BAT_REP}＝V_BAT (through sub-sampling and buffering), then equation 15 becomes:

i _COMP＝-F_SAMPLE*V_BAT*C_COMP (equation 16).

And if we wish to compensate only the original sampling current I _SAMP＝2*C1*V_BAT*F_SAMPLE, we need to:

c _COMP =2×c1 (equation 17).

In practice we have to also compensate for the secondary sampling network current (I _SAMPX) of the drive buffer and any additional stray capacitors on the switched capacitor plates connected to the high voltage side of the isolation barrier. In practice, therefore, we find that C _COMP >2 x C1.

Nodes N1 and N2 experience a brief disturbance caused by the initial sampled charge. The disturbance is then counteracted with the compensation network switching operation and buffer/level shifter settling. When properly optimized, the voltage will return to exactly match V _BAT at the end of each single sampling period (T/2 for a 2-phase double sampling design). The magnitude of the offset from V _BAT during the sampling period will depend on the value of V _BAT, increasing approximately proportionally as V _BAT increases. An example waveform is shown in fig. 20.

When the primary sampled input is simultaneously the input of the sigma-delta converter, then the digital output of the modulator can be used to control the negative current generating circuit under certain conditions. Fig. 10 and 11 show two prior art examples of this aspect.

Fig. 10 is a schematic diagram of a prior art circuit in which a switched capacitor network with switches operates on both the high and low voltage sides of an isolation barrier in synchronization with a modulator such that charge is capacitively coupled across the isolation barrier in a manner similar to that illustrated in fig. 8 and 9.

Fig. 11 is a schematic diagram of a prior art circuit in which the compensation charge is metered in the low voltage domain and then mirrored to the original input through a series of high voltage current mirrors. In this example, the isolation barrier is not just incorporated into the capacitor. A charge pump may additionally be required to ensure that the circuit can operate successfully when the battery cell being measured is close to the positive or negative power supply of the sensing circuit. For both circuits of fig. 10 and 11, the compensation level can be adjusted by changing the values of V _COMP and C _COMP. Fig. 10 may be used to compensate for bipolar inputs, but fig. 11 is limited to compensating for unipolar inputs unless significant complexity is added to the mirrored circuitry at the high voltage node-which is undesirable. The circuit of fig. 11 has the advantage that the compensating charge injection circuitry does not initially add an extra switched capacitor load to the input as in fig. 9 and 10, so a significantly smaller C _COMP can be used for any given V _COMP, thereby saving circuit area. This must be weighed against the larger area required for the additional high voltage current mirror.

Fig. 12 is a schematic diagram of a portion of a novel current-offset charge injection circuit. The circuit may use a fixed reference voltage as V _COMP and a pulse density modulated synchronous DATA stream to vary the time averaged compensated charge injection level to be proportional to the pulse density of the signal DATA. Fig. 17 shows a more detailed implementation of fig. 12, which contains the necessary switch control logic and data alignment for 2-phase operation. If we define a value D _COMP (which is allowed to vary between 0 and 1) to represent the time-averaged pulse density of the input signal DATA, where 1 represents a continuous stream of all 1's and 0 represents a stream of all zeros. The circuit can be described as follows:

q _COMP＝C_COMP*(V_BAT-2*V_COMP*D_COMP) (equation 18);

i _COMP＝F_SAMPLE*C_COMP*(V_BAT-2*V_COMP*D_COMP) (equation 19).

Now, if the DATA pulse stream is synchronously derived from the digital bit stream of the delta-sigma modulator as illustrated in fig. 13, D _COMP will be linearly related to the voltage V _BAT being sensed. We can define this linear relationship using the offset O _M and the gain factor G _M such that:

D _COMP＝G_M*(V_BAT)+O_M (equation 20).

Factors O _M and G _M are characteristic properties of the modulator structure and are generally related to the modulator gain and the minimum and maximum modulation densities achievable with the digital data stream. These factors are typically severely limited by the modulator order and its stability, noise, and operating range requirements.

The total input current can be summarized as:

I_IN＝F_SAMPLE*[V_BAT*(2*C1+C_COMP[1-2*V_COMP*G_M])-2*V_COMP*C_COMP*O_M]( Equation 21).

It is important to note that in the case of V _BAT = 0, the input current is always overcompensated 2*F _SAMPLE*V_COMP*C_COMP*O_M by the current component associated with the minimum modulation value OM.

In order for it to function properly, we have to let O _M = 0. This is not practical for any real modulator because the modulator loop will collapse at a modulation factor of 0. Furthermore, at any modulation value close to 0 (or 1), the frequency-shaped quantization noise will move to a region in the frequency domain where the low-pass digital decimation filter (after the modulator) can no longer reject it. To correct for this, more circuitry may be added to introduce an additional fixed positive current to offset the excessive negative offset current. This is complex and counterproductive.

A better solution is to find a way to transform the original data stream of the modulator into a second related data stream with minimal delay, which second related data stream conveys the same information about the input signal (V _BAT), but is more fully (almost 100%) modulated and thus more suitable as a driving signal for a switched capacitor charge cancellation circuit.

Fig. 14 is a schematic diagram of a circuit 1, the circuit 1 comprising a stack of eighteen batteries BAT1-BAT18 in series, a set of filter resistors R _FILT and filter capacitors C _FILT, an RC filter 2, and an analog-to-digital converter integrated circuit 3. The batteries may be rechargeable lithium ion batteries each having a nominal charge voltage of 3.6 volts and a maximum charge voltage of about 4.2 volts. The resistors may, for example, each have a resistance R _FILT of greater than 100 ohms and each capacitor may have a capacitance C _FILT of greater than 10 nanofarads. The analog-to-digital converter integrated circuit 3 measures the voltage V _BAT of each battery and stores the resulting 16-bit measurement value in a corresponding one of the eighteen 16-bit registers 4. The reference numbers N0-N18, VDD, GND, SDO, SDI, SCK and CSB identify integrated circuit terminals. The analog-to-digital converter integrated circuit 3 is powered by the VDD terminal. The supply voltage on the VDD terminal may be up to 90 volts.

The analog-to-digital converter integrated circuit 3 further comprises a first analog-to-digital converter circuit 5, a second analog-to-digital converter circuit 6 and a third analog-to-digital converter circuit 7, the first analog-to-digital converter circuit 5 measuring the voltage on each of the upper six batteries, the second analog-to-digital converter circuit 6 measuring the voltage on the middle six batteries and the third analog-to-digital converter circuit 7 measuring the voltage on the lower six batteries. Each of the analog-to-digital converter circuits 5-7, represented as blocks in fig. 14, contains a differential input voltage sensing circuit, a digital filter outputting a D _BAT value, and an input current cancellation circuit. IN the case of an analog-to-digital converter circuit 5 measuring the voltage on the upper six batteries, there is a first six-to-analog multiplexer 8, the first six-to-analog multiplexer 8 coupling a selected one of the voltage input terminals N0-N5 to the input voltage node IN1 of the analog-to-digital converter 5, and there is a second six-to-analog multiplexer 9, the second six-to-analog multiplexer 9 coupling the other selected one of the voltage input terminals N1-N6 to the input voltage node IN2 of the analog-to-digital converter 5. These analog multiplexers are controlled to measure the voltage on six batteries BAT1-BAT6 one at a time. When there is a common mode voltage of up to 100 volts (relative to the ground node at the bottom of the battery stack), the analog-to-digital converter circuit 5 can accurately measure the voltage across the battery. The multiplexers 10 and 11 are multiplexers for the analog-to-digital converter circuit 6. The multiplexers 12 and 13 are multiplexers for the analog-to-digital converter circuit 7.

Integrated circuit 3 further includes SPI bus input/output digital interface circuit 14. Circuitry external to the integrated circuit may load multi-bit digital values into the integrated circuit via SPI bus digital interface 14 such that the corresponding nine values loaded into trim register 16 are in turn supplied to each of the three a/D converters 5, 6 and 7. Thus, each of the three analog-to-digital converters 5, 6 and 7 receives its own set of three 10-bit digital trim values I/p_offset, I/p_gain and F/b_gain from the digital control circuitry 15. Circuitry external to the integrated circuit may also use SPI bus digital interface 14 to read the eighteen 16-bit measurement data values stored in eighteen registers 4. Digital control circuitry 15 outputs multiplexer selection control signals that are supplied to the selection input leads of multiplexers 8-13. If the semiconductor manufacturing process is changed during semiconductor manufacturing, the performance parameters of the circuit elements may change such that the circuit operation is affected, and this in turn may lead to incomplete cancellation and measurement errors. Advantageously, after integrated circuit fabrication, the analog-to-digital converters 5-7 are calibrated and trimmed, and the resulting digital trim values (I/p_offset, I/p_gain, and F/b_gain) are loaded into nine trim value registers 16. When the integrated circuit 3 is suitably trimmed, the trim value supplied to the analog-to-digital converter 5-7 is fixed by writing the trim value into an OTP (one time programmable) memory 17. The tunability of the integrated circuit 3 makes the integrated circuit 3 more manufacturable and reduces manufacturing costs. Digital control circuitry 15 also generates and outputs two non-overlapping clock signals a and B.

The bandgap reference voltage circuit 24 supplies a bandgap reference voltage VBG to each of the three analog-to-digital converter circuits 5-7.

In addition to the trimming functionality and circuitry described above, the integrated circuit 3 further includes additional trimming functionality and circuitry for adjusting the V _COMP reference voltage, the V _COMP reference voltage being supplied to each of the three analog-to-digital converter circuits 5-7. The VCOMP1 reference voltage supplied to analog-to-digital converter circuit 5 is determined and adjusted by a corresponding first 5-bit digital value, the VCOMP2 reference voltage supplied to analog-to-digital converter circuit 6 is determined and adjusted by a corresponding second 5-bit digital value, and the VCOMP3 reference voltage supplied to analog-to-digital converter circuit 7 is determined and adjusted by a corresponding third 5-bit digital value. Three complementary forms of 5 bit value 2. Circuitry external to the integrated circuit may use SPI bus digital interface 14 to write the three 5-bit values stored in three corresponding addressable 5-bit registers 26 in digital control circuitry 15. Once the desired 5-bit trim values have been determined and set, these values may be fixed by writing the 5-bit trim values into fifteen associated bits of OTP memory 27. Three 5-bit trim values in registers 26 of digital control circuitry 15 are supplied to VCOMP generator circuit 25 by fifteen associated conductors 28. For each 5-bit trim value, VCOMP generator circuit 25 generates a corresponding V _COMP reference voltage and outputs the V _COMP reference voltage via a pair of conductors to input current cancellation circuitry in an associated one of analog-to-digital converter circuits 5-7. Increasing the 5-bit trim value increases the supplied voltage V _COMP, thereby increasing the gain of the input current cancellation circuitry. The total gain of the input current cancellation circuitry of a given analog-to-digital converter 5-7 is a function of both its associated multi-bit digital trimming gain value stored in register 16 and its associated multi-bit compensation voltage value stored in register 26.

Fig. 15 is a simplified schematic diagram of one example of VCOMP generator 25 of fig. 14. The 5 bit code "01111" gives the maximum gain, the code "10000" gives the minimum gain, and the code "00000" gives the nominal gain. The corresponding voltages are approximately 4.537 volts, 4.255 volts, and 4.066 volts (the input reference voltage V _BG received from the bandgap circuit is given as 3.2768).

Fig. 16 is a schematic diagram of the analog-to-digital converter 5 portion of the entire analog-to-digital converter integrated circuit 3 according to one embodiment of the invention. The analog-to-digital converter integrated circuit 3 comprises two input voltage terminals and corresponding nodes N1 and N2, a voltage sensing circuit 18, a digital filter 19 and an input current cancellation circuit 20. The voltage sensing circuit 18 and the digital filter 19 together form a sigma-delta analog-to-digital converter circuit outputting a multi-bit digital output value D _BAT. The input current cancellation circuit 20 in the example of fig. 16 includes a digitally trimmable digital processing circuit (digital sigma-delta modulator) 21 and an average current cancellation circuit 22.

Fig. 17 is a simplified circuit diagram of an example of the average current cancellation circuit 22 of fig. 16. The circuit is a two-phase switched capacitor, serial data modulated variable charge injector. The appropriate one of the VCOMP voltage reference outputs of VCOMP generator circuit 25 of FIG. 14 is coupled to the V _COMPHI input conductor of FIG. 16. The V _COMPLO input conductor is coupled to GND. The modulated single bit digital signal DCOMP from the DMOD _OUT output of the digital sigma-delta modulator 21 of fig. 16 is supplied onto the DATA input lead of fig. 17. Signals a and B are non-overlapping clock signals a and B generated by digital control circuitry 15 of fig. 14.

Fig. 18 is a simplified circuit diagram of an example of the digital trimmable digital processing circuit 21 of fig. 16. The single bit digital signal DOUT is received from the voltage sensing circuit 18 of fig. 16. The modulated single bit digital signal DCOMP output from the circuit of fig. 18 is supplied to the average current cancellation circuit 22 of fig. 16.

In the embodiment of fig. 16, an analog modulator 23 of an arbitrary first order or higher is used as the main stage sampling network (in the voltage sensing circuit 18). The single bit output data stream DOUT is efficiently transformed into a deep pulse density modulated synchronization signal driving a compensation network. The additional circuitry is all implemented in the digital circuit domain, so in modern processes, where the digital logic is very compact, the solution adds only a very small circuit area. Furthermore, the parameters that determine the characteristics of the new circuit are accurately predictable and can be changed by simply changing the coefficient values in the digital logic. This greatly simplifies the process of compensating for any necessary trimming that may be required for element variation in the analog domain.

In the presently described analog-to-digital conversion integrated circuit of fig. 14, the digital interface terminals include an SDO terminal, an SDI terminal, an SCK terminal, and a CSB terminal. Digital interface circuit 14 (see fig. 14) coupled to these terminals implements an SPI serial bus interface. The SPI serial bus interface 14 can be used to load a 10-bit digital input OFFSET (I/P_OFFSET) value, a 10-bit digital input GAIN (I/P_GAIN) value, and a 10-bit digital feedback GAIN (F/B_GAIN) value into an integrated circuit. When an analog to digital conversion integrated circuit is being tested in the final test stage of integrated circuit production, a known input voltage is supplied to the voltage input terminal and errors are observed. The values of I/p_offset and I/p_gain are then adjusted by loading new I/p_offset and I/p_gain values into the integrated circuit via the digital interface circuit in order to change the transfer function of the overall input current cancellation circuit. New errors are then observed. This sequence of tuning the trim value and observing the resulting error is performed multiple times to determine the desired trim value. Once the desired trim values have been determined and loaded into the integrated circuit, they are then programmed into the fuse-type OTP (one-time programmable) memory 17 of the digital interface circuit 14.

In the presently described analog-to-digital conversion integrated circuit of fig. 16, the decimating digital filter may be a sinc filter. In one example where the decimating digital filter is a third order sinc filter, the sinc filter involves a cascade of three digital integrators, a digital sample and hold circuit, and a cascade of three digital differentiators. The digital integrator operates at the same data rate clock as the analog modulator, and the digital sample and hold circuit and the digital differentiator operate at the desired output data rate clock.

The analog to digital conversion integrated circuit 3 of fig. 16 differs from the circuits of fig. 13, 10 and 11 in that it incorporates a digital sigma-delta modulator in the input current compensation loop, and in that the transfer function of the input current compensation circuit is digitally programmable.

To achieve a high modulation depth at its output, a first order sigma-delta modulator is used and comprises a digital integrator that limits its output range. The limiting function serves to improve the transient stability and recovery time of the compensation loop and allows it to respond quickly to changes in battery voltage V _BAT or the onset of voltage sensing when being initiated from an idle state. An optional RESET may be used to further improve transient stability of the loop at the beginning of the measurement. The illustrated first order digital modulator is not the only possible implementation. Other implementations may decompose the summation of the input and integration functions into a plurality of separate adders, and may also use digital representations other than the illustrated 2's complement format. The block shown as MUX may also be implemented as an AND function.

In the implementation of digital trimmable digital processing circuit 21 of fig. 18, incoming signal DMOD _IN is a single bit input signal DOUT bit stream received from voltage sensing circuit 18 of fig. 16. The signal CLK may be, for example, a clock signal CLKA. Each of the two multiplexer symbols on the right of the diagram represents a 10-bit two-to-one multiplexer. The bipolar limiter receives the 10-bit digital value and outputs the same 10-bit value to the register unless the incoming value is greater than a predetermined maximum positive value (a greater positive number), in which case the bipolar limiter outputs the predetermined maximum positive value. If the incoming value is more negative (a greater negative number) than the predetermined maximum negative value, the bipolar limiter outputs the predetermined negative value. The register symbol represents a 10-bit register. The MSB of a 10-bit value as output from a register is a sign bit indicating whether the value is a positive value or a negative value. Single bit signal DMOD _OUT is an inverted version of the sign bit.

When the last registered value of the integrator is a positive value, the feedback GAIN value of F/B _ GAIN is subtracted on the next active clock edge to decrease the next value of the integrator. When the last value of the integrator is negative, a feedback value of 0 is added to the integrator in the opposite sense. On each active clock edge, a value equal to the value I/p_offset is subtracted from the integrator. Finally on each active clock edge, the value of I/P _ GAIN, or 0, is added to the integrator, depending on the state of the input DMOD _IN from the analog modulator. I/p_gain is added when DMOD _IN is 1, and 0 is added when DMOD _IN is 0. If I/p_gain has a value of 8 and if I/p_offset has a value of 1 and if F/b_gain has a value of 6, then a pulse density transformation between DMOD _IN and DMOD _OUT is observed as illustrated in fig. 19.

Negative feedback in the modulator attempts to keep the integrator value at 0. In this example, the value of F/B_GAIN is less than the value of I/P_GAIN. As a result, as the pulse density (D _DMODIN) of signal DMOD _IN increases, the pulse density (D _DMODOUT) of signal DMOD _OUT will increase more rapidly. The pulse density transfer function is given by the following equation: d _DMODOUT＝limit(1,0,[("I/P_GAIN"*D_DMODIN + "I/p_offset")/"F/b_gain" ]) (equation 22).

Here the limit function constrains the pulse density to be maximally 1 (all ones) and minimally 0 (all zeros).

In the circuit of fig. 18, when the value of the pulse density (D _DMODIN) of DMOD _IN is in a region where the output pulse density (D _DMODOUT) of DMOD _OUT becomes limited to all ones or all zeros, the integrator will naturally drift to an unbounded value and the modulator feedback loop is essentially disconnected. In this region, the operation of the bipolar limiter becomes important and now operates to set well-defined minimum and maximum integrator values. This prevents any problems that may arise from the digital value "wrapping" of the integrator due to limited word width limitations. The limitation of the integrator value also ensures that when the modulator input returns into a region that no longer saturates the modulator, the integrator value will return to a value close to zero with a few clock cycles. This improves the transient stability of the modulator and allows the compensation loop to respond quickly to changes in the input voltage and corresponding current. A balance must be chosen between the settling time and the normal operating range of the integrator values of the modulator.

The coefficients and transfer functions of fig. 19 are close to ideal when using a typical unipolar input range, second order sigma-delta modulator as the primary voltage sensing circuit. In this case, the input range of the converter may be shifted using a switched capacitor network such that with a differential input voltage of 0V, a pulse density of 12.5% (D _DMODIN =0.125) is generated at the modulator digital output. The gain of the modulator is set such that at the desired full scale input voltage, 87.5% pulse density (D _DMODIN =0.875) is returned. These minimum and maximum pulse densities ensure that quantization noise remains in the frequency region that is sufficiently suppressed by a simple third order sinc decimation filter.

The digital modulator advantageously converts the output digital data stream (DOUT in fig. 16) of the original analog modulator 23 of the voltage sensing circuit 18 into a new compensated digital data stream (DCOMP in fig. 16) that exhibits 100% pulse density at full scale input (V _BATMAX) and 0% pulse density at 0V. This action both removes the problem of excess input charge compensation at 0V (because the compensated data pulse density is now 0 at this input value) and allows the minimum value of V _COMP to be used-because the compensated data pulse density is now 1 at full scale input voltage. The digital modulator operates at the analog modulator sampling rate so there is very little delay in the current compensation path back to the input RC filter. The exact delay depends on the analog modulator coefficient, but is typically a few clock cycles at the analog modulator clock rate. This is much faster than the circuit has to wait for a full decimated conversion (involving a delay of possibly hundreds of analog modulator clock cycles) in order to determine the value of V _BAT.

If V _COMP has to be generated in low voltage circuitry, it is important to minimize the necessary value of V _COMP. However, if V _COMP can be generated in the high-voltage domain, there is an additional degree of freedom to reduce the value of C _COMP, and thus the circuit area. The reader will recall equation 21 and with a digital modulator in the compensation loop and at maximum input voltage V _BATMAX (where D _DMODOUT =1), we can now set the value of O _M to 0 and the value of G _M to 1/V _BATMAX. This gives:

max (I _IN)＝F_SAMPLE*V_BATMAX*(2*C1+C_COMP[1-2*V_COMP/V_BATMAX ]) (equation 23).

If we set I _IN to 0, we can solve for C _COMP with a given V _COMP:

C _COMP＝2C1/(2*V_COMP/V_BATMAX -1) (equation 24).

Or solve for V _COMP with a given C _COMP:

v _COMP＝V_BATMAX*(2C1+C_COMP)/(2*C_COMP) (equation 25).

Note that in both cases, when we set V _COMP＝V_BATMAX, then C _COMP =2×c1. This is exactly the same result for the circuit implementation of fig. 9 in equation 17. Here, however, we have the flexibility to adjust V _COMP to easily change the ratio of C _COMP to C1 if we wish. Higher V _COMP may be used to enable downsizing of C _COMP that may be necessary to save area. Alternatively, a lower V _COMP may be used with a higher C _COMP wherever it may be more advantageous.

Fig. 21, 22 and 23 show how the voltage observed between nodes N1 and N2 is modulated by the input current compensation circuit 20 according to the DCOMP control signal. It can be noted that we eliminate the requirement that the value of V _(N1,N2) be restored to V _BAT within T/2. Now, only the average value of V _(N1,N2) during the longer period of time matches the applied input voltage V _BAT. Three cases are shown for circuit operation in which the input operating range is 0V to 5V and the V _BAT values are 1.6V, 2.7V, and 4.4V. The peak-to-peak amplitude of the modulation is a function of the ratio of C _COMP to C _FILT. A larger C _FILT will reduce the modulation signal amplitude. In the waveforms of fig. 21, 22 and 23, signals a and B are non-overlapping clock signals a and B generated by digital control circuitry 15 of fig. 14.

In one example, an analog-to-digital converter with a novel input current cancellation circuit differs from prior art circuits in that there is a small voltage signal on the input terminals (e.g., N1 and N2 of fig. 14), for example, when the battery is being measured from these terminals. The voltage signal has spectral components below the sampling rate (frequencies of non-overlapping sampling signals a and B) and the amplitude of the spectral components is greater than the amplitude of any spectral component (of the voltage signal) at the sampling rate frequency or higher. In a similar circuit of the prior art that generates a signal of the type illustrated in fig. 20, there is no substantial spectral component (of the voltage signal present on the input terminal) at frequencies below the sampling rate frequency.

In general, the introduction of a digital modulator into the compensation loop enables the implementation of a sampled input current compensation circuit (fig. 16) that is at least as effective as the analog equivalent of the prior art (fig. 9 to 13), but now has the following significant advantages: (1) The parallel input sampling network or buffer structure is not needed in the compensation path; (2) A simple 2-phase switched capacitor differential charge injection circuit with serial pulse density modulation may be used; (3) May be used with any analog sigma-delta modulator of any order as the primary sense circuit; (4) With low area overhead due to digitally implementing additional modulators; (5) Can be easily trimmed in the digital domain by simply changing the digital coefficient values of the digital modulator; (6) Allowing to flexibly reduce or increase the size of the compensation capacitor C _COMP by means of a simple trade-off between the size of the DC voltages V _COMP and C _COMP.

Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. Accordingly, various modifications, adaptations, and combinations of the various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims (20)

1. An integrated circuit, the integrated circuit comprising:

a first node;

a second node;

An analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising:

A differential input voltage sensing circuit that senses a voltage between the first node and the second node and outputs a multi-bit digital output value indicative of the voltage, wherein the voltage sensing circuit conducts a first current between the voltage sensing circuit and the first node when the analog-to-digital conversion circuit performs analog-to-digital conversion, wherein the voltage sensing circuit conducts a second current between the voltage sensing circuit and the second node when the analog-to-digital conversion circuit performs analog-to-digital conversion; and

An input current cancellation circuit coupled to the first node and the second node, wherein the input current cancellation circuit conducts a third current between the input current cancellation circuit and the first node such that the first current is substantially cancelled, wherein the input current cancellation circuit conducts a fourth current between the input current cancellation circuit and the second node such that the second current is substantially cancelled, wherein the input current cancellation circuit comprises:

A digital processing circuit that outputs a modulated single bit digital bit stream; and an average current cancellation circuit that receives the modulated single bit digital bit stream signal from the digital processing circuit and outputs the third current and the fourth current.

2. The integrated circuit of claim 1, wherein the voltage sensing circuit further outputs a single bit digital bit stream, wherein the digital processing circuit of the input current cancellation circuit receives the single bit digital bit stream from the voltage sensing circuit.

3. The integrated circuit of claim 1, wherein the digital processing circuit comprises a digital sigma-delta modulator.

4. The integrated circuit of claim 3, the integrated circuit further comprising:

one or more registers storing multi-bit digital input gain values, wherein the multi-bit digital input gain values are supplied to the digital processing circuit.

5. The integrated circuit of claim 3, the integrated circuit further comprising:

One or more registers storing a multi-bit digital input gain value, a multi-bit digital input offset value, and a multi-bit digital feedback gain value, wherein the multi-bit digital input gain value, the multi-bit digital input offset value, and the multi-bit digital feedback gain value are supplied to the digital processing circuit.

6. The integrated circuit of claim 1, wherein the average current cancellation circuit comprises a switched capacitor, serially modulated charge injector.

7. The integrated circuit of claim 6, the integrated circuit further comprising:

One or more registers storing multi-bit compensation voltage values; and

A compensation voltage generator circuit that receives the multi-bit compensation voltage value and outputs a compensation voltage that is supplied to the average current cancellation circuit.

8. The integrated circuit of claim 1, the integrated circuit further comprising:

a first terminal;

A first analog multiplexer coupled to supply a voltage on the first terminal onto the first node;

A second terminal; and

A second analog multiplexer coupled to supply the voltage on the second terminal onto the second node.

9. The integrated circuit of claim 1, wherein during a period of time when the analog-to-digital conversion circuit is performing analog-to-digital conversion, there is a high common mode voltage present on both the first node and the second node, wherein the high common mode voltage is greater than 25 volts.

10. A method, the method comprising:

(a) Sensing a voltage between a first input node of a voltage sensing circuit and a second input node of the voltage sensing circuit, and outputting a multi-bit digital output value indicative of the voltage, wherein the voltage sensing circuit conducts a first current between the voltage sensing circuit and the first input node, wherein the voltage sensing circuit conducts a second current between the voltage sensing circuit and the second input node, wherein a first terminal of an integrated circuit is coupled to the first input node, and wherein a second terminal of the integrated circuit is coupled to the second input node;

(b) Conducting a third current between an input current cancellation circuit and the first input node such that the third current substantially cancels the first current such that substantially no current flows into or out of the integrated circuit through the first terminal, and conducting a fourth current between the input current cancellation circuit and the second input node such that the fourth current substantially cancels the second current such that substantially no current flows into or out of the integrated circuit through the second terminal;

(c) Receiving a single bit digital bit stream from the voltage sensing circuit onto a digital processing circuit and generating a modulated single bit digital bit stream from the single bit digital bit stream; and

(D) Receiving the modulated single bit digital bit stream from the digital processing circuit onto a charge injector circuit and controlling the charge injector circuit using the modulated single bit digital bit stream, wherein the charge injector circuit is coupled to the first input node and the second input node, wherein the voltage sensing circuit, the first terminal, the second terminal, and the input current cancellation circuit are all part of the integrated circuit, and wherein (a) through (d) are performed by the integrated circuit.

11. The method of claim 10, wherein the digital processing circuit comprises a digital sigma-delta modulator.

12. The method of claim 10, wherein the charge injector circuit comprises a switched capacitor, serial modulated charge injector.

13. The method of claim 10, the method further comprising:

(e) A multi-bit digital gain value is stored in one or more digital registers on the integrated circuit, wherein the multi-bit digital gain value is supplied to the digital processing circuit.

14. The method of claim 10, the method further comprising:

(e) Storing a multi-bit compensation voltage value in one or more digital registers on the integrated circuit; and

(F) The multi-bit compensation voltage value is used to control a compensation voltage generator circuit to cause the compensation voltage generator circuit to output a compensation voltage, wherein the compensation voltage is supplied to the charge injector circuit.

15. The method of claim 10, wherein during a period of time when the voltage sensing circuit is outputting the multi-bit digital output value, there is a high common mode voltage present on both the first input node and the second input node.

16. An integrated circuit, the integrated circuit comprising:

a first integrated circuit terminal;

a second integrated circuit terminal;

An analog-to-digital converter circuit that senses a voltage between a first input node and a second input node and outputs a multi-bit digital output value indicative of the voltage, wherein a first current flows from the first node into the analog-to-digital converter circuit during a period of time when the analog-to-digital converter circuit is performing analog-to-digital conversion, wherein a second current flows from a voltage sensing circuit to the second node during the period of time when the analog-to-digital converter circuit is performing the analog-to-digital conversion, wherein during the period of time a high common mode voltage is present on both the first input node and the second input node, and wherein the high common mode voltage during the period of time is greater than 25 volts;

A first multiplexer controlled during the time period to couple the first integrated circuit terminal to the first input node;

a second multiplexer controlled during the time period to couple the second integrated circuit terminal to the second input node;

Means for canceling the first current and the second current, wherein the means for canceling is for canceling the first current by supplying a third current from the means for canceling onto the first input node, wherein the means for canceling is further for canceling the second current by introducing a fourth current from the second input node into the means for canceling, wherein the means for canceling comprises:

A digital processing circuit; and

An average current cancellation circuit that receives a control signal from the digital processing circuit, wherein the average current cancellation circuit is coupled to the first input node and the second input node.

17. The integrated circuit of claim 16, the integrated circuit further comprising:

One or more digital registers storing multi-bit digital gain values, wherein the multi-bit digital gain values are supplied to the digital processing circuit.

18. The integrated circuit of claim 16, wherein the digital processing circuit comprises a digital sigma-delta modulator, and wherein the digital sigma-delta modulator receives a single bit digital bit stream from the analog-to-digital converter circuit.

19. The integrated circuit of claim 16, wherein the control signal received by the average current cancellation circuit from the digital processing circuit is a modulated single bit digital bit stream.

20. The integrated circuit of claim 16, wherein the analog-to-digital converter circuit comprises an input switch portion, an analog sigma-delta modulator portion, and a digital filter portion.