CN118213443A - Epitaxial growth method and structure of light-emitting diode - Google Patents

Abstract

The application relates to a growth method of light-emitting diode epitaxy, which comprises the following steps: providing a layer of substrate, wherein the substrate is one of an Al ₂O₃ substrate, an Al ₂O₃/SiO₂ composite substrate, a Si substrate, a BN substrate and a SiC substrate; sequentially depositing and growing a u-GaN layer, a dislocation middle fault and an N-GaN layer on a substrate, wherein the dislocation middle fault comprises a SiC inserting layer and a dislocation filling layer which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, and the N is more than or equal to 1; wherein the temperature used for depositing the SiC insert layer is 1000-1550 ℃; the gases used for depositing the SiC insert layer are silicon source gas and carbon source gas, the flow rate of the silicon source gas is 1-1000 sccm, and the flow rate of the carbon source gas is 1-1000 sccm; the flow rate of the gas carrier gas used for depositing the SiC insert layer is 10-500 slm; the deposition pressure of the SiC insert layer is 100-700 torr.

Description

Epitaxial growth method and structure of light-emitting diode

Technical Field

The present application relates to the field of light emitting diode technology, and in particular, to a method and a structure for epitaxial growth of a light emitting diode.

Background

A light emitting Diode (LIGHT EMITTING Diode, LED) is a semiconductor electronic component capable of emitting light. As a novel solid-state lighting source with high efficiency, environmental protection and green color, LEDs are a new generation of light sources with wide prospects, and are being rapidly and widely applied to such fields as traffic lights, interior and exterior lamps of automobiles, urban landscape lighting, indoor and outdoor display screens, small-pitch display screens, and the like.

In the related art, a light emitting diode epitaxial wafer is a semiconductor film grown on a single crystal material with a matched crystal structure, and a chip can be formed by processing the epitaxial wafer, and the light emitting diode is obtained after the chip is packaged. Conventional LED epitaxial wafers include at least a sapphire Al ₂O₃ substrate and a gallium nitride GaN layer grown on the substrate, with up to 13.8% lattice mismatch between Al ₂O₃ and the GaN layer, for example, a large number of dislocations are formed, including threading, edge and mixed dislocations, etc. These dislocations further form threading dislocations, extend to the light emitting structure, seriously affect electron hole recombination efficiency of the light emitting layer, and eventually cause the light emitting efficiency of the LED to become low.

For the above reasons, there is a need for a light emitting diode epitaxial wafer capable of interrupting the extension of underlying dislocations and effectively protecting the light emitting layer.

Disclosure of Invention

The application provides a growth method and a structure of light-emitting diode epitaxy, which are used for solving the problem of interrupting the extension of dislocation at a bottom layer and effectively protecting a light-emitting diode epitaxial wafer of a light-emitting layer.

The first aspect of the application provides a method for growing an epitaxial light emitting diode, which comprises the following steps:

Providing a layer of substrate, wherein the substrate is one of an Al ₂O₃ substrate, an Al ₂O₃/SiO₂ composite substrate, a Si substrate, a BN substrate and a SiC substrate;

Sequentially depositing and growing a u-GaN layer, a dislocation middle fault and an N-GaN layer on the substrate, wherein the dislocation middle fault comprises a SiC inserting layer and a dislocation filling layer which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, and the N is more than or equal to 1; wherein,

The temperature used for depositing the SiC insert layer is 1000-1550 ℃;

The gases used for depositing the SiC insert layer are silicon source gas and carbon source gas, the flow rate of the silicon source gas is 1-1000 sccm, and the flow rate of the carbon source gas is 1-1000 sccm;

The flow rate of the gas carrier gas used for depositing the SiC insert layer is 10-500 slm;

The deposition pressure of the SiC insert layer is 100-700 torr;

The deposition thickness of the SiC insert layer is 10-1000A;

the dislocation filling layer has a thickness of 0.1-2 um.

In one manner that may be implemented, the temperature used to deposit the SiC insertion layer is between 1000 and 1200 degrees.

In one manner of implementation, the silicon source gas is SiH ₄; the flow rate of the silicon source gas is 100-200 sccm.

In one implementation, the carbon source gas is any one or a combination of several of CH ₄、C₂H₄、C₂H₆ and C ₃H₈; the flow rate of the carbon source gas is 100-200 sccm.

In one manner of implementation, the gaseous carrier gas is H ₂; the flow rate of the gas carrier gas is 50-100 slm.

In one mode of practice, the deposition pressure of the SiC insert layer is 400-600 torr; the deposition thickness of the SiC insert layer is 100-200A.

In one way of implementation, the dislocation fill-in layer is a superlattice layer composed of at least one of GaN, alN, inN, inGaN, alGaN and InAlGaN; the dislocation filling layer is an unintentional doped layer or a Si doped N-type layer; the dislocation filling layer has a thickness of 0.5-1 um.

In one manner that may be implemented, the method further includes: a stress release layer, a multiple quantum well light-emitting layer, an electron blocking layer, a p-GaN layer and a metal contact layer which are sequentially grown on the n-GaN layer; wherein,

The n-GaN layer is Si doped GaN, the thickness is 1-3 um, and the concentration is 1E 18-5E 19atoms/cm ³;

the stress release layer is of an InGaN/GaN superlattice structure;

The multi-quantum well light-emitting layer is of an InGaN/GaN/AlGaN superlattice structure.

A second aspect of the present application provides a light emitting diode epitaxial structure, which is applied to the aforementioned method for growing light emitting diode epitaxy, and the light emitting diode epitaxial structure includes:

The substrate is one of an Al ₂O₃ substrate, an Al ₂O₃/SiO₂ composite substrate, a Si substrate, a BN substrate and a SiC substrate;

and sequentially stacking a u-GaN layer, a dislocation interrupt layer and an N-GaN layer which are positioned on the substrate, wherein the dislocation interrupt layer comprises a SiC insertion layer and a dislocation filling layer which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, and the N is more than or equal to 1.

In one manner that may be implemented, the method further includes:

And a stress release layer, a multiple quantum well light-emitting layer, an electron blocking layer, a p-GaN layer and a metal contact layer which are sequentially grown on the n-GaN layer.

The application has the beneficial effects that:

And depositing dislocation interrupt layers on the u-GaN layer of the substrate, wherein the dislocation interrupt layers comprise SiC insertion layers and dislocation filling layers which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, N is more than or equal to 1, and dislocation extension of the substrate and the u-GaN layer is interrupted by the dislocation interrupt layers, so that a luminescent layer arranged on the dislocation interrupt layers is protected, and the luminous efficiency is improved. Even if the lattice mismatch between the Al ₂O₃ and the GaN layer reaches 13.8%, the dislocation caused by the lattice mismatch can not extend to the top layer continuously through the interruption of the dislocation interrupt layer, so that the electron hole recombination efficiency of the light-emitting layer is prevented from being influenced, and the light-emitting efficiency of the light-emitting diode is improved. In addition, dislocation breaking layers can be grown between the substrate and the n-GaN layer in a circulating growth mode, so that the extension of lattice mismatch to the light-emitting layer is further interrupted, and the light-emitting effect of the light-emitting diode is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for epitaxial growth of a light emitting diode according to the present application;

FIG. 2 is a defect chart of a method for growing an LED epitaxy according to the present application;

Fig. 3 is a schematic diagram of an led epitaxial structure according to the present application.

Detailed Description

The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In embodiments of the invention, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In order to facilitate understanding of the technical solutions of the application, some concepts related to the present application will be described below first.

Warpage (warpage), which is a physical phenomenon in which the processed laminate is not shaped according to the designed shape, and surface distortion occurs, resulting in uneven shrinkage of the shaped laminate.

Lattice mismatch refers to a mismatch phenomenon that occurs due to the difference in lattice constants of the substrate and the epitaxial layer. When a single crystal layer of another substance is grown on a single crystal substrate, stress is generated near the growth interface due to the difference in lattice constants of the two substances, and crystal defect misfit dislocation is generated.

Bond energy, which refers to the energy released when a chemical bond is formed or the energy absorbed when a chemical bond breaks, can be used to mark the strength of the chemical bond.

The IV main group is the fourth main group element in the periodic table, and comprises five elements of carbon, silicon, germanium, tin, lead and lead.

Superlattice structure refers to a multilayer film in which two different group elements alternately grow in thin layers of several nanometers to several tens of nanometers and maintain strict periodicity.

Heteroepitaxy is a physical term. It means that the epitaxially grown thin film material and the substrate material are different, or that the chemical composition of the growth, even the physical structure and the substrate are completely different, and the corresponding process is called heteroepitaxy.

An Electron Blocking Layer (EBL) is a thin film capable of controlling the flow direction of electrons in an LED (blocking reverse leakage current) and improving luminous efficiency.

In the light-emitting diode, the substrate is mostly a sapphire Al ₂O₃,Al₂O₃ substrate, and the light-emitting diode has the advantages of good chemical stability, no absorption of visible light, moderate price and relatively mature manufacturing technology. Gallium nitride GaN can also be directly used as a substrate, and the dislocation density of the GaN substrate is obviously lower than that of the Al ₂O₃ substrate. However, since GaN is expensive and difficult to process, it cannot be matched with conventional LED epitaxial wafer processing methods, al ₂O₃ is used as a substrate, and GaN is grown on the substrate. However, since Al ₂O₃ has a high lattice mismatch with GaN, the luminous efficiency of the LED becomes low.

Based on the above reasons, the application provides a growth method of light emitting diode epitaxy, which is to place a silicon carbide SiC insertion layer and a dislocation filling layer between a u-type gallium nitride u-GaN layer and an n-type gallium nitride n-GaN layer to form a dislocation breaking layer, so as to break the threading dislocation formed by extending dislocation to the top layer due to lattice mismatch through the dislocation breaking layer, avoid the influence of the threading dislocation on the electron hole recombination efficiency of the light emitting layer, and improve the light emitting efficiency of the light emitting diode.

As shown in fig. 1, the present application provides a method for growing an led, which includes:

s100: a layer of substrate is provided.

The substrate can be one of an Al ₂O₃ substrate, a sapphire/silicon dioxide Al ₂O₃/SiO₂ composite substrate, a silicon Si substrate, a boron nitride BN substrate and a silicon carbide SiC substrate.

Illustratively, the substrate may be placed in a reaction chamber, which may be a reaction chamber of a metal organic compound vapor deposition apparatus, such as Veeoo K i MOCVD or Veeco C4 MOCVD. Further, if other layers are grown on the substrate, one or two mixed gases of hydrogen and nitrogen can be used as a carrier.

S200: and sequentially depositing and growing a u-GaN layer, a dislocation middle fault and an n-GaN layer on the substrate.

The dislocation breaking layer comprises a SiC insertion layer and a dislocation filling layer which are circularly grown on the u-GaN layer, wherein the times of the circular growth are N, and N is more than or equal to 1.

Illustratively, if the number of cyclic growth is 1, a u-GaN layer, a SiC insertion layer, a dislocation fill layer, and an n-GaN layer may be sequentially deposited on the substrate. If the number of the cyclic growth times is 2, a u-GaN layer, a SiC inserting layer, a dislocation filling layer and an n-GaN layer can be sequentially deposited and grown on the substrate. By analogy, the number of times of the cycle growth can be adjusted according to the actual situation, and the present embodiment does not limit the number of times of the cycle.

The SiC insertion layer is deposited at a temperature of 1000 to 1550 degrees. Illustratively, the temperature used for deposition may be 1000 degrees, 1050 degrees, 1100 degrees, 1150 degrees, 1200 degrees, 1250 degrees, 1300 degrees, 1350 degrees, 1400 degrees, 1450 degrees, 1500 degrees, or 1550 degrees, and may be other temperature values between 1000 and 1550 degrees, which are not shown.

Preferably, the temperature used for the deposition is between 1000 and 1200 degrees. The specific temperature values may be adjusted accordingly at different stages of the actual operation, and should not be understood as having to maintain a temperature from the beginning to the end of depositing the SiC insertion layer, but may be adjusted within a reasonable temperature range, for example, to a temperature range between 1000 and 1200 degrees, 1250 and 1350 degrees, or a temperature value.

It should be noted that the SiC insertion layer and the dislocation filling layer have the function of interrupting the stress and dislocation between the Al ₂O₃ and the u-GaN layer to extend to the top layer, thereby protecting the light emitting layer structure and improving the light emitting efficiency. Typically, the temperature at which the SiC insertion layer is deposited is selected to be between 650 and 1500 degrees celsius. If a higher temperature is selected, the quality of the SiC insertion layer is increased, and the melting point of the dislocation filling layer is also close to that of the dislocation filling layer, so that the material of the dislocation filling layer is damaged. Depositing the SiC intercalation layer at a lower temperature can result in poor film quality of the SiC, resulting in severe absorption. Thus, the temperature used for depositing the SiC insertion layer according to the present application is preferably 1000 to 1550 degrees. At this temperature, not only the quality of the SiC insertion layer but also the light absorption can be reduced, and the lattice mismatch between the SiC insertion layer and the dislocation fill layer can be ensured to be changed from conventional 13.8% to 3.5%. Wherein the dislocation fill layer herein refers to the dislocation fill layer at the top layer of the SiC insertion layer and the u-GaN layer or dislocation fill layer at the bottom layer.

Illustratively, as in FIG. 2, the downward triangle indicates the stress and dislocation formation defect between the Al ₂O₃ and the u-GaN layer, with dislocation break layers terminating the defect extension toward the top layer. It can be appreciated that some defects are larger, some defects are smaller, and when the defects are larger, one dislocation breaking layer can only reduce the defects, and dislocation extending to the top layer may not be interrupted well, so that dislocation breaking layers with more than two cycles need to be used for interruption so as to interrupt the defects more thoroughly, protect the light-emitting layer structure and improve the light-emitting efficiency.

Preferably, the gases used for depositing the SiC insert layer are a silicon source gas and a carbon source gas, and the flow rate of the silicon source gas is 1-1000 standard milliliters per minute sccm. The silicon source gas flow rate may be 1sccm, 100sccm, 300sccm, 500sccm, 700sccm, 900sccm, or 1000sccm, for example, and may be other flow rate values not shown in 1 to 1000 sccm.

Preferably, the flow rate of the carbon source gas is 1-1000 sccm. Illustratively, the carbon source gas flow rate may be 1sccm, 100sccm, 300sccm, 500sccm, 700sccm, 900sccm, or 1000sccm, and may be other flow rate values not shown in 1 to 1000sccm.

The silicon source gas may be monosilane SiH ₄.

SiH ₄ is used as a gas source for providing a silicon component, and can pass through the surface of the u-GaN layer or the dislocation filling layer at a high temperature of 1000-1550 ℃ at a speed of 1-1000 sccm and deposit on the surface of the u-GaN layer or the dislocation filling layer to form the SiC insertion layer.

Wherein, in order to better deposit the SiC insertion layer on the surface of the u-GaN layer or dislocation fill layer, the flow rate of the silicon source gas is preferably 100-200 sccm. The flow rate of the silicon source gas may be 100sccm, 110sccm, 120sccm, 130sccm, 140sccm, 150sccm, 160sccm, 170sccm, 180sccm, 190sccm, or 200sccm, or may be other flow rate values not shown in 100 to 200sccm, for example.

The carbon source gas may be any one or a combination of methane CH ₄, ethylene C ₂H₄, liquefied ethane C ₂H₆, or propane C ₃H₈.

Wherein, the composition of any one or more of CH ₄、C₂H₄、C₂H₆ and C ₃H₈ constituting the carbon source gas may be, for example: a combination of CH ₄ and C ₂H₄; a combination of CH ₄ and C ₂H₆; a combination of CH ₄ and C ₃H₈; a combination of C ₂H₄、C₂H₆ and C ₃H₈; a combination of CH ₄、C₂H₄ and C ₃H₈; combinations of C ₂H₄、C₂H₆ and C ₃H₈, and the like. The carbon source gas can pass through the surface of the u-GaN layer or the dislocation filling layer at 1-1000 sccm at the high temperature of 1000-1550 ℃ and is deposited on the surface of the u-GaN layer or the dislocation filling layer to form the SiC inserting layer. In order to deposit the SiC insertion layer on the surface of the u-GaN layer or dislocation fill layer more preferably, the flow rate of the carbon source gas is 100 to 200sccm. The flow rate of the carbon source gas may be, for example, 100sccm, 110sccm, 120sccm, 130sccm, 140sccm, 150sccm, 160sccm, 170sccm, 180sccm, 190sccm, or 200sccm, or may be other flow rate values not shown in 100 to 200sccm.

Preferably, the flow rate of the carrier gas used for depositing the SiC insert layer is 10-500 standard liters slm per minute. Illustratively, the flow rate of the gaseous carrier gas used to deposit the SiC insertion layer may be 10slm, 50slm, 100slm, 150slm, 200slm, 250slm, 300slm, 350slm, 400slm, 450slm or 500slm, and may also be other flow rate values not shown in 10-500 slm.

The gas carrier is preferably H ₂, and the flow rate of the gas carrier is preferably 50 to 100slm. Illustratively, the gas carrier gas flow rate may be 50slm, 55slm, 60slm, 65slm, 70slm, 75slm, 80slm, 85slm, 90slm, 95slm or 100slm, but may also be other flow rate values not shown in 50-100 slm.

The flow rate of the gas carrier can be adjusted in a small range, for example between 75 and 80slm, while ensuring the deposition effect. The silicon source gas and the carbon source gas can flow on the surface of the u-GaN layer or the dislocation filling layer by using the gas carrier, and are deposited.

The deposition pressure of the SiC insert layer is 100-700 torr. Illustratively, the deposition pressure of the SiC insert layer may be 100torr, 200torr, 300torr, 400torr, 500torr, 600torr, or 700torr, and may be other deposition pressures not shown in the range of 100to 700 torr.

Preferably, the deposition pressure of the SiC insert layer is 400-600 torr. Illustratively, the deposition thickness of the SiC insert layer may be 400torr, 420torr, 450torr, 470torr, 500torr, 530torr, 550torr, 580torr, or 600torr. The SiC insert layer formed by using 100-700 torr deposition pressure ensures the concentration of SiC molecules and improves the stability of the SiC insert layer and the strength of the SiC insert layer.

The deposition of the SiC insertion layer can be carried out under the condition of vacuum high temperature, the silicon source gas and the carbon source gas are led into the reaction box, the silicon source gas and the carbon source gas are deposited on the surface of the u-GaN layer or the dislocation filling layer at a certain flow rate, the concentration of SiC molecules is increased by the deposition pressure, gaps among the molecules can be reduced, the SiC insertion layer is prevented from warping, and the foundation is laid for the subsequent process.

The SiC insertion layer has a deposition thickness of 10 to 1000A in meter, and the deposition thickness of the SiC insertion layer may be 10A, 100A, 200A, 300A, 400A, 500A, 600A, 700A, 800A, 900A, or 1000A, or may be other deposition thicknesses not shown in 10 to 1000A, for example.

Preferably, the deposition thickness of the SiC insertion layer is 100-200A. Illustratively, the deposition thickness of the SiC insertion layer may be 100A, 110A, 120A, 130A, 140A, 150A, 160A, 170A, 180A, 190A, or 200A, and may be other deposition thicknesses not shown in 10 to 1000A.

The dislocation filling layer is a superlattice layer composed of at least one of GaN, aluminum nitride AlN, indium nitride InN, indium nitride gallium InGaN, aluminum nitride gallium AlGaN and aluminum nitride indium gallium InAlGaN, and preferably, the dislocation filling layer is GaN.

The dislocation fill-in layer is an unintentionally doped layer or a Si doped N-type layer. And the thickness of the dislocation filling layer is 0.5-1 um.

Specifically, the unintentionally doped layer is unintentionally doped with GaN, and the thickness of the unintentionally doped GaN is 0.1-2 micrometers um. The unintentionally doped GaN thickness may be, for example, 0.1um, 0.5um, 1um, 1.5um or 2um, but may also be other thicknesses not shown in 0.1-2 um. Preferably, the unintentionally doped GaN thickness is 0.5-1 um.

The Si doped N-type layer is Si doped GaN, and the thickness of the Si doped GaN is 0.1-2 um. The Si doped GaN thickness may be, for example, 0.1um, 0.5um, 1um, 1.5um or 2um, but may also be other thicknesses not shown in 0.1-2 um. Preferably, the Si doped N-type layer has a thickness of 0.5-1 um.

The use of dislocation fill layers can create high quality GaN layers with low defect densities.

In this example, siC is a C and Si stable compound in the iv main group, whose lattice structure consists of two sub-lattices densely arranged, C atoms and Si atoms being connected in a covalent bond, each Si (or C) atom being bonded to a surrounding C (Si) atom by oriented strong tetrahedral sp3 bonds, and the formation energy of the stacking fault is low although the tetrahedral bonds of SiC are strong. Because of the different stacking sequences of Si-C diatomic layers, siC has various crystal structures, and common polytypes are cubic close-packed 3C-SiC and hexagonal close-packed 4H-SiC and 6H-SiC. Different polytypes have different electrical and optical properties.

Among various crystal types of SiC, 3C-SiC has the lowest bond energy, the highest lattice free energy and easy nucleation, but 3C-SiC is in a metastable state and has the characteristics of lower stability and easy occurrence of solid phase transfer. Under the condition that the 3C-SiC is close to an equilibrium state, when the annealing temperature is respectively 1000 ℃ and 1100 ℃, the 3C-SiC can undergo phase transition and is partially converted into 6H-SiC and 4H-SiC. The order of bond energy of the formed 3 crystal forms is 3C-SiC <6H-SiC <4H-SiC, the smaller the bond energy is, the more unstable the bond energy is, and the more easily the phase change occurs under the influence of external conditions. Thus, by changing external conditions such as temperature, gas flow rate, deposition pressure, etc., 3C-SiC can undergo phase transition to other crystal forms.

In this embodiment, the addition of the SiC insertion layer allows the full width at half maximum of the GaN peak to be reduced compared to the full width at half maximum without the SiC insertion layer or with a general insertion layer. This is because the introduction of SiC effectively relieves lattice mismatch and thermal mismatch of GaN and Al ₂O₃, and the SiC insertion layer improves the crystalline quality of GaN, and because the thermal conductivity of SiC is much higher than that of GaN and Al ₂O₃, the lattice mismatch of SiC with GaN and Al ₂O₃ is further reduced.

Specifically, the growth mechanism of the u-GaN layer is mainly island growth. Triangles as shown in fig. 2, i.e. islands with slightly different crystal directions are inter-polymerized by diffusion. When stress is concentrated in a vacancy place formed at the coalescence of the islands, defects such as dislocation and the like are easily generated, and when an epitaxial u-GaN layer is heteroepitaxially grown, internal stress is generated due to lattice mismatch, so that defects such as dislocation and the like are generated, and the crystal quality of the u-GaN layer is reduced.

This embodiment addresses this situation by using SiC insertion layers and dislocation fill layers to reduce defects caused by lattice mismatch between Al ₂O₃ and u-GaN. It can be appreciated that the SiC insertion layer fills defects during deposition, thereby effectively relieving lattice mismatch, reducing internal stress, and reducing dislocation density.

In addition, as mentioned in the foregoing, u-GaN grown on Al ₂O₃ may produce lattice mismatch, forming defects of varying sizes, and when larger defects are encountered, a fault may not be able to complete the interruption of the defect if dislocation is grown once on the u-GaN. For this, dislocation-interrupting layers may be grown on the u-GaN layer in cycles to interrupt the extension of defects. When the problem of defect extension cannot be solved by the dislocation interruption layer twice, the dislocation interruption layer can be continuously grown for more times, and the description is omitted here. Therefore, the embodiment solves the problem of defect extension by utilizing the advantage of small lattice mismatch between the SiC insert layer and the dislocation middle fault, and improves the luminous efficiency of the LED.

In addition, since SiC has a price between Al ₂O₃ and GaN, if SiC is used only as a dislocation breaking layer, growing an SiC insertion layer on the u-GaN layer increases production costs. In this regard, in this embodiment, the dislocation interrupt layer composed of the SiC insertion layer and the dislocation fill layer is grown on the u-GaN layer, so that the extension of lattice mismatch defects between Al ₂O₃ and u-GaN can be reduced, the electron-hole recombination efficiency and the light-emitting efficiency of the LED can be improved, and the production cost can be reduced.

In one embodiment, as shown in fig. 3, the method for growing the light emitting diode epitaxy further comprises a stress release layer, a multiple quantum well light emitting layer MQWs, an electron blocking layer EBL, a p-GaN layer and a metal contact layer PP which are sequentially grown on the n-GaN layer.

Wherein the n-GaN layer is Si doped GaN, and the thickness of the n-GaN layer is 1-3 um, and the thickness of the n-GaN layer can be 1um, 1.5um, 2um, 2.5um or 3um by way of example. But may also be of other thicknesses not shown in 1-3 um. The n-GaN layer can reduce impurities in a formed growth plane, is beneficial to improving the growth quality of the stress release layer, and further improves the luminous efficiency of the LED.

Specifically, the Si doped GaN concentration is 1E 18-5E 19 atomic weight per cubic centimeter atom/cm ³.

The stress release layer is of an InGaN/GaN superlattice structure. The stress release layer is grown between the n-GaN layer and the multi-quantum well luminescent layer, can reduce the stress accumulated during the growth of the multi-quantum well luminescent layer, plays a role in releasing the stress of the bottom layer, and increases the radiation recombination efficiency of electrons and holes of the multi-quantum well luminescent layer.

The multi-quantum well light-emitting layer is of an InGaN/GaN/AlGaN superlattice structure.

The electron blocking layer can prevent electrons from transiting to the metal contact layer, is favorable for the electrons and holes to perform composite electron luminescence in the multi-quantum well luminescent layer, and improves the luminous efficiency of the light-emitting diode.

The metal contact layer is a P-type ohmic contact layer, and current expansion is more uniform by ohmic contact, so that the luminous efficiency of the LED can be further improved.

Corresponding to the foregoing embodiment of the method for growing light emitting diode epitaxy, the present application further provides a light emitting diode epitaxy structure, which is applied to the foregoing method for growing light emitting diode epitaxy, as shown in fig. 3, where the LED epitaxy structure includes:

The substrate is one of an Al ₂O₃ substrate, an Al ₂O₃/SiO₂ composite substrate, a Si substrate, a BN substrate and a SiC substrate;

and sequentially stacking a u-GaN layer, a dislocation interrupt layer and an N-GaN layer which are positioned on the substrate, wherein the dislocation interrupt layer comprises a SiC insertion layer and a dislocation filling layer which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, and the N is more than or equal to 1.

In one embodiment, the LED epitaxial structure further comprises a stress release layer, a multiple quantum well light emitting layer, an electron blocking layer, a p-GaN layer and a metal contact layer which are sequentially grown on the n-GaN layer.

The foregoing examples merely illustrate specific embodiments of the invention, which are described in greater detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention.

Claims (10)

1. A method for epitaxial growth of a light emitting diode, the method comprising:

Providing a layer of substrate, wherein the substrate is one of an Al ₂O₃ substrate, an Al ₂O₃/SiO₂ composite substrate, a Si substrate, a BN substrate and a SiC substrate;

Sequentially depositing and growing a u-GaN layer, a dislocation middle fault and an N-GaN layer on the substrate, wherein the dislocation middle fault comprises a SiC inserting layer and a dislocation filling layer which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, and the N is more than or equal to 1; wherein,

The temperature used for depositing the SiC insert layer is 1000-1550 ℃;

The gases used for depositing the SiC insert layer are silicon source gas and carbon source gas, the flow rate of the silicon source gas is 1-1000 sccm, and the flow rate of the carbon source gas is 1-1000 sccm;

The flow rate of the gas carrier gas used for depositing the SiC insert layer is 10-500 slm;

The deposition pressure of the SiC insert layer is 100-700 torr;

The deposition thickness of the SiC insert layer is 10-1000A;

the dislocation filling layer has a thickness of 0.1-2 um.

2. A method of epitaxial growth of a light emitting diode according to claim 1, wherein the SiC insertion layer is deposited at a temperature of 1000 to 1200 degrees.

3. The method of claim 1, wherein the silicon source gas is SiH ₄; the flow rate of the silicon source gas is 100-200 sccm.

4. The method for epitaxial growth of light emitting diode according to claim 1, wherein the carbon source gas is any one or a combination of several of CH ₄、C₂H₄、C₂H₆ and C ₃H₈; the flow rate of the carbon source gas is 100-200 sccm.

5. The method of claim 1, wherein the gaseous carrier gas is H ₂; the flow rate of the gas carrier gas is 50-100 slm.

6. The method for epitaxial growth of light emitting diode according to claim 1, wherein the deposition pressure of the SiC insertion layer is 400-600 torr; the deposition thickness of the SiC insert layer is 100-200A.

7. The method of claim 1, wherein the dislocation fill-in layer is a superlattice layer comprising at least one of GaN, alN, inN, inGaN, alGaN and InAlGaN; the dislocation filling layer is an unintentional doped layer or a Si doped N-type layer; the dislocation filling layer has a thickness of 0.5-1 um.

8. The method for epitaxial growth of a light emitting diode according to any one of claims 1 to 7, further comprising: a stress release layer, a multiple quantum well light-emitting layer, an electron blocking layer, a p-GaN layer and a metal contact layer which are sequentially grown on the n-GaN layer; wherein,

The n-GaN layer is Si doped GaN, the thickness is 1-3 um, and the concentration is 1E 18-5E 19atoms/cm ³;

the stress release layer is of an InGaN/GaN superlattice structure;

The multi-quantum well light-emitting layer is of an InGaN/GaN/AlGaN superlattice structure.

9. A light emitting diode epitaxial structure, characterized in that it is applied to the method for growing light emitting diode epitaxy according to any one of claims 1 to 8, comprising:

The substrate is one of an Al ₂O₃ substrate, an Al ₂O₃/SiO₂ composite substrate, a Si substrate, a BN substrate and a SiC substrate;

and sequentially stacking a u-GaN layer, a dislocation interrupt layer and an N-GaN layer which are positioned on the substrate, wherein the dislocation interrupt layer comprises a SiC insertion layer and a dislocation filling layer which are circularly grown on the u-GaN layer, the number of times of the circular growth is N, and the N is more than or equal to 1.

10. The light emitting diode epitaxial structure of claim 9, further comprising:

And a stress release layer, a multiple quantum well light-emitting layer, an electron blocking layer, a p-GaN layer and a metal contact layer which are sequentially grown on the n-GaN layer.