CN118199642A

CN118199642A - Analog-to-digital converter and semiconductor device having the same

Info

Publication number: CN118199642A
Application number: CN202311680612.5A
Authority: CN
Inventors: 黄元俊; 徐秉俊; 李柱炫
Original assignee: LX Semicon Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2022-12-13
Filing date: 2023-12-08
Publication date: 2024-06-14

Abstract

The present disclosure relates to an analog-to-digital converter that reduces power consumption by reducing an operation current, and a semiconductor device having the same. The analog-to-digital converter includes: a capacitor-resistor (C-R) hybrid digital-to-analog converter (DAC) circuit, the C-R hybrid DAC circuit comprising a capacitor digital-to-analog converter (CDAC) circuit and a resistor digital-to-analog converter (RDAC) circuit, the CDAC circuit comprising a capacitor array, the RDAC circuit comprising a resistor string; a comparator that compares an output voltage of the C-R hybrid DAC circuit with a common mode voltage and outputs a comparison result; and a control logic circuit controlling a switching operation of the C-R hybrid DAC circuit and a comparison operation of the comparator using a driving clock having a duty ratio greater than a duty ratio of the first clock based on the system clock, and determining each bit of the digital data by receiving a comparison result of the comparator.

Description

Analog-to-digital converter and semiconductor device having the same

Technical Field

The present disclosure relates to an analog-to-digital converter that can reduce power consumption by reducing an operation current, and a semiconductor device having the same.

Background

The electronic device includes an analog-to-digital converter (ADC) that converts an analog signal into digital data as a basic component.

For example, an ADC may be built into a microcontroller unit (MCU) and convert analog signals to digital data. The ADC may convert analog signals sensed via the sensor into digital data for digital signal processing.

Among analog-to-digital conversion schemes, a Successive Approximation Register (SAR) ADC is mainly used, which quantizes the voltage of an analog signal using a binary search scheme.

As resolution increases, SAR ADCs may have a capacitor-resistor (C-R) hybrid digital-to-analog converter (DAC) structure that includes a capacitor array and a resistor string.

SAR ADCs that include C-R hybrid DAC structures require a method to reduce operating current to reduce power consumption.

In one example, the types of ADCs include pipelined ADCs, algorithmic ADCs, and the like, in addition to the Successive Approximation Registers (SAR) described above.

SAR is mainly described herein, but the technical concepts of the present disclosure are applicable to various ADC technologies.

Disclosure of Invention

The present disclosure provides an analog-to-digital converter and a semiconductor device having the same, which can reduce power consumption by reducing an operation current.

An analog-to-digital converter according to an embodiment of the present disclosure includes: a capacitor-resistor (hereinafter, referred to as a C-R) hybrid digital-to-analog converter (hereinafter, referred to as a DAC) circuit including a capacitor digital-to-analog converter (CDAC) circuit including a capacitor array and a resistor digital-to-analog converter (RDAC) circuit including a resistor string; a comparator that compares an output voltage of the C-R hybrid DAC circuit with a common mode voltage and outputs a comparison result; and a control logic circuit controlling a switching operation of the C-R hybrid DAC circuit and a comparison operation of the comparator using a driving clock having a duty ratio greater than a duty ratio of the first clock based on the system clock, and determining each bit of the digital data by receiving a comparison result of the comparator.

An analog-to-digital converter according to an embodiment of the present disclosure includes: a capacitor-resistor (hereinafter, referred to as a C-R) hybrid digital-to-analog converter (hereinafter, referred to as a DAC) circuit including a capacitor digital-to-analog converter (CDAC) circuit including a capacitor array and a resistor digital-to-analog converter (RDAC) circuit including a resistor string; a comparator that compares an output voltage of the C-R hybrid DAC circuit with a common mode voltage and outputs a comparison result; and a successive approximation register (hereinafter, referred to as SAR) control logic circuit that controls a switching operation of the C-R hybrid DAC circuit and a comparison operation of the comparator using the driving clock and determines each bit of the digital data by receiving a comparison result of the comparator, and in each period of the driving clock, a voltage stabilization period after changing the switching of the C-R hybrid DAC circuit is ensured to be longer than a comparison operation period of the comparator and a bit determination period of the control logic circuit.

A semiconductor device according to one embodiment of the present disclosure includes an analog-to-digital converter.

A SAR ADC according to one embodiment of the present disclosure may use a driving clock having a duty ratio greater than that of the first clock in a conversion stage to ensure a voltage stabilization period after changing the switching of the C-R hybrid DAC circuit in each period of the driving clock, thereby reducing power consumption by suppressing an increase in current of the RDAC circuit.

The SAR ADC according to one embodiment of the present disclosure can ensure that a voltage stabilization period after a switching change of the C-R hybrid DAC circuit is much longer than a comparison operation period of the comparator and a bit determination period of the SAR control logic circuit during a conversion phase, thereby reducing power consumption by suppressing a current increase of the RDAC circuit for voltage stabilization.

Accordingly, the semiconductor device using the SAR ADC according to one embodiment of the present disclosure may reduce power consumption.

Drawings

Fig. 1 is a block diagram schematically illustrating a SAR ADC according to one embodiment of the present disclosure.

Fig. 2 is a circuit diagram specifically illustrating a SAR ADC according to one embodiment of the present disclosure.

Fig. 3 is an operational timing diagram of a SAR ADC according to one embodiment of the present disclosure.

Fig. 4 is an operational timing diagram of a SAR ADC according to one embodiment of the present disclosure.

Fig. 5 is a circuit diagram specifically illustrating a SAR ADC according to one embodiment of the present disclosure.

Fig. 6 is an operational timing diagram of a SAR ADC according to one embodiment of the present disclosure.

Fig. 7 is an operational timing diagram of a SAR ADC according to one embodiment of the present disclosure.

Fig. 8 is a block diagram illustrating a semiconductor device including an ADC according to one embodiment of the disclosure.

Fig. 9 is a block diagram showing a configuration of a camera module including an ADC according to one embodiment of the present disclosure.

Detailed Description

Like reference numerals refer to substantially identical components throughout this document. In the following description, when not related to the core composition of the present disclosure, detailed descriptions of compositions and functions known in the technical field of the present disclosure may be omitted. The meaning of the terms described herein should be understood as follows.

Advantages and features of the present disclosure and methods of accomplishing the same may become apparent with reference to the accompanying drawings and the embodiments described in detail below. However, the present disclosure is not to be limited to the embodiments disclosed below, and is to be implemented in various different forms. This embodiment merely ensures that the disclosure of the present disclosure is complete and is provided to fully convey the scope of the disclosure to those skilled in the art of the disclosure. The present disclosure is limited only by the scope of the claims.

Like reference numerals refer to like components throughout. In addition, in describing the present disclosure, when it is determined that detailed descriptions of related known techniques may unnecessarily obscure the gist of the present disclosure, the detailed descriptions will be omitted.

When the terms "comprising," "having," "consisting of," and the like are used herein, other components may be added unless the term "only" is used. When an element is expressed in the singular, the plural is contemplated unless specifically stated to the contrary.

In the description of a temporal relationship (e.g., a temporal precedent relationship between two events) such as "after", "subsequent", "preceding", etc., unless "immediate" or "direct" is indicated, another event may occur between them.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one element from another element. Accordingly, within the technical idea of the present disclosure, the first component mentioned below may be the second component.

The term "at least one" should be understood to include all possible combinations presented from one or more of the associated items. For example, "at least one of the first, second, and third items" may mean a combination of all items that may be presented from two or more of the first, second, and third items, and each of the first, second, or third items.

The respective features of the various embodiments of the present disclosure may be partially or fully coupled or combined with each other, and various technical interconnections and operations may be made. The embodiments may be implemented independently or together in a related relationship.

Hereinafter, preferred embodiments of the present disclosure will be described with reference to the accompanying drawings.

Referring to fig. 1, a SAR ADC 100 according to one embodiment may include a capacitor-resistor (hereinafter, referred to as C-R) hybrid digital-to-analog converter (hereinafter, referred to as DAC) circuit 110, a comparator 120, a Successive Approximation Register (SAR) control logic circuit 130, and a clock converter 150 or 150A. The SAR ADC 100 may receive an input voltage VIN, convert the input voltage VIN into digital data Dout, and output the digital data Dout.

The C-R hybrid DAC circuit 110 may include: a capacitor DAC (hereinafter, referred to as CDAC) circuit including a capacitor array and a switch array; and a resistor DAC (hereinafter RDAC) circuit comprising a resistor string and a switch array. In the C-R hybrid DAC circuit 110, the CDAC circuit may be used to determine the high order bits, and the RDAC circuit may be used to determine the low order bits together with the unit capacitor 1C of the CDAC circuit.

The C-R hybrid DAC circuit 110 may charge the capacitor array with charges based on the input voltage VIN, then discharge the charges charged in the capacitor array in response to the switch control based on the binary search of the SAR control logic circuit 130 to generate an output voltage, and then output the output voltage to the comparator 120.

The comparator 120 may compare an output voltage of the C-R hybrid DAC circuit 110 supplied to the first input (+) terminal with a common mode voltage supplied to the second input (-) terminal, and output an output bit COMPout to the SAR control logic circuit 130 based on the comparison result.

The SAR control logic 130 may use a binary search method to control the switching operation of the C-R hybrid DAC circuit 110. The SAR control logic 130 may receive the output bits COMPout from the comparator 120, sequentially determine the Most Significant Bit (MSB) to the Least Significant Bit (LSB), and output the digital data Dout.

The SAR ADC 100 according to one embodiment may operate in a sampling phase and a conversion phase to convert the input voltage VIN into digital data Dout. The conversion phase may be denoted as a comparison phase.

SAR control logic 130 can control C-R hybrid DAC circuit 110 and comparator 120 to operate in a sampling phase and a conversion phase.

During the sampling phase, the C-R hybrid DAC circuit 110 may sample the input voltage VIN and store the sampled input voltage VIN in the capacitor array.

In the conversion phase, the SAR control logic 130 may sequentially determine MSBs to LSBs in units of bits using a comparison result (COMPout) of the comparator 120, and the comparator 120 compares an output voltage varying in response to a switching operation of the C-R hybrid DAC circuit 110 with a common mode voltage.

The SAR control logic circuit 130 according to one embodiment may receive the first clock CLK1 and the second clock CLK2 of different phases from the clock converter 150 or 150A and generate a driving clock that controls the operation of the ADC. The SAR control logic 130 may use the first clock CLK1 and the second clock CLK2 to generate a driving clock having a duty cycle greater than that of the first clock CLK 1. The pulse width of the high logic period of the driving clock may be greater than the pulse width of the low logic period.

The SAR control logic 130 may change the switching of the C-R hybrid DAC circuit 110 at the rising time of the driving clock, and may control the comparator 120 to start the comparison operation at the falling time of the driving clock. In particular, since the pulse width of the high logic period of the driving clock is larger than that of the low logic period, a voltage stabilization period can be ensured after changing the switching of the C-R hybrid DAC circuit 110. Accordingly, the SAR ADC 100 can suppress an increase in current of the C-R hybrid DAC circuit 110 to ensure a voltage stabilization period after switching, thereby reducing power consumption.

The SAR control logic 130 according to one embodiment may use drive clocks with different duty cycles in the sampling phase and the transition phase. For example, the SAR control logic 130 may use the first clock CLK1 as a driving clock in the sampling phase, and may use a driving clock having a duty cycle greater than that of the first clock in the transition phase.

The SAR control logic 130 according to one embodiment may use a driving clock having the same duty cycle (that is, a driving clock having a duty cycle greater than that of the first clock CLK 1) in the sampling phase and the transition phase.

The clock converter 150 or 150A according to one embodiment may receive the system clock SCLK or the first clock CLK1 and output the first clock CLK1 and the second clock CLK2 to the SAR control logic circuit 130. The clock converter 150 or 150A may be built into the SAR control logic 130.

When receiving the system clock SCLK having a higher frequency than the driving clock, the clock converter 150 according to one embodiment may generate the first clock CLK1 by dividing the system clock SCLK and phase-shift the first clock CLK1 to output the second clock CLK2.

When receiving the system clock SCLK having the same frequency as the driving clock, the clock converter 150A according to one embodiment may output the system clock SCLK as the first clock CLK1 and phase-shift the first clock CLK1 to output the second clock CLK2.

Fig. 2 is a circuit diagram specifically showing a SAR ADC according to one embodiment of the present disclosure, and each of fig. 3 and 4 is an operation timing diagram of the SAR ADC according to one embodiment of the present disclosure shown in fig. 2.

Referring to fig. 2, the SAR ADC 100 according to one embodiment may include a C-R hybrid DAC circuit 110, a comparator 120, SAR control logic 130, and a clock converter 150.

The C-R hybrid DAC circuit 110 according to one embodiment may include a CDAC circuit 114 and an RDAC circuit 112, the CDAC circuit 114 including a capacitor array for determining the high order bits, and the RDAC circuit 112 including a resistor string for determining the low order bits. The CDAC circuit 114 may be used to determine the high n bits (n is an integer equal to or greater than 2) and the RDAC circuit 112 may be used to determine the low m bits (m is an integer equal to or greater than 2).

RDAC circuit 112 may receive the bias current from current generator 20 and generate a plurality of reference voltages VREFP through VREFN and a common mode voltage VCM having different voltage levels.

Current generator 20 may include an operational amplifier 142 and an output transistor 144 and may generate and output a bias current proportional to an input reference voltage VREF to RDAC circuit 112.

The operational amplifier 142 may receive an input reference voltage VREF from a reference voltage generator at a first input (+) terminal and a feedback voltage VFB supplied from the RDAC circuit 112 at a second input (-) terminal. The operational amplifier 142 may generate the control voltage such that the feedback voltage VFB fed back from the RDAC circuit 112 remains equal to the reference voltage VREF.

The output transistor 144 may generate a bias current (which is a constant current) in response to the control voltage output from the operational amplifier 142 and output the bias current to the RDAC circuit 112.

The RDAC circuit 112 may include a resistor string 112R and a switch array 112S, and the switch array 112S may include a plurality of switches S4 connected to a plurality of voltage divider nodes of the resistor string 112R, respectively.

The resistor string 112R may include a plurality of resistors connected in series with each other between an output line of the current generator 20 and the ground GND. Resistor string 112R may use the bias current supplied from current generator 20 to generate a positive reference voltage VREFP, a negative reference voltage VERFN, a common mode voltage VCM, and a plurality of variable reference voltages.

For example, the plurality of variable reference voltages generated in the resistor string 112R may include voltages VREFP/2 ⁿ and VREFN/2 ⁿ obtained by dividing the positive reference voltage VREFP and the negative reference voltage VREFN by a ratio of powers of 2 (2 ⁿ), respectively, in a range between the positive reference voltage VREFP and the negative reference voltage VREFN.

The switch array 112S may apply the positive reference voltage VREFP, the negative reference voltage VERFN, and the common mode voltage VCM generated by the resistor string 112R to the CDAC circuit 114 in response to control by the SAR control logic circuit 130.

The switch array 112S may sequentially output a variable reference voltage in response to the control of the SAR control logic 130, and apply the variable reference voltage to the unit capacitor 1C of the CDAC circuit 114. The plurality of variable reference voltages sequentially output from the RDAC circuit 112 may be applied to the unit capacitors 1C of the CDAC circuit 114 and used to sequentially determine the low order.

The CDAC circuit 114 may include a capacitor array 114C in which capacitors 1C, 2C, … …, 2 ^n-3 C, and 2 ^n-2 C having a ratio of powers of 2 are connected in parallel with each other, and a switch array 114S including switches S0, S1, S2, and S3 connected to a bottom plate of the capacitor array 114C. The top plate of the capacitor array 114C may be connected to a first input (+) terminal of the comparator 120 via a first node a and may be connected with a common switch vcm_sw that applies a common mode voltage VCM.

Each of the capacitors 1C, 2C, … …,2 ^n-3 C, and 2 ^n-2 C may receive the input voltage VIN via the sampling switch S0, and may receive the positive reference voltage VREFP via the switch S2, or may receive the negative reference voltage VREFN via the switch S3. One of the two unit capacitors 1C and 1C may receive the common mode voltage VCM via the switch S1.

The capacitors 2C, … …,2 ^n-3 C, and 2 ^n-2 C may have an equally divided capacitor (EDC: equally dividing capacitor) structure.

For example, a 16C (=2 ⁴ C) capacitor may include a pair of 8C (=2 ³ C) aliquoting capacitors. When the positive reference voltage VREFP and the negative reference voltage VREFN are respectively applied to the pair of 8C aliquoting capacitors, a 16C capacitor to which the common mode voltage VCM is applied can be realized. Depending on the comparison result (COMPout =1 or 0) of the comparator 120, the 8C aliquoting capacitor pair can realize a 16C capacitor to which the positive reference voltage VREFP or the negative reference voltage VREFN is applied. Each 8C aliquoting capacitor can receive the input voltage VIN via the sampling switch S0 and can selectively receive the positive reference voltage VREFP and the negative reference voltage VREFN via the switches S2 and S3.

The C-R hybrid DAC circuit 110 may allow the switch arrays 112S and 114S to perform switching operations under the control of the SAR control logic 130 and generate an output voltage VDAC-VIN at the first node a.

The comparator 120 may repeat the operation of comparing the output voltage VDAC-VIN generated at the first node a of the C-R hybrid DAC circuit 110 with the common mode voltage VCM applied to the second node B and output the output bits (COMPout =0, 1) to the SAR control logic circuit 130.

The SAR control logic 130 may control the operation of the C-R hybrid DAC circuit 110 and the comparator 120 in the sampling phase and the conversion phase based on the driving clock adc_clk shown in fig. 3. During the conversion phase, SAR control logic 130 may receive output bits COMPout from comparator 120, then determine the code in bits, and then output digital data Dout.

The SAR control logic 130 may receive the first clock CLK1 and the second clock CLK2 of different phases from the clock converter 150, and generate a driving clock adc_clk having a duty ratio greater than that of the first clock CLK1, and control ADC operation using the driving clock adc_clk. The driving clock adc_clk may have the same frequency as the first clock CLK1 and be synchronized with the first clock CLK1 in a rising time.

The clock converter 150 may receive the system clock SCLK and output the first clock CLK1 and the second clock CLK2 to the SAR control logic circuit 130, or may be built into the SAR control logic circuit 130. The clock converter 150 may include a clock divider circuit 152 and a phase shift circuit 154.

The clock converter 150 may receive a system clock SCLK having a higher frequency than the first clock CLK1, may generate the first clock CLK1 by dividing the system clock SCLK in the clock dividing circuit 152, and phase-shift the first clock CLK1 in the phase shift circuit 154 to output the second clock CLK2.

For example, as shown in fig. 3, the clock converter 150 may generate the first clock CLK1 by receiving the system clock SCLK having twice the frequency of the first clock CLK1 and dividing the system clock by 2, and may generate the second clock CLK2 by phase-shifting the first clock CLK1 by 90 degrees. The first clock CLK1 and the second clock CLK2 may have a phase difference of 90 degrees.

In contrast, the clock converter 150 may generate the first clock CLK1 by receiving the system clock SCLK having a frequency 4 times the first clock CLK1 and dividing the system clock by 4, and may generate the second clock CLK2 by phase shifting the first clock CLK1 by 45 degrees. The first clock CLK1 and the second clock CLK2 may have a phase difference of 45 degrees.

The SAR control logic circuit 130 may generate the driving clock adc_clk having a duty ratio greater than the first clock CLK1 by logically combining the first clock CLK1 and the second clock CLK2 with each other. The duty cycle of the driving clock adc_clk may be greater than 50% and less than 100% of the duty cycle. For example, the first clock CLK1 may have a duty ratio of 50%, and the driving clock adc_clk may have a duty ratio of 75%.

The high logic period t1 of the driving clock adc_clk may be greater than the low logic period t 2. The period of the high logic period t1 of the driving clock adc_clk may be greater than the high logic period of the first clock CLK1 by the phase difference Δθ between the first clock CLK1 and the second clock CLK2.

Referring to fig. 3, during a sampling phase, the SAR control logic 130 may control the C-R hybrid DAC circuit 110 to sample the input voltage VIN and charge the capacitor array with the input voltage during a plurality of periods of the driving clock adc_clk.

In the conversion stage, the SAR control logic 130 can control the switching operation of the C-R hybrid DAC circuit 110 and the comparison operation of the comparator 120 for each period 1T of the driving clock adc_clk.

In the conversion stage, the SAR control logic 130 may change the switch of the C-R hybrid DAC circuit 110 at the rising time of the driving clock adc_clk, and the comparator 120 may be controlled to start the comparison operation of the first node a and the second node B at the falling time of the driving clock adc_clk.

In particular, in the conversion stage, since the high logic period t1 is larger than the low logic period t2, the driving clock adc_clk can ensure a voltage stabilization period after changing the switch of the C-R hybrid DAC circuit 110. In other words, after the switching of the C-R hybrid DAC circuit 110 is changed in each period of the driving clock adc_clk by the driving clock adc_clk, it is possible to ensure that the voltage stabilizing period t1 is much longer than the comparison operation period of the comparator 120 and the bit determining period t2 of the SAR control logic circuit 130.

Thus, the SAR ADC according to one embodiment may suppress the current increase of the RDAC 112, thereby reducing power consumption, as compared to the case where the current of the RDAC 112 increases for voltage stabilization in the C-R hybrid DAC circuit 110.

The SAR control logic 130 may use the driving clocks adc_clk having different duty cycles or the same duty cycle in the sampling phase and the conversion phase.

Referring to fig. 3, the SAR control logic 130 according to one embodiment may use the first clock CLK1 as the driving clock adc_clk in the sampling phase, and may use the driving clock adc_clk having a duty cycle greater than that of the first clock CLK1 in the conversion phase.

Referring to fig. 4, the SAR control logic 130 according to one embodiment may use the driving clock adc_clk having the same duty ratio (that is, the driving clock adc_clk having a duty ratio greater than that of the first clock CLK 1) in the sampling phase and the conversion phase.

Fig. 5 is a circuit diagram specifically showing a SAR ADC according to an embodiment of the present disclosure, and each of fig. 6 and 7 is an operation timing diagram of the SAR ADC according to an embodiment of the present disclosure shown in fig. 5.

Because the SAR ADC shown in fig. 5 is different from the SAR ADC shown in fig. 2 in the internal configuration of the clock converter 150A, a description of components overlapping those in fig. 2 will be omitted or briefly described.

Referring to fig. 5, the clock converter 150A according to one embodiment may receive the first clock CLK1 as the system clock SCLK and output the first clock CLK1, and phase-shift the first clock CLK1 and output the second clock CLK2. The clock converter 150A may include a phase shift circuit 154. The clock converter 150A may be built into the SAR control logic 130.

When the system clock SCLK has the same frequency as the driving clock adc_clk, the clock converter 150A may output the system clock SCLK as the first clock CLK1, and phase-shift the first clock CLK1 and output the second clock CLK2 in the phase-shift circuit 154.

The SAR control logic 130 may receive the first clock CLK1 and the second clock CLK2 having different phases from the clock converter 150A, and logically combine the first clock CLK1 and the second clock CLK2 with each other to generate the driving clock adc_clk having a duty ratio greater than that of the first clock CLK 1. The high logic period t1 of the driving clock adc_clk may be greater than the low logic period t 2.

Referring to fig. 6, during a sampling phase, the SAR control logic 130 may control the C-R hybrid DAC circuit 110 to sample the input voltage VIN and charge the capacitor array with the input voltage during a plurality of periods of the driving clock adc_clk.

In the conversion stage, the SAR control logic 130 may change the switch of the C-R hybrid DAC circuit 110 at the rising time of the driving clock adc_clk for each period 1T of the driving clock adc_clk, and may control the comparator 120 to start the comparison operation of the first node a and the second node B at the falling time of the driving clock adc_clk.

In particular, in the conversion stage, the high logic period t1 of the driving clock adc_clk is larger than the low logic period t2, so that a voltage stabilization period can be ensured after changing the switch of the C-R hybrid DAC circuit 110 for each period of the driving clock adc_clk. In other words, in each period of the driving clock adc_clk, it can be ensured that the voltage stabilization period t1 after the switching change of the C-R hybrid DAC circuit 110 is longer than the comparison operation period of the comparator 120 and the bit determination period t2 of the SAR control logic circuit 130.

Referring to fig. 6, the SAR control logic 130 according to one embodiment may use the first clock CLK1 as the driving clock adc_clk in the sampling phase, and may use the driving clock adc_clk having a duty ratio greater than that of the first clock CLK1 in the conversion phase.

Referring to fig. 7, the SAR control logic 130 according to one embodiment may use the driving clock adc_clk having the same duty ratio (that is, the driving clock adc_clk having a duty ratio greater than that of the first clock CLK 1) in the sampling phase and the conversion phase.

Referring to fig. 8, in one embodiment, a semiconductor device 1000 may include an ADC 1100 according to one embodiment to convert an input analog signal into digital data and use the digital data.

For example, the semiconductor device 1000 may be one of various semiconductor devices such as a microcontroller unit (MCU), a processor, a Power Management Integrated Circuit (PMIC), a memory, and the like included in a device such as a computer, a smart phone, a tablet computer, and the like.

According to one embodiment, one of the SAR ADCs described in fig. 1-7 may be applied to ADC 1100. Accordingly, the ADC 1100 can secure a voltage stabilization period in each period of a driving clock by using the SAR ADC according to one embodiment described above to suppress an increase in current for voltage stabilization, thereby reducing power consumption.

Referring to fig. 9, a camera module 2000 according to an embodiment includes an actuator module 400, an Optical Image Stabilization (OIS) control driver 200, and a gyro sensor 300.

The camera module further includes a lens module 410 and an image sensor module (not shown). The lens module 410 may be coupled to the actuator module 400 and may be moved by driving the actuator module 400.

The lens module 410 may include a plurality of lenses, and may collect incident light and irradiate the light to a sensor surface of the image sensor. The image sensor module may divide incident light reflected from an object and collected via the lens module into R/G/B colors (red, green, and blue), and sense an optical signal of each color incident from each pixel and convert the signal into an electrical signal to sense an image.

The actuator module 400 may include a plurality of X-axis actuators ACT 432 and 434 and Y-axis actuators ACT 436 and 438, which are driven (moved) in response to actuator driving signals supplied from the OIS control driver 200 and move the lens module 410 in the X-axis direction and the Y-axis direction, respectively. The plurality of actuators 432, 434, 436, and 438 may be driven by individually receiving a plurality of actuator driving signals from the OIS control driver 200. The X-axis direction and the Y-axis direction may be defined as a first direction and a second direction among horizontal directions perpendicular to the optical axis (Z-axis) direction of the lens module 410.

The plurality of actuators 432, 434, 436, and 438 may move the lens module 410 by generating electromagnetic force between the coil and the magnet. The plurality of actuator drive signals may be current signals applied to coils of the plurality of actuators 432, 434, 436, and 438. The plurality of actuators 432, 434, 436, and 438 may be one of various types of actuators such as a Voice Coil Motor (VCM) type, a Shape Memory Alloy (SMA) type, and a ball type.

The plurality of actuators 432, 434, 436, and 438 may perform OIS functions that eliminate angle changes of the camera module caused by hand tremors by moving the lens module 410 under the control of the OIS control driver 200. OIS function may be expressed as a hand tremor prevention function, an image stabilization function, or a motion compensation function.

The actuator module 400 may include a plurality of hall sensors 422, 424, 426, and 428 that sense the position of a plurality of actuators 432, 434, 436, and 438, respectively. The plurality of hall sensors 422, 424, 426 and 428 may individually sense positions of the plurality of actuators 432, 434, 436 and 438 moving in the X-axis direction and the Y-axis direction, respectively, and output the plurality of sensed position signals to the OIS control driver 200. For example, hall sensors 422, 424, 426, and 428 may sense the magnetic field strength of the magnet caused by movement of actuators 432, 434, 436, and 438 to sense the position of actuators 432, 434, 436, and 438. Hall sensors 422, 424, 426 and 428 may be defined as position sensors.

The gyro sensor 300 may sense an angular change of the camera module caused by hand tremor, convert the angular change into angular velocity information, and output the angular velocity information to the OIS control driver 200. The gyro sensor 300 may be defined as a motion sensor or an angular velocity sensor.

The OIS control driver 200 may compensate for hand tremors by removing angular changes of the camera module caused by hand tremors sensed via the gyro sensor 300 by moving the lens module 410 in opposite directions via driving the plurality of actuators 432, 434, 436 and 438. OIS control driver 200 may be implemented as an Integrated Circuit (IC) by integrating controller 220 and driver 250 together. The OIS control driver 200 may be defined as a stable controller, OIS controller, or OIS driver.

OIS control driver 200 may include Analog Front End (AFE) circuits 260 and 210, controller 220, and driver 250.

The Analog Front End (AFE) circuits 260 and 210 may amplify the fine sensing signals output from the plurality of hall sensors 422, 424, 426 and 428, respectively, and convert the amplified sensing signals into digital sensing data and output the digital sensing data.

Analog front-end circuits 260 and 210 may include Programmable Gain Amplifier (PGA) 260 and ADC 210.

The PGA 260 may individually amplify the plurality of sensing signals output from the plurality of hall sensors 422, 424, 426 and 428. The PGA 260 may sequentially output the plurality of amplified sensing signals to the ADC 210 via a Multiplexer (MUX).

The ADC 210 may sequentially convert the sensing signals of the plurality of channels amplified via the PGA 260 into digital sensing data and output the digital sensing data to the controller 220. According to one embodiment, a SAR ADC according to one embodiment described in fig. 1-7 may be applied as ADC 210. Accordingly, the ADC 210 can suppress an increase in current for voltage stabilization by securing a voltage stabilization period in each period of a driving clock using the SAR ADC according to one embodiment described above, thereby reducing power consumption.

The controller 220 may calculate a target position value using the angular velocity information provided from the gyro sensor 300, calculate error values between the calculated target position value and the sensed data of the plurality of channels provided from the ADC 210, and generate control signals of the plurality of channels for correcting the calculated error values and output the control signals to the driver 250. The controller 220 may use a signal processor such as a Micro Controller Unit (MCU), a Central Processing Unit (CPU), or a Digital Signal Processor (DSP).

The driver 250 may individually drive the plurality of actuators 432, 434, 436, and 438 by generating actuator driving signals of a plurality of channels in response to control signals of the plurality of channels supplied from the controller 220. The actuator drive signal may be generated in the form of a constant current signal or a Pulse Width Modulation (PWM) signal. The driver 250 may correct hand tremor by driving the plurality of actuators 432, 434, 436, and 438 in response to actuator driving signals of the plurality of channels to move the lens module 410.

As described above, the SAR ADC according to one embodiment of the present disclosure may use a driving clock having a duty ratio greater than that of the first clock in the conversion stage to ensure a voltage stabilization period after changing the switching of the C-R hybrid DAC circuit in each period of the driving clock, thereby reducing power consumption by suppressing the current increase of the RDAC circuit.

Those skilled in the art to which the present disclosure pertains will appreciate that the above-described present disclosure may be implemented in other specific forms without changing the technical idea or essential characteristics thereof.

The above embodiments should therefore be understood as illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the appended patent claims, rather than the foregoing detailed description, and all changes and modifications that come within the meaning and range of equivalency of the patent claims are therefore intended to be embraced therein.

The present application claims the benefit of priority from korean patent application No.10-2022-0173353, filed on day 13 of 12 in 2022, and korean patent application No. 10-2023-018714, filed on day 7 of 9 in 2023, which are incorporated herein by reference as if fully set forth herein.

Claims

1. An analog-to-digital converter, the analog-to-digital converter comprising:

a capacitor-resistor C-R hybrid digital-to-analog converter DAC circuit, the C-R hybrid DAC circuit comprising a capacitor digital-to-analog converter, CDAC, circuit comprising a capacitor array, and a resistor digital-to-analog converter, RDAC, circuit comprising a resistor string;

a comparator configured to compare an output voltage of the C-R hybrid DAC circuit with a common mode voltage, and output a comparison result; and

A control logic circuit configured to control a switching operation of the C-R hybrid DAC circuit and a comparison operation of the comparator using a driving clock having a duty ratio greater than a duty ratio of a first clock based on a system clock, and determine each bit of digital data by receiving the comparison result of the comparator.

2. The analog-to-digital converter according to claim 1, wherein, in each period of the drive clock, a voltage stabilization period after changing the switch of the C-R hybrid DAC circuit is ensured to be longer than a comparison operation period of the comparator and a bit determination period of the control logic circuit.

3. The analog-to-digital converter of claim 1, wherein in each cycle of the drive clock, a switch of the C-R hybrid DAC circuit changes in synchronization with a rise time of the drive clock, the comparator performs the comparison operation from a fall time of the drive clock, and the control logic circuit determines the bit.

4. The analog-to-digital converter of claim 1, wherein in the drive clock, a high logic period is longer than a low logic period.

5. The analog-to-digital converter of claim 1, wherein the control logic circuit is configured to:

controlling the C-R hybrid DAC circuit to sample an input voltage in a sampling phase and charging the capacitor array with the input voltage; and

The switching operation of the C-R hybrid DAC circuit and the comparing operation of the comparator are controlled in a conversion phase.

6. The analog-to-digital converter of claim 5, wherein the control logic circuit uses the drive clock with the same duty cycle in the sampling phase and the conversion phase.

7. The analog-to-digital converter of claim 5, wherein the control logic is configured to use the drive clocks having different duty cycles in the sampling phase and the conversion phase,

Wherein the duty cycle of the drive clock in the transition phase is greater than the duty cycle in the sampling phase.

8. The analog-to-digital converter of claim 1, wherein the control logic circuit is configured to:

controlling the switching operation of the C-R hybrid DAC circuit in a sampling phase using the first clock; and

The switching operation of the C-R hybrid DAC circuit and the comparing operation of the comparator are controlled using the drive clock in a transition phase.

9. The analog-to-digital converter of claim 1, wherein the CDAC circuit comprises:

a capacitor array in which the division capacitors and the unit capacitors are connected in parallel to each other;

A first switch array configured to selectively apply an input voltage, a positive reference voltage, and a negative reference voltage to a bottom plate of the capacitor array and to selectively apply the common mode voltage to the unit capacitor in response to control of the control logic circuit; and

A common switch connected to a top plate of the capacitor array configured to generate the output voltage of the C-R hybrid DAC circuit, wherein the common switch is configured to selectively apply the common mode voltage.

10. The analog-to-digital converter of claim 1, wherein the RDAC circuit comprises:

a resistor string configured to receive a bias current from a current generator to generate a positive reference voltage, the common mode voltage, and a negative reference voltage, and to generate a plurality of variable reference voltages in a range between the positive reference voltage to the negative reference voltage; and

A second switch array configured to apply the positive reference voltage, the common mode voltage, and the negative reference voltage to the first switch array and apply the plurality of variable reference voltages to a first unit capacitor among a plurality of unit capacitors in response to control of the control logic circuit.