CN118198188A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN118198188A CN118198188A CN202410321742.8A CN202410321742A CN118198188A CN 118198188 A CN118198188 A CN 118198188A CN 202410321742 A CN202410321742 A CN 202410321742A CN 118198188 A CN118198188 A CN 118198188A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 139
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 167
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 149
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 149
- 230000000903 blocking effect Effects 0.000 claims abstract description 86
- 239000000463 material Substances 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
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- 238000000151 deposition Methods 0.000 claims description 24
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 28
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
- H01L31/1896—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates for thin-film semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/108—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the Schottky type
- H01L31/1085—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the Schottky type the devices being of the Metal-Semiconductor-Metal [MSM] Schottky barrier type
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
- H01L31/1808—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table including only Ge
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Abstract
The invention discloses a semiconductor device and a preparation method thereof, wherein the preparation method of the semiconductor device comprises the following steps: providing a first substrate; the material of the first substrate comprises silicon; forming a first buffer layer on one side of a first substrate; the first buffer layer comprises a plurality of intrinsic germanium layers and a dislocation blocking layer positioned between two adjacent intrinsic germanium layers; each dislocation blocking layer comprises a plurality of etching openings, and the etching openings of two adjacent dislocation blocking layers are arranged in a dislocation way; forming a second buffer layer on one side of the first buffer layer away from the first substrate; forming a semiconductor device layer on one side of the second buffer layer away from the first substrate; a second substrate is provided, a semiconductor device layer is bonded to one side of the second substrate, and the first substrate, the first buffer layer, and the second buffer layer are removed. The technical scheme provided by the embodiment of the invention improves the performance of the semiconductor device and reduces the manufacturing cost of the device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
With the diversification of semiconductor devices, a plurality of semiconductor material combinations are required to form the semiconductor devices, and in some scenes, an indium phosphide (InP) material is required to be used for preparing the photoelectric devices, however, the indium phosphide material is fragile, has a small wafer size, and is not suitable for directly preparing a large-size wafer.
Therefore, there is a need for forming an indium phosphide film on a silicon (Si) substrate in practice, however, lattice mismatch of silicon and indium phosphide is serious, about 8%, resulting in the generation of a large number of threading dislocations; the polarity of the indium phosphide is different from that of the silicon, and the thermal expansion coefficient is larger, so that the indium phosphide film epitaxially grown on the silicon substrate has serious domain inversion defects (anti-phase domainsdefects, APDs), a large-area high-quality indium phosphide film is difficult to obtain, a plurality of high-quality GaAs buffer layers are required to be arranged to improve the crystal quality of an epitaxial layer material in order to ensure the performance of the device, but the thickness of the GaAs buffer layer is too large, the silicon light integration is not facilitated, and the manufacturing cost is increased; in addition, the direct epitaxial GaAs buffer layer on the Si substrate still produces many defects that affect the detector performance.
Disclosure of Invention
The embodiment of the invention provides a semiconductor device and a preparation method thereof, which are used for improving the performance of the semiconductor device and reducing the manufacturing cost of the device.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
Providing a first substrate; the material of the first substrate comprises silicon;
Forming a first buffer layer on one side of the first substrate; wherein the first buffer layer comprises a plurality of intrinsic germanium layers and a dislocation blocking layer positioned between two adjacent intrinsic germanium layers; each dislocation blocking layer comprises a plurality of etching openings, and the etching openings of two adjacent dislocation blocking layers are arranged in a dislocation manner;
forming a second buffer layer on one side of the first buffer layer away from the first substrate;
Forming a semiconductor device layer on a side of the second buffer layer away from the first substrate;
and providing a second substrate, bonding the semiconductor device layer on one side of the second substrate, and removing the first substrate, the first buffer layer and the second buffer layer.
Optionally, forming a first buffer layer on one side of the first substrate includes:
Depositing a germanium material to form a first intrinsic germanium layer, wherein the first intrinsic germanium layer covers the surface of the first substrate;
forming a first layer of dislocation blocking layer on one side of the first intrinsic germanium layer away from the first substrate;
Etching the first layer of dislocation blocking layer to form an etching opening in the first layer of dislocation blocking layer;
depositing germanium material to form a second intrinsic germanium layer to fill the etched openings in the first dislocation blocking layer and to cover the first dislocation blocking layer;
Flattening the second intrinsic germanium layer, and forming a second dislocation blocking layer on one side of the second intrinsic germanium layer away from the first substrate;
etching the second layer of dislocation blocking layer, and forming an etching opening in the second layer of dislocation blocking layer; wherein the etched opening in the second layer of dislocation blocking layer and the etched opening in the first layer of dislocation blocking layer are arranged in a dislocation manner;
Depositing a germanium material to form a third intrinsic germanium layer to fill the etched openings in the second layer dislocation barrier layer and to cover the second layer dislocation barrier layer;
flattening the third intrinsic germanium layer, and forming a third dislocation blocking layer on one side of the third intrinsic germanium layer away from the first substrate;
Etching the third dislocation barrier layer to form an etched opening in the third dislocation barrier layer; wherein the etched opening in the third dislocation blocking layer and the etched opening in the second dislocation blocking layer are arranged in a dislocation manner;
Depositing germanium material to form a fourth intrinsic germanium layer to fill the etched openings in the third layer of dislocation-blocking layers and to cover the third layer of dislocation-blocking layers;
and so on until the preparation of the last intrinsic germanium layer is completed.
Optionally, forming a dislocation blocking layer on a side of the intrinsic germanium layer remote from the first substrate, comprising:
Forming a first barrier sub-layer on a side of the intrinsic germanium layer away from the first substrate; the material of the first barrier sublayer comprises aluminum oxide;
Forming a second barrier sub-layer on one side of the first barrier sub-layer away from the first substrate; the material of the second barrier sub-layer comprises silicon oxide.
Optionally, depositing a germanium material to form the intrinsic germanium layer includes:
growing a first intrinsic germanium sublayer at low temperature; the low temperature range is 360-460 ℃;
growing a second intrinsic germanium sub-layer on the first intrinsic germanium sub-layer at a high temperature; the high temperature range is 600-700 ℃.
Optionally, before bonding the semiconductor device layer on one side of the second substrate, the method further includes:
Sequentially forming a first dielectric layer and a second dielectric layer on one side of the second substrate; the material of the first dielectric layer comprises silicon oxide, and the material of the second dielectric layer comprises aluminum oxide.
Optionally, forming a semiconductor device layer on a side of the second buffer layer away from the first substrate includes:
forming a contact layer on one side of the second buffer layer away from the first substrate;
Forming a first doping type semiconductor layer on one side of the contact layer away from the first substrate;
forming an intrinsic absorption layer on a side of the first doping type semiconductor layer away from the first substrate;
A second doping type semiconductor layer is formed on a side of the intrinsic absorption layer remote from the first substrate.
Optionally, after bonding the semiconductor device layer on one side of the second substrate and removing the first substrate, the first buffer layer and the second buffer layer, the method further includes:
etching the semiconductor device layer to form a detector structure;
Forming a passivation layer on a side of the semiconductor device layer away from the second substrate;
Etching the passivation layer to form a first electrode hole and a second electrode hole;
and depositing a metal material in the first electrode hole and the second electrode hole to form a first electrode and a second electrode respectively.
Optionally, the detector structure includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure, or an APD type detector structure.
According to another aspect of the present invention, there is provided a semiconductor device formed by the method of manufacturing a semiconductor device according to any of the embodiments of the present invention; the semiconductor device includes:
a second substrate;
A semiconductor device layer located on one side of the second substrate; the semiconductor device layer includes at least one detector structure therein.
Optionally, a first dielectric layer and a second dielectric layer are sequentially arranged on one side, close to the semiconductor device layer, of the second substrate; the second substrate, the first dielectric layer and the second dielectric layer are used for forming a bonding substrate;
the detector structure includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure, or an APD type detector structure.
The embodiment of the invention provides a semiconductor device and a preparation method thereof, wherein the preparation method of the semiconductor device comprises the following steps: providing a first substrate; the material of the first substrate comprises silicon; forming a first buffer layer on one side of a first substrate; wherein the first buffer layer comprises a plurality of intrinsic germanium layers and a dislocation blocking layer positioned between two adjacent intrinsic germanium layers; each dislocation blocking layer comprises a plurality of etching openings, and the etching openings of two adjacent dislocation blocking layers are arranged in a dislocation way; forming a second buffer layer on one side of the first buffer layer away from the first substrate; forming a semiconductor device layer on one side of the second buffer layer away from the first substrate; a second substrate is provided, a semiconductor device layer is bonded to one side of the second substrate, and the first substrate, the first buffer layer, and the second buffer layer are removed. According to the technical scheme provided by the embodiment of the invention, the high-quality first buffer layer is formed by growing the intrinsic germanium layer in the multi-step selective area, so that good conditions are provided for the subsequent epitaxial growth of the second buffer layer and the semiconductor device layer, and the purpose of improving the crystal quality of the subsequent epitaxial layer and the performance of the semiconductor device is achieved by optimizing the structure of the Ge buffer layer; the second buffer layer (GaAs buffer layer) does not need to be formed in multiple layers, and the manufacturing cost of the device is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 2 is a schematic flow chart of step S120 in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 3 to 12 are cross-sectional structure diagrams of step S120 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 13 is a schematic flow chart of step S130 in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 14 is a cross-sectional view of step S130 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 15 is a schematic flow chart of step S140 in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 16 is a cross-sectional view of step S140 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 17 to 18 are cross-sectional structural diagrams of step S150 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 19 is a cross-sectional view of step S160 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 20 is a cross-sectional view of step S170 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 21 is a cross-sectional view of step S180 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 22 is a cross-sectional view of step S190 in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As background art, with the diversification of semiconductor devices, various combinations of semiconductor materials are required to construct the semiconductor devices. Short wave infrared detectors play an important role in many fields. Compared with visible light, the infrared detection technology can be better suitable for severe environments such as heavy fog darkness and the like. In communication, 1310nm and 1550nm are common optical communication wavelengths and are both in an infrared detection area; applications in the medical field include infrared thermal imaging techniques, where thermal imaging of cancer patients has significant asymmetry because diseased areas are well metabolized, blood supply is abundant, which can raise body skin temperature, and diseased areas are easily found from infrared imaging by scanning the body; in agriculture, crop growth and pest prevention can be monitored; in addition, the satellite infrared remote sensing imaging and the topography measurement are utilized to detect the earth resources so as to determine the land and forest areas and the components thereof, and the method has great effects on aspects of forest fire prevention, global environment pollution monitoring, climate change and the like.
The III-V family InGaAs material is a direct band gap semiconductor, and has the characteristics of high electron mobility, high photoelectric property, high radiation resistance, lattice matching with InP by component adjustment, and the like. The InGaAs detector can also show good performance at room temperature, refrigeration equipment is not needed, the cost of the detector system is reduced, and great potential is shown in the aspect of miniaturizing the detector system. Besides, the InGaAs detector has high quantum efficiency and high sensitivity. Infrared detectors fabricated from InP/InGaAs materials have significant advantages in terms of cost, performance, and fabrication process. In particular, the cut-off wavelength of In 0.53Ga0.47 As is 1.7 μm, which just includes two important optical communication bands of 1.33 μm and 1.55 μm, and the lattice of InP and In 0.53Ga0.47 As is completely matched when the In component In the In1-xGaxAs material is 0.53, so that a high-quality In 0.53Ga0.47 As epitaxial layer can be grown on an InP substrate, and a high-performance semiconductor device can be developed.
The conventional InGaAs/InP heterojunction vertical PIN structure short-wave infrared photoelectric detector is directly extended on a 2-inch or 4-inch InP wafer; meanwhile, researchers also adopt a bonding mode to transfer an epitaxial PIN structure on an InP substrate to an insulator substrate, but the size of a III-VOI (including InPOI or InGaAsOI) wafer formed by the scheme is limited by the size of the InP substrate, and mass production of large-size wafers cannot be realized. The current Si-based InGaAs material heteroepitaxy technology provides an important technical approach for mass production of large-size III-VOI wafers, but Si-based heteroepitaxy InP materials and InGaAs materials have the problems of lattice mismatch and polarity mismatch, the mismatch of crystal constants and thermal expansion coefficients can introduce a large number of dislocations and defects and even macrocracks in the heteroepitaxy process, the polarity mismatch can cause inversion domain problems, the problems can cause the degradation of device performance, and the crystal quality of the InGaAs materials is improved by arranging multiple buffer layers (such as multiple GaAs buffer layers), but the preparation cost and the volume of the device are increased.
In view of this, an embodiment of the present invention provides a method for manufacturing a semiconductor device, and fig. 1 is a schematic flow chart of the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 1, the method for manufacturing a semiconductor device includes:
S110, providing a first substrate; the material of the first substrate comprises silicon.
Specifically, in the embodiment of the present application, the material of the first substrate includes silicon, and the first substrate may be a silicon substrate. The surface of the first substrate may be in the horizontal direction, i.e. the surface of the first substrate is in the (001) direction; the surface of the first substrate may also form an angle with the horizontal, for example, the surface of the first substrate forms 6 ° with the horizontal, i.e., the first substrate may be a6 ° bevel silicon substrate, so that a diatomic step may be formed on the surface of the silicon substrate 100, and reverse domains generated by iii-v epitaxy may be suppressed, so that the first substrate and the buffer layer thereon may be improved to some extent. The material of the first substrate may also be other materials suitable for preparing large-sized (e.g., greater than 8 inch) wafers.
S120, forming a first buffer layer on one side of a first substrate; wherein the first buffer layer comprises a plurality of intrinsic germanium layers and a dislocation blocking layer positioned between two adjacent intrinsic germanium layers; each dislocation blocking layer comprises a plurality of etching openings, and the etching openings of two adjacent dislocation blocking layers are arranged in a dislocation way.
Specifically, the first buffer layer is epitaxially formed on the first substrate, and the lattice mismatch between the material of the first buffer layer and the first substrate is smaller, so that the film forming quality is higher, and the lattice mismatch between the first buffer layer and the second buffer layer is smaller, so that the film forming quality of the second buffer layer is better, and the quality of the semiconductor device layer formed on the second buffer layer can be ensured.
Wherein the first buffer layer comprises a plurality of intrinsic germanium layers and a dislocation blocking layer positioned between two adjacent intrinsic germanium layers. The first substrate is in contact with the bottom-most intrinsic germanium layer and the second buffer layer is in contact with the top-most intrinsic germanium layer. The rest of the intrinsic germanium layers except the bottom intrinsic germanium layer can be formed by a selective area growth mode, and the intrinsic germanium layer formed by the selective area growth mode at least comprises three layers. The step of forming the intrinsic germanium layer by selective growth comprises: forming a dislocation blocking layer, etching the dislocation blocking layer to pattern the dislocation blocking layer, and forming a plurality of etching openings in the dislocation blocking layer; a germanium material is deposited to form an intrinsic germanium layer to fill the etched openings in the dislocation-blocking layer and to cover the dislocation-blocking layer. Limiting the epitaxial growth of the intrinsic germanium layer in predefined regions by the pattern of dislocation-blocking layers provides additional control of the strain relaxation process, reducing dislocations by necking effect and Aspect Ratio Trapping (ART) techniques. And the etching openings of the two adjacent staggered barrier layers are staggered, and the intrinsic germanium layers can be grown in multiple staggered selected areas, so that the extension of cracks can be better blocked, the crack can be annihilated at the side wall, the defect density of the epitaxial layer is greatly reduced, a high-quality Ge buffer layer is obtained, and good conditions are provided for the subsequent epitaxial second buffer layer. Among them, the Deposition method of the Ge buffer layer includes, but is not limited to, LPCVD (Low Pressure Chemical Vapor Deposition ), PECVD (PLASMA ENHANCED CHEMICAL Vapor Deposition), and the like.
S130, forming a second buffer layer on one side of the first buffer layer away from the first substrate.
Specifically, the material of the second buffer layer includes GaAs, which is a GaAs buffer layer. The mismatch of Ge and GaAs is 0.08%, and the thermal expansion coefficient is relatively close, so that the problem of poor epitaxial quality caused by lattice mismatch and polarity mismatch of Si and InP/InGaAs can be further solved by extending the GaAs buffer layer on the Ge buffer layer and extending the InP film layer and the InGaAs film layer on the basis of the GaAs buffer layer to form a semiconductor device layer. Among them, the deposition method of the GaAs buffer layer is not limited to MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition).
And S140, forming a semiconductor device layer on one side of the second buffer layer away from the first substrate.
Specifically, the semiconductor device layer is used to fabricate the detector structure. Alternatively, the detector structure may be a PIN type detector structure, a NIP type detector structure, an MSM type detector structure, or an APD type detector structure.
And S150, providing a second substrate, bonding the semiconductor device layer on one side of the second substrate, and removing the first substrate, the first buffer layer and the second buffer layer.
Specifically, the bonding manner of the semiconductor device layer to one side of the second substrate includes, but is not limited to, BCB (benzocyclobutene) bonding. After bonding the semiconductor device layer to one side of the second substrate, the first buffer layer, and the second buffer layer are removed to expose the semiconductor device layer. Alternatively, the first substrate, the first buffer layer, and the second buffer layer may be removed using at least one process of Polishing (Grading), wet, dry, and CMP (CHEMICAL MECHANICAL Polishing).
According to the semiconductor device and the preparation method thereof, the high-quality first buffer layer is formed in a mode of growing the intrinsic germanium layer in the selected area for multiple steps (at least three times), good conditions are provided for epitaxial growth of the second buffer layer and the semiconductor device layer, and the purpose of improving the crystal quality of the subsequent epitaxial layer and the performance of the semiconductor device is achieved by optimizing the structure of the Ge buffer layer; the second buffer layer (GaAs buffer layer) does not need to be formed in multiple layers, and the manufacturing cost of the device is reduced.
For ease of understanding, the specific implementation of each of the above steps will be described in detail below.
In one embodiment of the present invention, fig. 2 is a schematic flow chart of step S120 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and fig. 3 to fig. 12 are cross-sectional structure diagrams of step S120 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 2 to fig. 12, step S120 forms a first buffer layer on one side of a first substrate, including:
S201, depositing germanium material to form a first intrinsic germanium layer, wherein the first intrinsic germanium layer covers the surface of the first substrate.
Specifically, referring to fig. 3, a germanium material is deposited on a surface of one side of the first substrate 10 to form a first intrinsic germanium layer 211. The process of forming the first intrinsic germanium layer 211 may be a deposition process, such as chemical vapor deposition (Chemical Vapor Deposition, CVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), or the like. Alternatively, the first intrinsic germanium layer 211 may comprise a multi-layer film layer grown under different temperature environments, for example comprising a first intrinsic germanium sub-layer and a second intrinsic germanium sub-layer grown under different temperature environments. The step of depositing the germanium material to form a first intrinsic germanium layer may specifically comprise: growing a first intrinsic germanium sublayer at low temperature; the low temperature range is 360-460 ℃; growing a second intrinsic germanium sub-layer on the first intrinsic germanium sub-layer at a high temperature; the high temperature range is 600-700 ℃. The effect of low-temperature growth of the first intrinsic germanium sublayer is that part of stress can be released, so that a film layer on the first intrinsic germanium sublayer can be grown under the condition of low stress or no stress, and high-temperature growth of the second intrinsic germanium sublayer can obtain an ideal second intrinsic germanium sublayer, so that an ideal first intrinsic germanium sublayer 211 is obtained.
Further, in the process of forming the first intrinsic germanium layer 211, a third intrinsic germanium sublayer may be grown between the first intrinsic germanium sublayer and the second intrinsic germanium sublayer, and the effect of growing the third intrinsic germanium sublayer at a medium temperature is that the third intrinsic germanium sublayer may serve as an intermediate temperature buffer region, promoting two-dimensional planar growth of germanium, improving lattice defects of the germanium film layer in the growth process, and facilitating formation of the second intrinsic germanium sublayer thereon, thereby further improving quality of the first intrinsic germanium layer 211.
S202, forming a first layer of dislocation blocking layer on one side of the first layer of intrinsic germanium away from the first substrate.
Specifically, referring to fig. 4, the first layer dislocation blocking layer 221 may be obtained using a deposition process, such as chemical vapor deposition, atomic layer epitaxy, or the like. Wherein the first layer dislocation blocking layer 221 includes a first blocking sub-layer 201 and a second blocking sub-layer 202 stacked. The material of the first barrier sublayer 201 comprises aluminum oxide; the material of the second barrier sublayer 202 comprises silicon oxide. Forming a first layer of dislocation blocking layer 221 on a side of the first layer of intrinsic germanium 211 remote from the first substrate 10, comprising: depositing Al 2O3 material on the side of the first intrinsic germanium layer 211 remote from the first substrate 10 to form a first barrier sub-layer 201; a second barrier sublayer 202 is formed by depositing SiO 2 material on the side of the first barrier sublayer 201 remote from the first substrate 10. The effect of growing the first barrier sub-layer 201 before the second barrier sub-layer 202 is to enhance the adhesion between the second barrier sub-layer 202 and the intrinsic germanium layer (first intrinsic germanium layer 211), thereby improving the robustness of the second barrier sub-layer 202. Wherein the thickness of the first barrier sublayer 201 is smaller than the thickness of the second barrier sublayer 202.
S203, etching the first layer of dislocation blocking layer, and forming an etching opening in the first layer of dislocation blocking layer.
Specifically, referring to fig. 5, the etching process may be a photolithography process by which the first layer dislocation blocking layer 221 is etched, and an etching opening 01 is formed in the first layer dislocation blocking layer 221. The step of etching the first layer dislocation blocking layer 221 through a photolithography process to form the etched opening 01 in the first layer dislocation blocking layer 221 may specifically include: forming a photoresist on the first layer dislocation blocking layer 221; obtaining patterned photoresist through photoetching and developing; etching the first layer dislocation blocking layer 221 by using the photoresist as a mask, thereby forming an etching opening 01 in the first layer dislocation blocking layer 221, and exposing the first layer dislocation blocking layer 221 by the etching opening 01 formed in the first layer dislocation blocking layer 221; and removing the photoresist layer.
S204, depositing germanium material to form a second intrinsic germanium layer to fill the etched opening in the first layer dislocation barrier layer and cover the first layer dislocation barrier layer.
Specifically, referring to fig. 6, a germanium material is deposited in the etched opening 01 of the first layer of dislocation barriers 221 and on the surface of the first layer of dislocation barriers 221 to form a second layer of intrinsic germanium 212. The process of forming the second intrinsic germanium layer 212 may be a deposition process such as chemical vapor deposition, molecular beam epitaxy, or the like. Alternatively, the second intrinsic germanium layer 212 may comprise a multi-layer film grown in different temperature environments, for example comprising a first intrinsic germanium sub-layer and a second intrinsic germanium sub-layer grown in different temperature environments. The step of depositing a second layer of germanium material to form an intrinsic germanium layer may specifically comprise: growing a first intrinsic germanium sublayer at low temperature; the low temperature range is 360-460 ℃; growing a second intrinsic germanium sub-layer on the first intrinsic germanium sub-layer at a high temperature; the high temperature range is 600-700 ℃. The action can be referred to the above steps, and will not be described here again. The second intrinsic germanium layer 212 is a selectively grown intrinsic germanium layer, and for the selectively grown intrinsic germanium layer, if a manner of growing in a different temperature environment is adopted, the thickness of the first intrinsic germanium sub-layer grown at a low temperature may be smaller than the depth of the etching opening (for example, the etching opening 01), or equal to the depth of the etching opening (for example, the etching opening 01), or greater than the depth of the etching opening (for example, the etching opening 01), which is not limited in the embodiment of the present invention. Further, in the process of forming the second intrinsic germanium layer 212, a third intrinsic germanium layer may be grown at a medium temperature between the first intrinsic germanium layer and the second intrinsic germanium layer, and the function may refer to the above steps, which are not repeated here.
And S205, flattening the second intrinsic germanium layer, and forming a second dislocation blocking layer on one side of the second intrinsic germanium layer far away from the first substrate.
Specifically, the planarization of the second intrinsic germanium layer 212 may make the upper surface of the second intrinsic germanium layer 212 relatively flat. Referring to fig. 7, a second layer of dislocation blocking layer 222 is formed on a side of the second intrinsic germanium layer 212 away from the first substrate 10, and specific steps may refer to the above-mentioned step S202, and will not be repeated here.
S206, etching the second layer of dislocation blocking layer, and forming an etching opening in the second layer of dislocation blocking layer; wherein, the etching opening in the second layer dislocation blocking layer and the etching opening in the first layer dislocation blocking layer are arranged in a dislocation way.
Specifically, referring to fig. 8, the second layer dislocation blocking layer 222 is etched, and an etching opening 02 is formed in the second layer dislocation blocking layer 222, and the specific steps may refer to the above step S203, which is not described herein again. It should be noted that, the etched opening 02 in the second layer of dislocation blocking layer 222 and the etched opening 01 in the first layer of dislocation blocking layer 221 are arranged in a dislocation manner, i.e. the positions of the openings of the two patterned photoresists are arranged in a dislocation manner. The etched openings of the two adjacent staggered barrier layers are staggered, and the intrinsic germanium layers can be grown in staggered selected areas, so that the extension of cracks can be better blocked, the cracks can be annihilated at the side wall, the defect density of the epitaxial layer is greatly reduced, a high-quality Ge layer is obtained, and good conditions are provided for the subsequent epitaxial second buffer layer 30.
S207, depositing germanium material to form a third intrinsic germanium layer to fill the etched opening in the second layer dislocation barrier layer and cover the second layer dislocation barrier layer.
Specifically, referring to fig. 9, a germanium material is deposited to form the third intrinsic germanium layer 213 to fill the etched opening 02 in the second layer of dislocation blocking layer 222 and cover the second layer of dislocation blocking layer 222, and the specific steps may refer to the above step S204, which is not repeated here.
And S208, flattening the third intrinsic germanium layer, and forming a third dislocation blocking layer on one side of the third intrinsic germanium layer away from the first substrate.
Specifically, referring to fig. 10, after the third intrinsic germanium layer 213 is planarized, a third dislocation blocking layer 223 is formed on a side of the third intrinsic germanium layer 213 away from the first substrate 10, and the specific steps may refer to the above-mentioned step S202, which is not repeated here.
S209, etching the third layer of dislocation blocking layer, and forming an etching opening in the third layer of dislocation blocking layer; and the etching opening in the third dislocation blocking layer and the etching opening in the second dislocation blocking layer are arranged in a staggered mode.
Specifically, referring to fig. 11, the third dislocation-blocking layer 223 is etched, and an etched opening 03 is formed in the third dislocation-blocking layer 223, and specific steps may refer to step S203 described above, and will not be described again. It should be noted that, the etched opening 03 in the third dislocation blocking layer 223 and the etched opening 02 in the second dislocation blocking layer 222 are arranged in a dislocation manner, that is, the positions of the openings of the two patterned photoresists are arranged in a dislocation manner. Alternatively, the etched opening 03 in the third dislocation-blocking layer 223 may be aligned with the etched opening 01 in the first dislocation-blocking layer 221.
And S2010, depositing germanium material to form a fourth intrinsic germanium layer so as to fill the etched opening in the third dislocation blocking layer and cover the surface of the third dislocation blocking layer.
Specifically, referring to fig. 12, a germanium material is deposited to form a fourth intrinsic germanium layer 214 to fill the etched opening 03 in the third dislocation-blocking layer 223 and cover the third dislocation-blocking layer 223, and specific steps may refer to the above-mentioned step S204, and will not be repeated here.
Steps S201 to S2010 above exemplarily illustrate that the first buffer layer 20 includes three selectively grown intrinsic germanium layers (the second intrinsic germanium layer 212, the third intrinsic germanium layer 213, and the fourth intrinsic germanium layer 204). In other embodiments of the present invention, the first buffer layer 20 comprises more than three layers of the selected grown intrinsic germanium layers, and so on, according to the above steps, until the preparation of the final intrinsic germanium layer is completed. It should be noted that after the deposition of the last intrinsic germanium layer, the last intrinsic germanium layer may be planarized to provide a flat deposition surface for the preparation of the second buffer layer 30.
Based on the foregoing embodiments, in one embodiment of the present invention, fig. 13 is a schematic flow diagram of step S130 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and fig. 14 is a cross-sectional structure diagram of step S130 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 13 to fig. 14, step S130 forms a second buffer layer on a side of the first buffer layer away from the first substrate, where the second buffer layer includes:
S301, growing a first GaAs buffer sub-layer at a low temperature; the low temperature range is 360-460 ℃.
S302, growing a second GaAs buffer sub-layer on the first GaAs buffer sub-layer at a high temperature; the high temperature range is 600-700 ℃.
Specifically, referring to fig. 14, in an embodiment of the present invention, the second buffer layer 30 includes a first GaAs buffer sub-layer grown at a low temperature and a second GaAs buffer sub-layer grown at a high temperature (not shown). The effect of growing the first GaAs buffer sub-layer at low temperature is that part of the stress can be released, so that the film thereon can be grown with low stress or without stress. The second GaAs buffer sub-layer is grown at high temperature to obtain the ideal GaAs layer.
Based on the foregoing embodiments, in one embodiment of the present invention, fig. 15 is a schematic flow chart of step S140 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and fig. 16 is a cross-sectional structure diagram of step S140 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 15 to fig. 16, step S140 forms a semiconductor device layer on a side of the second buffer layer away from the first substrate, including:
s401, forming a contact layer on one side of the second buffer layer away from the first substrate.
S402, forming a first doping type semiconductor layer on one side of the contact layer away from the first substrate.
S403, forming an intrinsic absorption layer on one side of the first doping type semiconductor layer away from the first substrate.
S404, forming a second doping type semiconductor layer on one side of the intrinsic absorption layer away from the first substrate.
Specifically, the material of the contact layer 41 may include InGaAs of the first doping type and heavily doped, the material of the first doping type semiconductor layer 42 includes InP (indium phosphide), the material of the intrinsic absorption layer 43 includes In xGa1-x As, and the composition of In is In the range of 0.53+.x+.1. The material of the layer of second doping type semiconductor 44 comprises InP. Alternatively, referring to fig. 16, the first doping type is P-type, the second doping type is N-type, i.e., the material of the contact layer 41 is P-type heavily doped InGaAs, the material of the first doping type semiconductor layer 42 is P-type InP, and the material of the second doping type semiconductor layer 44 is N-type InP.
Or the first doping type is N-type, the second doping type is P-type, namely the material of the first doping type semiconductor layer is N-type InP, and the material of the second doping type semiconductor layer is P-type InP. The semiconductor device layer 40 in the embodiment of the present invention is used to prepare a PIN type detector structure or a NIP type detector structure.
In another embodiment of the present invention (not shown), step S140 forms a semiconductor device layer on a side of the second buffer layer away from the first substrate, including:
And S411, forming a contact layer on one side of the second buffer layer away from the first substrate.
And S412, forming a first doping type semiconductor layer on one side of the contact layer away from the first substrate.
And S413, forming an intrinsic absorption layer on one side of the first doping type semiconductor layer away from the first substrate.
S414, forming an avalanche multiplication region layer of the first doping type on one side of the intrinsic absorption layer away from the first substrate.
And S415, forming a second doping type semiconductor layer on one side of the avalanche region layer of the first doping type, which is far away from the first substrate.
The semiconductor device layer in the embodiment of the invention is used for preparing an APD type detector structure.
In another embodiment of the present invention (not shown), step S140 forms a semiconductor device layer on a side of the second buffer layer away from the first substrate, including:
s421, an undoped semiconductor buffer layer is formed on one side, away from the first substrate, of the second buffer layer.
And S422, forming a second doping type semiconductor layer on one side of the buffer layer away from the first substrate.
S423, forming an undoped semiconductor layer on one side of the second doping type semiconductor layer far away from the first substrate.
The semiconductor device layer in the embodiment of the invention is used for preparing the MSM type detector structure.
Fig. 17 to 18 are cross-sectional structure diagrams of step S150 in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and referring to fig. 17 to 18, a semiconductor device layer 40 is bonded on one side of a second substrate 51, and the first substrate 10, the first buffer layer 20, and the second buffer layer 30 are removed by at least one process selected from polishing (patterning), wet, dry, and CMP.
On the basis of the above embodiments, in one embodiment of the present invention, before bonding the semiconductor device layer 40 on one side of the second substrate 51, it further includes:
A first dielectric layer 53 and a second dielectric layer 52 are sequentially formed on one side of the second substrate 51; wherein the material of the first dielectric layer 52 comprises silicon oxide and the material of the second dielectric layer 53 comprises aluminum oxide.
Specifically, the material of the second substrate 51 includes silicon, which may be a silicon substrate. A silicon oxide layer (first dielectric layer 53) and an aluminum oxide layer (second dielectric layer 52) are sequentially formed on one side of the second substrate 51, and the silicon substrate, the silicon oxide layer and the aluminum oxide layer are used to constitute a silicon-on-insulator (SOI) substrate 50. The material of the first substrate may also be other materials suitable for preparing large-sized (e.g., greater than 8 inch) wafers. Bonding the semiconductor device layer 40 to one side of the second substrate 51 includes: the semiconductor device layer 40 is bonded to the surface of the second dielectric layer 53 on the side remote from the second substrate 51. In the embodiment of the invention, the semiconductor device layer 40 is bonded on the bonding substrate 50, the dark current of the device can be reduced through the insulating layer on the bonding substrate 50, and the second substrate 51 and the first dielectric layer 52 can be used as resonant cavities, so that the responsivity of the prepared detector is improved.
On the basis of the above embodiments, in one embodiment of the present invention, step S150, after bonding the semiconductor device layer on one side of the second substrate and removing the first substrate, the first buffer layer and the second buffer layer, further includes:
s160, the semiconductor device layer 40 is etched to form a detector structure 401 (refer to fig. 19).
S170, a passivation layer 60 is formed on a side of the semiconductor device layer 40 away from the second substrate 51 (refer to fig. 20).
S180, the passivation layer 60 is etched to form the first electrode hole 61 and the second electrode hole 62 (refer to fig. 21).
S190, a metal material is deposited in the first electrode hole 61 and the second electrode hole 62 to form the first electrode 71 and the second electrode 72, respectively (refer to fig. 22).
In summary, in the related art, a heteroepitaxial GaAs layer directly on a Si substrate is used as a buffer layer, and a large number of dislocations are generated, so that the defect density of the GaAs layer is on the order of 10 7. In the embodiment of the invention, after the first selective growth of the intrinsic Ge layer, the order of magnitude is reduced to 10 5, and after three or more selective growth, the quality of the intrinsic Ge layer is higher and higher, and the defect density of the GaAs layer is greatly reduced. And the intrinsic Ge layer grows in multiple staggered selective areas, so that dislocation extension can be better blocked, self annihilation is carried out on the side wall of the intrinsic Ge layer, the defect density of the epitaxial layer is greatly reduced, a high-quality Ge layer is obtained, and good conditions are provided for the subsequent epitaxial GaAs layer. The mismatch of Ge and GaAs is 0.08%, and the thermal expansion coefficient is relatively close, so GaAs can be epitaxially grown on Si through the Ge buffer layer, and an InP layer and an InGaAs layer can be epitaxially grown on the Si buffer layer, so that the problem of poor epitaxial quality caused by lattice mismatch and polarity mismatch of Si, inP and InGaAs is solved, and the performances of dark current, responsivity and the like of the prepared InGaAs short wave infrared detection device on the insulator reach a relatively good level.
In addition, compared with the traditional InP substrate INGAAS PDS which can only be prepared on a 2-6 inch wafer, the embodiment of the invention can realize large-scale preparation of 8 inches and 12 inches based on the Si substrate, and the device cost is greatly reduced. Monolithic heterogeneous integration of InGaAs materials on Si substrates is realized, and various novel device applications and functions are made possible by utilizing excellent photoelectric properties of InGaAs materials and highly mature Si process technology. The technical scheme provided by the invention can continuously prepare InGaAs short wave infrared detectors on insulators with 8 inches and 12 inches, solves the problems of high price of the InP substrate, limited wafer size, fragile wafer and other pain points in the prior art, and lays a good technical foundation for large-scale production of Si-based III-V devices.
The embodiment of the invention also provides a semiconductor device, which is formed by the preparation method of the semiconductor device in any embodiment; referring to fig. 22, the semiconductor device includes:
A second substrate 51;
A semiconductor device layer 40 located on one side of the second substrate 51; at least one detector structure 401 is included in semiconductor device layer 40.
Optionally, a first dielectric layer 52 and a second dielectric layer 53 are sequentially disposed on a side of the second substrate 51, which is close to the semiconductor device layer 40; the second substrate 51, the first dielectric layer 52 and the second dielectric layer 53 are used to constitute the bond substrate 50; the detector structure 401 includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure, or an APD type detector structure. The semiconductor device provided by the embodiment of the invention has the corresponding beneficial effects of the preparation method, and is not repeated here.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
Providing a first substrate; the material of the first substrate comprises silicon;
Forming a first buffer layer on one side of the first substrate; wherein the first buffer layer comprises a plurality of intrinsic germanium layers and a dislocation blocking layer positioned between two adjacent intrinsic germanium layers; each dislocation blocking layer comprises a plurality of etching openings, and the etching openings of two adjacent dislocation blocking layers are arranged in a dislocation manner;
forming a second buffer layer on one side of the first buffer layer away from the first substrate;
Forming a semiconductor device layer on a side of the second buffer layer away from the first substrate;
and providing a second substrate, bonding the semiconductor device layer on one side of the second substrate, and removing the first substrate, the first buffer layer and the second buffer layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming a first buffer layer on one side of the first substrate comprises:
Depositing a germanium material to form a first intrinsic germanium layer, wherein the first intrinsic germanium layer covers the surface of the first substrate;
forming a first layer of dislocation blocking layer on one side of the first intrinsic germanium layer away from the first substrate;
Etching the first layer of dislocation blocking layer to form an etching opening in the first layer of dislocation blocking layer;
depositing germanium material to form a second intrinsic germanium layer to fill the etched openings in the first dislocation blocking layer and to cover the first dislocation blocking layer;
Flattening the second intrinsic germanium layer, and forming a second dislocation blocking layer on one side of the second intrinsic germanium layer away from the first substrate;
etching the second layer of dislocation blocking layer, and forming an etching opening in the second layer of dislocation blocking layer; wherein the etched opening in the second layer of dislocation blocking layer and the etched opening in the first layer of dislocation blocking layer are arranged in a dislocation manner;
Depositing a germanium material to form a third intrinsic germanium layer to fill the etched openings in the second layer dislocation barrier layer and to cover the second layer dislocation barrier layer;
flattening the third intrinsic germanium layer, and forming a third dislocation blocking layer on one side of the third intrinsic germanium layer away from the first substrate;
Etching the third dislocation barrier layer to form an etched opening in the third dislocation barrier layer; wherein the etched opening in the third dislocation blocking layer and the etched opening in the second dislocation blocking layer are arranged in a dislocation manner;
Depositing germanium material to form a fourth intrinsic germanium layer to fill the etched openings in the third layer of dislocation-blocking layers and to cover the third layer of dislocation-blocking layers;
and so on until the preparation of the last intrinsic germanium layer is completed.
3. The method of manufacturing a semiconductor device according to claim 2, wherein forming a dislocation-blocking layer on a side of the intrinsic germanium layer remote from the first substrate comprises:
Forming a first barrier sub-layer on a side of the intrinsic germanium layer away from the first substrate; the material of the first barrier sublayer comprises aluminum oxide;
Forming a second barrier sub-layer on one side of the first barrier sub-layer away from the first substrate; the material of the second barrier sub-layer comprises silicon oxide.
4. The method of manufacturing a semiconductor device according to claim 2, wherein depositing a germanium material to form the intrinsic germanium layer comprises:
growing a first intrinsic germanium sublayer at low temperature; the low temperature range is 360-460 ℃;
growing a second intrinsic germanium sub-layer on the first intrinsic germanium sub-layer at a high temperature; the high temperature range is 600-700 ℃.
5. The method of manufacturing a semiconductor device according to claim 1, wherein before bonding the semiconductor device layer to the side of the second substrate, further comprising:
Sequentially forming a first dielectric layer and a second dielectric layer on one side of the second substrate; the material of the first dielectric layer comprises silicon oxide, and the material of the second dielectric layer comprises aluminum oxide.
6. The method of manufacturing a semiconductor device according to claim 1, wherein forming a semiconductor device layer on a side of the second buffer layer away from the first substrate, comprises:
forming a contact layer on one side of the second buffer layer away from the first substrate;
Forming a first doping type semiconductor layer on one side of the contact layer away from the first substrate;
forming an intrinsic absorption layer on a side of the first doping type semiconductor layer away from the first substrate;
A second doping type semiconductor layer is formed on a side of the intrinsic absorption layer remote from the first substrate.
7. The method for manufacturing a semiconductor device according to claim 1, wherein after bonding the semiconductor device layer to one side of the second substrate and removing the first substrate, the first buffer layer, and the second buffer layer, further comprising:
etching the semiconductor device layer to form a detector structure;
Forming a passivation layer on a side of the semiconductor device layer away from the second substrate;
Etching the passivation layer to form a first electrode hole and a second electrode hole;
and depositing a metal material in the first electrode hole and the second electrode hole to form a first electrode and a second electrode respectively.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the detector structure comprises a PIN type detector structure, a NIP type detector mesa structure, an MSM type detector structure, or an APD type detector structure.
9. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 8; the semiconductor device includes:
a second substrate;
A semiconductor device layer located on one side of the second substrate; the semiconductor device layer includes at least one detector structure therein.
10. The semiconductor device of claim 9, wherein the semiconductor device comprises a semiconductor substrate,
A first dielectric layer and a second dielectric layer are sequentially arranged on one side, close to the semiconductor device layer, of the second substrate; the second substrate, the first dielectric layer and the second dielectric layer are used for forming a bonding substrate;
the detector structure includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure, or an APD type detector structure.
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| CN202410321742.8A Pending CN118198188A (en) | 2024-03-20 | 2024-03-20 | Semiconductor device and preparation method thereof |
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| CN (1) | CN118198188A (en) |
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