CN118198081A - Photomultiplier and preparation method thereof - Google Patents
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Abstract
The invention relates to a photomultiplier and a preparation method thereof. A photomultiplier includes a substrate and a plurality of grooves provided on the substrate; sequentially stacking an N-type doped semiconductor layer and a P-type doped semiconductor layer on a substrate; the trench penetrates through the P-type doped semiconductor layer to be in contact with the N-type doped semiconductor layer, a first insulating layer is arranged on the side wall of the trench, and conductive metal is filled in the center of the trench; the grooves are intersected to form a grid shape; the shallow surface layer of the P-type doped semiconductor layer is provided with a plurality of high-concentration P-type doped wells which are distributed at intervals; the surface of each high-concentration P-type doped well is provided with a light absorption region; the plurality of high-concentration P-type doped wells are connected to the quenching resistor in a one-to-one correspondence manner; each group of high-concentration P-type doped well and quenching resistor are led out together to form an anode; and a cathode is led out from the upper end of the conductive metal in the groove. The light blocking metal in the deep groove is used as the cathode extraction electrode, and the extraction electrode is not required to be additionally manufactured, so that the area of a chip is saved; while the dark count rate is reduced.
Description
Technical Field
The invention relates to the field of photoelectric detectors, in particular to a photomultiplier and a preparation method thereof.
Background
A silicon photomultiplier (SiPM) is photoelectric detection equipment with photon number resolution capability, has the characteristics of high gain, high sensitivity, low bias voltage, no magnetic field interference and the like, and is widely applied to the fields of medical imaging, laser radar ranging, high-energy particle detection and the like. As shown in FIG. 1, the SiPM structure is a planar array formed by connecting a plurality of Single Photon Avalanche Diodes (SPAD) microcells in parallel, and each microcell is formed by connecting a SPAD and a large-resistance quenching resistor in series. In operation, the SiPM is biased with a reverse bias voltage slightly greater than the SPAD diode breakdown voltage, with a high electric field in the depletion layer. If photons are incident into the depletion region, the energy of the photons absorbed by the electrons is transited to an excitation level to form electrons or holes, the electrons or holes are accelerated under the action of an electric field, more electron-hole pairs are formed after collision ionization, and finally avalanche occurs. The current in each microcell will suddenly increase after avalanche, the voltage dropped on the quenching resistor will also suddenly increase, the current in the microcell will instantaneously decrease, and the avalanche will stop. This excitation-quenching process forms a transient current pulse. Because the structure of each microcell in the SiPM and the resistance value of the quenching resistor are identical, each microcell excited by photons can theoretically output the same pulse, and the magnitude of the current output by the parallel array is in direct proportion to the number of the excited microcells, so that the number of the incident photons can be calculated according to the peak magnitude of the current.
In the conventional SiPM structure, most of the SiPM structures are vertical structures, i.e., the cathode and the anode are located on the front and back sides of the wafer, respectively, as shown in fig. 2. The high degree of customization of this structure is detrimental to integration with existing planar CMOS processes.
For this purpose, the present invention is proposed.
Disclosure of Invention
The invention mainly aims to provide a photomultiplier and a preparation method thereof, wherein light blocking metal in a deep groove is used as a cathode extraction electrode, and the extraction electrode is not required to be additionally manufactured, so that the chip area is saved; meanwhile, the SPAD infinitesimal is manufactured by using the PIN structure, so that the dark counting rate is reduced.
In order to achieve the above object, the present invention provides the following technical solutions.
A first aspect of the present invention provides a photomultiplier comprising a substrate and a plurality of trenches disposed on the substrate; sequentially stacking an N-type doped semiconductor layer and a P-type doped semiconductor layer on the upper surface of the substrate from bottom to top; the groove penetrates through the P-type doped semiconductor layer to be in contact with the N-type doped semiconductor layer, a first insulating layer is arranged on the side wall of the groove, and the center of the groove is filled with conductive metal; the grooves are intersected to form a grid shape;
The shallow surface layer of the P-type doped semiconductor layer is provided with a plurality of high-concentration P-type doped wells distributed at intervals, and two adjacent high-concentration P-type doped wells are isolated by the groove; the doping concentration of the high-concentration P-type doping well is larger than that of the P-type doping semiconductor layer; the surface of each high-concentration P-type doped well is provided with a light absorption region;
The plurality of high-concentration P-type doped wells are connected to the quenching resistor in a one-to-one correspondence manner; each group of high-concentration P-type doped wells and the quenching resistor are led out together to form an anode; and a cathode is led out from the upper end of the conductive metal in the groove.
Therefore, the stacked structure of the N-type doped semiconductor layer, the P-type doped semiconductor layer and the high-concentration P-type doped well is used as a PIN structure, and compared with the traditional P+/N well or N+/P well junction, the low doping concentration of the P-type doped semiconductor layer and the high-concentration P-type doped well reduces the tunnel effect, so that the dark counting rate is lower.
In addition, the metal in the groove has multiple functions, not only can block light, but also can be used as a cathode extraction electrode, and the extraction electrode does not need to be manufactured additionally, so that the area of a chip is saved.
Meanwhile, the cathode and the anode (namely the cathode and the anode) are led out from the same side, and can be compatible with the existing CMOS process.
The layer structure or the materials used for the layers of the photomultiplier can be further improved on this basis, as listed below.
Further, the substrate is a P-type silicon substrate, which has a faster integration speed.
Further, the shallow surface layer of the high-concentration P-type doped well is a P-type heavily doped region, the doping concentration of the P-type heavily doped region is larger than that of the high-concentration P-type doped well, and the anode is connected with the P-type heavily doped region. The P-type heavily doped region has higher doping concentration and can play a role in reducing contact resistance.
Further, the conductive metal in the groove is connected with the N-type doped semiconductor layer through a metal silicide layer. The metal silicide layer may reduce the contact resistance between the metal and silicon.
Further, the high-concentration P-type doped well is provided with an anti-reflection layer on the surface of the light absorption region. The anti-reflection layer is added, so that the light absorptivity can be improved, and the photoelectric detection efficiency and the result accuracy are improved.
Further, the quenching resistor is arranged around the periphery of the corresponding high-concentration P-type doped well, and is provided with two opposite free ends, one end of the quenching resistor is in conductive connection with the corresponding high-concentration P-type doped well, and the other end of the quenching resistor is connected with the anode. The quenching resistor adopts the structure to achieve the following effects: the resistor is adjusted by bypassing the length of the high-concentration P-type doped well.
Further, the method further comprises the following steps: and the anode is electrically connected with the quenching resistor through a contact plug penetrating through the second insulating layer, and the cathode is connected with the upper end of the conductive metal in the groove through the contact plug penetrating through the second insulating layer. The design can protect the electrode and is convenient to process.
A second aspect of the present invention provides a method of manufacturing a photomultiplier of the first aspect, comprising:
Providing a semiconductor substrate;
Forming an N-type doped semiconductor layer on the upper surface of the semiconductor substrate;
forming a P-type doped semiconductor layer on the upper surface of the N-type doped semiconductor layer;
etching a groove penetrating to the N-type doped semiconductor layer in the P-type doped semiconductor layer;
Forming a first insulating layer only on the side wall of the groove, and filling conductive metal in the center;
continuing doping P-type ions in a plurality of areas of the shallow surface layer of the P-type doped semiconductor layer to form a plurality of high-concentration P-type doped wells, wherein two adjacent high-concentration P-type doped wells are isolated by the groove;
Forming quenching resistors above each high-concentration P-type doped well in a one-to-one correspondence manner, wherein the quenching resistors are used as pixel units, and part of the surface of each high-concentration P-type doped well is used as a light absorption region;
interconnecting the high-concentration P-type doped well and the quenching resistor in each pixel unit, leading out an anode together, and leading out a cathode from the upper end of the conductive metal in the groove.
Therefore, the photomultiplier with low dark count rate and high integration degree is prepared by a layer-by-layer sequential formation mode, the whole flow is simple, the designed steps are simple to operate, and the photomultiplier is easier to popularize and mass production.
Further, the method further comprises the following steps of: and continuing to perform P-type doping on the shallow surface layer of the high-concentration P-type doping well to form a P-type heavily doped region, wherein the anode is connected with the P-type heavily doped region.
Further, the method of forming the first insulating layer includes:
the first insulating layer is formed by a thermal oxidation growth method or a chemical vapor deposition method.
Further, after forming the first insulating layer on the sidewall of the trench and before filling the center of the trench with the conductive metal, the method further includes:
And forming a metal silicide layer at the bottom of the groove.
Further, the method further comprises the following steps: and forming an anti-reflection layer on the surface of the light absorption region of the high-concentration P-type doped well.
In conclusion, compared with the prior art, the invention achieves the following technical effects:
(1) The adoption of the PIN structure different from the prior art reduces the tunnel effect and makes the dark count rate lower.
(2) The microelements are isolated by a groove, conductive metal is filled in the microelements, and the conductive metal is contacted with the N-type buried layer through metal silicide, so that the conductive metal can serve as a light blocking layer to prevent optical crosstalk, and simultaneously serve as a cathode lead-out electrode, an electrode is not required to be additionally manufactured, and the area of a chip can be saved.
(3) The cathode and the anode are led out from the same side and can be compatible with the existing CMOS process.
(4) The preparation method has simple flow.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a circuit diagram of an SiPM;
FIG. 2 is a schematic illustration of a vertical structure SiPM;
FIG. 3 is a cross-sectional view of a photomultiplier provided by the present invention;
FIG. 4 is a top view of one of the pixel cells of the photomultiplier tube of FIG. 3 (only conductive metal is shown in the trench);
FIG. 5 is a top view layout of the array of photomultiplier tubes shown in FIG. 3 (ellipses represent pixel cells not shown, not limiting the number of cells).
Reference numerals:
1-substrate, 2-N type doped semiconductor layer, 3-P type doped semiconductor layer, 4-antireflection layer, 5-second insulating layer, 6-passivation layer, 7-first insulating layer, 8-conductive metal, 9-metal silicide layer, 10-high concentration P type doped well, 11-P type heavily doped region, 12-contact plug, 13-light absorption region, 14-quenching resistor, 15-metal layer, 16-trench, 17-anode, 18-cathode.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
Because of the low degree of integration of existing photomultiplier tubes, there is typically a high dark count rate. To this end, the invention provides a photomultiplier tube. The photomultiplier improves the integration degree by changing the structural design of PIN and the lead-out structure of the cathode and the anode, saves the chip area, and reduces the dark counting rate, and the specific structure is as follows.
As shown in connection with fig. 3 to 5, a photomultiplier includes a substrate 1 and a plurality of grooves 16 provided on the substrate 1; an N-type doped semiconductor layer 2 and a P-type doped semiconductor layer 3 are stacked in this order from bottom to top on the upper surface of the substrate 1. The trench 16 penetrates through the P-type doped semiconductor layer 3 to be in contact with the N-type doped semiconductor layer 2, a first insulating layer 7 is arranged on the side wall of the trench 16, and the center of the trench 16 is filled with conductive metal 8; the plurality of grooves 16 intersect to form a grid.
The shallow surface layer of the P-type doped semiconductor layer 3 is provided with a plurality of high-concentration P-type doped wells 10 which are distributed at intervals, and two adjacent high-concentration P-type doped wells 10 are isolated by a groove 16; the doping concentration of the high-concentration P-type doped well 10 is greater than that of the P-type doped semiconductor layer 3; the surface of each high concentration P-type doped well 10 is provided with a light absorbing region 13.
The plurality of high-concentration P-type doped wells 10 are connected to the quenching resistor 14 in a one-to-one correspondence manner; each group of high-concentration P-type doped well 10 and quenching resistor 14 are led out together to form an anode; a cathode is led out from the upper end of the conductive metal 8 in the groove 16.
In the photomultiplier, the N-type doped semiconductor layer 2, the P-type doped semiconductor layer 3 and the high-concentration P-type doped well 10 are stacked to form a PIN structure to be used as a single photon avalanche diode; the electrode led out from the groove 16 is a cathode 18, and the electrode formed by connecting the quenching resistor 14 and the PIN in series is used as an anode 17; the single photon avalanche diode and a quenching resistor 14 are combined into a single element; the grid-like grooves 16 separate the plurality of microelements and realize the parallel connection of the plurality of microelements. The photomultiplier of fig. 3 to 5 has the following advantages compared to the photomultiplier shown in fig. 2: (1) Due to the low doping concentration of the P-type doped semiconductor layer 3 and the high concentration P-type doped well 10, the tunneling effect is reduced, so that the dark count rate is lower; (2) The metal in the groove 16 has multiple functions, can not only block light, but also be used as an extraction electrode of the cathode 18, and the extraction electrode is not required to be additionally manufactured, so that the area of a chip is saved; (3) The cathode 18 and anode 17 are led out from the same side of the substrate 1 and are compatible with existing CMOS processes.
In the above photomultiplier tube provided by the present invention, the substrate 1 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., and the corresponding top layer semiconductor material is silicon, germanium, silicon germanium, gallium arsenide, etc. The substrate 1 may also be a stacked structure of layers of semiconductor material. The substrate 1 may also be doped. In some embodiments, the substrate 1 is a P-type silicon substrate 1, exhibiting a faster integration speed.
In the above photomultiplier tube, the P-type heavily doped region 11 may be formed on the shallow surface of the high-concentration P-type doped well 10 by ion implantation or the like. The doping concentration of the P-type heavily doped region 11 is greater than that of the high-concentration P-type doped well 10, and the P-type heavily doped region 11 is connected with the anode, so that the effect of reducing contact resistance can be achieved. I.e. the more heavily doped P-type region 11 is used for connecting the electrodes.
The doping concentration of each P region can be appropriately adjusted according to actual needs, so long as the doping concentration of the P-type doped semiconductor layer 3 < the doping concentration of the high-concentration P-type doped well 10 < the doping concentration of the P-type heavily doped region 11 is satisfied. For example, in some embodiments, the doping concentration of the P-type doped semiconductor layer 3 is about 10 16cm-3, the doping concentration of the high-concentration P-type doped well 10 is about 10 to 17cm-3, and the doping concentration of the P-type heavily doped region 11 is about 10 to 20cm-3.
In addition, the conductive metal 8 in the trench 16 and the N-type doped semiconductor layer 2 may be connected by a metal silicide layer 9. The metal silicide layer 9 can reduce the contact resistance between the metal and silicon. The conductive metal 8 may be Al or other metallic material. The metal silicide layer 9 may be a silicide of Co, ni, cr, or the like. The first insulating layer 7 on the side wall of the trench 16 may be a material that is excellent in insulation property such as silicon oxide and is easy to integrate, and the bottom wall of the trench 16 is not an insulating material.
In some embodiments, the trench 16 may extend into a portion of the depth of the N-doped semiconductor layer 2 in order to better electrically conductive contact between the cathode 18 and the N-doped semiconductor layer 2.
In some embodiments, the high concentration P-type doped well 10 is provided with an anti-reflection layer 4 at the surface of the light absorbing region 13. If the anti-reflection layer 4 is not arranged, the light absorption region 13 of the high-concentration P-type doped well 10 is usually an exposed surface, and the anti-reflection layer 4 is added on the exposed surface, so that the light absorption rate can be improved, and the photoelectric detection efficiency and the result accuracy can be improved.
In some embodiments, as shown in fig. 3-5, quench resistors 14 are disposed around the periphery of their corresponding high concentration P-type doped wells 10 and have two opposite free ends, one end conductively connected to their corresponding high concentration P-type doped wells 10 and the other end connected to the anode. The quenching resistor 14 can achieve the following effects by adopting the structure: the resistance is adjusted by its length bypassing the high concentration P-type doped well 10. The quenching resistor 14 may be made of polysilicon.
Further, a second insulating layer 5 is stacked above the quenching resistor 14 in sequence from bottom to top, the anode is electrically connected with the quenching resistor 14 through a contact plug 12 penetrating through the second insulating layer 5, and the cathode is connected with the upper end of the conductive metal 8 in the trench 16 through the contact plug 12 penetrating through the second insulating layer 5. The design can protect the electrode and is convenient to process.
In addition, a passivation layer 6 is typically provided over the second insulating layer 5 for protecting the device.
The present invention also provides a method of preparing the photomultiplier of FIGS. 3 to 5, which essentially comprises the following steps (described with reference to FIGS. 3 to 5).
In step S1, a semiconductor substrate 1 is provided, and corresponding processing is performed according to whether the substrate 1 needs to be doped or undoped.
In step S2, an N-type doped semiconductor layer 2 is formed on the upper surface of the semiconductor substrate 1, in which a new N-type doped semiconductor layer 2 is deposited, or N-type ion implantation is performed on the shallow surface layer of the semiconductor substrate 1. The doping concentration of the N-type doped semiconductor layer 2 may be about 10 20cm-3. If a new N-doped semiconductor layer 2 is deposited, it may be any semiconductor material, such as silicon, germanium-silicon composite, etc.
And S3, forming a P-type doped semiconductor layer 3 on the upper surface of the N-type doped semiconductor layer 2, wherein a layer of P-type epitaxial layer can be grown on the silicon wafer by using a vapor phase epitaxy method, the doping concentration of the P-type epitaxial layer is about 10 16cm-3, and the thickness of the P-type epitaxial layer can be 5-10 mu m.
In step S4, a trench 16 is etched into the P-type doped semiconductor layer 3 through to the N-type doped semiconductor layer 2. This step can be achieved by means of a plurality of steps. For example, a silicon dioxide buffer layer and a silicon nitride layer are grown above the P-type doped semiconductor layer 3 as hard masks, and then a deep trench 16 is etched on the epitaxial layer by photolithography and etching processes, wherein the depth of the trench 16 can be slightly larger than the thickness of the P-type doped semiconductor layer 3 and is in contact with the N-type doped semiconductor layer 2.
In step S5, the first insulating layer 7 is formed only on the side walls of the trench 16. This step may be accomplished in either of two steps.
In step S5A, siO 2 is filled into trench 16 using chemical vapor deposition and SiO 2 is planarized using chemical mechanical polishing. And removing SiO 2 filling materials at the center and the bottom wall of the groove 16 by adopting photoetching and etching processes, exposing the N-type doped semiconductor layer 2 at the bottom, and only leaving SiO 2 on the side wall.
Or in step S5B, a thin oxide layer is grown in the trench 16 by thermal oxidation, and the thermal oxide layer at the bottom of the trench 16 is removed by anisotropic etching, exposing the N-type doped semiconductor layer 2 at the bottom, and leaving only the sidewall layer as the first insulating layer 7.
Next, in step S6, the trench 16 may be filled with a conductive metal 8, which may be Al, using a sputtering method; then flattening by chemical mechanical polishing; and then removing the sacrificial layers such as hard masks and the like which are possibly used in the previous steps by using chemical etching liquid.
Before step S6, a metal silicide layer 9 may be formed at the bottom of the trench 16, and the following step S6' may be adopted:
A thin metal layer, which may be Co, ni, cr or the like, is formed by sputtering, and then an annealing operation is performed to chemically react the thin metal layer with silicon at the bottom of the trench 16 to form a metal silicide, and then a chemical etching solution is used to remove the excess metal which does not participate in the chemical reaction, so that the formed metal silicide layer 9 is advantageous for reducing contact resistance.
In step S7, P-type ions are doped in a plurality of regions of the shallow surface layer of the P-type doped semiconductor layer 3, so as to form a plurality of high-concentration P-type doped wells 10, and two adjacent high-concentration P-type doped wells 10 are isolated by the trench 16, wherein the doping concentration of the high-concentration P-type doped wells may be 10 17cm-3. In order to reduce the resistance of the connection electrode of the P-type doped semiconductor layer 3, the P-type doped semiconductor layer 3 may be further doped in a predetermined light absorption region 13 (for example, a central position), so as to form a P-type heavily doped region 11, where the doping concentration may be 10 20cm-3.
Step S8, an anti-reflection layer 4 is grown over the P-type doped semiconductor layer 3 by chemical vapor deposition, which is optional.
In step S9, quenching resistors 14 are formed above each P-type heavily doped region 11 in a one-to-one correspondence manner as pixel units (i.e. microelements). The quenching resistor 14 may be disposed around the periphery of its corresponding P-type heavily doped region 11 and has two opposite free ends, one end conductively connected to its corresponding high concentration P-type doped well 10 and the other end for an extraction electrode. The material of the quenching resistor 14 can be polysilicon, and the patterning can be performed by means of photolithography.
In step S10, the second insulating layer 5 is formed by chemical vapor deposition, and a plurality of contact holes are formed by photolithography and etching processes, and for each pixel unit, there is a contact hole leading to the free end of the extraction electrode of the quenching resistor 14 and a contact hole leading to the conductive metal 8 in the trench 16. The contact holes are then filled with metal and planarized to form contact plugs 12.
In step S11, a metal layer 15 may be sputtered on the upper end of the contact plug 12 and patterned by photolithography and etching processes, i.e., an anode (i.e., anode 17) and a cathode (i.e., cathode 18) are drawn. Because all the pixel units share the N-type doped semiconductor layer, if all the grooves are interconnected, only a cathode is led out from the groove of one pixel unit, and complex wiring is omitted.
In step S12, chemical vapor deposition is used to fabricate the passivation layer 6.
In step S13, the passivation layer, the insulating layer, and other layers unfavorable for light absorption above the predetermined light absorption region 13 (typically disposed on a portion of the surface of the P-type heavily doped region 11) are removed by photolithography and etching processes, so as to expose the anti-reflection layer (if no anti-reflection layer is present, the surface of the P-type heavily doped region 11 is directly exposed).
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (12)
1. A photomultiplier tube comprising a substrate and a plurality of trenches disposed on the substrate; sequentially stacking an N-type doped semiconductor layer and a P-type doped semiconductor layer on the upper surface of the substrate from bottom to top; the groove penetrates through the P-type doped semiconductor layer to be in contact with the N-type doped semiconductor layer, a first insulating layer is arranged on the side wall of the groove, and the center of the groove is filled with conductive metal; the grooves are intersected to form a grid shape;
The shallow surface layer of the P-type doped semiconductor layer is provided with a plurality of high-concentration P-type doped wells distributed at intervals, and two adjacent high-concentration P-type doped wells are isolated by the groove; the doping concentration of the high-concentration P-type doping well is larger than that of the P-type doping semiconductor layer; the surface of each high-concentration P-type doped well is provided with a light absorption region;
The plurality of high-concentration P-type doped wells are connected to the quenching resistor in a one-to-one correspondence manner; each group of high-concentration P-type doped wells and the quenching resistor are led out together to form an anode; and a cathode is led out from the upper end of the conductive metal in the groove.
2. The photomultiplier tube of claim 1, wherein the substrate is a P-type silicon substrate.
3. The photomultiplier tube of claim 1, wherein the shallow surface of the high-concentration P-type doped well is a P-type heavily doped region having a doping concentration greater than that of the high-concentration P-type doped well, and the anode is connected to the P-type heavily doped region.
4. The photomultiplier tube of claim 1, wherein the conductive metal in the trench is connected to the N-doped semiconductor layer by a metal silicide layer.
5. The photomultiplier tube of any one of claims 1-4, wherein the high concentration P-type doped well is provided with an anti-reflective layer on a surface of the light absorbing region.
6. The photomultiplier tube of any one of claims 1-4, wherein the quenching resistor is disposed around the periphery of its corresponding high concentration P-doped well and has two opposite free ends, one end conductively connected to its corresponding high concentration P-doped well and the other end connected to the anode.
7. The photomultiplier of any one of claims 1-4, further comprising: and the anode is electrically connected with the quenching resistor through a contact plug penetrating through the second insulating layer, and the cathode is connected with the upper end of the conductive metal in the groove through the contact plug penetrating through the second insulating layer.
8. The method for manufacturing a photomultiplier tube according to claim 1, comprising:
Providing a semiconductor substrate;
Forming an N-type doped semiconductor layer on the upper surface of the semiconductor substrate;
forming a P-type doped semiconductor layer on the upper surface of the N-type doped semiconductor layer;
etching a groove penetrating to the N-type doped semiconductor layer in the P-type doped semiconductor layer;
Forming a first insulating layer only on the side wall of the groove, and filling conductive metal in the center;
continuing doping P-type ions in a plurality of areas of the shallow surface layer of the P-type doped semiconductor layer to form a plurality of high-concentration P-type doped wells, wherein two adjacent high-concentration P-type doped wells are isolated by the groove;
Forming quenching resistors above each high-concentration P-type doped well in a one-to-one correspondence manner, wherein the quenching resistors are used as pixel units, and part of the surface of each high-concentration P-type doped well is used as a light absorption region;
interconnecting the high-concentration P-type doped well and the quenching resistor in each pixel unit, leading out an anode together, and leading out a cathode from the upper end of the conductive metal in the groove.
9. The method of claim 8, further comprising, after the high concentration P-type doped well: and continuing to perform P-type doping on the shallow surface layer of the high-concentration P-type doping well to form a P-type heavily doped region, wherein the anode is connected with the P-type heavily doped region.
10. The method of manufacturing a photomultiplier tube according to claim 8, wherein the method of forming the first insulating layer comprises:
the first insulating layer is formed by a thermal oxidation growth method or a chemical vapor deposition method.
11. The method of manufacturing a photomultiplier tube according to claim 8, further comprising, after forming the first insulating layer on the side walls of the trench and before filling the center of the trench with a conductive metal:
And forming a metal silicide layer at the bottom of the groove.
12. The method of manufacturing a photomultiplier tube of claim 8, further comprising: and forming an anti-reflection layer on the surface of the light absorption region of the high-concentration P-type doped well.
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| CN202410222800.1A CN118198081A (en) | 2024-02-28 | 2024-02-28 | Photomultiplier and preparation method thereof |
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| CN202410222800.1A CN118198081A (en) | 2024-02-28 | 2024-02-28 | Photomultiplier and preparation method thereof |
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