CN118198057A - Self-protection shielding grid power device drain electrode front extraction structure and manufacturing method thereof - Google Patents
Self-protection shielding grid power device drain electrode front extraction structure and manufacturing method thereof Download PDFInfo
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- CN118198057A CN118198057A CN202211706305.5A CN202211706305A CN118198057A CN 118198057 A CN118198057 A CN 118198057A CN 202211706305 A CN202211706305 A CN 202211706305A CN 118198057 A CN118198057 A CN 118198057A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000605 extraction Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims description 46
- 238000002513 implantation Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 3
- 238000007521 mechanical polishing technique Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000004321 preservation Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 10
- 238000005498 polishing Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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Abstract
The invention discloses a self-protection shielding grid power device drain electrode front-side leading-out structure and a manufacturing method thereof. The self-protection SGT MOT and various protection circuits are integrated on one chip through the manufacturing process by combining the self-protection power device and the SGT MOS, so that the technical difficulty is solved, the process compatibility of the self-protection circuits is realized, and the high integration of the circuit module and the power module is realized.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a self-protection shielding grid power device drain electrode front extraction structure and a manufacturing method thereof.
Background
The self-protection power Device is characterized in that a Bipolar Device (BJT for short), a complementary metal Oxide Semiconductor (Complementary Metal-Oxide-Semiconductor for short) and the power Device are manufactured on the same chip, and the technology integrates the advantages of high transconductance and strong load driving capability of the BJT Device, high integration level and low power consumption of the CMOS, and more importantly, the advantages of high voltage and high current of the power Device.
The birth of the self-protection power device shows that the self-detection and self-protection functions can be realized while the performance of the power switch device is enhanced, the cost of the system is reduced, and the reliability is improved, so that the self-protection power device is widely applied in the field of automobile electronics.
In general, voltage withstanding voltages of about 70V are used in automotive electronics, while SGT MOS has been shown to have lower specific on-resistance and lower switching loss in low voltage applications than Vertical Double-diffused metal oxide semiconductor (VDMOS) applications. However, integration of the self-protection SGT MOT and various protection circuits, including an over-current protection circuit, an over-temperature protection circuit, and an electrostatic discharge (Electro-STATIC DISCHARGE abbreviated as ESD) protection circuit for a gate electrode, on a chip through a process integration technology with relatively high process compatibility becomes a difficulty.
Disclosure of Invention
In order to solve the problems, the invention provides a drain front-face extraction structure of a self-protection shielding grid power device and a manufacturing method thereof, and the process compatibility of a self-protection circuit is realized.
The invention provides a drain electrode front extraction structure of a self-protection shielding grid electrode power device and a manufacturing method thereof.
A self-protection shielding grid power device drain electrode front side leading-out structure utilizes a mode of combining a deep groove etching technology, a groove bottom oxide layer etching technology and a polysilicon (Polysilicon is called POLY) filling technology to lead the SGT drain electrode to the front side of the device.
The manufacturing method of the drain electrode front-side extraction structure of the self-protection shielding grid electrode power device specifically comprises the following steps:
The utility model provides a self preservation protects shielding grid power device drain electrode front and draws forth structure which characterized in that:
and the drain electrode of the SGT is led to the front surface of the device by utilizing a mode of combining a deep groove etching process, a groove bottom oxide layer etching technology and a polysilicon filling technology.
The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device as claimed in claim 1, comprising the following steps:
Step one: injecting a first N-type injection region serving as an N-type buried layer on the P-type substrate;
Step two: growing a first N-type epitaxial layer on the P-type substrate;
step three: depositing a mask dielectric layer, and etching a drain potential leading-out drain groove and an SGT groove;
step four: after sacrificial oxidation of the side wall and the bottom of the groove, depositing a first dielectric layer, and etching an oxide layer at the bottom of the drain groove by using a mask;
step five: depositing first N-type Poly, grinding and back-etching the Poly by using a chemical mechanical polishing technology and a dry etching technology to form a field plate of the SGT and an outlet end of the drain electrode groove;
Step six: etching the first dielectric layer by using a mask plate and adopting a wet process;
Step seven: growing the gate oxide of the SGT in a thermal oxidation mode;
Step eight: depositing a second N-type Poly, and grinding and back-etching the Poly by using a chemical mechanical polishing technology and a dry etching technology to form an SGT gate;
step nine: an ion implantation mode is adopted, a mask plate is utilized to sequentially manufacture a second N-type implantation region, a first P-type implantation region and a third N-type implantation region, and after well region is manufactured, field oxygen is grown to serve as an isolation medium between devices;
step ten: growing high-quality gate oxide on the epitaxial layer in a hot oxygen mode, depositing a layer of polycrystal on the high-quality gate oxide, and forming grids of the N-type metal oxide semiconductor and the P-type metal oxide semiconductor through an etching process;
step eleven: adopting an ion implantation mode, and sequentially making a fourth N-type implantation region and a second P-type implantation region by using a mask plate to form drain electrode and source electrode contacts of the metal oxide semiconductor, and emitter electrode, base electrode and collector electrode contacts of the BJT;
Step twelve: and depositing a second interlayer dielectric layer, etching the lead holes, and depositing top metal.
And in the first N-type implantation region, the implantation dosage is within the range of 1e17cm -2~5e18cm-2, and the implantation energy is within the range of 100 KeV-300 KeV.
And step three, the drain potential leading-out drain groove CD is 1.5-2 times of the SGT groove CD, two grooves with different depths are etched through a load effect, and the drain potential leading-out drain groove needs to penetrate through the first N-type epitaxial layer and is connected to the first N-type injection region.
And step six, the thickness of the first dielectric layer is adjusted according to the voltage resistance of the SGT, and the thickness is in the range of 0.2-0.25 mu m.
And thirdly, performing dry etching on the oxide layer at the bottom of the drain electrode groove by using a mask plate, and performing groove bottom injection at the bottom of the drain electrode groove, wherein the injection dosage is within the range of 1e15cm -2~1e16 cm-2, and the injection energy is within the range of 50 KeV-100 KeV.
And step five, the doping concentration of the first N type Poly is in the range of 1e17cm -3~1e18cm-3.
And step nine, specifically, si 3N4 is used as a mask, then field oxygen growth is carried out, and the thickness is 0.1-0.3 mu m, so that the silicon nitride film is used as an isolation medium layer between devices.
The invention leads the drain electrode of the SGT to the front surface of the device by combining the deep groove etching technology, the groove bottom oxide layer etching technology and the polysilicon (Polysilicon is called POLY) filling technology, thereby realizing the process compatibility of the self-protection circuit and realizing the high integration of the circuit module and the power module.
Drawings
The invention is described in further detail below with reference to the attached drawings and the detailed implementation method:
FIG. 1 is a schematic diagram of a second step of the manufacturing method according to the present invention;
FIG. 2 is a schematic diagram of a third step of the manufacturing method according to the present invention;
FIG. 3 is a schematic diagram of a fourth step of the manufacturing method according to the present invention;
FIG. 4 is a schematic diagram of a fifth step of the manufacturing method according to the present invention;
FIG. 5 is a step six schematic diagram of the manufacturing method according to the present invention;
FIG. 6 is a schematic diagram of a seventh step of the manufacturing method of the present invention;
FIG. 7 is a schematic diagram of a step eight of the manufacturing method according to the present invention;
FIG. 8 is a schematic diagram of a step nine of the manufacturing method according to the present invention;
FIG. 9 is a schematic diagram of a step eleven of the manufacturing method of the present invention;
fig. 10 is a schematic diagram showing steps of the manufacturing method according to the present invention.
In the figure, a P-type substrate 001, a first N-type injection region 002, a first N-type epitaxial layer 003, a drain potential extraction drain groove 004, an sgt groove 005, a first dielectric layer 006, a first N-type Poly 007, a gate oxide 008, a second N-type Poly 009, a second N-type injection region 010, a first P-type injection region 011, a third N-type injection region 012, a field oxide 013, a gate 014, a fourth N-type injection region 015, a second P-type injection region 016, a second interlayer dielectric layer 017, a wire hole 018, and a top metal 019.
Detailed Description
As shown in fig. 1 to 10, the present embodiment discloses a drain front extraction structure of a self-protection shielded gate power device and a manufacturing method thereof.
The manufacturing method comprises the following steps:
the method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device as claimed in claim 1, comprising the following steps:
step one: the first N-type implantation region 002 is implanted on the P-type substrate 001 to serve as an N-type buried layer, the implantation dosage is within the range of 1e17cm -2~5e18cm-2, and the implantation energy is within the range of 100 KeV-300 KeV;
Step two: as shown in fig. 1, a first N-type epitaxial layer 003 is grown on a P-type substrate;
Step three: as shown in fig. 2, a mask dielectric layer is deposited, drain potential leading-out drain groove 004 and SGT groove 005 are etched, drain potential leading-out drain groove CD is 1.5-2 times of SGT groove CD, two grooves with different depths are etched through a load effect, and drain potential leading-out drain groove needs to penetrate through a first N-type epitaxial layer and is connected to a first N-type injection region; the specific etching method comprises the steps of carrying out dry etching on an oxide layer at the bottom of a drain electrode groove by using a mask plate, and carrying out groove bottom injection at the bottom of the drain electrode groove, wherein the injection dosage is within the range of 1e15cm -2~1e16 cm-2, and the injection energy is 50 KeV-100 KeV;
Step four: as shown in fig. 3, after sacrificial oxidation of the sidewall and bottom of the trench, a first dielectric layer 006 is deposited, and the oxide layer at the bottom of the drain trench is etched away by using a mask;
Step five: as shown in fig. 4, a first N-type Poly 007 is deposited, and the field plate of the SGT and the drain trench leading-out end are formed by Polishing and back etching the Poly using a chemical mechanical Polishing technique (CHEMICAL MECHANICAL Polishing CMP) and a dry etching process in the range of 1e17cm -3~1e18cm-3 of the doping concentration of the N-type Poly;
step six: as shown in fig. 5, the first dielectric layer 006 is etched away using a wet process using a mask; the thickness of the first medium is regulated according to the withstand voltage of SGT, and the thickness is in the range of 0.2-0.25 mu m;
step seven: as shown in fig. 6, the gate oxide 008 of the SGT is grown by thermal oxidation;
Step eight: as shown in fig. 7, a second N-type Poly 009 is deposited, ground and etched back using CMP and dry etching processes to form an SGT gate;
step nine: as shown in fig. 8, an ion implantation mode is adopted, a second N-type implantation region 010, a first P-type implantation region 011 and a third N-type implantation region 012 are sequentially made by using a mask plate, after a well region is made, field oxygen 013 is grown as an isolation medium between devices, specifically Si 3N4 is used as a mask, and then field oxygen growth is performed, wherein the thickness of the field oxygen is 0.1-0.3 μm, and the field oxygen is used as an isolation medium layer between devices;
Step ten: growing high-quality gate Oxide on the epitaxial layer by a thermal oxygen mode, depositing a layer of polycrystal on the high-quality gate Oxide, and forming a grid 014 of an N-Metal-Oxide-Semiconductor (NMOS) and a P-Metal-Oxide-Semiconductor (PMOS) through an etching process;
Step eleven: as shown in fig. 9, an ion implantation method is adopted, and a mask is used to sequentially make a fourth N-type implantation region 015 and a second P-type implantation region 016, so as to form a drain electrode and a source electrode contact of a Metal-Oxide-Semiconductor (MOS), and an emitter electrode, a base electrode and a collector electrode of a BJT are contacted;
Step twelve: as shown in fig. 10, a second interlayer dielectric layer 017 is deposited, lead holes 018 are etched, and a top layer metal 019 is deposited.
The above examples are illustrative of the present invention in detail, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (8)
1. The utility model provides a self preservation protects shielding grid power device drain electrode front and draws forth structure which characterized in that:
and the drain electrode of the SGT is led to the front surface of the device by utilizing a mode of combining a deep groove etching process, a groove bottom oxide layer etching technology and a polysilicon filling technology.
2. The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device as claimed in claim 1, comprising the following steps:
step one: a first N-type injection region (002) is injected on the P-type substrate (001) to be used as an N-type buried layer;
step two: growing a first N-type epitaxial layer (003) on the P-type substrate;
step three: depositing a mask dielectric layer, and etching a drain potential leading-out drain groove (004) and an SGT groove (005);
step four: after sacrificial oxidation of the side wall and the bottom of the groove, a first dielectric layer (006) is deposited, and an oxide layer at the bottom of the drain groove is etched by using a mask;
Step five: depositing a first N-type Poly (007), grinding and back-etching the Poly using a chemical mechanical polishing technique and a dry etching process to form a field plate of the SGT, and an exit end of the drain trench;
step six: etching the first dielectric layer (006) by using a mask plate and adopting a wet process;
Step seven: growing the gate oxide of the SGT by thermal oxidation (008);
step eight: depositing a second N-type Poly (009), and grinding and etching back the Poly by using a chemical mechanical polishing technique and a dry etching technique to form an SGT gate;
Step nine: an ion implantation mode is adopted, a mask plate is utilized to sequentially manufacture a second N-type implantation region (010), a first P-type implantation region (011) and a third N-type implantation region (012), and after a well region is manufactured, field oxygen (013) is grown to serve as an isolation medium between devices;
Step ten: growing high-quality gate oxide on the epitaxial layer by a thermal oxygen mode, depositing a layer of polycrystal on the high-quality gate oxide, and forming grid electrodes of the N-type metal oxide semiconductor and the P-type metal oxide semiconductor through an etching process (014);
step eleven: adopting an ion implantation mode, and sequentially making a fourth N-type implantation region (015) and a second P-type implantation region (016) by using a mask plate to form a drain electrode and a source electrode contact of a metal oxide semiconductor, and an emitter electrode, a base electrode and a collector electrode of a BJT;
Step twelve: a second interlayer dielectric layer (017) is deposited, the lead holes (018) are etched, and a top metal (019) is deposited.
3. The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device according to claim 2, wherein the method comprises the following steps:
And in the first N-type implantation region, the implantation dosage is within the range of 1e17cm -2~5e18cm-2, and the implantation energy is within the range of 100 KeV-300 KeV.
4. The method for manufacturing the drain front extraction structure of the self-protection shielded gate power device according to claim 3, wherein the method comprises the following steps:
and step three, the drain potential leading-out drain groove CD is 1.5-2 times of the SGT groove CD, two grooves with different depths are etched through a load effect, and the drain potential leading-out drain groove needs to penetrate through the first N-type epitaxial layer and is connected to the first N-type injection region.
5. The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device according to claim 4, wherein the method comprises the following steps:
And step six, the thickness of the first dielectric layer is adjusted according to the voltage resistance of the SGT, and the thickness is in the range of 0.2-0.25 mu m.
6. The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device according to claim 5, wherein the method comprises the following steps:
And thirdly, performing dry etching on the oxide layer at the bottom of the drain electrode groove by using a mask plate, and performing groove bottom injection at the bottom of the drain electrode groove, wherein the injection dosage is within the range of 1e15cm -2~1e16 cm-2, and the injection energy is within the range of 50 KeV-100 KeV.
7. The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device according to claim 6, wherein the method comprises the following steps:
and step five, the doping concentration of the first N type Poly is in the range of 1e17cm -3~1e18cm-3.
8. The method for manufacturing the drain front-side extraction structure of the self-protection shielded gate power device according to claim 7, wherein the method comprises the following steps:
and step nine, specifically, si 3N4 is used as a mask, then field oxygen growth is carried out, and the thickness is 0.1-0.3 mu m, so that the silicon nitride film is used as an isolation medium layer between devices.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211706305.5A CN118198057A (en) | 2022-12-29 | 2022-12-29 | Self-protection shielding grid power device drain electrode front extraction structure and manufacturing method thereof |
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| CN202211706305.5A CN118198057A (en) | 2022-12-29 | 2022-12-29 | Self-protection shielding grid power device drain electrode front extraction structure and manufacturing method thereof |
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| CN118198057A true CN118198057A (en) | 2024-06-14 |
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| CN202211706305.5A Pending CN118198057A (en) | 2022-12-29 | 2022-12-29 | Self-protection shielding grid power device drain electrode front extraction structure and manufacturing method thereof |
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