CN118192884A - Read-write control method, nonvolatile memory and control device - Google Patents
Read-write control method, nonvolatile memory and control device Download PDFInfo
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Abstract
The application discloses a read-write control method, a nonvolatile memory and a control device, wherein the nonvolatile memory comprises: a first MUX connected to the first bus and the second bus, respectively; a configuration module connected to the first MUX; the memory unit comprises a first memory space, a second memory space and a third memory space, wherein the first memory space is used for storing chip calibration data, the second memory space is a reserved space with adjustable space capacity, the first space configuration value is a space configuration value of the second memory space, and the first space configuration value is determined according to the data volume of the chip calibration data and the space capacity of the memory unit; and the controller module is respectively connected with the storage unit and the configuration module. The capacity of the reserved space in the storage unit is dynamically determined based on the data size required to be programmed and the capacity of the storage unit, so that the storage unit is dynamically divided, and the address space utilization rate of the nonvolatile storage device can be effectively improved.
Description
Technical Field
The present application relates to the field of data storage technologies, but is not limited to, and in particular, to a read/write control method, a nonvolatile memory, and a control device.
Background
After the chip is manufactured and leaves the factory, because the process influences, the working voltage, current, clock and other important factors of the chip have deviation, the system cannot work stably and normally after the chip is electrified, the system is abnormal in function and seriously damages the chip, so that the chip needs to enter a testing stage after the chip is manufactured, the important parameters required by the chip system are calibrated, data are stored in a nonvolatile memory device, and the calibration value can be automatically loaded to finish the calibration when the chip is used. In the prior art, a whole nonvolatile memory device is used for storing calibration values, and due to the limited capacity of the nonvolatile memory device, a part of address space is reserved in the nonvolatile memory device, so that when the number of the system calibration values is required to be changed, the address allocation of the memory device cannot be flexibly changed, but the address space utilization rate of the nonvolatile memory device is not high due to the mode, and unused addresses cannot be effectively used.
Disclosure of Invention
The embodiment of the application provides a read-write control method, a nonvolatile memory and a control device, which can effectively improve the address space utilization rate of a nonvolatile memory device.
In a first aspect, an embodiment of the present application provides a nonvolatile memory, including:
The first MUX is connected with the first bus and the second bus respectively, wherein the first MUX conducts the first bus or the second bus based on a bus selection signal;
the configuration module is connected with the first MUX;
The storage unit comprises a first storage space, a second storage space and a third storage space, wherein the first storage space is used for storing chip calibration data, the second storage space is a reserved space with adjustable space capacity, the third storage space is used for storing a first space configuration value, the first space configuration value is a space configuration value of the second storage space, and the first space configuration value is determined according to the data volume of the chip calibration data and the space capacity of the storage unit;
And the controller module is respectively connected with the storage unit and the configuration module.
In some embodiments, the controller module is connected to the configuration module through a second MUX that is also connected to the third memory space, wherein the second MUX turns on the third memory space and the configuration module or turns on the third memory space and the controller module based on a second memory space parameter path signal.
In a second aspect, an embodiment of the present application provides a read-write control method, where the method is applied to the nonvolatile memory of the first aspect, and the method includes:
When the nonvolatile memory is powered on, the first MUX conducts the first bus based on the bus selection signal, the configuration module configures chip calibration data and a first burning address, and determines the first space configuration value based on the data amount of the chip calibration data and the space capacity of the memory unit, wherein the first burning address is an address for burning the chip calibration data in the memory unit;
The configuration module configures a second burning address, and sends a first trigger signal carrying the second burning address to the controller module, so that the controller module burns the first space configuration value into the third storage space, wherein the second burning address is an address for burning the first space configuration value in the storage unit;
The configuration module sends a second trigger signal carrying the first burning address to the controller module so that the controller module burns the chip calibration data into the first storage space;
the first MUX conducts the second bus based on the bus selection signal, generates a second trigger signal through the configuration module and sends the second trigger signal to the controller module;
the controller module reads the first space configuration value from the third storage space, sends the first space configuration value to the configuration module, and stores the first space configuration value to the controller module and the configuration module respectively;
The controller module polls and reads the chip calibration data in the first storage space based on the first space configuration value and sends the chip calibration data to the configuration module.
In some embodiments, the controller module is connected to the configuration module through a second MUX that is also connected to the third memory space, wherein the second MUX turns on the third memory space to the configuration module or turns on the third memory space to the controller module based on a second memory space parameter path signal, the method further comprising:
when the first space configuration value is detected to be not matched with the data quantity of the chip calibration data, the second MUX conducts the third storage space and the configuration module based on the second storage space parameter access signal;
triggering the controller module to read the chip calibration data of the first storage space and the first space configuration value of the third storage space through the configuration module;
The controller module sends the chip calibration data and the first spatial configuration value to the configuration module;
the configuration module redetermines a second spatial configuration value based on the chip calibration data;
The first MUX conducts the first bus based on the bus selection signal, the configuration module reconfigures a second burning address, and resends a first trigger signal carrying the second burning address to the controller module so that the controller module burns the second space configuration value into the third storage space.
In some embodiments, the method further comprises:
The first MUX conducts the second bus based on the bus selection signal, and the configuration module configures preset type data;
Generating a third trigger signal carrying the first space configuration value through the configuration module, and sending the third trigger signal to the controller module;
The controller module burns the preset type data to the second storage space based on the first space configuration value.
In some embodiments, the method further comprises:
And stopping the operation of burning the data of the preset type to the second storage space when the burning address corresponding to the first space configuration value is detected to exceed the address range of the second storage space.
In some embodiments, the method further comprises:
the first MUX conducts the second bus based on the bus selection signal, and the configuration module triggers the controller module to read the data of the second storage space;
The controller module sends the data of the second storage space to the configuration module, and stores the data of the second storage space to the configuration module.
In a third aspect, an embodiment of the present application provides a control apparatus, including at least one control processor and a memory for communicatively coupling with the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the read-write control method as described in the first aspect.
The embodiment of the application provides a read-write control method, a nonvolatile memory and a control device, wherein the nonvolatile memory comprises: the first MUX is connected with the first bus and the second bus respectively, wherein the first MUX conducts the first bus or the second bus based on a bus selection signal; the configuration module is connected with the first MUX; the storage unit comprises a first storage space, a second storage space and a third storage space, wherein the first storage space is used for storing chip calibration data, the second storage space is a reserved space with adjustable space capacity, the third storage space is used for storing a first space configuration value, the first space configuration value is a space configuration value of the second storage space, and the first space configuration value is determined according to the data volume of the chip calibration data and the space capacity of the storage unit; and the controller module is respectively connected with the storage unit and the configuration module. According to the scheme provided by the embodiment of the application, the capacity of the reserved space in the storage unit is dynamically determined based on the data volume to be programmed and the capacity of the storage unit, so that the storage unit is dynamically divided, and the address space utilization rate of the nonvolatile memory device can be effectively improved.
Drawings
FIG. 1 is a schematic diagram of a nonvolatile memory according to one embodiment of the present application;
FIG. 2 is a flowchart illustrating steps of a read/write control method according to another embodiment of the present application;
FIG. 3 is a flowchart illustrating a step of burning the second space configuration values into the third memory space according to another embodiment of the present application;
FIG. 4 is a flowchart illustrating a step of burning a predetermined type of data into a second memory space according to another embodiment of the present application;
FIG. 5 is a flowchart showing a step of stopping burning preset type data in a second memory space according to another embodiment of the present application;
FIG. 6 is a flowchart illustrating steps for reading data in a second memory space according to another embodiment of the present application;
Fig. 7 is a block diagram of a control apparatus according to another embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be appreciated that although functional block diagrams are depicted in the device diagrams, logical sequences are shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the block diagrams in the device. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
After the chip is manufactured and leaves the factory, because the process influences, the working voltage, current, clock and other important factors of the chip have deviation, the system cannot work stably and normally after the chip is electrified, the system is abnormal in function and seriously damages the chip, so that the chip needs to enter a testing stage after the chip is manufactured, the important parameters required by the chip system are calibrated, data are stored in a nonvolatile memory device, and the calibration value can be automatically loaded to finish the calibration when the chip is used. In the prior art, a whole nonvolatile memory device is used for storing calibration values, and due to the limited capacity of the nonvolatile memory device, a part of address space is reserved in the nonvolatile memory device, so that when the number of the system calibration values is required to be changed, the address allocation of the memory device cannot be flexibly changed, but the address space utilization rate of the nonvolatile memory device is not high due to the mode, and unused addresses cannot be effectively used.
In order to solve the above-mentioned problems, an embodiment of the present application provides a read-write control method, a nonvolatile memory, and a control device, where the nonvolatile memory includes: the first MUX is connected with the first bus and the second bus respectively, wherein the first MUX conducts the first bus or the second bus based on a bus selection signal; the configuration module is connected with the first MUX; the storage unit comprises a first storage space, a second storage space and a third storage space, wherein the first storage space is used for storing chip calibration data, the second storage space is a reserved space with adjustable space capacity, the third storage space is used for storing a first space configuration value, the first space configuration value is a space configuration value of the second storage space, and the first space configuration value is determined according to the data volume of the chip calibration data and the space capacity of the storage unit; and the controller module is respectively connected with the storage unit and the configuration module. According to the scheme provided by the embodiment of the application, the capacity of the reserved space in the storage unit is dynamically determined based on the data volume to be programmed and the capacity of the storage unit, so that the storage unit is dynamically divided, and the address space utilization rate of the nonvolatile memory device can be effectively improved.
Embodiments of the present application will be further described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a nonvolatile memory according to an embodiment of the present application, and the embodiment of the present application provides a nonvolatile memory, including:
The first MUX is connected with the first BUS BUS1 and the second BUS BUS2 respectively, wherein the first MUX conducts the first BUS BUS1 or the second BUS BUS2 based on a BUS selection signal BUS_SEL;
The configuration module NVM_CFG is connected with the first MUX;
The storage unit comprises a first storage SPACE, a second storage SPACE ADJ-SPACE and a third storage SPACE, wherein the first storage SPACE is used for storing chip calibration data, the second storage SPACE ADJ-SPACE is a reserved SPACE with adjustable SPACE capacity, the third storage SPACE is used for storing a first SPACE configuration value ADJ-VAL, the first SPACE configuration value ADJ-VAL is a SPACE configuration value of the second storage SPACE ADJ-SPACE, and the first SPACE configuration value ADJ-VAL is determined according to the data volume of the chip calibration data and the SPACE capacity of the storage unit;
The controller module NVM_CTRL is connected with the memory unit and the configuration module NVM_CFG respectively.
It should be noted that, the nonvolatile memory according to the embodiments of the present application may be implemented in an ASIC integrated chip or an FPGA chip using a digital circuit, which is not limited herein.
It will be appreciated that the nonvolatile memory of this embodiment includes a first MUX, which is a data selector of either one of two, which is connected to the first BUS1 and the second BUS2, respectively, and which turns on either the first BUS1 or the second BUS2 based on the BUS select signal BUS _ SEL, the logic processing steps of the nonvolatile memory in the chip test stage and the chip working stage are distinguished through the design of the double buses, wherein the nonvolatile memory is in the chip test stage when the first BUS BUS1 is conducted, and the nonvolatile memory is in the chip working stage when the second BUS BUS2 is conducted. In the chip testing stage, the contents of all storage SPACEs in the read-write storage unit can be realized through the combination of the configuration module NVM_CFG and the controller module NVM_CTRL, and in the chip working stage, the data of the first storage SPACE and the third storage SPACE or the data of the second storage SPACE ADJ-SPACE can be read through the combination of the configuration module NVM_CFG and the controller module NVM_CTRL, namely, the read-write permission division of the storage unit is realized through the design structure of the double buses, so that the misoperation of modifying key data operation during the normal working of the chip is prevented, and the system safety is improved.
It can be understood that, because the capacity of the reserved SPACE (i.e., the first SPACE matching value) in the storage unit is dynamically determined based on the data size to be programmed and the capacity of the storage unit, and the sizes of the chip test data corresponding to different chips are different, the specific SPACE capacity sizes and address ranges of the first storage SPACE, the second storage SPACE ADJ-SPACE and the third storage SPACE in the storage unit in the embodiment of the application are dynamically changed based on the data size of the chip calibration data and the capacity size of the storage unit, when the number of the chip calibration data is variable, the controller module nvm_ctrl can be triggered by the configuration module nvm_cfg to meet the time sequence required by the storage unit, control the flexible division of the address SPACE of the storage unit, and effectively improve the address SPACE utilization rate of the nonvolatile memory device.
It should be noted that, the first SPACE configuration value ADJ-VAL stored in the third storage SPACE of the present embodiment is the maximum address range value of the second storage SPACE ADJ-SPACE, and the first SPACE configuration value ADJ-VAL is determined according to the data size of the chip calibration data and the SPACE capacity of the storage unit, so that a person skilled in the art can determine a specific storage gear value of the first SPACE configuration value ADJ-VAL according to the actual situation.
It should be noted that, the dynamic change of the capacity of the second storage SPACE ADJ-SPACE in this embodiment depends on the specific type of the nonvolatile memory, and when the nonvolatile memory is an OTP device, the first SPACE configuration value ADJ-VAL of the second storage SPACE ADJ-SPACE can only be configured once, and the nonvolatile memory in this embodiment may be a FLASH memory, so that multiple configurations and dynamic changes of the first SPACE configuration value ADJ-VAL of the second storage SPACE ADJ-SPACE can be realized.
It should be noted that, in this embodiment, the second BUS2 may be turned on to implement the reading of the custom data in the second storage SPACE ADJ-SPACE, so that the unused reserved address is effectively utilized, thereby effectively improving the address SPACE utilization of the nonvolatile memory device.
In addition, in some embodiments, the controller module nvm_ctrl of the present embodiment is connected to the configuration module nvm_cfg through a second MUX, where the second MUX is further connected to the third memory SPACE, and the second MUX conducts the third memory SPACE with the configuration module nvm_cfg or conducts the third memory SPACE with the controller module nvm_ctrl based on the second memory SPACE ADJ-SPACE parameter path signal.
It will be appreciated that referring to fig. 1, the second storage SPACE parameter path signal space_ctrl_from_reg_sel is a selection signal capable of controlling the second MUX to select the data source of the first SPACE configuration value ADJ-VAL: (1) Configuring a first space configuration value ADJ-VAL from a configuration module nvm_cfg; or (2) acquiring the first SPACE configuration value ADJ-VAL which is burnt into the second storage SPACE ADJ-SPACE.
In addition, referring to fig. 2, fig. 2 is a flowchart showing steps of a read-write control method according to another embodiment of the present application, and the present embodiment provides a read-write control method applied to the nonvolatile memory according to the above embodiment, where the method includes, but is not limited to, the following steps:
Step S210, when the nonvolatile memory is powered on, the first MUX turns on the first BUS BUS1 based on the BUS selection signal BUS_SEL, the configuration module NVM_CFG configures chip calibration data and a first burning address, and determines a first space configuration value ADJ-VAL based on the data amount of the chip calibration data and the space capacity of the memory unit, wherein the first burning address is an address for burning the chip calibration data in the memory unit;
It can be understood that after the chip is powered on normally, the nonvolatile memory of the present embodiment is powered on simultaneously, at this time, the first MUX conducts the first BUS1 based on the BUS select signal bus_sel, so that the nonvolatile memory is in the chip test stage, at this time, the configuration module nvm_cfg configures the chip calibration data and the first writing address, and determines the first space configuration value ADJ-VAL based on the data amount of the chip calibration data and the space capacity of the memory unit, where the first writing address is the address of the writing chip calibration data in the memory unit, i.e. the address of the first memory space, so that an effective data basis can be provided for writing the chip calibration data into the first memory space and writing the first space configuration value ADJ-VAL into the third memory space. With reference to the description of the foregoing embodiment, since the capacity of the reserved SPACE (i.e., the first SPACE matching value) in the storage unit is dynamically determined based on the size of the data volume to be programmed and the capacity of the storage unit, and the sizes of the chip test data corresponding to different chips are different, the specific SPACE capacities and address ranges of the first storage SPACE, the second storage SPACE ADJ-SPACE and the third storage SPACE in the storage unit in the embodiment of the present application are dynamically changed based on the data volume of the chip calibration data and the capacity size of the storage unit, when the number requirement of the chip calibration data is changed, the controller module nvm_ctrl can be triggered by the configuration module nvm_cfg to meet the time sequence required by the storage unit, and the address SPACE of the storage unit is flexibly divided under control, so that the address SPACE utilization of the nonvolatile memory device is effectively improved.
Step S220, the configuration module NVM_CFG configures a second burning address, and sends a first trigger signal carrying the second burning address to the controller module NVM_CTRL, so that the controller module NVM_CTRL burns the first space configuration value ADJ-VAL into the third storage space, wherein the second burning address is an address for burning the first space configuration value ADJ-VAL in the storage unit;
Step S230, the configuration module NVM_CFG sends a second trigger signal carrying a first burning address to the controller module NVM_CTRL so that the controller module NVM_CTRL burns the chip calibration data into the first memory space;
It should be noted that, after the configuration module nvm_cfg completes the configuration of the first space configuration value ADJ-VAL, the configuration module nvm_cfg configures the address of the first space configuration value ADJ-VAL in the storage unit, i.e. the second address, and sends the first trigger signal carrying the second address to the controller module nvm_ctrl, so that the controller module nvm_ctrl burns the first space configuration value ADJ-VAL into the third storage space; the configuration module NVM_CFG sends a second trigger signal carrying the first burning address to the controller module NVM_CTRL so that the controller module NVM_CTRL burns the chip calibration data into the first storage space, thereby completing the operation of burning the chip calibration data and the first space configuration value ADJ-VAL into the storage unit in the chip test stage and providing an effective data basis for the operation of reading the data in the storage unit in the subsequent chip working stage.
Step S240, the first MUX turns on the second BUS2 based on the BUS selection signal bus_sel, generates a second trigger signal through the configuration module nvm_cfg and sends the second trigger signal to the controller module nvm_ctrl;
Step S250, the controller module NVM_CTRL reads the first space configuration value ADJ-VAL from the third storage space, and sends the first space configuration value ADJ-VAL to the configuration module NVM_CFG, and stores the first space configuration value ADJ-VAL to the controller module NVM_CTRL and the configuration module NVM_CFG respectively;
in step S260, the controller module nvm_ctrl polls and reads the chip calibration data in the first memory space based on the first space configuration value ADJ-VAL, and sends the chip calibration data to the configuration module nvm_cfg.
It can be understood that after the first MUX turns on the second BUS2 based on the BUS selection signal bus_sel, the working phase of the chip is entered, the controller module nvm_ctrl is triggered by the configuration module nvm_cfg to turn on the working state of the read memory unit, first, the configuration module nvm_cfg generates a second trigger signal and sends the second trigger signal to the controller module nvm_ctrl, so that the controller module nvm_ctrl reads the first SPACE configuration value ADJ-VAL from the third memory SPACE, sends the first SPACE configuration value ADJ-VAL to the configuration module nvm_cfg, saves the first SPACE configuration value ADJ-VAL to the controller module nvm_ctrl and the configuration module nvm_cfg, respectively, reads the capacity of the second memory SPACE ADJ-SPACE in the configuration module nvm_cfg through the second bus_cfg, and polls the controller module nvm_ctrl to read the capacity of the second memory SPACE ADJ-SPACE in the configuration module nvm_cfg based on the first SPACE configuration value ADJ-VAL, that is, and the calibration data is calibrated in the first memory SPACE of the chip is completed, and the calibration data is stored in the calibration memory phase of the chip is calibrated.
In addition, referring to fig. 3, in some embodiments, the controller module nvm_ctrl is connected to the configuration module nvm_cfg through a second MUX, and the second MUX is further connected to a third memory SPACE, where the second MUX conducts the third memory SPACE with the configuration module nvm_cfg or conducts the third memory SPACE with the controller module nvm_ctrl based on the second memory SPACE ADJ-SPACE parameter path signal, and the read-write control method of the embodiment of the present application includes, but is not limited to, the following steps:
Step S310, when the data quantity of the first SPACE configuration value ADJ-VAL and the chip calibration data is not matched, the second MUX conducts the third storage SPACE and the configuration module NVM_CFG based on the second storage SPACE ADJ-SPACE parameter channel signal;
Step S320, the controller module NVM_CTRL is triggered to read the chip calibration data of the first storage space and the first space configuration value ADJ-VAL of the third storage space through the configuration module NVM_CFG;
step S330, the controller module nvm_ctrl sends the chip calibration data and the first space configuration value ADJ-VAL to the configuration module nvm_cfg;
Step S340, the configuration module nvm_cfg re-determines the second spatial configuration value based on the chip calibration data;
In step S350, the first MUX turns on the first BUS1 based on the BUS select signal bus_sel, and the configuration module nvm_cfg reconfigures the second writing address and resends the first trigger signal carrying the second writing address to the controller module nvm_ctrl, so that the controller module nvm_ctrl writes the second space configuration value into the third memory space.
In addition, in some embodiments of the present application, when it is detected that the first SPACE configuration value ADJ-VAL does not match the data amount of the chip calibration data, it is indicated that the storage unit of the nonvolatile memory may have a fault in the first SPACE configuration value ADJ-VAL due to a manufacturing problem, and at this time, the second MUX switches on the third storage SPACE and the configuration module nvm_cfg based on the second storage SPACE parameter path signal space_ctrl_from_reg_sel, selects a mode in which the first SPACE configuration value ADJ-VAL is reconfigured FROM the configuration module nvm_cfg, re-triggers the controller module nvm_cfg to read the chip calibration data of the first storage SPACE and the first SPACE configuration value ADJ-VAL of the third storage SPACE through the configuration module nvm_cfg, and sends the chip calibration data and the first SPACE configuration value ADJ-VAL to the configuration module nvm_cfg through the controller module nvm_ctrl, so that the configuration module nvm_cfg can re-determine a new second SPACE configuration value, i.e., the second SPACE configuration value adj_cfg based on the chip calibration data and the first SPACE configuration value ADJ-VAL. And after the configuration module NVM_CFG acquires the calibrated second space configuration value, the operation of burning the second space configuration value into the third storage space is re-executed.
In addition, referring to fig. 4, in some embodiments, the read-write control method of the embodiment of the present application includes, but is not limited to, the following steps:
Step S410, the first MUX turns on the second BUS BUS2 based on the BUS select signal BUS_SEL, and the configuration module NVM_CFG configures preset type data;
Step S420, a third trigger signal carrying the first space configuration value ADJ-VAL is generated through the configuration module NVM_CFG, and the third trigger signal is sent to the controller module NVM_CTRL;
In step S430, the controller module nvm_ctrl burns the preset type data to the second storage SPACE ADJ-SPACE based on the first SPACE configuration value ADJ-VAL.
It can be understood that the second BUS2 is turned on through the first MUX, the configuration module nvm_cfg configures preset type data, the configuration module nvm_cfg generates a third trigger signal carrying the first SPACE configuration value ADJ-VAL and sends the third trigger signal to the controller module nvm_ctrl, the controller module nvm_ctrl burns the preset type data to the second storage SPACE ADJ-SPACE based on the first SPACE configuration value ADJ-VAL, so that the preset type data can be stored by using the second storage SPACE ADJ-SPACE, and the SPACE address reserved in the storage unit can be effectively used, thereby improving the utilization rate of the address SPACE of the nonvolatile memory.
It should be noted that, the preset type data in this embodiment may be data such as a key, which is determined by a person skilled in the art according to actual needs, and is not limited herein.
In addition, referring to fig. 5, in some embodiments, the read-write control method of the embodiment of the present application includes, but is not limited to, the following steps:
Step S510, stopping the operation of burning the preset type data to the second storage SPACE ADJ-SPACE when detecting that the burning address corresponding to the first SPACE configuration value ADJ-VAL exceeds the address range of the second storage SPACE ADJ-SPACE.
It should be noted that, in some embodiments, if it is detected that the address of the first SPACE configuration value ADJ-VAL corresponding to the writing address exceeds the address range of the second storage SPACE ADJ-SPACE, the configuration module nvm_cfg triggers the controller module nvm_ctrl to stop the operation of writing the preset type of data into the second storage SPACE ADJ-SPACE, so as to achieve the write permission division.
In addition, referring to fig. 6, in some embodiments, the read-write control method of the embodiment of the present application includes, but is not limited to, the following steps:
Step S610, the first MUX turns on the second BUS BUS2 based on the BUS selection signal BUS_SEL, and reads the data of the second storage SPACE ADJ-SPACE through the configuration module NVM_CFG trigger controller module NVM_CTRL;
In step S620, the controller module nvm_ctrl sends the data of the second storage SPACE ADJ-SPACE to the configuration module nvm_cfg, and stores the data of the second storage SPACE ADJ-SPACE to the configuration module nvm_cfg.
It can be understood that when reading the data of the second storage SPACE ADJ-SPACE, the first MUX is used to conduct the second BUS2, and the configuration module nvm_cfg is used to trigger the controller module nvm_ctrl to read the data of the second storage SPACE ADJ-SPACE, and all the data of the second storage SPACE ADJ-SPACE are automatically read out to the configuration module nvm_cfg to be stored. In some embodiments, on-demand fetching may also be implemented via the second BUS BUS2, without limitation.
As shown in fig. 7, fig. 7 is a block diagram of a control device according to an embodiment of the present application. The present application also provides a control device 700, comprising:
The processor 710 may be implemented by a general purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an Application SPECIFIC INTEGRATED Circuit (ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solutions provided by the embodiments of the present application;
The Memory 720 may be implemented in the form of a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a random access Memory (Random Access Memory, RAM). The memory 720 may store an operating system and other application programs, and when the technical solution provided in the embodiments of the present specification is implemented by software or firmware, relevant program codes are stored in the memory 720, and the processor 710 invokes the read-write control method for executing the embodiments of the present application, for example, executing the method steps S210 to S260 in fig. 2, the method steps S310 to S350 in fig. 3, the method steps S410 to S430 in fig. 4, the method step S510 in fig. 5, and the method steps S610 to S620 in fig. 6 described above;
an input/output interface 730 for implementing information input and output;
the communication interface 740 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g., USB, network cable, etc.), or may implement communication in a wireless manner (e.g., mobile network, WIFI, bluetooth, etc.);
bus 750 transfers information between the various components of the device (e.g., processor 710, memory 720, input/output interface 730, and communication interface 740);
wherein processor 710, memory 720, input/output interface 730, and communication interface 740 implement a communication connection among each other within the device via bus 750.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit and scope of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (8)
1. A nonvolatile memory, comprising:
The first MUX is connected with the first bus and the second bus respectively, wherein the first MUX conducts the first bus or the second bus based on a bus selection signal;
the configuration module is connected with the first MUX;
The storage unit comprises a first storage space, a second storage space and a third storage space, wherein the first storage space is used for storing chip calibration data, the second storage space is a reserved space with adjustable space capacity, the third storage space is used for storing a first space configuration value, the first space configuration value is a space configuration value of the second storage space, and the first space configuration value is determined according to the data volume of the chip calibration data and the space capacity of the storage unit;
And the controller module is respectively connected with the storage unit and the configuration module.
2. The non-volatile memory of claim 1, wherein the controller module is coupled to the configuration module via a second MUX that is also coupled to the third memory space, wherein the second MUX either turns on the third memory space to the configuration module or turns on the third memory space to the controller module based on a second memory space parameter path signal.
3. A read-write control method applied to the nonvolatile memory according to any one of claims 1 to 2, the method comprising:
When the nonvolatile memory is powered on, the first MUX conducts the first bus based on the bus selection signal, the configuration module configures chip calibration data and a first burning address, and determines the first space configuration value based on the data amount of the chip calibration data and the space capacity of the memory unit, wherein the first burning address is an address for burning the chip calibration data in the memory unit;
The configuration module configures a second burning address, and sends a first trigger signal carrying the second burning address to the controller module, so that the controller module burns the first space configuration value into the third storage space, wherein the second burning address is an address for burning the first space configuration value in the storage unit;
The configuration module sends a second trigger signal carrying the first burning address to the controller module so that the controller module burns the chip calibration data into the first storage space;
the first MUX conducts the second bus based on the bus selection signal, generates a second trigger signal through the configuration module and sends the second trigger signal to the controller module;
the controller module reads the first space configuration value from the third storage space, sends the first space configuration value to the configuration module, and stores the first space configuration value to the controller module and the configuration module respectively;
The controller module polls and reads the chip calibration data in the first storage space based on the first space configuration value and sends the chip calibration data to the configuration module.
4. The read-write control method according to claim 3, wherein the controller module is connected to the configuration module through a second MUX, the second MUX being further connected to the third storage space, wherein the second MUX turns on the third storage space and the configuration module or turns on the third storage space and the controller module based on a second storage space parameter path signal, the method further comprising:
when the first space configuration value is detected to be not matched with the data quantity of the chip calibration data, the second MUX conducts the third storage space and the configuration module based on the second storage space parameter access signal;
triggering the controller module to read the chip calibration data of the first storage space and the first space configuration value of the third storage space through the configuration module;
The controller module sends the chip calibration data and the first spatial configuration value to the configuration module;
the configuration module redetermines a second spatial configuration value based on the chip calibration data;
The first MUX conducts the first bus based on the bus selection signal, the configuration module reconfigures a second burning address, and resends a first trigger signal carrying the second burning address to the controller module so that the controller module burns the second space configuration value into the third storage space.
5. A read-write control method according to claim 3, characterized in that the method further comprises:
The first MUX conducts the second bus based on the bus selection signal, and the configuration module configures preset type data;
Generating a third trigger signal carrying the first space configuration value through the configuration module, and sending the third trigger signal to the controller module;
The controller module burns the preset type data to the second storage space based on the first space configuration value.
6. The read-write control method according to claim 5, characterized in that the method further comprises:
And stopping the operation of burning the data of the preset type to the second storage space when the burning address corresponding to the first space configuration value is detected to exceed the address range of the second storage space.
7. The read-write control method according to claim 5, characterized in that the method further comprises:
the first MUX conducts the second bus based on the bus selection signal, and the configuration module triggers the controller module to read the data of the second storage space;
The controller module sends the data of the second storage space to the configuration module, and stores the data of the second storage space to the configuration module.
8. A control device comprising at least one control processor and a memory for communication with the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the read-write control method according to any one of claims 3 to 7.
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