CN118173648A - Heterojunction doped layer preparation method and solar cell - Google Patents
Heterojunction doped layer preparation method and solar cell Download PDFInfo
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- CN118173648A CN118173648A CN202410229649.4A CN202410229649A CN118173648A CN 118173648 A CN118173648 A CN 118173648A CN 202410229649 A CN202410229649 A CN 202410229649A CN 118173648 A CN118173648 A CN 118173648A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 222
- 238000000034 method Methods 0.000 claims abstract description 176
- 230000008569 process Effects 0.000 claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 239000002346 layers by function Substances 0.000 claims abstract description 39
- 230000001965 increasing effect Effects 0.000 claims abstract description 23
- 230000003247 decreasing effect Effects 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims 4
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- 238000006243 chemical reaction Methods 0.000 abstract description 6
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- 230000031700 light absorption Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 19
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 16
- 238000000576 coating method Methods 0.000 description 16
- 239000011248 coating agent Substances 0.000 description 13
- 239000007789 gas Substances 0.000 description 9
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000005922 Phosphane Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 229910000064 phosphane Inorganic materials 0.000 description 1
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- 229910000077 silane Inorganic materials 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The application discloses a preparation method of a heterojunction doped layer and a solar cell, wherein the preparation method of the heterojunction doped layer comprises the steps of providing a silicon substrate; placing the silicon substrate into a first process cavity to form a seed layer on the surface of the silicon substrate; placing the silicon substrate into a second process cavity to form a functional layer on the surface of the seed layer; placing the silicon substrate into a third process cavity to form a contact layer on the surface of the functional layer; wherein, the temperature difference among the first process chamber, the second process chamber and the third process chamber satisfies one of the following temperature changing processes: the temperature is increased in sequence; or the temperature is reduced in sequence; or the temperature is firstly increased and then decreased; or the temperature is reduced and then increased. The temperature in each process cavity is different, so that the deposition temperature of each film layer of the seed layer, the functional layer and the contact layer is controlled, the doping effect of the film layer is improved, and the electrical property and the optical property of the battery piece are matched to a better state, so that higher photoelectric conversion rate and light absorption effect are obtained at the same time.
Description
Technical Field
The application relates to the technical field of solar cell preparation, in particular to a preparation method of a heterojunction doped layer and a solar cell.
Background
Heterojunction materials are semiconductor materials of a certain junction type composed of two different elements or different composition materials. The conductivity type of both sides of the junction is controlled by doping, and the doping types are different and are called as 'heteroheterojunction'. The devices manufactured by the materials on the two sides of the junction with different forbidden band widths and other characteristics can obtain high amplification factor and high response speed, can be prepared by adopting a chemical vapor deposition method, and can be widely used in the fields of optoelectronic devices and the like. Heterojunction solar cells are cells based on heterostructures, which allow for improved performance by creating a heterojunction between the positive and negative electrode.
In the related art, when preparing a heterojunction doped layer, the doped layer is usually prepared by adopting at least one process chamber, the process temperature of the doped layer is generally 200-210 ℃, the doped layer generally comprises a plurality of different functional layers, and the plurality of different functional layers all adopt the same process temperature. However, the temperature adjustment window is narrow, and the electrical performance and the optical performance of the prepared solar cell cannot be matched.
Disclosure of Invention
In order to solve at least one of the technical problems, the application provides a preparation method of a heterojunction doped layer and a solar cell, which can widen the debugging window range by utilizing a temperature changing mode, improve the crystallinity of the doped layer, improve the carrier mobility and the effective doping concentration and improve the conversion efficiency of the cell.
In a first aspect, the present application provides a method for preparing a heterojunction doped layer, including
Providing a silicon substrate;
placing the silicon substrate into a first process cavity to form a seed layer on the surface of the silicon substrate;
placing the silicon substrate into a second process cavity to form a functional layer on the surface of the seed layer;
placing the silicon substrate into a third process cavity to form a contact layer on the surface of the functional layer;
Wherein, the temperature difference among the first process chamber, the second process chamber and the third process chamber satisfies one of the following temperature changing processes: the temperature is increased in sequence; or the temperature is reduced in sequence; or the temperature is firstly increased and then decreased; or the temperature is reduced and then increased.
As an alternative implementation manner, in some examples of the first aspect of the present application, the temperature during the temperature changing sequentially increases, the temperature of the second process chamber is 10 to 40 ℃ higher than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ higher than the temperature of the second process chamber.
As an alternative implementation manner, in some examples of the first aspect of the present application, the temperature during the temperature changing process is sequentially reduced, the temperature of the second process chamber is 10 to 40 ℃ lower than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ lower than the temperature of the second process chamber.
As an alternative implementation manner, in some examples of the first aspect of the present application, the temperature during the temperature changing is increased and then decreased, the temperature of the second process chamber is 10 to 40 ℃ higher than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ lower than the temperature of the second process chamber.
As an alternative implementation manner, in some examples of the first aspect of the present application, the temperature during the temperature changing is reduced and then increased, the temperature of the second process chamber is 10 to 40 ℃ lower than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ higher than the temperature of the second process chamber.
In some embodiments of the first aspect of the present application, the method for preparing a heterojunction doped layer further comprises, before the silicon substrate is placed in the first process chamber
And forming an intrinsic layer on the surface of the silicon substrate.
In some embodiments of the first aspect of the present application, after the silicon substrate is placed in the third process chamber, the method for preparing a heterojunction doped layer further includes
Forming a TCO layer on the surface of the contact layer;
and forming a metal electrode on the surface of the TCO layer.
As an alternative implementation manner, in some examples of the first aspect of the present application, the silicon substrate includes a first surface and a second surface that are disposed opposite to each other, the first surface is used to form a P-type doped layer, the thickness of the seed layer of the P-type doped layer is 0-3 nm, the thickness of the functional layer is 20-40 nm, and the thickness of the contact layer is 0-5 nm; and/or
The second surface is used for forming an N-type doped layer, the thickness of the seed layer of the N-type doped layer is 0-3 nm, the thickness of the functional layer is 10-30 nm, and the thickness of the contact layer is 0-5 nm.
As an alternative implementation manner, in some examples of the first aspect of the present application, the silicon substrate includes a first surface and a second surface that are disposed opposite to each other, where the first surface is used to form a P-type doped layer, and a process temperature of the P-type doped layer is 130 ℃ to 200 ℃; and/or
The second surface is used for forming an N-type doped layer, and the process temperature of the N-type doped layer is 150-210 ℃.
In a second aspect, the present application also provides a solar cell prepared by the method for preparing a heterojunction doped layer as provided in the first aspect.
The embodiment of the application has at least the following beneficial effects: by adopting the preparation method, the silicon substrate can have a temperature changing process in the process of entering the first process cavity, the second process cavity and the third process cavity in sequence, and the deposition temperature control of each film layer of the seed layer, the functional layer and the contact layer is facilitated by utilizing the temperature difference in each process cavity, so that the preparation requirements of different film layers are met, the crystallinity of the doped layer is improved, and the carrier mobility and the effective doping concentration are improved. By designing each film layer of the doped layers, for example, setting different doping substances, doping thicknesses, doping process temperatures and the like, the electrical performance and the optical performance of the solar cell are matched to a better state. By adopting the preparation method of the heterojunction doped layer, the processes of changing the temperature are utilized to widen the process debugging window for matching and debugging the electrical property and the optical property of the battery piece of the solar battery, the deposition temperatures of each film layer of the seed layer, the functional layer and the contact layer are controlled respectively in the process of changing the temperature and coating the films of different film layers, so that the electrical property matching of the seed layer and the intrinsic layer is improved, the electrical property matching of the seed layer and the functional layer is improved, the electrical property matching of the functional layer and the contact layer is improved, the electrical property matching of the contact layer and the TCO transparent oxidation conductive film is improved, the crystallinity of the whole N-type doped layer and the P-type doped layer is improved, the carrier mobility and the effective doping concentration are improved, parasitic absorption is reduced, and the current, the open-circuit voltage and the filling factor of the solar battery are improved, so that the higher photoelectric conversion rate is obtained.
Drawings
The described and/or additional aspects and advantages of embodiments of the present application will become apparent and readily appreciated from the following description taken in conjunction with the accompanying drawings. It should be noted that the embodiments shown in the drawings below are exemplary only and are not to be construed as limiting the application.
Fig. 1 is a schematic view of a solar cell according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a doped layer of a solar cell according to an embodiment of the present application;
fig. 3 is a flowchart of a method for preparing a heterojunction doped layer according to an embodiment of the present application.
Reference numerals: 100. a solar cell; 10. a silicon substrate; 11. a first surface; 12. a second surface; 20. an intrinsic layer; 30. a doped layer; 31. a seed layer; 32. a functional layer; 33. a contact layer; 40. a TCO layer; 50. a metal electrode.
Detailed Description
Embodiments of the present application are described in detail below in conjunction with fig. 1-3, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, it should be understood that, if the terms "center", "middle", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc. are used as directions or positional relationships based on the directions shown in the drawings, the directions are merely for convenience of description and for simplification of description, and do not indicate or imply that the apparatus or element to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present application. Furthermore, features defining "first", "second" may include one or more such features, either explicitly or implicitly. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1 and 2, the present application provides a solar cell 100, wherein the solar cell 100 includes a silicon substrate 10, and an intrinsic layer 20, a doped layer 30, a TCO layer 40 (transparent conductive oxide layer TRANSPARENT CONDUCT IVE OXIDE, TCO) and a metal electrode 50 sequentially disposed on a surface of the silicon substrate 10. Illustratively, the silicon substrate 10 may employ an N-type monocrystalline silicon wafer.
In some embodiments, the silicon substrate 10 has a first surface 11 and a second surface 12 disposed opposite to each other, and the intrinsic layer 20, the doped layer 30, the TCO layer 40, and the metal electrode 50 are disposed on both the first surface 11 and the second surface 12. That is, the above-described structure is symmetrically disposed about the silicon substrate 10 on the first surface 11, the second surface 12. Depending on the doping materials, different doping layers 30 may be disposed on the first surface 11 and the second surface 12, for example, a P-type doping layer 30 is disposed on the first surface 11, and an N-type doping layer 30 is disposed on the second surface 12, so as to satisfy the requirement of disposing the heterojunction doping layer 30 on the solar cell 100.
In some embodiments, doped layer 30 may be prepared using a chemical vapor deposition process. Specifically, a gas phase substance containing the film element of the doped layer, such as silane, phosphane, hydrogen and the like, is introduced into the process chamber, and the gas phase substance and the surface of the silicon substrate 10 are subjected to doping effect under the high temperature of the process chamber to generate the doped layer 30 with a thin film structure. Illustratively, the doped layer 30 includes a seed layer 31, a functional layer 32, and a contact layer 33, and each layer structure may be sequentially prepared by separately introducing different gases into different process chambers.
The N-type doped layer 30 and the P-type doped layer 30 will be described below, respectively.
The seed layer 31 of the N-type doped layer 30 has the function of reducing the defect state density of the N-type doped layer and the interface between the N-type doped layer and the intrinsic layer 20, optimizing the coating quality of the doped layer 30 and enhancing the passivation effect. Illustratively, the seed layer 31 of the N-type doped layer 30 includes, but is not limited to, siH 4、H2、CO2、PH3, where H 2/SiH4＝0～500,PH3/SiH4＝0～5％,CO2/SiH4 =0-100%. The pressure range is 2-8 torr, the cathode interval is 10-60 mm, the power density range is 0.1-0.3W/cm 2, and the coating temperature range is 150-210 ℃.
The function of the functional layer 32 of the N-doped layer 30 is to form an effective phosphorus doping, and through electrons, holes are blocked, so that an effective back electric field is formed, and meanwhile, the optical band gap is improved, sufficient light transmittance is ensured, and the utilization of light by the battery substrate material is improved. Illustratively, the functional layer 32 of the N-type doped layer 30 includes, but is not limited to, siH 4、H2、CO2、PH3, where H 2/SiH4＝0～500,PH3/SiH4＝1～5％,CO2/SiH4 =0 to 100%. The pressure range is 2-8 torr, the cathode interval is 10-60 mm, the power density range is 0.1-0.3W/cm 2, and the coating temperature range is 150-210 ℃.
The contact layer 33 of the N-doped layer 30 serves to reduce the interfacial contact barrier, enhance contact with the TCO layer 40, and reduce bulk and series resistance. Exemplary gases for the contact layer of N-type doped layer 30 include, but are not limited to, siH 4、H2、PH3, where H 2/SiH4＝1～500,PH3/SiH4 =1-10%. The pressure range is 2-8 torr, and the cathode spacing is 10-60 mm; the power density range is 0.1-0.3W/cm 2; the coating temperature range is 150-210 ℃.
The seed layer 31 of the P-type doped layer 30 has the function of reducing the defect state density of the interface between the seed layer and the intrinsic layer, optimizing the coating quality of the doped layer and enhancing the passivation effect. Exemplary gases for use in seed layer 31 of P-type doped layer 30 include, but are not limited to, siH 4、H2、CO2、B2H6, wherein ,H2/SiH4＝0～500,B2H6/SiH4＝0～5％,CO2/SiH4＝0～100％. is at a pressure in the range of 2 to 8torr, a cathode spacing in the range of 10 to 60mm, a power density in the range of 0.1 to 0.3W/cm 2, and a coating temperature in the range of 130 to 200 ℃.
The function of the functional layer 32 of the P-doped layer 30 is to form an effective boron doping, to form an effective PN junction, and to increase the open circuit voltage of the solar cell 100. Exemplary, the dopant gases used for the functional layer 32 of the P-type doped layer 30 include, but are not limited to, siH 4、H2、CO2、B2H6, where H 2/SiH4＝0～500,B2H6/SiH4 =1-5%. The pressure range is 2-8 torr, the cathode interval is 10-60 mm, the power density range is 0.1-0.3W/cm 2, and the coating temperature range is 130-200 ℃.
The effect of the contact layer 33 of the P-doped layer 30 is to reduce the interfacial contact barrier, enhance contact with the TCO layer 40, and reduce bulk and series resistance. Illustratively, the contact layer 33 of the P-type doped layer 30 may include, but is not limited to, siH 4、H2、B2H6, where H 2/SiH4＝0～500,B2H6/SiH4 =1 to 10%. The pressure range is 2-8 torr, the cathode interval is 10-60 mm, the power density range is 0.1-0.3W/cm 2, and the coating temperature range is 130-200 ℃.
In the related art, after different gases are introduced into the same process chamber or different process chambers, the process chambers generally use the same process temperature, however, the process chambers have different functional effects for the doped layers of the same doping element with different functions, and the optimal temperature for the doping effect is different, for example, the process temperature for preparing the N-type doped layer 30 ranges from 150 ℃ to 210 ℃, the process temperature for preparing the P-type doped layer 30 ranges from 130 ℃ to 200 ℃, and the relatively low process temperature is beneficial to the doping effect of the phosphorus element or the boron element in the seed layer 31 and the silicon substrate 10 more easily, so that the battery performance is improved. Therefore, if the same temperature is adopted in different process chambers, the doping effect is not improved.
In view of this, referring to fig. 3, the present application provides a method for preparing a heterojunction doped layer, comprising the following steps:
S1, providing a silicon substrate;
S2, placing the silicon substrate into a first process cavity to form a seed layer on the surface of the silicon substrate;
s3, placing the silicon substrate into a second process cavity to form a functional layer on the surface of the seed layer;
s4, placing the silicon substrate into a third process cavity to form a contact layer on the surface of the functional layer;
Wherein, the temperature difference among the first process chamber, the second process chamber and the third process chamber satisfies one of the following temperature changing processes: the temperature is increased in sequence; or the temperature is reduced in sequence; or the degree is firstly increased and then decreased; or the temperature is reduced and then increased.
By adopting the preparation method, the silicon substrate 10 can have a temperature changing process in the process of entering the first process cavity, the second process cavity and the third process cavity in sequence, and the deposition temperature control of each film layer of the seed layer 31, the functional layer 32 and the contact layer 33 is facilitated by utilizing the temperature difference in each process cavity, so that the preparation requirements of different film layers are met, and the doping effect of the film layers is improved. Generally, the performance indexes of the solar cell 100 include electrical performance and optical performance, wherein the electrical performance refers to the photoelectric conversion efficiency of the solar cell 100, that is, the ability of the solar cell 100 to convert light energy into electric energy after absorbing the light energy, and the optical performance refers to the light absorption ability of the solar cell 100, and the electrical performance and the optical performance of the solar cell 100 are related to the doping effect of the doping layer 30. By designing each of the film layers of the doped layer 30, for example, by providing different doping substances, doping thicknesses, doping process temperatures, etc., the electrical and optical properties of the solar cell 100 are matched to a better state. According to the description above, the ratios of the elements and the components of the gases used in the N-type doped layer and the P-type doped layer are different, and the ratios of the components of the gases in the seed layer 31, the functional layer 32, and the contact layer 33 are also different in the same type of doped layer (for example, the N-type doped layer 30), so that the debugging of the coating process is facilitated by adopting different process temperatures for the respective layers. By adopting the preparation method of the heterojunction doped layer, temperature difference can be formed among various process cavities by utilizing the variable temperature processes, so that different coating process temperatures are respectively set for the seed layer 31, the functional layer 32 and the contact layer 33 to widen the process debugging window for matching and debugging the electrical property and the optical property of the cell piece of the solar cell, and the deposition temperatures of the seed layer 31, the functional layer 32 and the contact layer 33 are respectively controlled in the variable temperature coating process of different film layers, so that the electrical property matching of the seed layer and the intrinsic layer is improved, the electrical property matching of the seed layer and the functional layer is improved, the electrical property matching of the functional layer and the contact layer is improved, the electrical property matching of the contact layer and the TCO transparent oxidation conductive film is improved, the crystallinity of the whole N-type doped layer 30 and the P-type doped layer 30 is improved, the carrier mobility and the effective doping concentration are improved, parasitic absorption is reduced, the current, the open-circuit voltage and the filling factor of the solar cell are improved, and the photoelectric conversion rate is simultaneously obtained.
In some embodiments, the temperature during the temperature change is sequentially increased, the temperature of the second process chamber is 10 to 40 ℃ higher than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ higher than the temperature of the second process chamber. For example, the temperature of the first process chamber is 150 ℃, the temperature of the second process chamber is 170 ℃, and the temperature of the third process chamber is 190 ℃. In this example, the process temperature for preparing the functional layer 32 is higher than the temperature of the seed layer 31, and the process temperature for preparing the contact layer 33 is higher than the temperature of the functional layer 32, so that the effect that the process temperature is sequentially increased in the sequential processing and forming from the first process chamber to the third process chamber is achieved, the effect of forming the variable-temperature coating film is facilitated, and the crystallinity of the doped layer 30 is improved, and the carrier mobility and the effective doping concentration are improved.
In some embodiments, the temperature during the temperature change is sequentially reduced, the temperature of the second process chamber is 10 to 40 ℃ lower than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ lower than the temperature of the second process chamber. For example, the temperature of the first process chamber is 190 ℃, the temperature of the second process chamber is 170 ℃, and the temperature of the third process chamber is 150 ℃. In this example, the process temperature for preparing the functional layer 32 is lower than the temperature of the seed layer 31, and the process temperature for preparing the contact layer 33 is lower than the temperature of the functional layer 32, so that the effect that the process temperature is sequentially reduced in the sequential processing from the first process chamber to the third process chamber is achieved, the effect of forming the variable-temperature coating film is facilitated, the crystallinity of the doped layer 30 is improved, and the carrier mobility and the effective doping concentration are improved.
In some embodiments, the temperature during the temperature change is increased and then decreased, the temperature of the second process chamber is 10 to 40 ℃ higher than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ lower than the temperature of the second process chamber. For example, the temperature of the first process chamber is 150 ℃, the temperature of the second process chamber is 170 ℃, and the temperature of the third process chamber is 150 ℃. In this example, the process temperature for preparing the energy-passing layer 32 is higher than the process temperature of the seed layer 31, the process temperature for preparing the contact layer 33 is lower than the process temperature of the functional layer 32, and the process temperature for preparing the seed layer 31 is the same as the process temperature for preparing the contact layer 33 (although it may be different in other examples), so as to achieve the effect of increasing and then decreasing the process temperature in the sequential processing and construction from the first process chamber to the third process chamber, thereby helping to obtain the effect of forming a variable-temperature coating film, improving the crystallinity of the doped layer 30, and improving the carrier mobility and the effective doping concentration.
In some embodiments, the temperature during the temperature change is decreased and then increased, the temperature of the second process chamber is 10 to 40 ℃ lower than the temperature of the first process chamber, and the temperature of the third process chamber is 10 to 40 ℃ higher than the temperature of the second process chamber. For example, the temperature of the first process chamber is 170 ℃, the temperature of the second process chamber is 150 ℃, and the temperature of the third process chamber is 190 ℃. In this example, the process temperature for preparing the functional layer 32 is lower than that of the seed layer 31, the process temperature for preparing the contact layer 33 is higher than that of the contact layer 33, and the process temperature for preparing the seed layer 31 and the contact layer 33 are different (of course, the same may be adopted in other examples), so that the effect that the process temperature is reduced and then increased in the sequential processing and forming from the first process chamber to the third process chamber is achieved, the effect of forming a variable-temperature coating film is facilitated, the crystallinity of the doped layer 30 is improved, and the carrier mobility and the effective doping concentration are improved.
In some embodiments, before step S2, the method for preparing a heterojunction doped layer further comprises the following steps:
s5, forming an intrinsic layer on the surface of the silicon substrate.
In some embodiments, after step S5, the heterojunction doped layer preparation method further comprises the steps of:
s6, forming a TCO layer on the surface of the contact layer;
s7, forming a metal electrode on the surface of the TCO layer.
The intrinsic layer 20 is rich in a large amount of H ions (hydrogen ions), which can effectively passivate defects on the surface of the silicon substrate 10, thereby passivating dangling bonds, reducing interface defect state density, and improving minority carrier lifetime of the silicon substrate 10, thereby improving open-circuit voltage of the solar cell 100 and further improving conversion efficiency of the solar cell 100. The TCO layer 40 can transmit light through the structure to enter the silicon substrate 10, thereby acting as an anti-reflection layer to reduce reflection of light, and meanwhile, the TCO layer 40 can also protect the amorphous silicon film and transport charges generated by the PN junction photovoltaic effect.
In some embodiments, the silicon substrate 10 includes a first surface 11 and a second surface 12 disposed opposite to each other, the first surface 11 is used to form the P-type doped layer 30, the thickness of the seed layer 31 of the P-type doped layer 30 is 0 to 3nm, for example, 1nm, 2nm, 3nm, or no seed layer (i.e., 0 nm), the thickness of the functional layer 32 is 20 to 40nm, for example, 20nm, 23nm, 25nm, 30nm, 35nm, 40nm, and the thickness of the contact layer 33 is 0 to 5nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, or no contact layer (i.e., 0 nm).
In some embodiments, the silicon substrate 10 includes a first surface 11 and a second surface 12 disposed opposite to each other, the second surface 12 is used to form an N-type doped layer 30, the thickness of a seed layer 31 of the N-type doped layer 30 is 0 to 3nm, for example, 1nm, 2nm, 3nm, or no seed layer (i.e., 0 nm), the thickness of a functional layer 32 is 10 to 30nm, for example, 10nm, 13nm, 15nm, 20nm, 25nm, 30nm, and the thickness of a contact layer 33 is 0 to 5nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, or no contact layer (i.e., 0 nm).
In the description of the present specification, if a description appears that makes reference to the term "one embodiment," "some examples," "some embodiments," "an exemplary embodiment," "an example," "a particular example," or "some examples," etc., it is intended that the particular feature, structure, material, or characteristic described in connection with the embodiment or example be included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present application.
In the description of the present application, the terms "and" if used in the singular are intended to mean "and" as opposed to "or". For example, the patent name "a A, B" describes that what is claimed in the present application is: a technical scheme with a subject name A and a technical scheme with a subject name B.
Claims (10)
1. A preparation method of a heterojunction doped layer is characterized by comprising the following steps: comprising
Providing a silicon substrate;
placing the silicon substrate into a first process cavity to form a seed layer on the surface of the silicon substrate;
placing the silicon substrate into a second process cavity to form a functional layer on the surface of the seed layer;
placing the silicon substrate into a third process cavity to form a contact layer on the surface of the functional layer;
Wherein, the temperature difference among the first process chamber, the second process chamber and the third process chamber satisfies one of the following temperature changing processes:
the temperature is increased in sequence; or (b)
The temperature is reduced in sequence; or (b)
The temperature is firstly increased and then decreased; or (b)
The temperature is decreased and then increased.
2. The method for preparing a heterojunction doped layer according to claim 1, wherein: the temperature in the temperature changing process is sequentially increased, the temperature of the second process chamber is 10-40 ℃ higher than the temperature of the first process chamber, and the temperature of the third process chamber is 10-40 ℃ higher than the temperature of the second process chamber.
3. The method for preparing a heterojunction doped layer according to claim 1, wherein: the temperature in the temperature changing process is reduced in sequence, the temperature of the second process chamber is 10-40 ℃ lower than the temperature of the first process chamber, and the temperature of the third process chamber is 10-40 ℃ lower than the temperature of the second process chamber.
4. The method for preparing a heterojunction doped layer according to claim 1, wherein: the temperature in the temperature changing process is firstly increased and then decreased, the temperature of the second process chamber is 10-40 ℃ higher than that of the first process chamber, and the temperature of the third process chamber is 10-40 ℃ lower than that of the second process chamber.
5. The method for preparing a heterojunction doped layer according to claim 1, wherein: the temperature in the temperature changing process is firstly reduced and then increased, the temperature of the second process chamber is 10-40 ℃ lower than that of the first process chamber, and the temperature of the third process chamber is 10-40 ℃ higher than that of the second process chamber.
6. The method of manufacturing a heterojunction doped layer as claimed in any one of claims 1 to 5, wherein: the preparation method of the heterojunction doped layer further comprises the following steps before the silicon substrate is placed in the first process chamber
And forming an intrinsic layer on the surface of the silicon substrate.
7. The method of manufacturing a heterojunction doped layer as claimed in any one of claims 1 to 5, wherein: the preparation method of the heterojunction doped layer further comprises the following steps of after the silicon substrate is placed in the third process chamber
Forming a TCO layer on the surface of the contact layer;
and forming a metal electrode on the surface of the TCO layer.
8. The method of manufacturing a heterojunction doped layer as claimed in any one of claims 1 to 5, wherein: the silicon substrate comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is used for forming a P-type doping layer, the thickness of a seed layer of the P-type doping layer is 0-3 nm, the thickness of the functional layer is 20-40 nm, and the thickness of the contact layer is 0-5 nm; and/or
The second surface is used for forming an N-type doped layer, the thickness of the seed layer of the N-type doped layer is 0-3 nm, the thickness of the functional layer is 10-30 nm, and the thickness of the contact layer is 0-5 nm.
9. The method of manufacturing a heterojunction doped layer as claimed in any one of claims 1 to 5, wherein: the silicon substrate comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is used for forming a P-type doping layer, and the process temperature of the P-type doping layer is 130-200 ℃; and/or
The second surface is used for forming an N-type doped layer, and the process temperature of the N-type doped layer is 150-210 ℃.
10. A solar cell, characterized in that: the solar cell is prepared by the heterojunction doping layer preparation method as claimed in any one of claims 1 to 9.
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