CN118160094A

CN118160094A - Semiconductor device and electronic apparatus

Info

Publication number: CN118160094A
Application number: CN202280071806.2A
Authority: CN
Inventors: 山崎舜平; 国武宽司; 和田理人; 加藤清; 大贯达也
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2021-11-05
Filing date: 2022-10-21
Publication date: 2024-06-07

Abstract

Provided is a semiconductor device which realizes miniaturization. The semiconductor device includes a first layer and a second layer on the first layer. The first layer includes a p-channel type first transistor containing silicon in a channel formation region. The second layer includes an n-channel type second transistor including a metal oxide in a channel formation region. The first transistor and the second transistor constitute a CMOS circuit. The channel length of the first transistor is longer than the channel length of the second transistor.

Description

Semiconductor device and electronic apparatus

Technical Field

One embodiment of the present invention relates to a semiconductor device and an electronic apparatus.

Note that one embodiment of the present invention is not limited to the above-described technical field. Examples of the technical field of one embodiment of the present invention disclosed in the present specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input/output device, a driving method of these devices, and a manufacturing method of these devices.

Background

In recent years, semiconductor devices have been developed, and LSIs, CPUs (CentralProcessing Unit: central processing units), memories and the like are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor elements including an integrated circuit (including at least a transistor and a memory) in which a semiconductor wafer is processed into chips and formed with electrodes as connection terminals.

An Integrated Circuit (IC) such as an LSI, a CPU, and a memory is mounted on a circuit board such as a printed wiring board, and is used as one of the components of various electronic devices.

In addition, a technique of forming a transistor by using a semiconductor thin film formed over a substrate having an insulating surface is attracting attention. Such a transistor is widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known. As other materials, oxide semiconductors are attracting attention.

In addition, it is known that a leakage current of a transistor using an oxide semiconductor is extremely low in a non-conductive state. For example, patent document 1 discloses a low power consumption CPU or the like that uses a characteristic of low leakage current of a transistor using an oxide semiconductor. Further, for example, patent document 2 discloses a memory device that realizes long-term retention of memory contents by utilizing the characteristic of low leakage current of a transistor using an oxide semiconductor.

[ Prior Art literature ]

[ Patent literature ]

[ Patent document 1] Japanese patent application laid-open No. 2012-257187

[ Patent document 2] Japanese patent application laid-open No. 2011-151383 ]

Disclosure of Invention

Technical problem to be solved by the invention

An object of one embodiment of the present invention is to provide a semiconductor device that realizes miniaturization. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Further, it is an object of one embodiment of the present invention to provide a novel semiconductor device.

Note that the description of these objects does not hinder the existence of other objects. Note that one embodiment of the present invention is not required to achieve all of the above objects. Other objects than the above objects can be extracted from the description of the specification, drawings, claims, and the like.

Means for solving the technical problems

One embodiment of the present invention is a semiconductor device including a first layer including a p-channel type first transistor including silicon in a first channel formation region, and a second layer over the first layer including an n-channel type second transistor including a metal oxide in a second channel formation region, wherein a CMOS circuit is formed using the first transistor and the second transistor, and a channel length of the first transistor is longer than a channel length of the second transistor.

In the above manner, the channel length of the first transistor may be 15nm or more, and the channel length of the second transistor may be less than 15nm.

In the above manner, the channel length of the first transistor may be 15nm or more and 40nm or less, and the channel length of the second transistor may be 3nm or more and less than 15nm.

In the above manner, the first layer may include a single crystal silicon substrate, and the first transistor may have a first channel formation region in the single crystal silicon substrate.

In the above manner, the second layer may include a memory circuit.

In the above aspect, the memory circuit may include a third transistor, a fourth transistor, and a capacitor, one of a source and a drain of the third transistor may be electrically connected to a gate of the fourth transistor, and a gate of the fourth transistor may be electrically connected to one electrode of the capacitor.

In the above aspect, the third transistor and the fourth transistor may include a metal oxide in the second channel formation region.

An electronic device including the semiconductor device and the display portion according to one embodiment of the present invention is also one embodiment of the present invention.

Effects of the invention

According to one embodiment of the present invention, a semiconductor device that can be miniaturized can be provided. Further, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not hinder the existence of other effects. Furthermore, one embodiment of the present invention need not have all of the above effects. Effects other than the above can be derived from the descriptions of the specification, drawings, claims, and the like.

Brief description of the drawings

Fig. 1 is a block diagram showing a structural example of a semiconductor device.

Fig. 2 is a perspective view showing a structural example of the semiconductor device.

Fig. 3 is a circuit diagram showing a structural example of the CMOS circuit.

Fig. 4A to 4H are circuit diagrams showing a structural example of a memory circuit.

Fig. 5 is a perspective view showing a structural example of the semiconductor device.

Fig. 6is a circuit diagram showing a structural example of the memory circuit.

Fig. 7A is a plan view showing a structural example of the transistor. Fig. 7B to 7D are sectional views showing structural examples of the transistor.

Fig. 8A and 8B are sectional views showing structural examples of the transistor.

Fig. 9 is a cross-sectional view showing a structural example of a transistor.

Fig. 10A and 10B are sectional views showing structural examples of the transistor.

Fig. 11A and 11B are sectional views showing structural examples of the transistor.

Fig. 12A and 12B are sectional views showing structural examples of the transistor.

Fig. 13A to 13F are sectional views showing structural examples of the transistor.

Fig. 14 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 15 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 16 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 17 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 18 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 19 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 20 is a cross-sectional view showing a structural example of the semiconductor device.

Fig. 21A and 21B are block diagrams showing a structural example of the semiconductor device.

Fig. 22A and 22B are diagrams showing an example of an electronic component.

Fig. 23A to 23E are diagrams showing one example of a storage device.

Fig. 24A to 24H are diagrams showing one example of an electronic device.

Fig. 25A and 25B are diagrams showing transition of power consumption of a normally-off processor.

Fig. 26 is a diagram showing a measurement circuit.

Fig. 27 is a graph showing the temperature dependence of the off-state current.

Modes for carrying out the invention

The embodiments will be described below with reference to the drawings. It is noted that one of ordinary skill in the art can easily understand the fact that the embodiments may be implemented in a plurality of different forms, and that the manner and details thereof may be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

The ordinal numbers such as "first" and "second" in the present specification are added to avoid confusion of the constituent elements, and do not indicate any order or sequence such as the process order or the lamination order. Note that, in order to avoid confusion of constituent elements, ordinal words may be added to the terms such as the present specification. Note that, with respect to terms used in this specification and the like, there are cases where different ordinal words are added to the terms in the claims. Note that, regarding terms such as the ordinal numbers attached to the present specification, the ordinal numbers thereof are sometimes omitted in the claims.

In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, and the like shown in the drawings.

In this specification and the like, unless otherwise specified, an off-state current (off-state current) refers to a drain current when a transistor is in an off state (also referred to as a non-conducting state, an off state). Unless otherwise specified, the off state in the n-channel transistor refers to a state in which the voltage V _gs between the gate and the source is lower than the threshold voltage V _th (V _gs is higher than V _th in the p-channel transistor).

In the present specification and the like, the metal oxide (metaloxide) refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as OS) and the like. For example, in the case where a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor may be referred to as a transistor including a metal oxide or an oxide semiconductor.

The structure in which the Oxide Semiconductor (OS) is integrated may be referred to as OSLSI.

In addition, the oxide semiconductor used as OSLSI contains at least indium (In) and oxygen (O). Typically, indium Gallium Zinc Oxide (IGZO), indium zinc oxide (IZO (registered trademark)), and Indium Oxide (IO) are exemplified. In addition, the oxide semiconductor may contain hydrogen as an impurity.

(Embodiment 1)

In this embodiment mode, a semiconductor device according to an embodiment of the present invention is described with reference to the drawings.

One embodiment of the present invention relates to a semiconductor device including a first layer and a second layer over the first layer. The first layer is provided with a transistor (hereinafter also referred to as a Si transistor or SiFET) containing silicon in a channel formation region. Specifically, the first layer includes a single crystal silicon substrate in which the Si transistor may have a channel formation region. The second layer is provided with a transistor (hereinafter also referred to as an OS transistor or an OSFET) containing a metal oxide in the channel formation region. By providing the semiconductor device with a stacked structure in this manner, the number of transistors provided in one layer can be reduced, and the occupied area of the semiconductor device can be reduced. Thus, the semiconductor device according to one embodiment of the present invention can be a semiconductor device that realizes miniaturization.

In this specification and the like, a transistor including single crystal silicon in a channel formation region is referred to as a single crystal Si transistor. For example, a transistor including a channel formation region in a single crystal silicon substrate is a single crystal Si transistor.

In the semiconductor device according to one embodiment of the present invention, a CMOS (Complementary Metal Oxide Semiconductor) circuit is configured using a first transistor which is a p-channel Si transistor provided in a first layer and a second transistor which is an n-channel OS transistor provided in a second layer. Here, when the channel length and the channel width are equal, mobility of a Si transistor such as a single crystal Si transistor is higher than that of an OS transistor. On the other hand, when the difference between the mobility of the p-channel transistor and the mobility of the n-channel transistor constituting the CMOS is large, the CMOS circuit may not be normally driven.

In view of this, in one embodiment of the present invention, the channel length of the first transistor as a Si transistor is made longer than the channel length of the second transistor as an OS transistor. The longer the channel length is, the higher the source-drain resistance and the lower the mobility, and thus by making the channel length of the first transistor longer than that of the second transistor, the difference in mobility between the first transistor and the second transistor can be further reduced as compared with the case where the channel lengths of the first transistor and the second transistor are equal. Therefore, the difference between on-state currents of the first transistor and the second transistor can be reduced, so that even if a CMOS circuit is configured using the first transistor as a Si transistor and the second transistor as an OS transistor, the CMOS circuit can be normally driven.

Specifically, for example, in view of ease of manufacturing the second transistor, it is preferable that the channel length of the first transistor is 15nm or more and the channel length of the second transistor is less than 15nm. Alternatively, the channel length of the first transistor is preferably set to 15nm or more and 40nm or less, and the channel length of the second transistor is preferably set to 3nm or more and less than 15nm. The channel length of the second transistor may typically be 5nm or more and 8nm or less.

By setting the channel lengths of the first transistor and the second transistor to be within the above range, the second transistor (OSFET) can be designed such that the off-state current (Ioff) is lower by 4 bits to 5 bits or more than that of the first transistor (SiFET). By adopting this design, on-state current (Ion) can be reduced.

The semiconductor device according to one embodiment of the present invention further includes a memory portion in which memory circuits are arranged in a matrix. The memory circuit includes a write transistor, a read transistor, and a select transistor. For example, one of the source and the drain of the write transistor is electrically connected to the gate of the read transistor, and one of the source and the drain of the read transistor is electrically connected to one of the source and the drain of the select transistor.

The write transistor has a function as a switch for controlling writing and holding of data to the memory circuit. When the write transistor is turned on, data is written into the memory circuit, and when the write transistor is turned off, data is held in the memory circuit. The read transistor has a function of amplifying and reading out data held in the memory circuit. The selection transistor has a function as a switch for selecting a memory circuit for reading data. When the selection transistor is turned on, data held in the memory circuit is read. Specifically, when the selection transistor is turned on, a current corresponding to data held in the memory circuit flows between the drain and source of the read transistor and the drain and source of the selection transistor, and the data is amplified and read.

As the writing transistor, a transistor with a small off-state current is preferably used, so that data can be held in the memory circuit for a long period of time. As such a transistor, an OS transistor is given. In addition, it is preferable to use a transistor with a large on-state current as the read transistor and the select transistor, so that data can be read from the memory circuit at high speed. As such a transistor, a Si transistor is given.

Thus, by providing the read transistor and the select transistor in the first layer where the Si transistor is provided and providing the write transistor in the second layer where the OS transistor is provided, data can be held in the memory circuit for a long period of time and read out from the memory circuit at high speed. Note that the writing transistor, the reading transistor, and the selecting transistor may be n-channel transistors.

On the other hand, when the channel length, the channel width, and the like of the Si transistor provided in the first layer and the OS transistor provided in the second layer are equal, it is necessary to change the potential supplied to the gate of the transistor serving as a switch according to the kind of the transistor. For example, it is necessary to make the potential supplied to the gate of a write transistor serving as an OS transistor for switching higher when the write transistor is turned on than the potential supplied to the gate of a select transistor serving as a Si transistor for switching when the select transistor is turned on.

In one embodiment of the present invention, as described above, the channel length of the Si transistor provided in the first layer is made longer than the channel length of the OS transistor provided in the second layer. Thus, the potential supplied to the gate of the Si transistor used as a switch when the Si transistor is turned on can be made equal to the potential supplied to the gate of the OS transistor used as a switch when the OS transistor is turned on. Further, the potential supplied to the gate of the Si transistor used as a switch when the Si transistor is turned off may be made equal to the potential supplied to the gate of the OS transistor used as a switch when the OS transistor is turned off. Thus, the gate potential of the Si transistor serving as a switch and the gate potential of the OS transistor serving as a switch can be supplied from the same power supply.

In the case where the channel length of the Si transistor provided in the first layer is made longer than the channel length of the OS transistor provided in the second layer, the integration level of the transistor in the second layer can be made smaller than that of the transistor in the first layer. For example, in a memory portion in which memory circuits are arranged in a matrix, the integration of transistors in the second layer may be made smaller than the integration of transistors in the first layer.

Structural example of semiconductor device 1-

Fig. 1 is a block diagram showing a structural example of a semiconductor device 10 according to an embodiment of the present invention. The semiconductor device 10 includes a memory unit 20, a word line driver circuit 31, a bit line driver circuit 32, a control circuit 33, a communication circuit 34, and an input/output circuit 35.

In the drawings of the present specification, constituent elements are classified according to their functions and are shown as block diagrams of blocks independent of each other, but in reality, constituent elements are difficult to be completely divided according to their functions, and one constituent element involves a plurality of functions.

In the memory unit 20, the memory circuits 21 are arranged in a matrix. The memory circuit 21 is used as a memory element.

In this specification and the like, a semiconductor device including a memory portion is sometimes referred to as a memory device. For example, the semiconductor device 10 may be referred to as a memory device.

Various storage methods can be used as the storage unit 20. For example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), phase change memory (PCM: phase-ChangeMemory), resistive random access memory (ReRAM: resistiveRandomAccessMemory), magnetoresistive random access memory (MRAM: magnetoresistiveRandomAccessMemory), ferroelectric random access memory (FeRAM: ferroelectricRandomAccessMemory), or antiferroelectric memory (Antiferroelectric Memory) or the like may also be used.

Also, NOSRAM (Nonvolaite Oxide Semiconductor RandomAccess Memory) or DOSRAM (Dynamic Oxide Semiconductor RandomAccess Memory) may be used as the storage unit 20.

"NOSRAM (registered trademark)" is an abbreviation of "Nonvolatile Oxide Semiconductor RandomAccess Memory (RAM)". NOSRAM refers to a memory in which the memory circuit is a two transistor (2T) or three transistor (3T) gain cell and the access transistor is an OS transistor. The OS transistor flows a current between the source and the drain in an off state, that is, a leakage current is extremely small. NOSRAM can perform readout (non-destructive readout) without destroying the held data.

"DOSRAM (registered trademark)" is an abbreviation of "Dynamic Oxide SemiconductorRAM (oxide semiconductor dynamic random access memory)" and refers to a RAM including a 1T (transistor) 1C (capacitor) memory cell. As with NOSRAM, DOSRAM is also a memory using the feature that the off-state current of the OS transistor is low.

The word line driving circuit 31 is electrically connected to the memory circuit 21 through a word line. For example, the memory circuits 21 of the same row may all be electrically connected to the same word line. The word line driving circuit 31 has a function of supplying signals to the memory circuit 21 for writing data and the memory circuit 21 for reading data. That is, the word line driving circuit 31 has the following functions: signals for selecting the memory circuit 21 for writing data and the memory circuit 21 for reading data, that is, selection signals are generated.

The bit line driver circuit 32 is electrically connected to the memory circuit 21 via a bit line. For example, the memory circuits 21 of the same column may all be electrically connected to the same bit line. The bit line driver circuit 32 has a function of generating data written to the memory circuit 21. Specifically, the data generated by the bit line driver circuit 32 is written to the memory circuit 21 selected by the selection signal generated by the word line driver circuit 31. The bit line driver circuit 32 has a function of amplifying and reading out data held in the memory circuit 21. Specifically, the data held in the memory circuit 21 selected by the selection signal generated by the word line driving circuit 31 is amplified and read by the bit line driving circuit 32.

The control circuit 33 has a function of controlling driving of the word line driving circuit 31 and the bit line driving circuit 32. Specifically, the control circuit 33 may process a signal such as an enable signal supplied from the outside of the semiconductor device 10 to the control circuit 33 to supply a control signal to the word line driving circuit 31 and the bit line driving circuit 32. The control circuit 33 may have a function of controlling driving of the communication circuit 34 and the input/output circuit 35. The control circuit 33 may include, for example, a CPU.

The communication circuit 34 has a function of performing communication wirelessly or by wire. In particular, when the wireless communication function is provided, the number of components such as cables for connection can be omitted, which is preferable.

The communication circuit 34 can communicate via an antenna when having a function of communicating wirelessly. As communication protocol or communication technology may be used: communication standards such as LTE (LongTerm Evolution: long term evolution), GSM (Global SystemforMobile Communication: global system for mobile communications) (registered trademark), EDGE (ENHANCEDDATARATES FORGSM EVOLUTION: enhanced data rates for GSM evolution), CDMA2000 (CodeDivisionMultiple Access: code division multiple access 2000), W-CDMA (registered trademark); or specifications standardized by IEEE (institute of electrical and electronics engineers) communication such as Wi-Fi (registered trademark), bluetooth (registered trademark), zigBee (registered trademark), and the like.

The communication circuit 34 CAN input or output information by connecting the semiconductor device 10 to other devices via a computer network such as the internet, intranet, extranet, PAN (Personal Area Network: personal area network), LAN (LocalAreaNetwork: local area network), CAN (CampusAreaNetwork: campus network), MAN (MetropolitanAreaNetwork: metropolitan area network), WAN (WideArea Network: wide area network), GAN (GlobalAreaNetwork: global network) or the like, which are the basis of world wide web (WWW: world wide web).

The input/output circuit 35 has a function of supplying a signal supplied to the semiconductor device 10 from outside the semiconductor device 10 to a circuit included in the semiconductor device 10. For example, the input-output circuit 35 has a function of receiving a signal from the outside of the semiconductor device 10 and supplying the signal to the control circuit 33. The input/output circuit 35 may have a function of supplying a signal supplied to the communication circuit 34 to a circuit included in the semiconductor device 10, such as the control circuit 33.

The input/output circuit 35 has a function of outputting a signal generated by a circuit in the semiconductor device 10 to the outside of the semiconductor device 10. For example, the input/output circuit 35 has a function of outputting a data signal indicating data read out from the memory circuit 21 by the bit line driving circuit 32 to the outside of the semiconductor device 10. The input/output circuit 35 may also have a function of supplying a signal generated by a circuit in the semiconductor device 10 to the communication circuit 34. The signal supplied to the communication circuit 34 may be output to the outside of the semiconductor device 10.

Fig. 2 is a perspective view showing a structural example of a semiconductor device 10A which is one type of the semiconductor device 10. As shown in fig. 2, the semiconductor device 10A includes a layer 11 and a layer 12 on the layer 11.

Layer 11 is provided with Si transistors. Specifically, the layer 11 includes a silicon substrate, and a Si transistor is provided in such a manner that a channel formation region is formed in the silicon substrate. The Si transistor may be, for example, a single crystal Si transistor. For example, by providing a single crystal silicon substrate in the layer 11 and providing a transistor in such a manner that a channel formation region is formed in the single crystal silicon substrate, a single crystal Si transistor can be provided in the layer 11. Note that a transistor including polysilicon in a channel formation region (hereinafter also referred to as a poly-Si transistor) may be provided in the layer 11, for example.

Layer 12 is provided with n-channel transistors, for example with OS transistors. Specifically, an interlayer insulating film may be provided on the layer 11 and an OS transistor may be provided on the interlayer insulating film.

The OS transistor has a characteristic that an off-state current is extremely low. Therefore, when an OS transistor is used as a transistor provided in the memory circuit 21, data written to the memory circuit 21 can be held for a long period of time. Fig. 2 shows an example in which a memory section 20 including a memory circuit 21 is provided in the layer 12.

Examples of metal oxides that can be used for the OS transistor include In oxide, zn oxide, zn—sn oxide, ga—sn oxide, in—ga oxide, in—zn oxide, and in—m—zn oxide (M is Ti, ga, Y, zr, la, ce, nd, sn or Hf). In particular, when a metal oxide using Ga as M is used for an OS transistor, a transistor having excellent electrical characteristics such as field effect mobility can be formed by adjusting the element ratio, which is preferable. In addition, the oxide containing indium and zinc may further contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

The word line driver circuit 31, the bit line driver circuit 32, the control circuit 33, the communication circuit 34, and the input/output circuit 35 shown in fig. 1 use various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit. These circuits include CMOS circuits.

As described above, the OS transistor provided in the layer 12 may be an n-channel type transistor. Then, in the semiconductor device 10A, an n-channel type transistor among transistors constituting a CMOS circuit is provided in the layer 12, and a p-channel type transistor is provided in the layer 11. In the semiconductor device 10A, a word line driver circuit 31p, a bit line driver circuit 32p, a control circuit 33p, a communication circuit 34p, and an input/output circuit 35p each including a p-channel transistor are provided in the layer 11, and a word line driver circuit 31n, a bit line driver circuit 32n, a control circuit 33n, a communication circuit 34n, and an input/output circuit 35n each including an n-channel transistor are provided in the layer 12.

The word line driving circuit 31 is constituted by a word line driving circuit 31p and a word line driving circuit 31 n. The bit line driver circuit 32 is constituted by a bit line driver circuit 32p and a bit line driver circuit 32 n. The control circuit 33 is constituted by a control circuit 33p and a control circuit 33 n. The communication circuit 34 is constituted by a communication circuit 34p and a communication circuit 34 n. The input/output circuit 35 is constituted by an input/output circuit 35p and an input/output circuit 35 n.

Layer 11 includes a plurality of Si transistors and layer 12 includes a plurality of OS transistors. Thus, it can be said that layer 11 includes a Si transistor group and layer 12 includes an OS transistor group. Here, for example, all Si transistors in the layer 11 may be collectively referred to as one Si transistor group, and all OS transistors in the layer 12 may be collectively referred to as one OS transistor group.

Alternatively, layer 11 may be said to comprise a plurality of Si transistor groups and layer 12 may comprise a plurality of OS transistor groups. For example, each circuit can also be said to comprise a different transistor group. For example, it can be said that the word line driver circuit 31p and the bit line driver circuit 32p include different Si transistor groups, and the word line driver circuit 31n and the bit line driver circuit 32n include different OS transistor groups. In the case where the layer 11 includes a plurality of Si transistor groups and the layer 12 includes a plurality of OS transistor groups, it can be said that one Si transistor group and one OS transistor group are used to constitute a circuit having one or more functions.

Fig. 3 is a circuit diagram showing an example of a CMOS circuit included in the semiconductor device 10A. In fig. 3, an inverter is shown as an example of a CMOS circuit.

As shown in fig. 3, an inverter may be constituted by a transistor 41p provided in the layer 11 and a transistor 41n provided in the layer 12. The transistor 41p is a p-channel Si transistor, and the transistor 41n is an n-channel OS transistor.

The gate of the transistor 41p and the gate of the transistor 41n are electrically connected to the terminal IN. One of a source and a drain of the transistor 41p and one of a source and a drain of the transistor 41n are electrically connected to the terminal OUT. The other of the source and the drain of the transistor 41p is supplied with the potential VDD. The other of the source and the drain of the transistor 41n is supplied with the potential VSS.

The potential VDD and the potential VSS may be power supply potentials. The potential VDD is also referred to as a high potential or a high-level side power supply potential, and the potential VSS is also referred to as a low potential or a low-level side power supply potential.

The inverter shown IN fig. 3 has a function of inverting a logic value shown by a digital signal input to the terminal IN and outputting from the terminal OUT. Specifically, when a digital signal having a logical value of "0" is input to the terminal IN, a digital signal having a logical value of "1" is output from the terminal OUT. IN addition, when a digital signal having a logical value of "1" is input to the terminal IN, a digital signal having a logical value of "0" is output from the terminal OUT. Specifically, for example, when a low potential signal, which is a digital signal having a logical value of "0", is input to the terminal IN, the transistor 41p is turned on, the transistor 41n is turned off, and a high potential signal is output from the terminal OUT as a digital signal having a logical value of "1". On the other hand, when a high potential signal is input to the terminal IN, the transistor 41p is turned off, the transistor 41n is turned on, and a low potential signal is output from the terminal OUT as a digital signal having a logical value of "0".

A p-channel type transistor is provided in layer 11 and an n-channel type transistor is provided in layer 12. That is, a structure in which p-channel type transistors and n-channel type transistors are stacked is adopted, whereby the number of transistors provided in the layer 11, for example, can be reduced. Therefore, the occupied area of the semiconductor device can be reduced. Therefore, the semiconductor device 10A can be miniaturized. Note that all n-channel transistors included in the semiconductor device 10A may not be provided in the layer 12. For example, an n-channel transistor which does not constitute a CMOS circuit may also be provided in the layer 11.

Here, when the channel length and the channel width are equal, the mobility of the Si transistor is higher than that of the OS transistor. In particular, when a Si transistor in which silicon having higher crystallinity than amorphous silicon is used for a channel formation region, such as a single crystal Si transistor or a polycrystalline Si transistor, is used as the Si transistor, the mobility of the Si transistor is higher than that of the OS transistor. On the other hand, when the difference between the mobility of the p-channel transistor and the mobility of the n-channel transistor constituting the CMOS is large, the CMOS circuit may not be normally driven. For example, when the difference between the mobility of the transistor 41p and the mobility of the transistor 41n shown in fig. 3 is large, the difference between the on-state current of the transistor 41p and the on-state current of the transistor 41n is also large, and thus the inverter may not be normally driven. For example, a digital signal having a logical value of "0" may not be output from the terminal OUT.

In view of this, in the semiconductor device 10A, the channel length of the Si transistor provided in the layer 11 among the transistors constituting the CMOS circuit is made longer than the channel length of the OS transistor provided in the layer 12. For example, the channel length of the transistor 41p is made longer than the channel length of the transistor 41 n. Since the longer the channel length is, the higher the source-drain resistance and the lower the mobility are, for example, by making the channel length of the transistor 41p longer than the channel length of the transistor 41n, the difference between the mobilities of the transistor 41p and the transistor 41n can be further reduced as compared with the case where the channel lengths of the transistor 41p and the transistor 41n are equal. For example, the mobility of the transistor 41p may be 300 times or less, 100 times or less, 50 times or less, 30 times or less, or 10 times or less the mobility of the transistor 41 n.

Thus, the difference between on-currents of the transistor 41p and the transistor 41n can be reduced, and thus an inverter as a CMOS circuit can be normally driven. Specifically, both a digital signal having a logical value of "0" and a digital signal having a logical value of "1" may be output from the terminal OUT. Even in a CMOS circuit other than the inverter, normal driving can be performed by making the channel length of the Si transistor provided in the layer 11 longer than the channel length of the OS transistor provided in the layer 12.

Hereinafter, with respect to an inverter shown as one example of a CMOS circuit in fig. 3, specific examples of the channel length of the transistor 41p as a Si transistor provided in the layer 11 and the channel length of the transistor 41n as an OS transistor provided in the layer 12 are described.

For example, in view of ease of manufacturing the transistor 41n, it is preferable that the channel length of the transistor 41p be 15nm or more and the channel length of the transistor 41n be less than 15nm. Alternatively, the channel length of the transistor 41p is preferably 15nm or more and 40nm or less, and the channel length of the transistor 41n is preferably 3nm or more and less than 15nm. The channel length of the transistor 41n may be typically 5nm or more and 8nm or less.

In addition, the integration level of the transistor in the layer 12 may be made lower than that of the transistor in the layer 11. For example, the integration level of the transistors in the layer 11 including the Si transistors may be 50/μm ² or more, preferably 100/μm ² or more. On the other hand, the integration level of transistors in layer 12 including OS transistors may be less than 50/μm ². In addition, the integration level of the transistor in the layer 12 may be 0.01 or more and less than 1 of the integration level of the transistor in the layer 11. In particular, for example, in the case where an n-channel transistor which does not constitute a CMOS circuit is provided in the layer 11, the integration of the transistor in the layer 12 can be made lower than that of the transistor in the layer 11.

In this specification and the like, the integration level of transistors indicates the number of transistors per unit area. The integration of a transistor may also be referred to as the density of the transistor. In addition, the integration level of a transistor may also be referred to as the integration level of a transistor group.

An OS transistor, which is a transistor including a metal oxide in a channel formation region, may have easily changed electrical characteristics when an oxygen vacancy (V _O) exists in the channel formation region, and may have reduced reliability. In addition, hydrogen in the vicinity of the oxygen vacancy forms a defect (hereinafter sometimes referred to as V _O H) in which hydrogen enters the oxygen vacancy, and electrons that become carriers may be generated. When V _O H is formed in the metal oxide, the metal oxide sometimes becomes a low-resistance region or an n-type region. In addition, indium (In) and V _O H are bonded to a metal oxide to form InV _O H. The InV _O H is used as part of an n-type region (also referred to as an n-type conductivity region). In this case, the metal oxide has a region where a channel is formed and an n-type region, and the region where a channel is formed is preferably in a state where oxygen vacancies (V _O) are smaller than the n-type region.

More specifically, when oxygen vacancies are included in a region of a metal oxide where a channel is formed, the transistor has normally-on characteristics (characteristics that a channel exists and a current flows in the transistor even if a voltage is not applied to a gate electrode). Accordingly, in the channel formation region of the metal oxide, oxygen vacancies and V _O H are preferably reduced as much as possible. In other words, it is preferable that the carrier concentration of the region forming the channel in the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

In contrast, oxygen vacancies and VoH can be reduced by supplying oxygen to the channel formation region of the metal oxide in the manufacturing process of the OS transistor. For example, oxygen can be supplied from an insulator containing oxygen (hereinafter, sometimes referred to as excess oxygen) detached by heating to the metal oxide by performing heat treatment in the vicinity of the metal oxide.

The semiconductor device according to one embodiment of the present invention may have a structure in which the channel length of the OS transistor is short and the integration level is low. Thus, in particular, when oxygen is supplied from the insulator containing excess oxygen to the metal oxide, the amount of oxygen supplied to the metal oxide per unit area is large. Specifically, by making the channel length of the OS transistor shorter than the channel length of the Si transistor and making the integration of the OS transistor lower than that of the Si transistor, the amount of oxygen supplied to the unit area of the metal oxide can be appropriately increased. Thus, oxygen vacancies and VoH of the metal oxide can be appropriately reduced, and the semiconductor device according to one embodiment of the present invention can be made highly reliable.

< Structural example of memory Circuit >

Here, a configuration example of the memory circuit 21 is described with reference to fig. 4A to 4H. The memory circuits 21A to 21H shown in fig. 4A to 4H are memory circuits using OS transistors, and can be roughly divided into NOSRAM of fig. 4A to 4F and DOSRAM of fig. 4G and 4H.

Fig. 4A shows a circuit configuration example applicable to the memory circuit 21. Here, the memory circuit 21A is a two transistor type (2T) gain unit. The memory circuit 21A includes a transistor MW1, a transistor MR1, and a capacitor CS1. One of the source and the drain of the transistor MW1 is electrically connected to the gate of the transistor MR1, and the gate of the transistor MR1 is electrically connected to one electrode of the capacitor CS1. The transistors MW1 and MR1 may be OS transistors. The transistor MW1 is a write transistor, and the transistor MR1 is a read transistor.

The other of the source and the drain of the transistor MW1 is electrically connected to the bit line WBL. The gate of transistor MW1 is electrically connected to word line WWL. One of the source and the drain of the transistor MR1 is electrically connected to the bit line RBL. The other of the source and the drain of the transistor MR1 is electrically connected to the source line SL. The back gate of the transistor MW1 and the back gate of the transistor MR1 are electrically connected to the wiring BGL.

The write transistor has a function as a switch for controlling writing and holding of data to the memory circuit 21. When the write transistor is turned on, data is written into the memory circuit 21, and when the write transistor is turned off, data is held in the memory circuit 21. The read transistor has a function of amplifying and reading out data held in the memory circuit 21.

Since the write transistor is constituted by an OS transistor, the memory circuit 21A consumes no power when holding data. Therefore, the memory circuit 21A is a low power consumption memory circuit capable of holding data for a long period of time, and the memory section 20 can be used as a nonvolatile memory device.

The memory circuit 21B shown in fig. 4B is a 3T type gain cell including a transistor MW2, a transistor MR2, a transistor MS2, and a capacitor CS2. The transistor MW2, the transistor MR2, and the transistor MS2 are a writing transistor, a reading transistor, and a selection transistor, respectively. The back gate of the transistor MW2, the back gate of the transistor MR2, and the back gate of the transistor MS2 are electrically connected to the wiring BGL. The memory circuit 21B is electrically connected to the word line RWL, the word line WWL, the bit line RBL, the bit line WBL, the capacitor line CDL, and the power supply line PL. For example, the capacitor line CDL and the power supply line PL are input with a potential GND (low-level side power supply potential).

The selection transistor has a function as a switch of the memory circuit 21 that selects readout data. By turning on the selection transistor, the data held in the memory circuit 21 is read. Specifically, by turning on the selection transistor, a current corresponding to the data held in the memory circuit 21 flows between the drain-source electrodes of the read transistor and the selection transistor, and the data is amplified and read.

Fig. 4C and 4D show other structural examples of the 2T-type gain unit. In the memory circuit 21C shown in fig. 4C, the read transistor is constituted by an n-channel Si transistor. In the memory circuit 21C shown in fig. 4D, the read transistor is constituted by a p-channel Si transistor. As shown in fig. 4C and 4D, a structure in which an OS transistor and a Si transistor are combined as transistors in a memory circuit may be employed.

Fig. 4E and 4F show other structural examples of the 3T-type gain unit. The memory circuit 21E shown in fig. 4E includes a transistor MW3, a transistor MR3, a transistor MS3, and a capacitor CS3. The transistor MW3, the transistor MR3, and the transistor MS3 are a writing transistor, a reading transistor, and a selection transistor, respectively. In the memory circuit 21E, the read transistor and the select transistor are formed of n-channel Si transistors. In the example shown in fig. 4E, the power supply line PL is inputted with the potential VSS. In the memory circuit 21F shown in fig. 4F, the read transistor and the select transistor are constituted by p-channel Si transistors. In the example shown in fig. 4F, the power supply line PL is inputted with the potential VDD.

As shown in fig. 4C to 4F, when the memory circuit 21 includes a Si transistor, the transistor may be provided in the layer 11. Accordingly, the memory circuit 21 may adopt a structure including a Si transistor provided in the layer 11 and an OS transistor provided in the layer 12.

In the gain cell, a bit line that serves as both a bit line RBL for reading and a bit line WBL for writing may be provided.

Fig. 4G and 4H show examples of 1T1C (capacitor) memory circuits. The memory circuit 21G shown in fig. 4G is electrically connected to the word line WL, the bit line BL, the capacitor line CDL, and the wiring BGL. The memory circuit 21G includes a transistor MW4 and a capacitor CS4. The back gate of the transistor MW4 is electrically connected to the wiring BGL. In addition, in the memory circuit 21H shown in fig. 4H, a structure of a ferroelectric memory using a capacitor containing a ferroelectric material as the capacitor CS4 is shown. For example, hfZrO _X can be used as the ferroelectric material.

Structural example of semiconductor device 2-

Fig. 5 is a perspective view showing a structural example of a semiconductor device 10B which is one type of the semiconductor device 10. Hereinafter, a structure of the semiconductor device 10B different from that of the semiconductor device 10A will be mainly described.

In the semiconductor device 10B, the layer 11 is provided with memory portions 20r, and the memory portions 20r are arranged in a matrix form with circuits 21r. The layer 12 is provided with memory sections 20w, and the memory sections 20w are arranged in a matrix form with circuits 21w. The memory unit 20 is constituted by a memory unit 20r and a memory unit 20w, and the memory circuit 21 is constituted by a circuit 21r and a circuit 21w.

In the semiconductor device 10B, the memory circuit 21 can have a structure shown in fig. 4C to 4F. For example, in the case where the memory circuit 21 includes a write transistor and a read transistor, the read transistor is provided in the circuit 21r, and the write transistor is provided in the circuit 21 w. In addition, in the case where the memory circuit includes a selection transistor, the selection transistor is provided in the circuit 21 r.

As shown in fig. 5, by forming the memory portion 20 across both the layers 11 and 12, the occupied area of the memory portion 20 can be further reduced as compared with the case where, for example, all the constituent elements of the memory portion 20 are formed in the layers 11 or 12. Therefore, the occupied area of the semiconductor device can be reduced. Therefore, the semiconductor device 10B can be miniaturized.

Note that in the semiconductor device 10B, for example, the word line driver circuit 31, the bit line driver circuit 32, the control circuit 33, the communication circuit 34, and the input/output circuit 35 may not be formed across both the layers 11 and 12. For example, the components of the word line driver circuit 31, the bit line driver circuit 32, the control circuit 33, the communication circuit 34, and the input/output circuit 35 may be formed only in the layer 11, not in the layer 12. At this time, all the transistors included in the word line driver circuit 31, the bit line driver circuit 32, the control circuit 33, the communication circuit 34, and the input/output circuit 35 may be Si transistors.

Fig. 6 is a circuit diagram showing an example of the memory circuit 21 included in the semiconductor device 10B. Fig. 6 shows an example in which the memory circuit 21 has the structure shown in fig. 4E.

As shown in fig. 6, the memory circuit 21 in the semiconductor device 10B includes a layer 11 and a layer 12 on the layer 11. Layer 11 is provided with transistor MR3 and transistor MS3. Layer 12 is provided with transistor MW3 and capacitor CS3. The transistors MR3, MS3 and MW3 may be n-channel transistors. Note that the capacitor CS3 may be provided in a layer other than the layer 12. For example, the capacitor CS3 may be disposed in a layer above the layer 12.

One of the source and the drain of the transistor MR3 is electrically connected to one of the source and the drain of the transistor MS 3. The gate of the transistor MR3 is electrically connected to one of the source and the drain of the transistor MW 3. One of the source and the drain of the transistor MW3 is electrically connected to one electrode of the capacitor CS 3.

The other of the source and the drain of the transistor MR3 is electrically connected to the power supply line PL. The other of the source and the drain of the transistor MS3 is electrically connected to the bit line RBL. The gate of the transistor MS3 is electrically connected to the word line RWL. The other of the source and the drain of the transistor MW3 is electrically connected to the bit line WBL. The gate of transistor MW3 is electrically connected to word line WWL. The back gate of the transistor MW3 is electrically connected to the wiring BGL. The other electrode of the capacitor CS3 is electrically connected to the capacitance line CDL.

The transistor MR3 and the transistor MS3 are provided in the layer 11, and thus may be Si transistors. Transistor MW3 is disposed in layer 12 and thus may be an OS transistor. As described above, when the Si transistor, particularly the single crystal Si transistor, the poly-Si transistor, and the like are equal to the channel length, the channel width, and the like of the OS transistor, mobility is larger than that of the OS transistor, and thus on-state current is larger than that of the OS transistor. Therefore, when the Si transistor is used as the transistor MR3 or the transistor MS3, data can be read out from the memory circuit 21 at a higher speed than when, for example, an OS transistor is used as the transistor MR3 or the transistor MS 3. On the other hand, the off-state current of the OS transistor is smaller than that of the Si transistor. Therefore, in the case where an OS transistor is used as the transistor MW3, data can be held in the memory circuit 21 for a long period of time as compared with the case where, for example, an Si transistor is used as the transistor MW 3.

On the other hand, when the channel length, channel width, and the like of the Si transistor provided in the layer 11 and the OS transistor provided in the layer 12 are equal, it is necessary to change the potential supplied to the gate of the transistor serving as a switch according to the kind of the transistor. For example, it is necessary to make the potential supplied to the word line WWL when the transistor MW3 as the OS transistor serving as a switch is turned on higher than the potential supplied to the word line RWL when the transistor MS3 as the Si transistor serving as a switch is turned on.

In the semiconductor device 10B, the channel length of the Si transistor provided in the layer 11 among the transistors included in the memory circuit 21 is made longer than the channel length of the OS transistor provided in the layer 12. For example, the channel length of the transistor MR3 and the transistor MS3 is made longer than the channel length of the transistor MW 3. Thus, for example, the potential supplied to the word line RWL when the transistor MS3 is turned on and the potential supplied to the word line WWL when the transistor MW3 is turned on can be equalized. In addition, for example, the potential supplied to the word line RWL when the transistor MS3 is turned off and the potential supplied to the word line WWL when the transistor MW3 is turned off may be equalized. Therefore, the potential supplied to the word line RWL and the potential supplied to the word line WWL can be supplied from the same power supply, for example. In the semiconductor device 10B, by further making the channel length of the Si transistor longer than the channel length of the OS transistor among the transistors serving as switches provided in the circuits other than the memory section 20, the potential supplied to the gate of the n-channel Si transistor and the potential supplied to the gate of the OS transistor can be supplied from the same power supply.

In this specification and the like, for example, the potential supplied to the word line WWL when the transistor MW3 is turned on is referred to as a first potential, the potential supplied to the word line WWL when the transistor MW3 is turned off is referred to as a second potential, the potential supplied to the word line RWL when the transistor MS3 is turned on is referred to as a third potential, and the potential supplied to the word line RWL when the transistor MS3 is turned on is referred to as a fourth potential. Note that the ordinal words "first" to "fourth" may also be exchanged as appropriate.

A specific example of the channel lengths of the transistor MR3 and the transistor MS3 as Si transistors provided in the layer 11 and the channel length of the transistor MW3 as OS transistors provided in the layer 12 in the memory circuit 21 shown in fig. 6 will be described below.

For example, in view of ease of manufacturing the transistor MW3, it is preferable that the channel lengths of the transistors MR3 and MS3 be 15nm or more and the channel length of the transistor MW3 be less than 15nm. Alternatively, it is preferable that the channel length of the transistor MR3 and the transistor MS3 be 15nm or more and 40nm or less and the channel length of the transistor MW3 be 3nm or more and less than 15nm. The channel length of transistor MW3 may typically be above 5nm and below 8 nm.

Here, for example, in the case where the memory circuit 21 has the structure shown in fig. 6, two transistors are provided in the circuit 21r shown in fig. 5, and one transistor is provided in the circuit 21 w. Therefore, in the semiconductor device 10B, for example, the integration of the transistor in the memory portion 20w can be made lower than the integration of the transistor in the memory portion 20 r. For example, the integration level of the transistors in the memory portion 20r may be 50 or more per μm ², and preferably 100 or more per μm ². On the other hand, the integration level of the transistors in the memory portion 20w may be less than 50/μm ². Note that, as described above, for example, the channel length of the transistor MW3 is shorter than that of the transistor MR2, and therefore, even if the memory circuit 21 does not include the transistor MS3, the integration of the transistor in the memory portion 20w can be made smaller than that of the transistor in the memory portion 20 r.

As described above, the semiconductor device according to one embodiment of the present invention may have a structure in which the channel length of the OS transistor is short and the integration level is low. Thus, in particular, when oxygen is supplied from the insulator containing excess oxygen to the metal oxide, the amount of oxygen supplied to the metal oxide per unit area is large. Specifically, by making the channel length of the OS transistor shorter than the channel length of the Si transistor and making the integration of the OS transistor lower than that of the Si transistor, the amount of oxygen supplied to the unit area of the metal oxide can be appropriately increased. Thus, oxygen vacancies and VoH of the metal oxide can be appropriately reduced, and the semiconductor device according to one embodiment of the present invention can be made highly reliable.

< Structural example of transistor >

Fig. 7A is a plan view showing a transistor 200, which is an OS transistor included in the semiconductor device according to an embodiment of the present invention, and a configuration example around the transistor 200. Fig. 7B, 7C, and 7D are cross-sectional views showing examples of the structure of the transistor 200 and the periphery thereof. Here, fig. 7B is a cross-sectional view of a portion along the chain line A1-A2 in fig. 7A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Fig. 7C is a cross-sectional view of a portion along the chain line A3 to A4 in fig. 7A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In addition, fig. 7D is a sectional view of a portion along the chain line A5-A6 in fig. 7A. Note that, in the plan view of fig. 7A, some constituent elements are omitted for clarity.

The transistor 200 may be disposed in the layer 12 shown in fig. 2, 3, 5, and 6. For example, as the transistor 41n shown in fig. 3 and the transistor MW3 shown in fig. 6, the transistor 200 can be used.

A semiconductor device according to one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, and an insulator 285 over the insulator 283 and the insulator 274. The insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, the insulator 285, the insulator 274, and the insulator 285 are used as interlayer films. Further, a conductor 240a and a conductor 240b which are electrically connected to the transistor 200 and function as plugs are included. Further, an insulator 241a in contact with the side surface of the conductor 240a and an insulator 241b in contact with the side surface of the conductor 240b are also included.

In this specification and the like, a plurality of conductors used as plugs or wirings are sometimes denoted by the same reference numerals. In this specification, the wiring and the plug connected to the wiring may be one component. That is, a part of the electric conductor is sometimes used as a wiring, and a part of the electric conductor is sometimes used as a plug.

Further, the insulator 285 and the conductor 240a are provided with a conductor 246a electrically connected to the conductor 240a and used as a wiring, and the insulator 285 and the conductor 240b are provided with a conductor 246b electrically connected to the conductor 240b and used as a wiring. Further, the insulator 283 is in contact with a portion of the top surface of the insulator 214, the side surface of the insulator 280, and the side and top surfaces of the insulator 282.

The insulator 241a is provided so as to be in contact with the inner walls of the openings of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240a is provided so as to be in contact with the side surface of the insulator 241 a. Further, the insulator 241b is provided so as to be in contact with the inner walls of the openings of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240b is provided so as to be in contact with the side surface of the insulator 241 b. The insulators 241a and 241b have a structure in which a first insulator is provided so as to be in contact with the inner wall of the opening, and a second insulator is provided inside the first insulator. The conductor 240a has a structure in which a first conductor is provided so as to contact the side surface of the insulator 241a, and a second conductor is provided inside the first conductor. The conductor 240b has a structure in which a first conductor is provided so as to contact the side surface of the insulator 241b, and a second conductor is provided inside the first conductor. Here, the top surface height of the conductor 240a may be substantially identical to the top surface height of the insulator 285 overlapping the region of the conductor 246 a. Here, the top surface height of the conductor 240b may be substantially identical to the top surface height of the insulator 285 overlapping the region of the conductor 246 b.

In the transistor 200, the first insulator and the second insulator of each of the insulator 241a and the insulator 241b are stacked, but the present invention is not limited thereto. For example, the insulator 241a and the insulator 241b may have a single-layer structure or a stacked-layer structure of three or more layers. In the transistor 200, the first conductor and the second conductor of each of the conductors 240a and 240b are stacked, but the present invention is not limited thereto. For example, the conductor 240a and the conductor 240b may have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a laminated structure, ordinals may be given in order of formation to distinguish them from each other.

Transistor 200 includes insulator 216 on insulator 214, insulator 205 (conductor 205a and conductor 205 b) disposed embedded in insulator 216, insulator 222 on insulator 216 and conductor 205, insulator 224 on insulator 222, metal oxide 230a on insulator 224, metal oxide 230b on metal oxide 230a, conductor 242a on metal oxide 230b, insulator 271a on conductor 242a, conductor 242b on conductor 242b, insulator 252 on metal oxide 230b, insulator 250 on insulator 252, insulator 254 on insulator 250, conductor 260 (conductor 260a and conductor 260 b) on insulator 254 and overlapping a portion of metal oxide 230b, and insulators 275 disposed on insulator 222, insulator 224, metal oxide 230a, metal oxide 230b, conductor 242a, conductor 242b, conductor 271a and insulator 275 b. Here, as shown in fig. 7B and 7C, the insulator 252 is in contact with at least a portion of each of the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the metal oxide 230a, the side and top surfaces of the metal oxide 230B, the side surfaces of the conductors 242a and 242B, the side surfaces of the insulators 271a and 271B, the side surface of the insulator 275, the side surface of the insulator 280, and the bottom surface of the insulator 250. The top surface of the conductor 260 is disposed so as to have a height substantially equal to the heights of the uppermost portion of the insulator 254, the uppermost portion of the insulator 250, the uppermost portion of the insulator 252, and the top surface of the insulator 280. In addition, insulator 282 is in contact with at least a portion of the top surface of each of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

Hereinafter, the metal oxide 230a and the metal oxide 230b may be collectively referred to as a metal oxide 230. Further, the conductors 242a and 242b may be collectively referred to as conductors 242. In addition, the insulator 271a and the insulator 271b are sometimes collectively referred to as an insulator 271.

Openings to the metal oxide 230b are provided in the insulator 280 and the insulator 275. That is, the opening can be said to include a region overlapping with the metal oxide 230 b. Further, the insulator 275 can be said to include an opening that overlaps with an opening included in the insulator 280. Further, an insulator 252, an insulator 250, an insulator 254, and a conductor 260 are provided in openings provided in the insulator 280 and the insulator 275 and reaching the metal oxide 230 b. That is, the conductor 260 includes a region overlapping the metal oxide 230b with the insulator 252, the insulator 250, and the insulator 254 interposed therebetween. Further, in the channel length direction of the transistor 200, the conductors 260, 252, 250, and 254 are provided between the conductors 271a and 242a and between the conductors 271b and 242 b. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

The metal oxide 230 preferably includes a metal oxide 230a on the insulator 224 and a metal oxide 230b on the metal oxide 230 a. When the metal oxide 230a is included under the metal oxide 230b, diffusion of impurities from a structure formed under the metal oxide 230a to the metal oxide 230b can be suppressed.

Note that in the transistor 200, the metal oxide 230 has a two-layered structure of the metal oxide 230a and the metal oxide 230b, but the present invention is not limited thereto. For example, the metal oxide 230 may have a single layer or a stacked structure of three or more layers of the metal oxide 230b, or may have a stacked structure of the metal oxide 230a and the metal oxide 230 b.

The electrical conductor 260 is used as a first gate (also referred to as a top gate) electrode and the electrical conductor 205 is used as a second gate (also referred to as a back gate) electrode. In addition, the insulator 252, the insulator 250, and the insulator 254 are used as a first gate insulator, and the insulator 222 and the insulator 224 are used as a second gate insulator. Note that the gate insulator is sometimes referred to as a gate insulating layer or a gate insulating film. Further, the conductor 242a is used as one of the source and the drain, and the conductor 242b is used as the other of the source and the drain. Further, at least a part of the region of the metal oxide 230 overlapping with the conductor 260 is used as a channel formation region.

Here, fig. 8A shows an enlarged view of the vicinity of the channel formation region in fig. 7B. Since the metal oxide 230b is supplied with oxygen, a channel formation region is formed in a region between the conductor 242a and the conductor 242 b. Accordingly, as shown in fig. 8A, the metal oxide 230b has a region 230bc serving as a channel formation region of the transistor 200, and a region 230ba and a region 230bb serving as source or drain regions thereof. As shown in fig. 8A, the region 230ba and the region 230bb are provided so as to sandwich the region 230 bc. At least a portion of region 230bc overlaps with conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242 b. Region 230ba overlaps conductor 242a and region 230bb overlaps conductor 242 b.

Since the region 230bc serving as a channel formation region has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, the region 230bc is a high-resistance region having a low carrier concentration. Thus, region 230bc may be said to be an i-type (intrinsic) or substantially i-type region.

In addition, the regions 230ba and 230bb used as the source region and the drain region have a large number of oxygen vacancies or have a high concentration of impurities such as hydrogen, nitrogen, and metal elements, and thus have a high carrier concentration, and therefore have a low resistance. That is, the region 230ba and the region 230bb are n-type regions having a higher carrier concentration and a lower resistance than the region 230 bc.

Here, the carrier concentration of the region 230bc used as the channel formation region is preferably 1×10 ¹⁸cm^-3 or less, more preferably less than 1×10 ¹⁷cm^-3, further preferably less than 1×10 ¹⁶cm^-3, more preferably less than 1×10 ¹³cm^-3, further preferably less than 1×10 ¹²cm^-3. The lower limit value of the carrier concentration of the region 230bc used as the channel formation region is not particularly limited, and may be set to 1×10 ^-9cm^-3, for example.

Further, a region having a carrier concentration equal to or lower than that of the region 230ba and the region 230bb and equal to or higher than that of the region 230bc may be formed between the region 230bc and the region 230ba or the region 230 bb. In other words, this region is used as a junction region of the region 230bc and the region 230ba or the region 230 bb. The hydrogen concentration of the junction region is sometimes equal to or lower than the hydrogen concentration of the regions 230ba and 230bb and equal to or higher than the hydrogen concentration of the region 230 bc. In addition, the oxygen vacancies of the junction region are sometimes equal to or less than the oxygen vacancies of region 230ba and region 230bb and equal to or more than the oxygen vacancies of region 230 bc.

Note that fig. 8A shows an example in which the region 230ba, the region 230bb, and the region 230bc are formed in the metal oxide 230b, but the present invention is not limited thereto. For example, the regions described above may be formed in the metal oxide 230b and the metal oxide 230 a.

In the metal oxide 230, it may be difficult to clearly observe the boundary of each region. The concentrations of the metal element and the impurity element such as hydrogen and nitrogen detected in each region do not need to be changed stepwise for each region, and may be changed gradually for each region. That is, the concentration of the metal element and the impurity element such as hydrogen and nitrogen may be lower as the channel formation region is closer.

A metal oxide used as a semiconductor (hereinafter, sometimes referred to as a metal oxide semiconductor) is preferably used for the metal oxide 230 (the metal oxide 230a, the metal oxide 230 b) including a channel formation region in the transistor 200.

The band gap of the metal oxide used as the semiconductor is preferably 2eV or more, more preferably 2.5eV or more. By using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced.

For example, as the metal oxide 230, a metal oxide such as an in—m—zn metal oxide containing indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. In addition, as the metal oxide 230, in—ga metal oxide, in—zn metal oxide, or indium metal oxide may also be used.

The metal oxide 230 preferably has a stacked structure of a plurality of metal oxide layers having different chemical compositions from each other. For example, the atomic number ratio of the element M of the metal element with respect to the main component in the metal oxide for the metal oxide 230a is preferably larger than the atomic number ratio of the element M of the metal element with respect to the main component in the metal oxide for the metal oxide 230 b. In addition, the atomic number ratio of In to the element M In the metal oxide for the metal oxide 230a is preferably larger than the atomic number ratio of In to the element M In the metal oxide for the metal oxide 230 b. By adopting such a structure, diffusion of impurities and oxygen from a structure formed below the metal oxide 230a to the metal oxide 230b can be suppressed.

Here, it is preferable that the atomic number ratio of In to the element M In the metal oxide used for the metal oxide 230b is larger than the atomic number ratio of In to the element M In the metal oxide used for the metal oxide 230 a. By adopting this structure, the transistor 200 can obtain a high on-state current and a high frequency characteristic.

Further, since the metal oxide 230a and the metal oxide 230b contain a common element as a main component in addition to oxygen, the defect state density of the interface between the metal oxide 230a and the metal oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 200 can obtain high on-state current and high frequency characteristics.

Specifically, as the metal oxide 230a, a metal oxide having a composition of In: M: zn=1:3:4 [ atomic number ratio ] or the vicinity thereof or a composition of In: M: zn=1:1:0.5 [ atomic number ratio ] or the vicinity thereof may be used. As the metal oxide 230b, a metal oxide having a composition of In: M: zn=1:1:1 [ atomic number ratio ] or the vicinity thereof, a composition of In: M: zn=1:1:1.2 [ atomic number ratio ] or the vicinity thereof, a composition of In: M: zn=1:1:2 [ atomic number ratio ] or the vicinity thereof, or a composition of In: M: zn=4:2:3 [ atomic number ratio ] or the vicinity thereof may be used. Note that the nearby composition includes a range of ±30% of the desired atomic number ratio. Further, gallium is preferably used as the element M. In addition, when a single layer of the metal oxide 230b is provided as the metal oxide 230, a metal oxide usable for the metal oxide 230a can be used as the metal oxide 230 b.

In the case of depositing a metal oxide by a sputtering method, the atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and may be an atomic ratio of a sputtering target used for the deposition of the metal oxide.

The metal oxide 230b preferably has crystallinity. In particular, CAAC-OS (c-axis alignedcrystallineoxidesemiconductor: c-axis oriented crystalline metal oxide semiconductor) is preferably used as the metal oxide 230b.

The CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, the CAAC-OS can have a dense structure with higher crystallinity by performing a heat treatment at a temperature (for example, 400 ℃ or more and 600 ℃ or less) at which the metal oxide is not polycrystallized after the metal oxide is formed. Thus, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

In addition, since a clear grain boundary is not easily observed in CAAC-OS, a decrease in electron mobility due to the grain boundary is not easily generated. Thus, the metal oxide containing CAAC-OS is stable in physical properties. Therefore, the metal oxide having the CAAC-OS has heat resistance and high reliability.

In addition, when a metal oxide having crystallinity such as CAAC-OS is used as the metal oxide 230b, oxygen extraction from the metal oxide 230b by the source electrode or the drain electrode can be suppressed. Therefore, oxygen extraction from the metal oxide 230b can be reduced even by heat treatment, so that the transistor 200 is stable to high temperatures (so-called thermal budget) in the manufacturing process.

In a transistor using a metal oxide semiconductor, if impurities and oxygen vacancies exist in a region of the metal oxide semiconductor where a channel is formed, electrical characteristics tend to be changed, and reliability may be lowered. In addition, hydrogen in the vicinity of the oxygen vacancy forms a defect (hereinafter sometimes referred to as V _O H) in which hydrogen enters the oxygen vacancy, and electrons that become carriers may be generated. Therefore, when oxygen vacancies are included in a region of the metal oxide semiconductor where a channel is formed, the transistor has normally-on characteristics (characteristics that a channel exists and a current flows in the transistor even if a voltage is not applied to the gate electrode). Accordingly, in the region where the channel is formed in the metal oxide semiconductor, impurities, oxygen vacancies, and V _O H are preferably reduced as much as possible. In other words, it is preferable that the carrier concentration of the region forming the channel in the metal oxide semiconductor is reduced and is i-typed (intrinsic) or substantially i-typed.

In contrast, by providing an insulator containing oxygen (hereinafter, sometimes referred to as excess oxygen) desorbed by heating in the vicinity of the metal oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the metal oxide semiconductor to reduce oxygen vacancies and V _O H. Note that when too much oxygen is supplied to the source region or the drain region, there is a possibility that on-state current of the transistor 200 is lowered or field-effect mobility is lowered. Also, when the amount of oxygen supplied to the source region or the drain region is uneven in the substrate surface, the characteristics of the semiconductor device including the transistor are uneven. Further, when oxygen supplied from the insulator to the metal oxide semiconductor diffuses into conductors such as a gate electrode, a source electrode, and a drain electrode, the conductors may be oxidized, which may cause a loss of conductivity, and thus adversely affect the electrical characteristics and reliability of the transistor.

Therefore, in the metal oxide semiconductor, it is preferable that the carrier concentration of the region 230bc serving as the channel formation region is reduced and is i-shaped or substantially i-shaped. On the other hand, it is preferable that the regions 230ba and 230bb serving as the source region or the drain region have a high carrier concentration and are n-type. In other words, it is preferable that oxygen vacancies and V _O H of the region 230bc and the region 230ba and the region 230bb of the metal oxide semiconductor are reduced and that excessive oxygen is not supplied. Further, it is preferable to use a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like.

In this embodiment mode, the semiconductor device has a structure in which oxygen is efficiently supplied to the region 230bc and oxidation of the conductors 242a, 242b, and 260 is suppressed.

In order to supply oxygen to the region 230bc, an insulator which is easily permeable to oxygen is preferably used as the insulator 250. Further, as the insulator 280, an insulator containing excess oxygen is preferably used. By adopting this structure, oxygen contained in the insulator 280 can be supplied to the region 230bc through the insulator 250.

Further, in order to suppress oxidation of the conductors 242a, 242b, and 260, an insulator having a function of suppressing diffusion of oxygen is preferably provided in the vicinity of each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 252, the insulator 254, or the insulator 275.

Insulator 252 preferably has oxygen barrier properties. Insulator 252 is disposed between insulator 250 and conductor 242a and between insulator 250 and conductor 242 b. Accordingly, oxygen included in the insulator 250 can be prevented from diffusing to the conductors 242a and 242b, whereby the conductors 242a and 242b can be suppressed from being oxidized. Or the amount of oxygen contained in the insulator 250 that diffuses into the conductors 242a and 242b is reduced, whereby the layers (corresponding to the layers 244a and 244b described later) formed on the side surfaces of the conductors 242a and 242b can be thinned. Further, an insulator 252 is disposed between the insulator 250 and the metal oxide 230 b. Therefore, for example, when the heat treatment is performed, oxygen release from the region 230bc of the metal oxide 230b can be suppressed.

Note that the thickness of the insulator 252 is preferably thin. For example, insulator 252 preferably includes a region having a thickness less than the thickness of insulator 250. Insulator 250 includes a region that contacts the top surface of metal oxide 230 b. By reducing the thickness of the insulator 252, it is possible to supply oxygen contained in the insulator 250 to the region 230bc of the metal oxide 230b and suppress the supply excess of oxygen contained in the insulator 250. Further, the insulator 252 is disposed between the insulator 280 and the insulator 250, and includes a region that contacts a sidewall of an opening included in the insulator 280. By thinning the thickness of the insulator 252, oxygen contained in the insulator 280 can be supplied to the insulator 250 and supply excess of oxygen contained in the insulator 280 can be suppressed.

The insulator 254 preferably has oxygen barrier properties. The insulator 254 is disposed between the insulator 250 and the electrical conductor 260. Accordingly, oxygen contained in the insulator 250 can be prevented from diffusing to the conductor 260 and the conductor 260 can be suppressed from being oxidized. Note that the insulator 254 is at least less permeable to oxygen than the insulator 250.

As the insulator 275, an insulator having a function of suppressing oxygen permeation is preferably used. Insulator 275 is disposed between insulator 280 and conductors 242a and 242b. By adopting this structure, diffusion of oxygen contained in the insulator 280 to the conductors 242a and 242b can be suppressed. Accordingly, the on-state current can be reduced by suppressing oxidation of the conductors 242a and 242b due to oxygen contained in the insulator 280, which increases the resistivity. Note that, at least, the insulator 275 is less permeable to oxygen than the insulator 250.

By adopting the above structure, the region 230bc serving as a channel formation region can be i-type or substantially i-type and the region 230ba and the region 230bb serving as a source region or a drain region can be n-type, and a semiconductor device having excellent electrical characteristics can be provided. Further, by adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it is possible to have good electrical characteristics. For example, good electrical characteristics can be obtained even if the gate length is 20nm or less, 15nm or less, 10nm or less, or 7nm or less, and 2nm or more, 3nm or more, or 5nm or more. Note that the gate length is described later.

Further, the high frequency characteristics can be improved by miniaturizing the transistor 200. Specifically, the cutoff frequency can be increased. When the gate length is within the above range, for example, in a room temperature environment, the cut-off frequency of the transistor may be 50GHz or more or 100GHz or more.

Note that, as the conductor 242a, the conductor 242b, the conductor 260, a conductive material which is not easily oxidized, a conductive material having a function of suppressing oxygen diffusion, or the like is preferably used. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material including metal and nitrogen is used for the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 include at least metal and nitrogen.

Any one or more of the conductors 242a, 242b, and 260 may have a stacked structure. For example, when the conductors 242a and 242b have a stacked-layer structure, a conductive material which is not easily oxidized, a conductive material having a function of suppressing oxygen diffusion, or the like is preferably used as a layer in contact with the metal oxide 230 b. For example, as shown in fig. 7B, when the conductor 260 has a stacked structure of the conductor 260a and the conductor 260B, a conductive material which is not easily oxidized, a conductive material having a function of suppressing oxygen diffusion, or the like can be used as the conductor 260 a.

As the metal oxide 230b, a metal oxide having crystallinity such as CAAC-OS is preferably used. As the metal oxide, the metal oxide that can be used for the metal oxide 230 is preferably used. Particularly preferred is the use of a metal oxide comprising indium, zinc and one or more selected from gallium, aluminum and tin. In addition, CAAC-OS is a metal oxide having a crystal with a c-axis that is substantially perpendicular to the surface or formed face of the metal oxide. This can suppress the extraction of oxygen from the metal oxide 230b by the conductor 242a or the conductor 242 b. Further, the decrease in conductivity of the conductors 242a and 242b can be suppressed.

The insulator 282 provided on the insulator 280 is preferably formed by a method capable of adding oxygen to the insulator 280. Thereby, the insulator 280 may be made to contain excess oxygen.

In this embodiment mode, the semiconductor device has a structure for suppressing the mixing of hydrogen into the transistor 200 in addition to the above-described structure. For example, an insulator having a function of suppressing diffusion of hydrogen is provided so as to cover the transistor 200. In the semiconductor device described in this embodiment mode, the insulator is, for example, the insulator 212 or the insulator 283.

As the insulator 212, an insulator having a function of suppressing diffusion of hydrogen is preferably used. This can suppress diffusion of hydrogen from below the insulator 212 to the transistor 200.

As the insulator 283, an insulator having a function of suppressing diffusion of hydrogen is preferably used. This can suppress diffusion of hydrogen from above the insulator 283 to the transistor 200. Further, the hydrogen diffusion transistor 200 included in the insulator 274 can be suppressed.

Fig. 9 shows an enlarged view of the vicinity of the channel formation region in fig. 7B. The solid arrows shown in fig. 9 are visible as they diffuse oxygen. Further, the arrows of the broken lines shown in fig. 9 are visible as if hydrogen diffuses. With the above structure, oxygen can be efficiently supplied to the region 230bc, and oxidation of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed. Further, the mixing of hydrogen into the transistor 200 can be suppressed.

In this embodiment, the metal oxide 230b is subjected to a microwave treatment in an oxygen-containing atmosphere in a state where the conductor 242a and the conductor 242b are provided thereon, so that oxygen vacancies and V _O H in the region 230bc are reduced. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma by microwaves.

By performing the microwave treatment in an atmosphere containing oxygen, the oxygen gas can be plasmatized using high Frequency such as microwave or RF (Radio Frequency) to cause the oxygen plasma to act. At this time, a high frequency such as microwave or RF may be irradiated to the region 230bc. V _O H in region 230bc can be separated into oxygen vacancies and hydrogen by the action of plasma, microwaves, or the like, and the hydrogen can be removed from region 230bc to fill the oxygen vacancies with oxygen. This reduces the hydrogen concentration, oxygen vacancies, and V _O H in the region 230bc, thereby reducing the carrier concentration.

When the microwave treatment is performed in an oxygen-containing atmosphere, the action of high frequency such as microwaves and RF, oxygen plasma, and the like is shielded by the conductors 242a and 242b, and does not relate to the regions 230ba and 230bb. Further, the effect of oxygen plasma can be reduced by the insulator 271 and the insulator 280 covering the metal oxide 230b and the conductor 242. Thus, the decrease in V _O H and the excessive supply of oxygen do not occur in the region 230ba and the region 230bb during the microwave treatment, and therefore, the decrease in carrier concentration can be prevented.

In addition, it is preferable to perform microwave treatment with an oxygen-containing atmosphere after depositing the insulating film to be the insulator 252 or after depositing the insulating film to be the insulator 250. In this manner, by performing microwave treatment in an oxygen-containing atmosphere through the insulator 252 or the insulator 250, oxygen can be efficiently injected into the region 230 bc. Further, by disposing the insulator 252 so as to be in contact with the side surface of the conductor 242 and the surface of the region 230bc, the region 230bc can be prevented from being injected with unnecessary oxygen, and therefore oxidation of the side surface of the conductor 242 can be prevented. In addition, the side surface of the conductor 242 can be suppressed from being oxidized when the insulating film serving as the insulator 250 is deposited.

As oxygen injected into the region 230bc, there are various types of oxygen atoms, oxygen molecules, oxygen radicals (also referred to as O radicals, including atoms, molecules, or ions of unpaired electrons), and the like. Oxygen injected into region 230bc may be any one or more of the ways described above, with oxygen radicals being particularly preferred. In addition, since the film quality of the insulator 252 and the insulator 250 can be improved, the reliability of the transistor 200 can be improved.

As described above, oxygen vacancies and V _O H can be selectively removed in the region 230bc of the metal oxide semiconductor to make the region 230bc i-type or substantially i-type. Further, the region 230ba and the region 230bb serving as the source region or the drain region can be kept from being supplied with excessive oxygen, and the n-type region before the microwave treatment can be kept. This suppresses variation in the electrical characteristics of the transistor 200, and suppresses variation in the electrical characteristics of the transistor 200 in the substrate plane.

By adopting the above structure, a semiconductor device with small non-uniformity of transistor characteristics can be provided. Further, a semiconductor device with good reliability can be provided. Further, a semiconductor device having good electrical characteristics can be provided. In addition, a semiconductor device which can be miniaturized or highly integrated can be provided.

As shown in fig. 7C, a curved surface may be provided between the side surface of the metal oxide 230b and the top surface of the metal oxide 230b when viewed in cross section of the channel width of the transistor 200. That is, the end portions of the side surfaces and the end portions of the top surface may also be curved (hereinafter, also referred to as rounded).

The radius of curvature of the curved surface is preferably greater than 0nm and less than the thickness of the metal oxide 230b in the region overlapping the conductor 242 or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0nm and 20nm or less, preferably 1nm or more and 15nm or less, and more preferably 2nm or more and 10nm or less. By adopting the above-described shape, the coverage of the metal oxide 230b of the insulator 252, the insulator 250, the insulator 254, and the conductor 260 can be improved.

Further, for example, as shown in fig. 7C, since the insulator 252 made of aluminum oxide or the like is provided so as to be in contact with the top surface and the side surface of the metal oxide 230, indium contained in the metal oxide 230 may be distributed at and near the interface between the metal oxide 230 and the insulator 252. Therefore, the vicinity of the surface of the metal oxide 230 has an atomic ratio close to that of indium metal oxide or an atomic ratio close to that of in—zn metal oxide. When the atomic number of indium in the vicinity of the surface of the metal oxide 230, particularly the metal oxide 230b is relatively large in this manner, the field-effect mobility of the transistor 200 can be improved.

At least one of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 is preferably used as a blocking insulating film which suppresses diffusion of impurities such as water, hydrogen, or the like from the substrate side or over the transistor 200 to the transistor 200. Therefore, at least one of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 preferably uses an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂O、NO、NO₂ or the like), copper atoms or the like (the impurities are not easily permeated). Further, an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) is preferably used (the oxygen is not easily transmitted).

In this specification, the barrier insulating film means an insulating film having barrier properties. In the present specification, the barrier property means a function of suppressing diffusion of a corresponding substance (also referred to as low permeability). Or refers to the function of capturing and immobilizing the corresponding substance (also referred to as gettering).

As the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285, an insulator having a function of suppressing diffusion of impurities such as water and hydrogen, oxygen, and the like is preferably used, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc metal oxide, silicon nitride, silicon oxynitride, or the like can be used. For example, silicon nitride or the like having higher hydrogen barrier property is preferably used as the insulator 212, the insulator 275, and the insulator 283. For example, as the insulator 214, the insulator 271, the insulator 282, and the insulator 285, alumina, magnesia, or the like having high hydrogen capturing and fixing performance is preferably used. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Or diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 285 to the transistor 200 side can be suppressed. Or diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214 may be suppressed. Or oxygen contained in the insulator 280 or the like can be suppressed from diffusing upward of the transistor 200 through the insulator 282 or the like. As described above, the transistor 200 is preferably surrounded by the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285, which have a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.

Here, as the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285, a metal oxide having an amorphous structure is preferably used. For example, a metal oxide such as AlO _x (x is an arbitrary number greater than 0) or MgO _y (y is an arbitrary number greater than 0) is preferably used. The above metal oxide having an amorphous structure sometimes has a property that an oxygen atom has a dangling bond and hydrogen is trapped or immobilized by the dangling bond. By using the metal oxide having the amorphous structure described above as a constituent element of the transistor 200 or disposing the metal oxide around the transistor 200, hydrogen contained in the transistor 200 or hydrogen existing around the transistor 200 can be trapped or fixed. In particular, hydrogen contained in a channel formation region in the transistor 200 is preferably trapped or fixed. By using a metal oxide having an amorphous structure as a constituent element of the transistor 200 or by providing the metal oxide around the transistor 200, the transistor 200 and the semiconductor device having favorable characteristics and high reliability can be manufactured.

The insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 preferably have an amorphous structure, but a region having a polycrystalline structure may be formed in a part thereof. The insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a layer having a polycrystalline structure is formed over a layer having an amorphous structure may be used.

The insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 may be deposited by sputtering, for example. The sputtering method does not require the use of molecules containing hydrogen as a deposition gas, and therefore, the hydrogen concentration of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 can be reduced. As the deposition method, a Chemical Vapor Deposition (CVD) method, a molecular beam epitaxy (MBE: molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: pulsed Laser Deposition) method, an atomic layer deposition (ALD: atomic Layer Deposition) method, or the like can be suitably used in addition to the sputtering method.

In addition, it is sometimes preferable to reduce the resistivity of the insulator 212, the insulator 275, and the insulator 283. For example, by making the resistivity of the insulator 212, the insulator 275, and the insulator 283 approximately 1×10 ¹³ Ω cm, charge accumulation of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 may be alleviated by the insulator 212, the insulator 275, and the insulator 283 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 275, and the insulator 283 is preferably 1×10 ¹⁰ Ω cm or more and 1×10 ¹⁵ Ω cm or less.

Further, dielectric constants of the insulator 216, the insulator 274, the insulator 280, and the insulator 285 are preferably lower than those of the insulator 214. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 216, the insulator 274, the insulator 280, and the insulator 285, silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, or the like may be appropriately used.

In this specification, "silicon oxynitride" refers to a material having a greater oxygen content than nitrogen content in its composition, and "silicon oxynitride" refers to a material having a greater nitrogen content than oxygen content in its composition. In the present specification, aluminum oxynitride refers to a material having an oxygen content greater than a nitrogen content, and "aluminum oxynitride" refers to a material having a nitrogen content greater than an oxygen content.

The conductor 205 is disposed so as to overlap with the metal oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be fitted into an opening formed in the insulator 216. In addition, a portion of the conductor 205 is sometimes embedded in the insulator 214.

The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided so as to contact the bottom surface and the side wall of the opening. The conductor 205b is provided so as to be fitted into a recess formed in the conductor 205 a. Here, the height of the top surface of the conductor 205b is substantially equal to the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216.

Here, as the conductor 205a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂O、NO、NO₂ or the like), copper atoms, or the like is preferably used. Or a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule or the like) is preferably used.

By using a conductive material having a function of reducing diffusion of hydrogen as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the metal oxide 230 through the insulator 216, the insulator 224, and the like. Further, by using a conductive material having a function of suppressing diffusion of oxygen as the conductive body 205a, the conductive body 205b can be suppressed from being oxidized and the conductivity can be reduced. As the conductive material having a function of suppressing oxygen diffusion, for example, titanium nitride, tantalum nitride, ruthenium oxide, or the like can be used. Therefore, the conductive material may be used as the conductive body 205a in a single layer or a stacked layer. For example, titanium nitride may be used as the conductor 205 a.

Further, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, tungsten may be used for the conductor 205 b.

The conductor 205 is sometimes used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, vth of the transistor 200 can be increased and off-state current can be reduced. Thus, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced as compared with the case where a negative potential is not applied to the conductor 205.

Further, the resistivity of the conductor 205 is designed in consideration of the above-described potential applied to the conductor 205, and the thickness of the conductor 205 is set in accordance with the resistivity. The thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, the thickness of the conductor 205 and the insulator 216 is preferably reduced within a range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that diffusion of the impurities to the metal oxide 230 can be reduced.

As shown in fig. 7A, the conductor 205 is preferably larger than a region of the metal oxide 230 that does not overlap with the conductor 242a and the conductor 242 b. In particular, as shown in fig. 7C, the conductor 205 preferably extends to a region outside the ends of the metal oxide 230a and the metal oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other with an insulator therebetween on the outer side of the side surface in the channel width direction of the metal oxide 230. By having the above-described structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 serving as the first gate electrode and the electric field of the conductor 205 serving as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by an electric field of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

In this specification and the like, a transistor of an S-channel structure refers to a structure in which a channel formation region is electrically surrounded by an electric field of one of a pair of gate electrodes and the other. The S-channel structure disclosed in the present specification and the like has a structure different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in the present specification and the like can also be regarded as one of Fin-type structures. In this specification and the like, the Fin-type structure refers to a structure in which the gate electrode is arranged so as to surround at least two or more surfaces (specifically, two surfaces, three surfaces, four surfaces, or the like) of the channel. By using the Fin type structure and the S-channel structure, a transistor having improved resistance to short channel effects, in other words, a transistor having less tendency to generate short channel effects can be realized.

The Channel formation region may be electrically surrounded by transistor 200 being normally off and having the S-Channel structure described above. Thus, the transistor 200 can also be said to have a GAA (GateAllAround: fully-surrounding gate) structure or a LGAA (Lateral GateAllAround: laterally fully-surrounding gate) structure. By providing the transistor 200 with an S-Channel structure, a GAA structure, or a LGAA structure, a Channel formation region formed at or near the interface of the metal oxide 230 and the gate insulator can be provided over the entire bulk of the metal oxide 230. Therefore, the current density flowing through the transistor can be increased, and thus an on-state current of the transistor or an improvement in field-effect mobility of the transistor can be expected.

Note that a transistor having an S-channel structure is shown as the transistor 200 in fig. 7A to 7D, but the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, as a transistor structure which can be used in one embodiment of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure may be used.

Further, as shown in fig. 7C, the conductor 205 is extended to serve as a wiring. However, the present invention is not limited to this, and an electric conductor used as a wiring may be provided under the electric conductor 205. Furthermore, one conductor 205 need not be provided in each transistor. For example, the conductor 205 may be commonly used in a plurality of transistors.

Note that although the structure in which the conductor 205a and the conductor 205b are stacked as the conductor 205 in the transistor 200 is shown, the present invention is not limited to this. For example, the conductor 205 may have a single-layer structure or a stacked structure of three or more layers.

Insulator 222 and insulator 224 are used as gate insulators.

The insulator 222 preferably has a function of suppressing diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules, etc.). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule, or the like). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen, as compared with the insulator 224.

As the insulator 222, an insulator containing a metal oxide of one or both of aluminum and hafnium is preferably used as an insulating material. As the insulator, aluminum oxide, hafnium oxide, a metal oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Or preferably metal oxides comprising hafnium and zirconium, for example hafnium zirconium metal oxides. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer for suppressing release of oxygen from the metal oxide 230 to the substrate side and diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the metal oxide 230. Therefore, by providing the insulator 222, diffusion of impurities such as hydrogen into the transistor 200 can be suppressed, and generation of oxygen vacancies in the metal oxide 230 can be suppressed. Further, the reaction of the conductor 205 with oxygen contained in the insulator 224 and the metal oxide 230 can be suppressed.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be subjected to nitriding treatment. Further, as the insulator 222, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

As the insulator 222, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium metal oxide, or the like may be used in a single layer or a stacked layer. When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator to be used as a gate insulator, the gate potential of the transistor when operating can be reduced while maintaining physical thickness. As the insulator 222, a substance having a high dielectric constant such as lead zirconate titanate (PZT) or strontium titanate (SrTiO ₃)、(Ba,Sr)TiO₃ (BST) may be used.

As the insulator 224 in contact with the metal oxide 230, for example, silicon oxide, silicon oxynitride, or the like may be appropriately used.

In the manufacturing process of the transistor 200, the heat treatment is preferably performed in a state where the surface of the metal oxide 230 is exposed. The heat treatment is preferably performed at 100 ℃ or more and 600 ℃ or less, more preferably 350 ℃ or more and 550 ℃ or less, for example. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed under an oxygen atmosphere. Thereby, oxygen is supplied to the metal oxide 230, so that oxygen vacancies can be reduced. The heat treatment may be performed under reduced pressure. The heat treatment may be performed under an atmosphere of nitrogen gas or inert gas, and then under an atmosphere containing 10ppm or more, 1% or more, or 10% or more of oxidizing gas in order to fill out the detached oxygen. The heat treatment may be performed in an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed continuously in an atmosphere of nitrogen gas or an inert gas.

By supplying oxygen to the metal oxide 230, oxygen vacancies in the metal oxide 230 can be filled. Further, the hydrogen remaining in the metal oxide 230 reacts with the supplied oxygen, and the hydrogen can be removed (dehydrated) as H ₂ O. This can suppress recombination of hydrogen and oxygen vacancies remaining in the metal oxide 230 to form V _O H.

The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the stacked structure is not limited to the stacked structure using the same material, and may be a stacked structure using a different material. The insulator 224 may be formed in an island shape and overlap with the metal oxide 230 a. In this case, the insulator 275 is in contact with the side surface of the insulator 224 and the top surface of the insulator 222. Note that in this specification and the like, an island shape refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

The conductors 242a and 242b are in contact with the top surface of the metal oxide 230 b. The conductors 242a and 242b are used as a source electrode or a drain electrode of the transistor 200, respectively.

As the conductor 242 (the conductor 242a and the conductor 242 b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferably used. Further, for example, ruthenium oxide, ruthenium nitride, a metal oxide containing strontium and ruthenium, a metal oxide containing lanthanum and nickel, or the like can also be used. These materials are preferably conductive materials that do not oxidize easily or materials that maintain conductivity even when oxygen is absorbed.

Note that hydrogen contained in the metal oxide 230b or the like sometimes diffuses into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used as the conductor 242a and the conductor 242b, hydrogen contained in the metal oxide 230b or the like may be easily diffused into the conductor 242a or the conductor 242b, and the diffused hydrogen is bonded to nitrogen contained in the conductor 242a or the conductor 242b. That is, hydrogen contained in the metal oxide 230b or the like is sometimes absorbed by the conductor 242a or the conductor 242b.

Further, it is preferable that a curved surface is not formed between the side surface of the conductor 242 and the top surface of the conductor 242. By making the conductor 242 not have such a curved surface, as shown in fig. 7D, the cross-sectional area of the conductor 242 in the cross-section in the channel width direction can be increased. This increases the conductivity of the conductor 242, and thus the on-state current of the transistor 200 can be increased.

When the heat treatment is performed in a state where the conductor 242a (conductor 242 b) is in contact with the metal oxide 230b, the sheet resistance of the metal oxide 230b in the region overlapping with the conductor 242a (conductor 242 b) may be reduced. In addition, the carrier concentration may increase. Therefore, the metal oxide 230b in the region overlapping with the conductor 242a (conductor 242 b) can be self-aligned to have low resistance.

Insulator 271a is in contact with the top surface of conductor 242a and insulator 271b is in contact with the top surface of conductor 242 b. The insulator 271 is preferably used as an insulating film having at least barrier property against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of further suppressing oxygen diffusion as compared with the insulator 280. As the insulator 271, an insulator such as silicon nitride, aluminum oxide, or magnesium oxide can be used.

Insulator 275 is provided so as to cover insulator 224, metal oxide 230a, metal oxide 230b, conductor 242, and insulator 271. Specifically, insulator 275 includes regions that contact the sides of metal oxide 230b, the sides of conductor 242a, and the sides of conductor 242 b. The insulator 275 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes silicon nitride or a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide. For example, a stacked film of aluminum oxide and silicon nitride over the aluminum oxide may be used as the insulator 275.

By providing the insulator 271 and the insulator 275, the insulator having a barrier property against oxygen can surround the conductor 242. In other words, oxygen contained in the insulator 224 and the insulator 280 can be suppressed from diffusing into the conductor 242. This can suppress the on-state current from decreasing due to the increase in resistivity caused by the direct oxidation of the conductor 242 by oxygen contained in the insulator 224 and the insulator 280.

The insulator 252 is used as part of a gate insulator. An oxygen barrier insulating film is preferably used as the insulator 252. As the insulator 252, an insulator usable for the insulator 282 may be used. As the insulator 252, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, alumina is used as the insulator 252. At this time, the insulator 252 contains at least oxygen and aluminum.

As shown in fig. 7C, the insulator 252 is provided in contact with the top surface and the side surface of the metal oxide 230b, the side surface of the metal oxide 230a, the side surface of the insulator 224, and the top surface of the insulator 222. That is, in the cross section in the channel width direction, the region of the metal oxide 230a, the metal oxide 230b, and the insulator 224 that overlaps the conductor 260 is covered with the insulator 252. Accordingly, oxygen in the metal oxide 230a and the metal oxide 230b can be prevented from being removed by the insulator 252 having oxygen blocking property, for example, when heat treatment is performed. Therefore, oxygen vacancies formed in the metal oxide 230a and the metal oxide 230b can be reduced. Thereby, oxygen vacancies and V _O H formed in the region 230bc can be reduced. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

In addition, conversely, even if the insulator 280, the insulator 250, and the like contain excessive oxygen, the oxygen can be prevented from being excessively supplied to the metal oxide 230a and the metal oxide 230b. Therefore, the region 230ba and the region 230bb are excessively oxidized by the region 230bc, and thus, the on-state current of the transistor 200 is prevented from being reduced or the field-effect mobility is prevented from being reduced.

As shown in fig. 7B, the insulator 252 is provided so as to contact the side surfaces of the conductors 242, 271, 275, and 280. Therefore, the side surface of the conductor 242 can be reduced from being oxidized and an oxide film can be formed on the side surface. Therefore, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

In addition, the insulator 252 needs to be provided in an opening formed in the insulator 280 or the like together with the insulator 254, the insulator 250, and the conductor 260. To achieve miniaturization of the transistor 200, the thickness of the insulator 252 is preferably small. The thickness of the insulator 252 is 0.1nm or more and 5.0nm or less, preferably 0.5nm or more and 3.0nm or less, and more preferably 1.0nm or more and less than 3.0nm. At this time, at least a part of the insulator 252 may be a region having the above thickness. In addition, the thickness of insulator 252 is preferably smaller than the thickness of insulator 250. At this time, at least a part of the insulator 252 may be a region having a smaller thickness than the insulator 250.

To deposit the insulator 252 thin as described above, the insulator 252 is preferably deposited using an ALD method. Examples of the ALD method include a thermal ALD (ThermalALD) method in which a precursor and a reactant are reacted only by thermal energy, and a PEALD (Plasma EnhancedALD) method in which a reactant excited by plasma is used. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so that it is sometimes preferable.

ALD processes can deposit atoms in layers, producing the following effects: being capable of depositing extremely thin films; enabling deposition of high aspect ratio structures; the deposition can be performed with few defects such as pinholes; can perform deposition with excellent coverage; capable of deposition at low temperatures; etc. Accordingly, the insulator 252 can be deposited with the above-described small thickness and high coverage on the side of the opening formed in the insulator 280, for example.

The precursor used in the ALD method contains carbon, for example. Therefore, the film formed by the ALD method may contain more impurities such as carbon than the film formed by other deposition methods. Further, the quantification of impurities can be measured by secondary ion mass spectrometry (SIMS: secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or Auger electron spectroscopy (AES: augerElectronSpectroscopy).

Further, by appropriately adjusting the deposition conditions of the insulating film to be the insulator 250, the conditions of the microwave treatment in the oxygen-containing atmosphere, the oxygen added to the insulator 280 due to the deposition of the insulator 282, and the like, oxygen vacancies and V _O H formed in the region 230bc can be reduced in some cases, and excessive oxidation of the regions 230ba and 230bb can be suppressed. In this case, by adopting a structure in which the insulator 252 is not provided, the manufacturing process of the semiconductor device can be simplified, and improvement in productivity can be achieved.

The insulator 250 is used as part of a gate insulator. Insulator 250 is preferably configured to contact the top surface of insulator 252. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having voids, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. At this time, the insulator 250 is an insulator containing at least oxygen and silicon.

Like the insulator 224, the concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1nm to 20nm, more preferably 0.5nm to 15 nm. In particular, in order to manufacture a micro transistor (for example, a transistor having a gate length of 10nm or less), the thickness of the insulator 250 is preferably 0.5nm or more and 10nm or less, more preferably 0.5nm or more and 5nm or less. In the above case, at least a part of the insulator 250 may be a region having the above thickness.

In fig. 7A to 7D and 8A, the insulator 250 is shown as having a single-layer structure, but the present invention is not limited thereto, and a stacked structure of two or more layers may be employed. For example, as shown in fig. 8B, the insulator 250 may have a laminated structure of two layers, that is, an insulator 250a and an insulator 250B on the insulator 250 a.

Note that the insulator 252, the insulator 250, and the insulator 254 are used as a gate insulating film (also referred to as a top gate insulating film or TGI) in a transistor. The thickness of the gate insulating film is preferably 1.3nm to 10nm, more preferably 1.5nm to 5 nm. Note that the thickness of the gate insulating film in the above transistor is equivalent oxide thickness (EOT: equivalent Oxide Thickness). The equivalent oxide thickness is a value obtained by converting the physical thickness into an electrical thickness equal to that of silicon oxide.

For example, in the case where aluminum oxide, silicon oxide, and silicon nitride are used as the insulator 252, the insulator 250, and the insulator 254, respectively, the total thickness of the insulator 252, the insulator 250, and the insulator 254 may be converted into equivalent oxide thickness.

By setting the thickness of the gate insulating film to be within the above range, the subthreshold swing value (S value) which is one of the characteristics of the transistor can be reduced. For example, by setting the channel length L of the OSFET to be in the range of 3nm to 10nm, and the thickness of the gate insulating film of the OSFET to be in the range of 1.5nm to 5nm, the S value of the OSFET may be 60 mV/dec.or more and 200 mV/dec.or less, preferably 60 mV/dec.or more and 100 mV/dec.or less, more preferably 60 mV/dec.or more and 80 mV/dec.or less. In addition, by setting the thickness of the gate insulating film in the OSFET to be within the above range, the frequency characteristics (f characteristics) of the transistor may be improved. In the OSFET, the drain voltage (Vd) and the gate voltage (Vg) of the transistor can be operated in a range of 0.5V or more and 3V or less.

As shown in fig. 8B, in the case where the insulator 250 has a two-layered structure, it is preferable that the insulator 250a of the lower layer is formed using an insulator that easily transmits oxygen, and the insulator 250B of the upper layer is formed using an insulator that has a function of suppressing diffusion of oxygen. By adopting such a structure, diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, a decrease in the amount of oxygen supplied to the metal oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a may be made of the material that can be used for the insulator 250, and the insulator 250b may be made of an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, hafnium oxide is used as the insulator 250 b. At this time, the insulator 250b is an insulator containing at least oxygen and hafnium. The thickness of the insulator 250b is 0.5nm or more and 5.0nm or less, preferably 1.0nm or more and 5.0nm or less, and more preferably 1.0nm or more and 3.0nm or less. At this time, at least a part of the insulator 250b may be a region having the above thickness.

Note that when silicon oxide, silicon oxynitride, or the like is used for the insulator 250a, the insulator 250b may be formed using an insulating material of a high-k material having a high relative dielectric constant. By using a stacked structure of the insulator 250a and the insulator 250b as a gate insulator, a stacked structure having high thermal stability and a high relative dielectric constant can be formed. Accordingly, the gate potential applied when the transistor operates can be reduced while maintaining the physical thickness of the gate insulator. In addition, the Equivalent Oxide Thickness (EOT) of the insulator used as the gate insulator can be reduced. Therefore, the dielectric breakdown voltage of the insulator 250 can be improved.

The insulator 254 is used as part of the gate insulator. A hydrogen blocking insulating film is preferably used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the metal oxide 230b. The insulator 254 may be the insulator 283. For example, silicon nitride deposited by PEALD method may be used as the insulator 254. At this time, the insulator 254 is an insulator containing at least nitrogen and silicon.

The insulator 254 may also have oxygen barrier properties. Thereby, diffusion of oxygen contained in the insulator 250 to the conductor 260 can be suppressed.

In addition, the insulator 254 needs to be provided in an opening formed in the insulator 280 or the like together with the insulator 252, the insulator 250, the conductor 260. To achieve miniaturization of the transistor 200, the thickness of the insulator 254 is preferably small. The thickness of the insulator 254 is 0.1nm or more and 5.0nm or less, preferably 0.5nm or more and 3.0nm or less, and more preferably 1.0nm or more and 3.0nm or less. At this time, at least a part of the insulator 254 may be a region having the above thickness. In addition, the thickness of the insulator 254 is preferably smaller than the thickness of the insulator 250. At this time, at least a part of the insulator 254 may be a region having a smaller thickness than the insulator 250.

Further, as shown in fig. 8B, when the insulator 250 has a two-layer stacked structure, the insulator 250B can also have the function of the insulator 254 by using an insulator such as hafnium oxide having a function of suppressing permeation of impurities such as hydrogen and oxygen as the insulator 250B. In this case, by adopting a structure in which the insulator 254 is not provided, the manufacturing process of the semiconductor device can be simplified, and improvement in productivity can be achieved.

The conductor 260 is used as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surfaces of the conductor 260b. Further, as shown in fig. 7B and 7C, the top surface of the conductor 260 is substantially aligned with the top surface of the insulator 250. Although the conductor 260 has a two-layer structure of the conductor 260a and the conductor 260B in fig. 7B and 7C, a single-layer structure or a stacked structure of three or more layers may be used.

As the conductor 260a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms is preferably used. Further, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule or the like) is preferably used.

Further, when the conductor 260a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 250 can be suppressed from oxidizing the conductor 260b, resulting in a decrease in conductivity. As the conductive material having a function of suppressing oxygen diffusion, for example, titanium nitride, tantalum nitride, ruthenium oxide, or the like can be used.

Further, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used for the conductor 260 b. The conductor 260b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-described conductive material.

In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill, for example, an opening formed in the insulator 280. By forming the conductor 260 in this manner, the conductor 260 can be surely arranged without alignment in the region between the conductor 242a and the conductor 242 b.

As shown in fig. 7C, the height of the bottom surface of the region of the conductor 260 where the conductor 260 does not overlap with the metal oxide 230b is preferably lower than the height of the bottom surface of the metal oxide 230b with respect to the bottom surface of the insulator 222 in the channel width direction of the transistor 200. By adopting a structure in which the conductor 260 used as a gate electrode covers the side surfaces and the top surface of the channel formation region of the metal oxide 230b with the insulator 250 interposed therebetween, for example, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the metal oxide 230 b. This can improve the on-state current and frequency characteristics of the transistor 200. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the metal oxide 230b in the region where the metal oxide 230a and the metal oxide 230b do not overlap with the conductor 260 when the bottom surface of the insulator 222 is used as a reference is 0nm or more and 100nm or less, preferably 3nm or more and 50nm or less, and more preferably 5nm or more and 20nm or less.

Insulator 280 is disposed on insulator 275, and openings are formed in the areas where insulator 250 and conductor 260 are disposed. In addition, the top surface of insulator 280 may also be planarized.

It is preferable that the dielectric constant of the insulator 280 used as the interlayer film is low. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Insulator 280 is preferably formed of the same material as insulator 216, for example. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. Or, a material such as silicon oxide, silicon oxynitride, or silicon oxide having voids is particularly preferable because a region containing oxygen which is desorbed by heating is easily formed.

The concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. For example, an oxide containing silicon such as silicon oxide or silicon oxynitride may be appropriately used as the insulator 280.

The insulator 282 is preferably used as a barrier insulating film for suppressing diffusion of impurities such as water and hydrogen from above to the insulator 280, and has a function of trapping impurities such as hydrogen. Further, the insulator 282 is preferably used as a blocking insulating film that suppresses oxygen permeation. As the insulator 282, a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide may be used. At this time, the insulator 282 is an insulator containing at least oxygen and aluminum. By providing the insulator 282 having a function of capturing impurities such as hydrogen in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283, impurities such as hydrogen contained in the insulator 280 can be captured, for example, and the amount of hydrogen in the region can be kept constant. In particular, the insulator 282 preferably uses alumina having an amorphous structure, because hydrogen can be trapped or fixed more effectively in some cases. Thus, the transistor 200 and the semiconductor device having good characteristics and high reliability can be manufactured.

As the insulator 282, aluminum oxide is preferably deposited by a sputtering method, and more preferably aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform to improve the sputtering rate and film quality. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the lower layer of insulator 282 may be controlled according to the amount of RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the underlying layer of insulator 282, which is susceptible to saturation even if insulator 282 is thinner. In addition, the greater the RF power, the greater the amount of oxygen injected into the underlying layers of insulator 282.

The RF power is set to, for example, 0W/cm ² or more and 1.86W/cm ² or less. In other words, the oxygen amount may be changed to an amount suitable for the characteristics of the transistor according to the RF power at the time of forming the insulator 282 and injected. Accordingly, oxygen in an amount suitable for improving the reliability of the transistor can be injected.

The frequency of RF is preferably 10MHz or more. Typically 13.56MHz. The higher the frequency of RF, the less damage can be done to the substrate.

Insulator 283 is in contact with a portion of the top surface of insulator 214, the side surface of insulator 216, the side surface of insulator 222, the side surface of insulator 275, the side surface of insulator 280, and the side and top surfaces of insulator 282.

The insulator 283 serves as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above to the insulator 280. Insulator 283 is disposed on insulator 282. As the insulator 283, a nitride containing silicon such as silicon nitride or silicon oxynitride is preferably used. For example, silicon nitride deposited by a sputtering method may be used as the insulator 283. By depositing the insulator 283 using a sputtering method, a silicon nitride film with high density can be formed. Further, as the insulator 283, silicon nitride deposited by a PEALD method or a CVD method may be further stacked on silicon nitride deposited by a sputtering method.

The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

When a stacked structure is used as the conductor 240, a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used as the first conductor disposed in the vicinity of the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271. For example, tantalum nitride, titanium nitride, ruthenium oxide, or the like is preferably used. The conductive material having a function of suppressing permeation of impurities such as water and hydrogen can be used in a single layer or a stacked layer. Further, impurities such as water and hydrogen contained in a layer above the insulator 283 can be prevented from being mixed into the metal oxide 230 through the conductors 240a and 240 b.

As the insulator 241a and the insulator 241b, a block insulating film which can be used for the insulator 275 or the like may be used. As the insulator 241a and the insulator 241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 283, the insulator 282, and the insulator 271, impurities such as water and hydrogen contained in the insulator 280 or the like can be prevented from being mixed into the metal oxide 230 through the conductors 240a and 240 b. In particular, silicon nitride is preferable because it has high hydrogen barrier properties. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240 b.

When the insulator 241a and the insulator 241B have a stacked structure as shown in fig. 7B, it is preferable to use an oxygen-blocking insulating film and a hydrogen-blocking insulating film in combination as a first insulator that contacts the inner wall of the opening of the insulator 280 or the like and a second insulator inside thereof.

For example, aluminum oxide deposited by an ALD method may be used as the first insulator, and silicon nitride deposited by a PEALD method may be used as the second insulator. By adopting such a structure, oxidation of the conductor 240 can be suppressed, and entry of hydrogen into the conductor 240 can be suppressed.

The conductors 246 (the conductors 246a and 246 b) used as wirings may be arranged so as to be in contact with the top surface of the conductor 240a and the top surface of the conductor 240 b. The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be fitted into an opening formed in the insulator.

Fig. 10A and 10B are cross-sectional views showing examples of the structure of the transistor 200 and the periphery thereof, and are modified examples of the structure shown in fig. 7B and 7C. Fig. 10A shows a structural example of the transistor 200 in the channel length direction, and fig. 10B shows a structural example of the transistor 200 in the channel width direction. The structure shown in fig. 10A and 10B is different from the structure shown in fig. 7B and 7C in that: the conductor 205 serving as the second gate electrode of the transistor 200 is not provided.

In the transistor 200 shown in fig. 10A and 10B, since the conductor 205 is not provided, the insulator 222 and the insulator 224 are not used as gate insulators. Here, since the metal oxide 230 forming the channel formation region of the transistor 200 is provided on the insulator 224, the transistor 200 is provided on the insulator 224. Thus, the insulator 224 can be said to be a base insulator.

The insulator 224 may be separated for each transistor. Accordingly, the semiconductor device including the plurality of transistors 200 is provided with the plurality of insulators 224. The plurality of insulators 224 are sometimes collectively referred to as a base insulator group.

As shown in fig. 10B, the conductor 260 serving as the gate electrode of the transistor 200 covers the top surfaces of the metal oxide 230 and the insulator 224 and the side surfaces in the channel width direction with the insulator 252, the insulator 250, and the insulator 254 serving as the gate insulator of the transistor 200 interposed therebetween. For example, the conductor 260 covers the top surfaces of the metal oxide 230 and the insulator 224, the entire side surface of the metal oxide 230 in the channel width direction of the transistor 200, and at least a part of the side surface of the insulator 224 in the channel width direction of the transistor 200 via the insulator 252, the insulator 250, and the insulator 254. That is, the transistor 200 shown in fig. 10B can be said to be a Fin-type transistor.

By using Fin-type transistors as the transistor 200 as the OS transistors, the channel width in effect is increased, and the on-characteristics of the transistor 200 can be improved. Further, since the influence of the electric field of the gate electrode can be increased, the off characteristic of the transistor 200 can be improved.

Fig. 11A and 11B are cross-sectional views showing a transistor 300, which is a Si transistor included in a semiconductor device according to an embodiment of the present invention, and a configuration example of the periphery thereof. Here, fig. 11A is a cross-sectional view of the transistor 300 in the channel length direction, and fig. 11B is a cross-sectional view of the transistor 300 in the channel width direction.

The transistor 300 may be disposed in the layer 11 shown in fig. 2, 3, 5, and 6. For example, as the transistor 41p shown in fig. 3 and the transistors MR3 and MS3 shown in fig. 6, the transistor 300 can be used.

The transistor 300 is provided over a substrate 310, and includes an element separation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 formed by a portion of the substrate 310, a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b. The semiconductor region 313 may be a channel formation region of the transistor 300. Insulator 315 is used as the gate insulator for transistor 300 and conductor 316 is used as the gate electrode for transistor 300.

As the substrate 310, a silicon substrate, for example, a single crystal silicon substrate is used. The substrate 310 may contain Ge (germanium), siGe (silicon germanium), gaAs (gallium arsenide), gaAlAs (gallium aluminum arsenide), gaN (gallium nitride), or the like. Substrate 310 may use silicon that applies stress to the crystal lattice to alter the interplanar spacing to control the effective mass. Alternatively, the transistor 300 may be made to be a HEMT (HighElectronMobility Transistor: high electron mobility transistor) by using GaAs, gaAlAs, or the like as the substrate 310.

As shown in fig. 11B, the semiconductor region 313 formed of a part of the substrate 310 has a convex portion. In the transistor 300, the conductor 316 covers the top surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315. In this manner, by providing the transistor 300 with a Fin-type structure, the channel width in effect increases, and thus the on-state characteristics of the transistor 300 can be improved. In addition, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved.

The low-resistance region 314a and the low-resistance region 314b contain an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron in addition to the semiconductor material used for the semiconductor region 313.

As the conductor 316 used as the gate electrode, a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

Further, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, a material such as titanium nitride or tantalum nitride is preferably used as the conductor. For both conductivity and embeddability, a laminate of metal materials such as tungsten and aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.

An element separation layer 312 is provided to separate a plurality of transistors formed over the substrate 310 from each other. The element separation layer can be formed using, for example, a LOCOS (LOCal OxidationofSilicon: local oxidation of silicon), STI (ShallowTrenchIsolation: shallow trench isolation), mesa isolation, or the like.

The transistor 300 includes an insulator 320, an insulator 322, an insulator 324, and an insulator 326 stacked in this order from the substrate 310 side.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

The insulator 322 can also be used as a planarizing film for planarizing a step generated by the transistor 300 or the like covered with the insulator 320 and the insulator 322. For example, in order to improve the flatness of the top surface of the insulator 322, the top surface thereof may be planarized by a planarization process using a chemical mechanical Polishing (CMP: CHEMICAL MECHANICAL Polishing) method or the like.

As the insulator 324, a film having barrier properties capable of preventing diffusion of hydrogen, impurities, and the like from the substrate 310, the transistor 300, or the like to a region where the transistor 200 which can be an OS transistor is provided is preferably used. As described above, the transistor 300 is provided in the layer 11 shown in fig. 2,3, 5, and 6, and the transistor 200 is provided in the layer 12 on the layer 11.

As an example of the film having hydrogen blocking property, silicon nitride formed by CVD method can be used. Here, hydrogen may diffuse into an OS transistor such as the transistor 200, which may deteriorate the characteristics of the transistor. Therefore, a film that suppresses diffusion of hydrogen is preferably provided between the transistor 200 and the transistor 300. Specifically, the film that suppresses diffusion of hydrogen refers to a film that has a small amount of hydrogen desorption.

The amount of hydrogen desorption may be measured, for example, by Thermal Desorption Spectroscopy (TDS). For example, in the range of 50 ℃ to 500 ℃ of the film surface temperature in the TDS analysis, when the amount of the hydrogen atoms released is converted into the amount per unit area of the insulator 324, the amount of the hydrogen released in the insulator 324 may be 10×10 ¹⁵atoms/cm² or less, preferably 5×10 ¹⁵atoms/cm² or less.

Note that the dielectric constant of insulator 326 is preferably lower than that of insulator 324. For example, the relative dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative dielectric constant of the insulator 324. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

Further, the conductors 328, 330, and the like are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductors 328 and 330 have a plug or wiring function.

As the material of the conductor 328 and the conductor 330, a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity, and tungsten is particularly preferable. Or preferably a low resistance conductive material such as aluminum or copper. The wiring resistance can be reduced by using a low-resistance conductive material.

Fig. 12A is a cross-sectional view in the channel length direction, in which a structural example of a gate electrode of the transistor 200 as an OS transistor and its surroundings is shown. Fig. 12B is a cross-sectional view in the channel length direction, in which a structure example of a gate electrode of the transistor 300 as a Si transistor and its surroundings is shown.

In fig. 12A, a channel length of the transistor 200 is represented by a distance L _OS. The distance L _OS may be, for example, a distance between a lower end portion of the conductor 242a and a lower end portion of the conductor 242 b. In fig. 12B, a channel length of the transistor 300 is shown by a distance L _Si. The distance L _Si may be, for example, a distance between an upper end portion of the low-resistance region 314a and an upper end portion of the low-resistance region 314 b.

Note that in silicon transistors, for example, the process node of the semiconductor (e.g., the 5nm node) does not correspond to the channel length of the actual product in many cases. For example, when a transistor is manufactured with a process node of a semiconductor of 5nm node, a channel length is sometimes 14nm or more and 16nm or less, a line width (L) is sometimes 5nm or more and 7nm or less, and a pitch (S) is sometimes 30nm or more and 35nm or less. Note that the line width (L) represents the minimum line width of the transistor, and the pitch (S) represents the minimum pitch width of the transistor. Therefore, the value of the process node of the semiconductor is only one indicator of the degree of miniaturization. Therefore, in the semiconductor device according to one embodiment of the present invention, as shown in fig. 12A and 12B, a comparison between the distance L _OS of the channel length of the transistor 200 and the distance L _Si of the channel length of the transistor 300 is an important element.

In addition, the channel width (W) of the transistor depends on the on-state current (Ion) of the transistor required in the circuit design. Accordingly, the practitioner can appropriately select an appropriate range of the channel width (W) of the transistor.

In the case where a CMOS circuit is configured using the transistor 200 shown in fig. 12A and the transistor 300 shown in fig. 12B, as described above, by making the distance L _Si longer than the distance L _OS, the difference in mobility between the transistor 200 and the transistor 300 can be reduced. Thus, even if a CMOS circuit is configured using the transistor 200 as an OS transistor and the transistor 300 as an Si transistor, the CMOS circuit can be normally driven.

In the case where the memory circuit 21 is configured using the transistor 200 shown in fig. 12A and the transistor 300 shown in fig. 12B, as described above, by making the distance L _Si longer than the distance L _OS, the potential can be supplied from the same power source to the gate of the transistor 200 and the gate of the transistor 300, respectively.

As described above, the distance L _OS is preferably set to less than 15nm and the distance L _Si is preferably set to 15nm or more. Or preferably, the distance L _OS is set to 3nm or more and less than 15nm and the distance L _Si is set to 15nm or more and 40nm or less. The distance L _OS may typically be above 5nm and below 8 nm.

The gate length of the transistor 200 as an OS transistor is described below.

Fig. 13A shows an enlarged view of the vicinity of the channel formation region in fig. 7B. Fig. 13A is a cross-sectional view of the transistor 200 in the channel length direction. As described above, the insulator 252, the insulator 250, and the insulator 254 are used as the first gate insulator.

Insulator 252, insulator 250, and insulator 254 are sometimes collectively referred to hereinafter as insulator 256. At this time, the insulator 256 includes the insulator 252, the insulator 250 on the insulator 252, and the insulator 254 on the insulator 250. Further, an insulator 256 is used as the first gate insulator.

Fig. 13B shows a cross-sectional view of the insulator 252, the insulator 250, and the insulator 254 included in fig. 13A replaced with an insulator 256. In fig. 13B, a single-layer conductor 260 is shown for simplicity of drawing. Note that, as described above, the conductor 260 may have a stacked structure of the conductor 260a and the conductor 260b or a stacked structure of three or more layers.

The width Lg shown in fig. 13A and 13B is the width of the bottom surface of the conductor 260 in the region overlapping the metal oxide 230B in the cross section in the channel length direction. The bottom surface of the conductor 260 in the region overlapping the metal oxide 230b in the cross section in the channel length direction may be simply referred to as the bottom surface of the conductor 260 in the region overlapping the metal oxide 230 b. That is, the bottom surface of the conductor 260 in the region overlapping with the metal oxide 230b, which will be described later, may be sometimes referred to as the bottom surface of the conductor 260 in the region overlapping with the metal oxide 230b in the cross section in the channel length direction.

The gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is in operation, and is the width of the bottom surface of the gate electrode in a top view of the transistor. In this specification and the like, the gate length is the width of the bottom surface of the conductor 260 in the region overlapping the metal oxide 230b in the cross section in the channel length direction. That is, the gate length is the width Lg shown in fig. 13A and 13B. Note that the conductor 260 is provided inside the opening included in the insulator 275 and the insulator 280. Furthermore, the sidewalls of the opening are perpendicular or oblique to the substrate face. In particular, when the angle formed between the sidewall of the opening and the substrate surface is 90 ° or less, the minimum width of the conductor 260 in the region overlapping with the metal oxide 230b is the width Lg. Therefore, the conductor 260 may also include a region having a width Lg in the cross section in the channel length direction.

The bottom surface of the conductor 260 in the region overlapping with the metal oxide 230b preferably has a flat region. As shown in fig. 13A and 13B, when the bottom surface of the conductor 260 in the region overlapping with the metal oxide 230B has a flat region, the width Lg is the width of the flat region. By having a flat region on the bottom surface of the conductor 260 in the region overlapping with the metal oxide 230b, an electric field can be uniformly generated in the channel formation region of the metal oxide 230.

Fig. 13A and 13B show a structure in which the bottom surface of the conductor 260 in the region overlapping with the metal oxide 230B has a flat region, but the present invention is not limited thereto. The bottom surface of the conductor 260 in the region overlapping with the metal oxide 230b in the cross section in the channel length direction may have a curved line.

Fig. 13C shows a modified example of the transistor 200 shown in fig. 13B. Fig. 13C is a cross-sectional view of the transistor 200 in the channel length direction. For example, as shown in fig. 13C, the bottom surface of the conductor 260 in the region overlapping with the metal oxide 230b may include a flat region and a region having a curve. Note that the areas with curves are located at the ends of both sides of the bottom surface. Here, the point at which the curve on the side of the conductor 242a on the bottom surface contacts the side surface on the side of the conductor 242a of the conductor 260 is the point Qa. The point at which the curve on the side of conductor 242b on the bottom surface contacts the side of conductor 242b on the side of conductor 260 is point Qb. In this structure, the width Lg is the line segment length connecting the point Qa and the point Qb.

Fig. 13D shows a modified example of the transistor 200 shown in fig. 13B. Fig. 13D is a cross-sectional view of the transistor 200 in the channel length direction. For example, as shown in fig. 13D, the conductor 260 may have an arc-shaped bottom surface. Note that this arc is an arc whose center of curvature P is located within the conductor 260 and whose radius r. In this structure, the width Lg is a width of a region where a straight line including the center of curvature P and parallel to the bottom surface of the metal oxide 230b overlaps the conductor 260 in a cross section in the channel length direction. In other words, the width Lg is 2 times the radius r. Note that a straight line indicated by a broken line in fig. 13D is a straight line including the curvature center P and parallel to the bottom surface of the metal oxide 230 b.

Note that, in the bottom surface shape of the conductor 260 shown in fig. 13D, when the radius r is large (for example, when the radius r is larger than the channel length), the distance from the curvature center P to the channel formation region of the metal oxide 230b also becomes large. In this case, the gate length of this shape may be the width Lg shown in fig. 13C. That is, the width Lg may be calculated from the shape determination points Qa and Qb of the bottom surface of the conductor 260 shown in fig. 13D.

In the bottom surface shape of the conductor 260 shown in fig. 13C, it is sometimes difficult to determine the points Qa and Qb. In this case, the gate length of this shape may be the width Lg shown in fig. 13D. That is, the width Lg may be calculated by determining the curvature center P based on the shape of the bottom surface of the conductor 260 shown in fig. 13C.

The gate length is described above. Next, the channel length is described.

As described above, the channel length of the transistor 200 is represented by the distance L _OS. The distance L _OS may be, for example, a distance between a lower end portion of the conductor 242a and a lower end portion of the conductor 242 b.

In the above structure, the channel length is set according to the material for the conductor 260, the gate length, the material and thickness for the first gate insulator, and the like. In any of the above ranges, the channel length may be, for example, 60nm or less, 50nm or less, 40nm or less, or 30nm or less, and 10nm or more, 15nm or more, or 20nm or more.

When openings are formed in the insulator 280 and the insulator 275, an upper portion of the metal oxide 230b in a region overlapping with the openings is sometimes removed, which will be described in detail later. At this time, as shown in fig. 13E, the thickness of the region of the metal oxide 230b overlapping the conductor 260 is thinner than the thickness of the region of the metal oxide 230b overlapping the conductor 242 a. Note that the transistor 200 shown in fig. 13E is a modified example of the transistor 200 shown in fig. 13B. Fig. 13E is a cross-sectional view of the transistor 200 in the channel length direction.

Here, the difference Lt between the thickness of the region of the metal oxide 230b overlapping the conductor 260 and the thickness of the region of the metal oxide 230b overlapping the conductor 242a is the difference Lt (see fig. 13E). At the difference Lt, for example, the distance between the lower end portion of the conductor 242a and the lower end portion of the conductor 242b can be regarded as the channel length.

In addition, as described above, when the thin insulator 252 is formed, as shown in fig. 13F, the layer 244a may be formed between the conductor 242a and the insulator 256. Likewise, layer 244b is sometimes formed between conductor 242b and insulator 256. In other words, transistor 200 sometimes includes layer 244a between conductor 242a and insulator 256 and layer 244b between conductor 242b and insulator 256. Note that the transistor 200 shown in fig. 13F is a modified example of the transistor 200 shown in fig. 13E. Fig. 13F is a cross-sectional view of the transistor 200 in the channel length direction.

The layers 244a and 244b are formed by oxidizing the side surfaces of the conductors 242a and 242b, respectively. Thus, the layer 244a contains an element and oxygen included in the conductor 242 a. In addition, the layer 244b includes an element and oxygen included in the conductor 242 b. For example, when both the conductor 242a and the conductor 242b have metal and nitrogen, both the layer 244a and the layer 244b have the metal and oxygen.

Layer 244a is less conductive than conductor 242 a. Further, layer 244b has lower conductivity than conductor 242 b. Therefore, when the transistor 200 includes the layer 244a and the layer 244b, the distance L between the lower end portion of the conductor 242a and the lower end portion of the conductor 242b can be regarded as a channel length. That is, by forming the layers 244a and 244b, the channel length can be increased. Therefore, the source-drain withstand voltage of the transistor 200 can be improved to realize a transistor with high reliability.

Note that in the cross section in the channel length direction, the length in the channel length direction of the layer 244a is the length Lo (see fig. 13F). Note that the length of the layer 244b in the channel length direction is equal to or substantially equal to the length Lo. The length Lo is preferably small. For example, the length Lo is preferably smaller than the width Lg. Specifically, the length Lo is preferably 1nm or more and less than 8nm, more preferably 2nm or more and less than 5nm. By adopting this structure, even if the gate length is in any of the above ranges, the transistor 200 can obtain good electrical characteristics.

< Structural example of semiconductor device 3>

Fig. 14 is a cross-sectional view showing a structural example of a semiconductor device including the transistor 200 and the transistor 300. Fig. 14 shows an example of an inverter formed using an n-channel transistor 200 and a p-channel transistor 300. That is, in the example shown in fig. 14, the transistor 200 corresponds to the transistor 41n shown in fig. 3, and the transistor 300 corresponds to the transistor 41p shown in fig. 3. Fig. 14 shows an example in which the transistor 200 has the structure shown in fig. 7B and the transistor 300 has the structure shown in fig. 11A.

[ Wiring layer ]

Wiring layers including interlayer films, wirings, plugs, and the like may be provided between the structures. Further, the wiring layer may be provided as a plurality of layers according to design. Here, in the conductor having a function of a plug or a wiring, a plurality of structures may be denoted by the same symbol. In this specification, the wiring and the plug electrically connected to the wiring may be one component. That is, a part of the electric conductor is sometimes used as a wiring, and a part of the electric conductor is sometimes used as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 300. Further, the conductors 328, 330, and the like are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Further, the electric conductor 328 and the electric conductor 330 are used as plugs or wirings.

Further, an insulator used as an interlayer film may be used as a planarizing film covering the concave-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization may also be achieved by a planarization process using a Chemical Mechanical Polishing (CMP) method.

Further, a wiring layer may be provided on the insulator 326 and the conductor 330. For example, in fig. 14, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Further, conductors 356 are formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 is used as a plug or wiring.

Similarly, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are filled with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like. The electrical conductor 218 is used as a plug or wiring. Further, an insulator 150 is provided on the conductor 112.

Here, like the insulator 241 in the above embodiment, the insulator 217 is provided so as to be in contact with the side surface of the conductor 218 used as a plug. The insulator 217 is provided in contact with the inner walls of openings formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. In other words, insulator 217 is disposed between conductor 218 and insulator 210, insulator 212, insulator 214, and insulator 216. The conductor 205 may be formed in parallel with the conductor 218, so the insulator 217 is sometimes formed in contact with the side surface of the conductor 205.

As the insulator 217, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, it is possible to suppress impurities such as water and hydrogen from being mixed into the metal oxide 230 from the insulator 210, the insulator 216, and the like through the conductor 218. In particular, silicon nitride has high barrier properties against hydrogen, so that it is preferable. Further, oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218.

The insulator 217 may be formed using the same method as the insulator 241. For example, silicon nitride is deposited using a PEALD process, and an opening to the conductor 356 may be formed using an anisotropic etch.

Examples of insulators that can be used as an interlayer film include oxides, nitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

For example, by using a material having a relatively low dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material is preferably selected according to the function of the insulator.

For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like are preferably insulators having a low relative dielectric constant. For example, the insulator preferably contains silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, and resin. Or the insulator preferably has a stacked structure of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, or silicon oxide having voids and resin. Since silicon oxide and silicon oxynitride have thermal stability, a stacked structure having thermal stability and low relative dielectric constant can be realized by combining them with a resin. Examples of the resin include polyesters, polyolefins, polyamides (nylon, aramid, etc.), polyimides, polycarbonates, and acrylic resins.

Further, the transistor using an oxide semiconductor is surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, whereby the electrical characteristics of the transistor can be stabilized. Accordingly, as the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.

As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or stacked layers. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide and the like, silicon oxynitride, silicon nitride and the like can be used.

As a conductor which can be used for wiring and a plug, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Further, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus may be used. Further, a silicide such as nickel silicide may be used.

For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials may be used in a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity, and tungsten is preferably used. Or preferably using a low resistance conductive material such as aluminum, copper, or the like. The wiring resistance can be reduced by using a low-resistance conductive material.

[ Wiring or plug provided with layer of oxide semiconductor ]

Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In this case, an insulator having barrier properties is preferably provided between the insulator having the excess oxygen region and the conductor provided to the insulator having the excess oxygen region.

For example, in fig. 14, an insulator 241 is preferably provided between an insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can have a structure sealed with an insulator having barrier properties.

That is, by providing the insulator 241, the excess oxygen in the insulator 224 and the insulator 280 can be prevented from being absorbed by the conductor 240. Further, by having the insulator 241, diffusion of hydrogen as an impurity to the transistor 200 through the conductor 240 can be suppressed.

Further, as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen is preferably used. For example, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like is preferably used. In particular, silicon nitride has high barrier properties against hydrogen, so that it is preferable. For example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

As in the above embodiment, the transistor 200 may be sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283. By adopting the above-described structure, for example, the hydrogen contained in the insulator 274, the insulator 150, or the like is reduced from being mixed into the insulator 280.

Here, the conductor 240 penetrates the insulator 283 and the insulator 282, the conductor 218 penetrates the insulator 214 and the insulator 212, and the insulator 241 is provided in contact with the conductor 240 and the insulator 217 is provided in contact with the conductor 218 as described above. This can reduce the mixing of hydrogen into the inside of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 through the conductors 240 and 218. In this manner, the transistor 200 can be sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 or the like can be reduced from being mixed in from the outside.

[ Cutting line ]

Next, dicing lines (sometimes referred to as dicing lines, breaking lines, or cutting lines) provided when dividing a large-area substrate into a plurality of semiconductor devices having a chip shape for each semiconductor device will be described. As a dividing method, for example, after grooves (dicing lines) for dividing semiconductor modules are first formed in a substrate, the grooves are cut at the dicing lines, and a plurality of divided (divided) semiconductor devices are obtained.

Here, for example, as shown in fig. 14, it is preferable to design such that the region where the insulator 283 and the insulator 214 are in contact overlaps with the dicing line. That is, openings are provided in the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, and the insulator 216 in the vicinity of a region to be a dicing line provided at an edge of the memory circuit including the plurality of transistors 200.

That is, in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, and the insulator 216, the insulator 214 is in contact with the insulator 283.

For example, openings may be formed in the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, the insulator 216, and the insulator 214. By adopting such a structure, the insulator 212 is in contact with the insulator 283 in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, the insulator 216, and the insulator 214. At this time, the insulator 212 and the insulator 283 may be formed using the same material and the same method. By forming the insulator 212 and the insulator 283 using the same material and the same method, the compactability can be improved. For example, silicon nitride is preferably used.

By adopting this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if a substrate is divided into a plurality of chips for each circuit region where the semiconductor element shown in this embodiment mode is formed, impurities such as hydrogen and water are prevented from being mixed in from the side surface direction of the divided substrate and diffusing to the transistor 200.

Further, by adopting this structure, the excess oxygen in the insulator 280 and the insulator 224 can be prevented from diffusing to the outside. Accordingly, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the channel-forming oxide in the transistor 200. Due to this oxygen, oxygen vacancies of the oxide forming a channel in the transistor 200 can be reduced. Thus, the oxide forming the channel in the transistor 200 can be an oxide semiconductor having a low defect state density and stable characteristics. That is, the reliability can be improved while suppressing variation in the electrical characteristics of the transistor 200.

Fig. 15 is a cross-sectional view showing a structural example of the semiconductor device, and is a modified example of the structure shown in fig. 14. In the semiconductor device shown in fig. 15, the transistor 200 has the structure shown in fig. 10A.

Fig. 16 is a cross-sectional view of the semiconductor device shown in fig. 15 along the channel width direction of the transistor 200 and the transistor 300. As shown in fig. 16, when both the transistor 200 and the transistor 300 are Fin-type transistors, both the transistor 200 and the transistor 300 may be transistors having high on characteristics and high off characteristics, which is preferable.

Transistor 300 may not be a Fin-type transistor. Fig. 17 shows a modified example of the semiconductor device shown in fig. 15, in which the transistor 300 is a planar transistor. By using a planar transistor as the transistor 300, the manufacturing process of the transistor 300 can be simplified.

< Structural example of semiconductor device 4>

Fig. 18 is a cross-sectional view showing an example of the structure of a semiconductor device including the transistor 200 and the transistor 300. In fig. 18, the transistor 200 corresponds to, for example, the transistor MW3 shown in fig. 6, and the transistor 300 corresponds to, for example, the transistor MR3 shown in fig. 6. Fig. 18 shows an example in which capacitor 100 is provided above transistor 200. The capacitor 100 corresponds to, for example, the capacitor CS3 shown in fig. 6. Fig. 18 shows an example in which the transistor 200 has the structure shown in fig. 7B and the transistor 300 has the structure shown in fig. 11A.

[ Capacitor ]

The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as one of a pair of electrodes, a conductor 120 serving as the other of the pair of electrodes, and an insulator 130 serving as a dielectric. Here, the insulator 130 is preferably an insulator which can be used as the insulator 283 described above.

For example, the conductor 112 and the conductor 110 provided on the conductor 240 may be separately formed. Further, the conductor 112 is used as a plug or wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

Fig. 18 shows an example in which the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited to this, and may have a laminated structure of two or more layers. For example, a conductor having high adhesion to a conductor having barrier properties and a conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

As the insulator 130, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like can be used. As the insulator 130, layers containing these materials may be provided in a stack or a single layer.

For example, a stacked structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material is preferably used for the insulator 130. By adopting this structure, the capacitor 100 can suppress electrostatic breakdown while securing sufficient capacitance.

Note that as the high dielectric constant material (material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, nitride containing silicon and hafnium, and the like can be given. Alternatively, the insulator 130 may be a stacked structure of the high dielectric constant material. Examples of the laminated structure include a three-layer structure of zirconia, alumina on the zirconia, and zirconia on the alumina.

On the other hand, as a material having a high dielectric strength (a material having a low relative dielectric constant), there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, resin, and the like.

Fig. 19 is a cross-sectional view showing a structural example of the semiconductor device, and is a modified example of the structure shown in fig. 18. In the semiconductor device shown in fig. 19, the transistor 200 has the structure shown in fig. 10A. Here, a cross section along the channel width direction of the transistor 200 and the transistor 300 may have a structure shown in fig. 16. The transistors 200 and 300 shown in fig. 19 are Fin transistors. As described above, when both the transistor 200 and the transistor 300 are Fin-type transistors, both the transistor 200 and the transistor 300 may be transistors having high on characteristics and high off characteristics, which is preferable.

As described above, the transistor 300 may not be a Fin-type transistor. Fig. 20 shows a modified example of the semiconductor device shown in fig. 19, in which the transistor 300 is a planar transistor. As described above, by using a planar transistor as the transistor 300, the manufacturing process of the transistor 300 can be simplified.

As described above, at least a part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments and other examples described in this specification.

(Embodiment 2)

In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is described with reference to fig. 21A and 21B. A plurality of circuits (systems) are mounted on the chip 1200. As such, a technology in which a plurality of circuits (systems) are integrated on one Chip is sometimes referred to as a System on Chip (SoC).

As shown in fig. 21A, the chip 1200 includes a CPU1211, a GPU1212, one or more analog computation portions 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

The chip 1200 is provided with bumps (not shown) connected to the first surface of the package substrate 1201 as shown in fig. 21B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, and the bumps 1202 are connected to the motherboard 1203.

Further, a memory device such as a DRAM1221 and a flash memory 1222 may be provided on the motherboard 1203. For example, DOSRAM shown in the above embodiment can be applied to the DRAM1221. Further, NOSRAM shown in the above embodiment can be applied to the flash memory 1222, for example.

The CPU1211 preferably has a plurality of CPU cores. Furthermore, the GPU1212 preferably has multiple GPU cores. Further, the CPU1211 and the GPU1212 may each have a memory that temporarily stores data. Alternatively, a memory commonly used by the CPU1211 and the GPU1212 may be provided on the chip 1200. The above NOSRAM or DOSRAM can be applied to the memory. Furthermore, the GPU1212 is suitable for parallel computing of multiple data, which may be used for image processing or product-sum operations. By providing an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention as the GPU1212, image processing and product-sum operation can be performed with low power consumption.

Further, since the CPU1211 and the GPU1212 are provided on the same chip, wiring between the CPU1211 and the GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between memories possessed by the CPU1211 and the GPU1212, and operation result transfer from the GPU1212 to the CPU1211 after operation in the GPU1212 is completed can be performed at high speed.

The analog operation unit 1213 includes one or both of an a/D (analog/digital) conversion circuit and a D/a (digital/analog) conversion circuit. The product-sum operation circuit may be provided in the analog operation unit 1213.

The memory controller 1214 has a circuit used as a controller of the DRAM1221 and a circuit used as an interface of the flash memory 1222.

The interface 1215 has an interface circuit between the display device, a speaker, a microphone, a camera, or a controller, and an external connection apparatus. The controller includes a mouse, a keyboard, a game machine controller, and the like. As the interface, for example, USB (Universal SerialBus: universal serial bus), HDMI (High-DefinitionMultimediaInterface: high-definition multimedia interface) (registered trademark) can be used.

The network circuit 1216 includes a network circuit such as a LAN (Local Area Network: local area network). In addition, a network security circuit may be provided.

The above-described circuits (systems) may be formed on the chip 1200 through the same manufacturing process. Thus, even if the number of circuits required for the chip 1200 increases, the chip 1200 can be manufactured at low cost without increasing the number of manufacturing steps.

The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU1212, the DRAM1221, and the flash memory 1222 may be referred to as a GPU module 1204.

The GPU module 1204 may reduce its size by having a chip 1200 using SoC technology. Furthermore, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, or portable (portable) gaming devices due to its high image processing capability. Further, by using a product-sum operation circuit using the GPU1212, a method such as a Deep Neural Network (DNN), a Convolutional Neural Network (CNN), a Recurrent Neural Network (RNN), an automatic encoder, a Deep Boltzmann Machine (DBM), or a Deep Belief Network (DBN) may be performed, whereby the chip 1200 may be used as an AI chip, or the GPU module 1204 may be used as an AI system module.

Embodiment 3

The present embodiment shows an example of an electronic component and an electronic device to which the storage device described in the above embodiment is attached.

< Electronic Member >

First, an example of an electronic component in which the storage device 720 is incorporated will be described with reference to fig. 22A and 22B.

Fig. 22A shows a perspective view of the electronic component 700 and a substrate (circuit board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in fig. 22A includes a memory device 720 within a mold 711. In fig. 22A, a part of the electronic component 700 is omitted to show the inside thereof. The electronic component 700 includes a land (land) 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 through a wire 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. The circuit board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702, respectively.

The memory device 720 includes a driving circuit layer 721 and a memory circuit layer 722.

Fig. 22B shows a perspective view of the electronic component 730. Electronic component 730 is an example of a SiP (SYSTEM INPACKAGE: system on package) or MCM (Multi ChipModule: multi-chip Module). In the electronic component 730, a package substrate 732 (printed circuit board) is provided with a interposer 731, and the interposer 731 is provided with a semiconductor device 735 and a plurality of memory devices 720.

The electronic component 730 shows an example of using the storage device 720 as a high bandwidth memory (HBM: high Bandwidth Memory). The semiconductor device 735 may be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

The package substrate 732 may use a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The board 731 may be a silicon board, a resin board, or the like.

The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different pitches. The plurality of wirings are constituted by a single layer or a plurality of layers. Further, the interposer 731 has a function of electrically connecting an integrated circuit provided on the interposer 731 with an electrode provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate (rewiring substrate)" or an "intermediate substrate". In addition, a through electrode may be provided in the interposer 731, whereby the integrated circuit and the package substrate 732 may be electrically connected to each other through the through electrode. In addition, in the case of using a silicon interposer, a TSV (Through Silicon Via: through silicon via) may be used as the through electrode.

As the plug 731, a silicon plug is preferably used. Since the silicon interposer does not need to be provided with active elements, it can be manufactured at lower cost than an integrated circuit. On the other hand, since the wiring formation of the silicon interposer can be performed in the semiconductor process, fine wirings which are difficult to form when using the resin interposer can be easily formed.

In HBM, many wires need to be connected in order to achieve a wide memory bandwidth. For this reason, it is required that fine wiring can be formed at high density on a board on which HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

In addition, in an SiP, MCM, or the like using a silicon interposer, degradation in reliability due to differences in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Further, since the surface flatness of the silicon interposer is high, a connection failure is not easily generated between the integrated circuit provided on the silicon interposer and the silicon interposer. Silicon interposer is particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged and disposed across the interposer.

Further, a heat sink (heat radiation plate) may be provided so as to overlap with the electronic component 730. In the case of providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the board 731 uniform. For example, in the electronic component 730 shown in the present embodiment, it is preferable that the height of the memory device 720 is uniform with that of the semiconductor device 735.

In order to mount the electronic component 730 on another substrate, the electrode 733 may be provided on the bottom of the package substrate 732. Fig. 22B shows an example of forming the electrode 733 with a solder ball. The BGA (Ball GRID ARRAY: ball grid array) can be mounted by disposing solder balls in a matrix on the bottom of the package substrate 732. The electrode 733 may be formed using a conductive needle. The PGA (PIN GRID ARRAY: pin grid array) can be mounted by providing conductive pins in a matrix form on the bottom of the package substrate 732.

The electronic component 730 may be mounted on other substrates by various mounting means, not limited to BGA and PGA. For example, mounting methods such as SPGA (STAGGEREDPINGRIDARRAY: staggered pin grid array), LGA (LANDGRIDARRAY: land grid array), QFP (QuadFlat Package: quad Flat package), QFJ (QuadFlatJ-LEADEDPACKAGE: quad J-lead Flat package), or QFN (Quad Flat No-LEADED PACKAGE: quad no-lead Flat package) may be employed.

Embodiment 4

In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device according to the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smart phone, an electronic book reader, a digital camera (including a video camera), a video recording/reproducing device, and a navigation system). Note that herein, a computer includes a tablet computer, a notebook computer, a desktop computer, and a mainframe computer such as a server system. Or the semiconductor device shown in the above embodiment mode is applied to various removable storage devices such as a memory card (e.g., SD card), a USB memory, an SSD (solid state disk), and the like. Fig. 23A to 23E schematically show several structural examples of the removable storage device. For example, the semiconductor device shown in the above embodiment modes is processed into a packaged memory chip and used for various memory devices or removable memories.

Fig. 23A is a schematic diagram of a USB memory. USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device according to the above embodiment mode can be mounted on the memory chip 1105, for example.

Fig. 23B is an external schematic view of the SD card, and fig. 23C is a schematic view of the internal structure of the SD card. SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on a substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device according to the above embodiment mode can be mounted on the memory chip 1114, for example.

Fig. 23D is an external schematic view of the SSD, and fig. 23E is a schematic view of the internal structure of the SSD. SSD1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and for example, DOSRAM chips may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD1150 can be increased. The semiconductor device shown in the above embodiment modes can be assembled to the memory chip 1154, for example.

Embodiment 5

The semiconductor device according to one embodiment of the present invention can be applied to a processor or a chip such as a CPU or a GPU. Fig. 24A to 24H show specific examples of an electronic device having a processor or a chip such as a CPU or a GPU according to an embodiment of the present invention.

< Electronic device and System >

A GPU or chip according to one embodiment of the present invention may be mounted on a wide variety of electronic devices. Examples of the electronic device include electronic devices having a large screen such as a television set, a display for a desktop or notebook type information terminal, a digital signage (DIGITAL SIGNAGE), and a large-sized game machine such as a pachinko machine, and examples thereof include a digital camera, a digital video camera, a digital photo frame, an electronic book reader, a mobile phone, a portable game machine, a portable information terminal, and a sound reproducing device. In addition, by providing a GPU or a chip according to an embodiment of the present invention in an electronic device, the electronic device can be provided with artificial intelligence.

The electronic device according to an embodiment of the present invention may include an antenna. By receiving the signal using the antenna, an image, information, or the like can be displayed on the display portion. Further, when the electronic device includes an antenna and a secondary battery, the antenna may be used for noncontact power transmission.

The electronic device according to one embodiment of the present invention may include a sensor (the sensor has a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, smell, or infrared ray).

The electronic device according to one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (still image, moving picture, character image, etc.) on the display unit; a function of a touch panel; a function of displaying a calendar, date, time, or the like; executing functions of various software (programs); a function of performing wireless communication; a function of reading out a program or data stored in the storage medium; etc. Fig. 24A to 24H show examples of the electronic apparatus.

[ Information terminal ]

Fig. 24A shows a mobile phone (smart phone) which is one of information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102, and the display portion 5102 includes a touch panel as an input interface and buttons are provided on the housing 5101.

By applying the chip of one embodiment of the present invention to the information terminal 5100, an application program using artificial intelligence can be executed. Examples of the application program using artificial intelligence include an application program that recognizes a session to display the content of the session on the display portion 5102, an application program that recognizes characters, graphics, or the like input by a user to a touch panel provided in the display portion 5102 to display the characters, graphics, or the like on the display portion 5102, and an application program that performs biometric recognition of fingerprints, voice prints, or the like.

Fig. 24B shows a notebook information terminal 5200. The notebook information terminal 5200 includes an information terminal main body 5201, a display portion 5202, and a keyboard 5203.

As with the information terminal 5100, by applying the chip according to one embodiment of the present invention to the notebook information terminal 5200, an application program using artificial intelligence can be executed. Examples of the application program using artificial intelligence include design support software, article collation software, and menu automatic generation software. In addition, novel artificial intelligence can be developed by using the notebook information terminal 5200.

Note that in the above example, fig. 24A and 24B show a smart phone and a notebook information terminal, respectively, as examples of electronic devices, but information terminals other than the smart phone and the notebook information terminal may be applied. Examples of information terminals other than smart phones and notebook-type information terminals include PDAs (personal digital assistants), desktop information terminals, and workstations.

[ Game machine ]

Fig. 24C illustrates a portable game machine 5300 as an example of the game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection portion 5305 provided in the housing 5301 to another housing (not shown), the video output to the display portion 5304 can be output to another video display device (not shown). At this time, the housing 5302 and the housing 5303 can be used as the operation portions, respectively. Thus, a plurality of game players can play a game at the same time. The chips shown in the above embodiments may be embedded in chips or the like provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

In addition, fig. 24D shows a stationary game machine 5400 of one of the game machines. The stationary game machine 5400 is connected to the controller 5402 wirelessly or by wire.

By applying the GPU or the chip according to one embodiment of the present invention to a game machine such as the portable game machine 5300 and the stationary game machine 5400, a low-power-consumption game machine can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

Further, by applying the GPU or the chip according to one embodiment of the present invention to the portable game machine 5300, the portable game machine 5300 provided with artificial intelligence can be realized.

The progress of the game, the expression of the creature language appearing in the game, the phenomenon appearing on the game, and the like are originally specified by the program of the game, but by applying artificial intelligence to the portable game machine 5300, expression of a program not limited to the game can be realized. For example, the presentation of the content of a game player question, the progress of a game, time, the change in the language of a character appearing on the game, etc. may be achieved.

Further, when a game requiring a plurality of game players is played using the portable game machine 5300, the anthropomorphic game players can be constituted by using artificial intelligence, whereby the artificial intelligence game players can be regarded as opponents, and one person can play a game played by a plurality of persons.

Although fig. 24C and 24D show a portable game machine and a stationary game machine as an example of the game machine, the game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or the chip according to one embodiment of the present invention is applied include a arcade game machine installed in an amusement facility (a game center, an amusement park, or the like), a ball pitching machine for ball hitting practice installed in a sports facility, and the like.

[ Mainframe computer ]

The GPU or chip of one embodiment of the present invention may be applied to a mainframe computer.

Fig. 24E shows a supercomputer 5500 as an example of a mainframe computer. Fig. 24F shows a rack (rackmount) computer 5502 included in the super computer 5500.

The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that a plurality of computers 5502 are housed in the chassis 5501. The computer 5502 is provided with a plurality of boards 5504, and GPUs and chips described in the above embodiments can be mounted on the boards.

The supercomputer 5500 is mainly a mainframe computer suitable for scientific computing. Since scientific calculation requires a huge operation at high speed, power consumption is large and heat generation of a chip is high. By applying the GPU or chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

In fig. 24E and 24F, a super computer is shown as an example of a mainframe computer, but a mainframe computer to which a GPU or a chip according to an embodiment of the present invention is applied is not limited thereto. Examples of the mainframe computer to which the GPU or the chip according to one embodiment of the present invention is applied include a computer (server) that provides a service, a mainframe general-purpose computer (host), and the like.

[ Moving object ]

The GPU or the chip according to one embodiment of the present invention can be applied to an automobile as a moving body and the periphery of a driver's seat of the automobile.

Fig. 24G is a view showing a front windshield surrounding an automobile interior of an example of a mobile body. Fig. 24G shows a display panel 5701 mounted on a dashboard, a display panel 5702, a display panel 5703, and a display panel 5704 mounted on a pillar.

The display panels 5701 to 5703 can provide various information by displaying a setting of a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, or an air conditioner. In addition, the user can appropriately change the display contents, layout, and the like displayed on the display panel according to the preference, and the designability can be improved. The display panels 5701 to 5703 can also be used as illumination devices.

By displaying an image captured by an imaging device (not shown) provided in the automobile on the display panel 5704, it is possible to compensate for a field of view (dead angle) blocked by the pillar. That is, by displaying an image captured by an imaging device provided outside the automobile, a dead angle can be compensated for, and safety can be improved. Further, by displaying an image that compensates for the invisible portion, the safety can be confirmed more naturally and more comfortably. The display panel 5704 can also be used as an illumination device.

Because the GPU or chip of one embodiment of the present invention can be used as a constituent element of artificial intelligence, the chip can be used for an automatic driving system of an automobile, for example. The chip may also be used in systems for navigation or hazard prediction, etc. In addition, information such as navigation and danger prediction may be displayed on the display panels 5701 to 5704.

Although an automobile is described as an example of the moving body in the above example, the moving body is not limited to an automobile. For example, as a mobile body, an electric car, a monorail, a ship, a flying object (a helicopter, an unmanned plane (unmanned plane), an airplane, a rocket), or the like can be given, and the chip according to one embodiment of the present invention can be applied to the mobile body to provide a system using artificial intelligence.

[ Electrical products ]

Fig. 24H shows an electric refrigerator-freezer 5800 which is an example of an electric product. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

By applying the chip according to one embodiment of the present invention to the electric refrigerator/freezer 5800, the electric refrigerator/freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 can be provided with a function of automatically generating a menu based on the consumption period of the food stored in the electric refrigerator-freezer 5800, a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food, or the like, for example.

The electric refrigerator-freezer is described as an example of the electric appliance, but examples of the other electric appliance include a vacuum cleaner, a microwave oven, an electric rice cooker, a water heater, an IH cooker, a water dispenser, a cooling and heating air conditioner including an air conditioner, a washing machine, a clothes dryer, and an audio-visual appliance.

The electronic device described in this embodiment mode, the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be implemented in appropriate combination with the description of other electronic devices.

Embodiment 6

A semiconductor device according to an embodiment of the present invention can be suitably used for a processor using power gating which reduces unnecessary power consumption, for example. In addition, the semiconductor device according to one embodiment of the present invention can be suitably used for a memory (also referred to as an OS memory) using OSFETs. A more specific structure will be described with reference to fig. 25A and 25B.

Power gating is known in which power supply to an inactive arithmetic circuit is temporarily stopped to reduce unnecessary power consumption. In addition, processors that utilize power gating are sometimes referred to as "normally off processors" or "Noff processors. In a normally-off processor, it is necessary to back up data necessary for restoration in a nonvolatile memory before stopping power supply and read out the data at the time of restoration.

Flash memory, ferroelectric random access memory (FeRAM), and the like are known as nonvolatile memories. They have a slow access speed and limit the number of rewrites and are therefore unsuitable for use in non-volatile memories where the processor is normally shut down. As a nonvolatile memory for a normally-off processor, a Magnetoresistive Random Access Memory (MRAM), a resistive random access memory (ReRAM), a Phase Change Memory (PCM), or the like using MTJ elements can be given.

As the nonvolatile memory for the normally-off processor, an OS memory is preferably used. The OS memory is a memory element using an OS transistor. As OS memories, DOSRAM (registered trademark) and NOSRAM (registered trademark) are known.

The OS memory can hold written data for a period of 1 year or more, even 10 years or more, even when power supply is stopped. Further, since the amount of charge written to the OS memory is not easily changed for a long period of time, the OS memory can hold data of a multi-value (multi-bit) or analog value in addition to data of 2 values (1 bit).

Further, the OS memory adopts a method of writing charges to the node through the OS transistor, and thus, for example, a high voltage required for the existing flash memory is not required, and a high-speed writing operation can be realized. In addition, in the flash memory, the charge injection and the charge extraction into and from the charge trapping layer are not performed, and the atomic-level structural change such as MRAM and ReRAM does not occur. Thus, the OS memory can perform data writing and reading virtually indefinitely, and the memory is less degraded than the above memory, and can obtain higher reliability.

Fig. 25A and 25B are diagrams showing transition of power consumption of a normally-off processor. In fig. 25A and 25B, the horizontal axis represents time and the vertical axis represents power consumption. In fig. 25A and 25B, the operation period of the arithmetic circuit is denoted as a period Tact, and the stop period (sleep period) is denoted as a period Tslp.

In fig. 25A and 25B, the power consumed when the supply of power is restarted and the backed-up data is read out is represented as recovered power 910, the power consumed by the operation circuit in normal operation is represented as active power 920, the power consumed by the leakage current in normal operation is represented as leakage power 930, and the power consumed by the data backup immediately before the period Tslp is represented as backup power 940. During normal operation, active power 920 and leakage power 930 are consumed. Note that the recovered power 910 may also be referred to as the power up.

Fig. 25A shows a power consumption transition in the case where an MTJ element is used as a nonvolatile memory for a normally-off processor. Fig. 25B shows a transition of power consumption in the case where the OS memory is used as the nonvolatile memory for the normally-off processor.

The MTJ element cannot hold the multi-value data and the analog data, so the time required for recovery is longer (in other words, the rise time is longer) compared to a normally-off processor using an OS memory capable of holding the multi-value data and the analog data, and thus more recovery power 910 is required. On the other hand, a normally-off processor using an OS memory can restore data in a short time (in other words, a rise time is short), so that high voltage is not required for reading and writing data. By using the OS memory, a normally-off processor with further reduced power consumption can be realized.

Examples

< High temperature Properties of CAAC-OS FET >

The field effect type OS transistor (hereinafter referred to as CAAC-OSFET) that can be provided in the semiconductor device according to one embodiment of the present invention has low temperature dependency and can stably operate even in a high temperature environment. Experiments and the results thereof concerning the high temperature characteristics of the CAAC-OS FET are described in this example.

The CAAC-OS FET can be manufactured by the BEOL (Back End Of Line) steps of a semiconductor manufacturing process such as CMOS. Therefore, it is possible to laminate with a Si transistor (in this embodiment, a field effect type Si transistor in the Si transistor is also referred to as "Si FET"). For example, a circuit requiring high-speed operation can be manufactured by a Si FET process and a circuit requiring low leakage current can be manufactured by a CAAC-OS FET process.

In addition, siFET the off-state current increases with increasing temperature, and the off-state current of the CAAC-OSFET is always the measurement lower limit. Then, the temperature characteristics of the off-state current of the Si FET of L (channel length)/W (channel width) =60 nm/120nm and the temperature characteristics of the off-state current of the CAAC-OS FET of L/w=21 nm/25nm are compared. The off-state currents of both were measured using the circuit shown in fig. 26.

The circuit shown in fig. 26 includes a FET DUT (Device Under Test), a write transistor WFET, and a read circuit SF. The write transistor WFET is a CAAC-OSFET. The sensing circuit SF comprises a series connection of CAAC-OS FETs. Terminal S of the FET of the DUT is used as a terminal to which the source voltage is input. In addition, 1 CAAC-OSFET including a top gate TG and a back gate BG is shown as DUT in FIG. 26. In practice 20000 CAAC-OS FETs are connected in parallel as DUTs. Note that this is not limiting when the DUT is a Si FET.

In the case where the DUT in fig. 26 is SiFET, the measurement conditions of the off-state current of SiFET are as follows: gate voltage V _G = -0.4V, source voltage V _S =0v, drain voltage V _D =1.2v, bulk voltage V _B =0v. In addition, in the case where the DUT in fig. 26 is a CAAC-OS FET, the measurement conditions of the off-state current of the CAAC-OSFET are as follows: gate voltage V _G = -1.0V, source voltage V _S = 0V, drain voltage V _D = 1.2V, back gate voltage V _BG = -5.0V.

Fig. 27 shows the measurement results. In fig. 27, the horizontal axis represents 1000/absolute temperature (temp.), and the vertical axis represents off-state current (off-state leakage current). Note that in fig. 27, a lower measurement limit of a usual measurement apparatus is indicated by a dashed line drawn at 1.0×10 ^-13 a/μm.

As shown in FIG. 27, the off-state current of the Si FET was about 3.1X10 ^-11 A/μm at a measured temperature of 144 ℃. Furthermore, the off-state current of the CAAC-OS FET is about 2.5X10 ^-18 A/μm at a measured temperature of 150 ℃. The CAAC-OS FET can maintain a low off-state current even in a high temperature environment. In addition, by adjusting the back gate voltage, the off-state current can be further reduced.

[ Description of the symbols ]

10A: semiconductor device, 10B: semiconductor device, 10: semiconductor device, 11: layer, 12: layer, 20r: storage unit, 20w: storage unit, 20: storage unit, 21A: storage circuit, 21B: storage circuit, 21C: storage circuit, 21E: storage circuit, 21F: storage circuit, 21G: storage circuit, 21H: storage circuit, 21r: circuit, 21w: circuit, 21: storage circuit, 31n: word line driving circuit, 31p: word line driving circuit, 31: word line driving circuit, 32n: bit line driving circuit, 32p: a bit line driving circuit, 32: bit line driving circuit, 33n: control circuit, 33p: control circuit, 33: control circuit, 34n: communication circuit, 34p: communication circuit, 34: communication circuit, 35n: input/output circuit, 35p: input/output circuit, 35: input/output circuit, 41n: transistor, 41p: transistor, 100: capacitor, 110: an electrical conductor, 112: electrical conductor, 120: conductor, 130: insulator, 150: insulator, 200: transistor, 205a: conductor, 205b: conductor, 205: electrical conductor, 210: insulator, 212: an insulator (insulator), 214: insulator, 216: insulator, 217: insulator, 218: electrical conductor, 222: insulator, 224: insulator, 230a: metal oxide, 230b: metal oxide, 230ba: region, 230bb: region, 230bc: region, 230: metal oxide, 240a: conductor, 240b: conductor, 240: conductor, 241a: insulator, 241b: insulator, 241: insulator, 242a: conductor, 242b: conductor, 242: conductor, 244a: layer, 244b: layer, 246a: a conductor(s), 246b: conductor, 246: conductor, 250a: insulator, 250b: insulator, 250: insulator, 252: insulator, 254: insulator, 256: insulator, 260a: conductor, 260b: electrical conductor, 260: conductor, 271a: insulator, 271b: insulator, 271: insulator, 274: insulator, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 285: insulator, 300: transistor, 310: substrate, 312: element separation layer, 313: a semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: electrical conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: an electrical conductor, 330: an electrical conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 700: electronic component, 702: printed circuit board, 704: circuit board, 711: mold, 712: connection pad, 713: electrode pads, 714: lead wire, 720: storage device, 721: drive circuit layer, 722: a memory circuit layer, 730: electronic component 731: board, 732: package substrate, 733: electrode, 735: semiconductor device, 910: recovery power, 920: active power, 930: leakage power, 940: backup power, 1100: USB memory, 1101: a housing, 1102: cover, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: a controller chip, 1150: SSD, 1151: shell, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog operation unit 1214: storage controller 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 5100: an information terminal, 5101: housing 5102: display unit, 5200: notebook information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game machine, 5301: housing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection part, 5306: operation key, 5400: stationary gaming machine, 5402: controller, 5500: supercomputer, 5501: frame, 5502: computer, 5504: substrate, 5701: display panel, 5702: display panel, 5703: a display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerating chamber door, 5803: freezing chamber door

Claims

1. A semiconductor device, comprising:

A first layer; and

A second layer on the first layer,

Wherein the first layer includes a p-channel type first transistor including silicon in a first channel formation region,

The second layer includes an n-channel type second transistor including a metal oxide in a second channel formation region,

A CMOS circuit is formed using the first transistor and the second transistor,

And, the channel length of the first transistor is longer than the channel length of the second transistor.

2. The semiconductor device according to claim 1,

Wherein a channel length of the first transistor is 15nm or more,

And the channel length of the second transistor is less than 15nm.

3. The semiconductor device according to claim 1,

Wherein a channel length of the first transistor is 15nm or more and 40nm or less,

And the channel length of the second transistor is 3nm or more and less than 15nm.

4. The semiconductor device according to any one of claim 1 to 3,

Wherein the first layer comprises a monocrystalline silicon substrate,

And the first transistor has the first channel formation region in the single crystal silicon substrate.

5. The semiconductor device according to any one of claim 1 to 4,

Wherein the second layer includes memory circuitry.

6. The semiconductor device according to claim 5,

Wherein the memory circuit includes a third transistor, a fourth transistor and a capacitor,

One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,

And a gate of the fourth transistor is electrically connected to one electrode of the capacitor.

7. The semiconductor device according to claim 6,

Wherein the third transistor and the fourth transistor contain a metal oxide in the second channel formation region in each channel formation region.

8. An electronic device, comprising:

The semiconductor device according to any one of claims 1 to 7; and

And a display unit.