CN118159974A

CN118159974A - Method for designing a circuit, electronic device, computer-readable storage medium and program product

Info

Publication number: CN118159974A
Application number: CN202280070825.3A
Authority: CN
Inventors: 游江坤; 龚辰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-01-10
Filing date: 2022-01-10
Publication date: 2024-06-07
Also published as: WO2023130464A1

Abstract

The present disclosure relates to a method and an electronic device for designing a circuit. The method automatically converts code described by a designer in a source language such as Chisel into circuit programming code described in a target language such as Verilog. More specifically, the method automatically converts a source representation of a domain segment described in a source language as transmitted over a circuit interface into a target representation described in a target language for representing the domain segment transmitted over the circuit interface. In this way, the designer does not need to know the bit range corresponding to each domain segment in the signal transmitted through the circuit interface, but only needs to know the name of the domain segment to access the data corresponding to the domain segment. Therefore, compared with the situation that in the conventional scheme, a designer needs to know each bit range of each domain segment in the hardware description language in advance to correctly access the data corresponding to the domain segment, the scheme according to the present disclosure can reduce the cognitive burden of the designer and improve the design efficiency.

Description

Method for designing a circuit, electronic device, computer-readable storage medium and program product

Technical Field

The present disclosure relates to the field of hardware design, and more particularly to a method, an electronic device, a computer readable storage medium, and a program product for designing a circuit.

Background

In the field of integrated circuit (INTEGRATED CIRCUIT, IC) chip design, hardware description language (hardware description language, HDL) is commonly used for circuit design and description. Common hardware description languages include Verilog language, VHDL language, and the like. The basic data structure of this type of hardware description language is mainly a signal type, in which a signal is represented by bits (bits) having a specific bit width. In chip design, the field multiplexing of interface/data structures is often the case, especially in the transmission and processing of messages involved in network chips. There are often tens of packet header format definitions for messages, and the flow and functionality of processing is substantially similar for both packet sending and packet de-sending, and therefore a circuit interface is typically multiplexed. The input or output parameters of the signals transmitted via the circuit interface may be data domain multiplexed to exhibit different data hierarchies in different scenarios.

Because conventional HDLs cannot describe the hierarchical structure of data transferred via a circuit interface, when the above multiplexing scenario is designed and implemented using HDLs, multiplexing of data can be accomplished using only different bit field segments of one signal. However, in conventional HDL designs, manual computation is required each time data for a different domain segment is computed, which is prone to computational errors. In addition, when the HDL is used to design the above scenario, multiple designers may design different scenarios in parallel, which may cause the bit widths of the signals that are negotiated in advance and include multiple domain segments to change, which causes the designers to repeatedly brush the computation refresh document to know the bit ranges of the domain segments in the hardware description language. Problems such as those described above can lead to inefficiency in circuit design.

Disclosure of Invention

In view of the above, embodiments of the present disclosure are directed to methods, electronic devices, computer-readable storage media, and program products for designing a circuit, which may be used to improve the efficiency of circuit design.

According to a first aspect of the present disclosure, a method for designing a circuit is provided. The method comprises the following steps: receiving a first source indication for a first field segment in a set of field segments represented by a source language, the set of field segments representing a set of data transmitted via a circuit interface, the first field segment representing a first portion of data in the set of data; converting the first source indication into a first intermediate representation; and determining, based on the first intermediate representation, a first target indication in a target language, the first target indication representing a range of bits of the first portion of data in the data set transmitted via the circuit interface. The designer accesses the data communicated by the circuit interface through a source indication of the source language expression, which can be automatically converted to a target indication of the target language expression, such as HDL. In this way, the designer does not need to know the bit range corresponding to each domain segment in the signal transmitted through the circuit interface, but only needs to know the name of the domain segment to access the data corresponding to the domain segment. Therefore, compared with the situation that in the conventional scheme, a designer needs to know each bit range of each domain segment in the hardware description language in advance to correctly access the data corresponding to the domain segment, the scheme according to the present disclosure can reduce the cognitive burden of the designer and improve the design efficiency.

In one implementation of the first aspect, the source language may be a high-level language such as Chisel or SpinaHDL and the target language may be an underlying language such as Verilog or VHDL. The source language is a high-level language that is more designer-friendly than the target language, which is more underlying design. Since the source language is a high-level language, it is easier for the designer to understand and is also less prone to error. In this regard, coding and maintenance efficiency may be greatly improved.

In one implementation of the first aspect, an application programming interface (application programming interface, API) may be constructed to enable programming of the circuit by a user. That is, the API may be used to receive user input to the circuit, for example, a designer input of a first source indication of a first domain segment in a set of domain segments represented by a source language.

In one implementation of the first aspect, the method includes implementing a circuit design based on the first target indication. For example, the connection of the circuit interface to the corresponding circuit component is determined based on the transmission of the respective domain segment of the signal at the circuit interface.

In one implementation of the first aspect, determining the first target indication in the target language based on the first intermediate representation includes: converting the first intermediate representation into an intermediate representation of the target language; and converting the intermediate representation of the target language into a first target indication. Further, in an implementation manner of the first aspect, the method further includes mapping the intermediate representation of the target language to the target code of the target language, wherein each intermediate representation of the target language is mapped to the target code of the target language, for example, a rule of HDL syntax, which may be directly implemented using an intermediate representation mapping rule of a conventional HDL. By compiling the code of the high-level language expression, and by converting the intermediate representation after compiling the conversion into an intermediate representation of the low-level language expression such as HDL, the code written in the high-level language can be optimized to obtain the target code of the low-level language expression.

In one implementation of the first aspect, the first intermediate representation includes an intermediate representation for defining a complex or bundle, the intermediate representation carrying variable names of the complex or bundle variables themselves, as well as variable names and corresponding bit widths of all elements in the complex or bundle. Further, the first intermediate representation may also include an intermediate representation defining elements in the access complex or bundle.

In one implementation manner of the first aspect, the method further includes: a complex (union) is constructed, the complex comprising at least one first source element represented by a source language corresponding to each domain segment in the set of domain segments, the bit width corresponding to the complex being a maximum of the at least one bit width corresponding to the at least one first source element, the first source indication being associated with the complex. In one possible implementation, constructing the complex may be performed prior to the designer entering the first source indication. Alternatively, the API may also provide a default association without requiring the user to build the association. The complex is a data structure with a data hierarchy, and can be provided with a plurality of different data elements, wherein the data elements share the same memory, and the occupied size of the memory is the memory occupied by the largest data in the members.

In one implementation manner of the first aspect, the method further includes: a bundle is constructed, the bundle comprising at least one second source element represented by a source language corresponding to each of the set of domain segments, the bit width corresponding to the bundle being a sum of at least one bit width corresponding to the at least one second source element, the first source indication being associated with the bundle. In one possible implementation, the build beam may be prior to the designer entering the first source indication. Alternatively, the API may also provide a default bundle without requiring the user to build the bundle. In a high-level language such as Chisel or spindle, the meaning of bundles is similar to a structure in a programming language (struct) that can bundle different domain segments together as one data stream while being transmitted via different bits of a circuit interface. In contrast, the complex does not require different domain segments to be transmitted simultaneously via different bits of the circuit interface. For example, the first domain segment and the second domain segment in the complex may be transmitted sequentially via the same bits of the circuit interface.

In one implementation of the first aspect, the complex and bundle may be nested with each other. In other words, in one possible implementation, the complex may be embedded in the bundle, and in another possible implementation, the bundle may be embedded in the complex. For example, in one implementation of the first aspect, constructing the bundle includes constructing the bundle based on the association. In another possible implementation, constructing the association includes constructing the association based on the bundle. By nesting the complexes and bundles with one another, the flexibility of the designer in hardware programming can be significantly improved, and the programming efficiency can be significantly improved.

In one implementation manner of the first aspect, the method further includes: modifying the complex by adding another source element to the complex, the bit width corresponding to the complex being the maximum of the at least one bit width corresponding to each first source element in the modified complex, the first source indication being associated with the modified complex. In one implementation manner of the first aspect, the method further includes: the bundle is modified by adding another source element to the complex, the bit width corresponding to the bundle being the sum of the second source elements in the modified bundle, the first source indication being associated with the modified bundle. By adding new elements to the complex or bundle, when the newly added scene is subsequently added, the data structure of the newly added scene is only needed to be added to the complex or bundle, and the scheme can automatically calculate the maximum bit width in the compiling stage without recalculating all scenes and refreshing documents. In this regard, the implementation is better backward compatibility than conventional schemes, which significantly reduces the cognitive burden on the designer and improves programming efficiency, as the designer does not need to know the condition of the individual domain segments of the circuit interface at any time.

In one implementation manner of the first aspect, the method further includes: constructing an intermediate representation of the complex; and constructing a first access intermediary representation for accessing the elements within the complex. In one implementation manner of the first aspect, the method further includes: determining a bit width of the complex based on the complex; and determining bit ranges corresponding to the elements within the complex based on the bit widths of the complex and the first access intermediate representation. By building and accessing the intermediate representation of the complex, domain segments of the high-level language input by the designer through the API can be automatically mapped to individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy.

In one implementation manner of the first aspect, the method further includes: the bit widths of all elements of the intermediate representation of the complex are automatically calculated, and a maximum bit width is determined based on the bit widths of all elements, and the maximum bit width is determined to be the bit width of the complex. The method further includes converting the intermediate representation of the complex to a signal with bit width in a target language such as HDL. The method further includes automatically calculating and federating a range of signal interception bits for a target language, such as HDL, corresponding to each element in the access intermediate representation.

In one implementation manner of the first aspect, the method further includes: constructing an intermediate representation of the bundle; and constructing a second access intermediate representation for accessing the element within the bundle. In one implementation manner of the first aspect, the method further includes: determining the position width of the beam body based on the beam body; and determining bit ranges corresponding to the elements within the bundle based on the bit widths of the bundle and the second access intermediate representation. By constructing and accessing the intermediate representation of the bundle, domain segments of the high-level language input by the designer through the API can be automatically mapped to individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy.

In one implementation manner of the first aspect, the method further includes: the bit widths of all elements of the intermediate representation of the bundle are automatically calculated and the bit width of the bundle is determined based on the sum of the bit widths of all elements. The method further includes converting the intermediate representation of the bundle to a signal with bit width in a target language such as HDL. The method further includes automatically calculating and bundles accessing a range of signal interception bits for a target language, such as HDL, corresponding to each element in the intermediate representation.

According to a second aspect of the present disclosure, an electronic device for designing a circuit is provided. The electronic device includes: a receiving unit, a converting unit and a determining unit. The receiving unit is configured to receive a first source indication for a first field segment of a set of field segments represented by a source language, the set of field segments representing a set of data transmitted via the circuit interface, the first field segment representing a first portion of data in the set of data. The conversion unit is configured to convert the first source indication into a first intermediate representation. The determining unit is configured to determine, based on the first intermediate representation, a first target indication in a target language, the first target indication representing a range of bits of the first portion of data in a data set transmitted via the circuit interface. The designer accesses the data communicated by the circuit interface through a source indication of the source language expression, which can be automatically converted to a target indication of the target language expression, such as HDL. In this way, the designer does not need to know the bit range corresponding to each domain segment in the signal transmitted through the circuit interface, but only needs to know the name of the domain segment to access the data corresponding to the domain segment. Therefore, compared with the situation that in the conventional scheme, a designer needs to know each bit range of each domain segment in the hardware description language in advance to correctly access the data corresponding to the domain segment, the scheme according to the present disclosure can reduce the cognitive burden of the designer and improve the design efficiency.

In one implementation of the second aspect, the source language may be a high-level language such as Chisel or SpinaHDL and the target language may be an underlying language such as Verilog or VHDL. The source language is a high-level language that is more designer-friendly than the target language, which is more underlying design. Since the source language is a high-level language, it is easier for the designer to understand and is also less prone to error. In this regard, coding and maintenance efficiency may be greatly improved.

In one implementation of the second aspect, an API may be constructed to enable programming of the circuit by a user. That is, the API may be used to receive user input to the circuit, for example, a designer input of a first source indication of a first domain segment in a set of domain segments represented by a source language.

In an implementation manner of the second aspect, the conversion unit is further configured to: converting the first intermediate representation into an intermediate representation of the target language; and converting the intermediate representation of the target language into a first target indication. Further, in one implementation of the second aspect, the method further includes mapping the intermediate representations of the target languages to target code of the target languages, wherein each of the intermediate representations of the target languages is mapped to target code of the target languages, such as rules of HDL grammar, which may be implemented directly with intermediate representation mapping rules of conventional HDLs. By compiling the code of the high-level language expression, and by converting the intermediate representation after compiling the conversion into an intermediate representation of the low-level language expression such as HDL, the code written in the high-level language can be optimized to obtain the target code of the low-level language expression.

In one implementation of the second aspect, the first intermediate representation includes an intermediate representation for defining a complex or bundle, the intermediate representation carrying variable names of the complex or bundle variables themselves, as well as variable names and corresponding bit widths of all elements in the complex or bundle. Further, the first intermediate representation may also include an intermediate representation defining elements in the access complex or bundle.

In one implementation manner of the second aspect, the electronic device further includes: a building unit configured to build a complex comprising at least one first source element represented by a source language corresponding to each domain segment in the set of domain segments, the bit width corresponding to the complex being a maximum of the at least one bit width corresponding to the at least one first source element, the first source indication being associated with the complex. In one possible implementation, constructing the complex may be performed prior to the designer entering the first source indication. Alternatively, the API may also provide a default association without requiring the user to build the association. The complex is a data structure with a data hierarchy, and can be provided with a plurality of different data elements, wherein the data elements share the same memory, and the occupied size of the memory is the memory occupied by the largest data in the members.

In an implementation manner of the second aspect, the building unit is further configured to: a bundle is constructed, the bundle including at least one second source element represented by a source language corresponding to each of the set of domain segments, the bit width corresponding to the bundle being a sum of at least one bit width corresponding to the at least one second source element, the first source indication being associated with the bundle. In one possible implementation, the build beam may be prior to the designer entering the first source indication. Alternatively, the API may also provide a default bundle without requiring the user to build the bundle. In a high-level language such as Chisel or spindle, the meaning of bundles is similar to a structure in a programming language (struct) that can bundle different domain segments together as one data stream while being transmitted via different bits of a circuit interface. In contrast, the complex does not require different domain segments to be transmitted simultaneously via different bits of the circuit interface. For example, the first domain segment and the second domain segment in the complex may be transmitted sequentially via the same bits of the circuit interface.

In one implementation of the second aspect, the complex and bundle may be nested with each other. In other words, in one possible implementation, the complex may be embedded in the bundle, and in another possible implementation, the bundle may be embedded in the complex. For example, in one implementation of the second aspect, constructing the bundle includes constructing the bundle based on the association. In another possible implementation, constructing the association includes constructing the association based on the bundle. By nesting the complexes and bundles with one another, the flexibility of the designer in hardware programming can be significantly improved, and the programming efficiency can be significantly improved.

In an implementation manner of the second aspect, the electronic device further includes a modification unit. The modification unit is configured to modify the complex by adding another source element to the complex, the bit width corresponding to the complex being the maximum of the at least one bit width corresponding to each first source element in the modified complex, the first source indication being associated with the modified complex. In an implementation manner of the second aspect, the modification unit is further configured to modify the bundle by adding another source element to the association, a bit width corresponding to the bundle being a sum of second source elements in the modified bundle, the first source indication being associated with the modified bundle. By adding new elements to the complex or bundle, when the newly added scene is subsequently added, the data structure of the newly added scene is only needed to be added to the complex or bundle, and the scheme can automatically calculate the maximum bit width in the compiling stage without recalculating all scenes and refreshing documents. In this regard, the implementation is better backward compatibility than conventional schemes, which significantly reduces the cognitive burden on the designer and improves programming efficiency, as the designer does not need to know the condition of the individual domain segments of the circuit interface at any time.

In an implementation form of the second aspect, the building unit is further configured to build an intermediate representation of the complex; and constructing a first access intermediary representation for accessing the elements within the complex. In an implementation manner of the second aspect, the determining unit is further configured to determine a bit width of the association based on the association; and determining bit ranges corresponding to the elements within the complex based on the bit widths of the complex and the first access intermediate representation. By building and accessing the intermediate representation of the complex, domain segments of the high-level language input by the designer through the API can be automatically mapped to individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy.

In an implementation manner of the second aspect, the electronic device further includes a computing unit. The computing unit is configured to: the bit widths of all elements of the intermediate representation of the complex are automatically calculated, and a maximum bit width is determined based on the bit widths of all elements, and the maximum bit width is determined to be the bit width of the complex. The conversion unit is further configured to convert the intermediate representation of the complex into a signal with bit width in a target language such as HDL. The computing unit is further configured to automatically compute and associate a range of signal interception bits of a target language, such as HDL, corresponding to each element in the access intermediate representation of the complex.

In an implementation of the second aspect, the construction unit is further configured to construct an intermediate representation of the bundle; and constructing a second access intermediate representation for accessing the element within the bundle. In an implementation manner of the second aspect, the determining unit is further configured to: determining the position width of the beam body based on the beam body; and determining bit ranges corresponding to the elements within the bundle based on the bit widths of the bundle and the second access intermediate representation. By constructing and accessing the intermediate representation of the bundle, domain segments of the high-level language input by the designer through the API can be automatically mapped to individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy.

In one implementation manner of the second aspect, the computing unit is configured to: the bit widths of all elements of the intermediate representation of the bundle are automatically calculated and the bit width of the bundle is determined based on the sum of the bit widths of all elements. The method further includes converting the intermediate representation of the bundle to a signal with bit width in a target language such as HDL. The method further includes automatically calculating and bundles accessing a range of signal interception bits for a target language, such as HDL, corresponding to each element in the intermediate representation.

In a third aspect of the present disclosure, an electronic device is provided. The electronic device includes: at least one processor; at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions when executed by the at least one processor cause the apparatus to perform the method according to the first aspect.

In a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium stores a computer program which, when executed by a processor, implements a method according to the first aspect.

In a fifth aspect of the present disclosure, a computer program product is provided. The computer program product comprises computer executable instructions which, when executed by a processor, cause the computer to implement the method according to the first aspect.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIG. 1 shows a flow chart of a design fabrication process of an integrated circuit;

FIG. 2 shows a schematic diagram of the transmission of individual domain segment data in a signal over a circuit interface;

FIG. 3 illustrates a schematic flow diagram for designing a circuit according to some embodiments of the present disclosure;

FIG. 4 shows a schematic flow diagram for designing a circuit according to further embodiments of the present disclosure;

FIG. 5 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure; and

Fig. 6 illustrates a block diagram of an example apparatus for designing a circuit, according to an embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below.

In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.

As described above, one circuit interface is generally multiplexed in the course of circuit design. The input or output parameters of the signals transmitted via the circuit interface may be data domain multiplexed to exhibit different data hierarchies in different scenarios. However, in conventional HDL designs, manual computation is required each time data for a different domain segment is computed, which is prone to computational errors. In addition, when the HDL is used to design the above scenario, multiple designers may design different scenarios in parallel, which may cause the bit width of the signal including multiple domain segments negotiated in advance to change, which causes the designer to repeatedly brush the computation refresh document to know the respective bit ranges of the respective domain segments in the hardware description language. Problems such as those described above can lead to inefficiency in circuit design.

In the present disclosure, a method and an electronic device for designing a circuit are provided. The method automatically converts code described by a designer in a source language, such as a high-level language, into circuit programming code described in a target language, such as HDL. More specifically, the method automatically converts a source representation of a domain segment described in a high-level language that is transmitted over a circuit interface into a target representation described in a target language such as HDL that is used to represent the domain segment that is transmitted over the circuit interface. In this way, the designer does not need to know the bit range corresponding to each domain segment in the signal transmitted through the circuit interface, but only needs to know the name of the domain segment to access the data corresponding to the domain segment. Therefore, compared with the situation that in the conventional scheme, a designer needs to know each bit range of each domain segment in the hardware description language in advance to correctly access the data corresponding to the domain segment, the scheme according to the present disclosure can reduce the cognitive burden of the designer and improve the design efficiency.

Fig. 1 shows a flow chart of a design fabrication process of an integrated circuit. The design fabrication process 100 begins with specification 110. In the stage of specification 110, the functional and performance requirements that the integrated circuit needs to meet are determined. Then, in the stage of the integrated circuit design 120, the circuit design 122 is first performed by means of EDA software. After the circuit is determined, the circuit is layout planned for layout design 124. After the circuit layout is obtained, a mask fabrication 16 may be performed to obtain a mask for forming the designed circuits on the wafer. Subsequently, in a stage of manufacturing 130, integrated circuits are formed on the wafer by photolithography, etching, ion implantation, thin film deposition, polishing, and the like. In the stage of packaging 140, the wafer is cut to obtain a die, and the die is packaged by processes such as adhesion, soldering, and die sealing to obtain a chip. The resulting chips are tested in a stage of testing 150 to ensure that the performance of the finished chips meets the requirements determined in specification 110. Eventually, the chips 160 that are under test may be delivered to the customer.

In the course of circuit design 122, various interfaces of the circuit need to be designed. More specifically, the circuit interfaces need to be multiplexed for different scenarios. In conventional HDL designs, each time data for a different field segment is calculated, the designer is required to make the calculation with knowledge of the bit ranges corresponding to the individual field segments, which can easily lead to calculation errors and reduce the efficiency of the circuit design.

For example, fig. 2 shows a schematic diagram of the transmission of individual field segment data in a signal via the circuit interface 20. For example, in case S0, the data of the field segments F0, F1, F2 and F3 are transmitted in parallel through the circuit interface 20, for example, from the right side to the left side in fig. 2. In this case, the signal includes data of four field segments. Assuming that the data of field segments F0, F1, F2, and F3 occupy 4 bits, respectively (i.e., 4 bits wide), the designer needs to know the bit ranges of the individual field segments in case S0, e.g., field segment F0 occupies the bit range of [3,0], field segment F1 occupies the bit range of [7,4], field segment F2 occupies the bit range of [11,8], and field segment F3 occupies the bit range of [15,12 ].

In case S1 following case S0, the data of the field segments F4, F2 and F3 are transmitted in parallel through the circuit interface 20, for example from the right to the left in fig. 2. In this case, the signal includes data of three field segments. Assuming that field segment F4 occupies 8 bits, F2 occupies 4 bits, and F3 occupies 4 bits, the designer needs to know the bit ranges of the individual field segments in case S1, e.g., field segment F4 occupies the bit range of [7,0], field segment F2 occupies the bit range of [11,8], and field segment F3 occupies the bit range of [15,12 ].

In case S2 following case S1, the data of the field segments F5, F6A, F B and F7 are transmitted in parallel through the circuit interface 20, for example from right to left in fig. 2. In this case, the signal includes data of four field segments. Assuming that field segment F5 occupies 4 bits, F6A occupies 4 bits, F6B immediately following F6A occupies 3 bits, and F7 occupies 8 bits, the designer needs to know the bit ranges and timing relationships of the respective field segments in case S2, e.g., field segment F5 occupies the bit range of [3,0], field segment F6A occupies the bit range of [7,4], field segment F6B transmitted immediately after field segment F6A occupies the bit range of [6,4], and field segment F7 occupies the bit range of [15,8 ].

Conventional circuit design schemes can be particularly difficult when multiple designers design different scenarios in parallel. This may lead to variations in the bit width of the signal negotiated in advance, resulting in the designer having to repeatedly brush the computational refresh document to determine a specific distribution of bit widths of the field segments in each case. In addition, designers need to repeatedly confirm the meaning of different domain segments against the design document for HDL encoding at the time of encoding, which makes it inefficient. Furthermore, HDL maintenance personnel cannot directly read the meaning of the field segments in the code from the code, because the code is represented by the data segments like [ xx: xx ] (x represents an integer) instead of being directly named in natural language, which greatly influences the maintenance efficiency. It follows that the hardware programming efficiency is greatly affected in conventional schemes by describing the domain segments of the signal in HDL in terms of domain segment bit ranges.

Fig. 3 illustrates a schematic flow diagram of a method 300 for designing a circuit according to some embodiments of the present disclosure. In one embodiment, the method 300 may be implemented by an electronic device having computing capabilities, such as a computer. At 302, an electronic device receives a first source indication for a first domain segment in a set of domain segments represented by a source language. The set of domain segments is used to represent a set of data transmitted via the circuit interface, wherein a first domain segment is used to represent a first portion of data in the set of data.

In one embodiment, a designer (also referred to as a "user") may use an API to enable programming of a circuit by a user. That is, the API may be used to receive user input to the circuit, for example, a designer input of a first source indication of a first domain segment in a set of domain segments represented by a source language. In one embodiment, the source language may be a high-level language such as Chisel or SpinaHDL and the target language may be an underlying language such as Verilog or VHDL. The source language is a high-level language that is more designer-friendly than the target language, which is more underlying design. Since the source language is a high-level language, it is easier for the designer to understand and is also less prone to error. In this regard, coding and maintenance efficiency may be greatly improved.

For example, in the case where a signal transmitted through the circuit interface includes the field segments F0, F4, and F5 in chronological order, the designer can input the following code to access the field segments F0, F4, and F5 in fig. 2.

F0// Access Domain field F0, corresponding to HDL semantics of u [3:0]

F4// Access Domain segment F4, corresponding to HDL semantics of u [7:0]

F5// Access Domain segment F5, corresponding to HDL semantics of u [3:0]

Where u represents a complex. In this embodiment, u.f0, u.f4, or u.f5 may be some examples of the first source indication.

In one embodiment, the data structure of the complex may be set by defining u. The complex is a data structure with a data hierarchy, and can be provided with a plurality of different data elements, wherein the data elements share the same memory, and the occupied size of the memory is the memory occupied by the largest data in the members. Data members within the complex may also be accessed by a.number such as u.a/u.b/u.c, where a, b, or c respectively represent different domain segment names.

For the case where the complex includes F0, F4, and F5, in one embodiment, the following code may be given in the source language environment to define or construct the complex u.

Wherein F0, F4, or F5 is the first source element within the complex, which corresponds to the respective domain segment.

In a high-level language environment such as the source language, the API may automatically define a signal with the largest bit width based on the definition of u, as described below.

Wire u [7:0]// defines an 8-bit-wide signal

It will be appreciated that where the complex includes F0, F4 and F5, F4 has the largest bit width, i.e., 8 bits wide. Thus, the bit width of F4 may be defined by the API as the bit width of complex u. If the bit width of F5 is 16 bits, and the bit widths of F0 and F4 are unchanged, then the bit width of F5 is defined herein as the bit width of complex u. The above scenario is only an example and does not limit the scope of the present disclosure.

In one embodiment, the complex u may be defined by the user by means of an API. In other embodiments, the circuit design software may also provide default complex definitions for use by the user, which is not limiting of the present disclosure. Although examples of designer input source indications in a source language environment are shown here as examples of complexes, this is merely illustrative and not limiting of the scope of the disclosure. In other embodiments, other data structures may be used to input the source indication. Other data structures are, for example, bundles.

For example, in the case where the signals transmitted through the circuit interface include the field segments F4, F2, and F3 at the same time, the designer can input the following code to access the field segments F4, F2, and F3 in fig. 2.

S1.F4// Access Domain segment F4, corresponding HDL semantics are u [7:0]

S1.F2// Access Domain segment F2, corresponding HDL semantics are u [11:8]

S1.F3// Access Domain segment F3, corresponding HDL semantics are u [15:12]

Wherein S1 represents a bundle. In this embodiment, s1.f4, s1.f2, or s1.f3 may be some examples of the first source indication.

In one embodiment, the data structure of the bundle may be set by defining S1. The complex is a data structure with a data hierarchy, and the bundle can be provided with a plurality of different data elements, wherein the data elements share the same memory, and the occupied size of the memory is the total memory occupied by the members. The data members within the complex may also be accessed by a.number such as S1.A/S1.B/S1.C, where a, b, or c respectively represent different domain segment names.

For the case where the bundle includes F4, F2, and F3, in one embodiment, the following code may be given in the source language environment to define or construct the bundle S1.

Wherein F4, F2 or F3 is the second source element within the bundle, which corresponds to the respective domain segment.

In a high-level language environment such as the source language, the API may automatically define a signal having a bit width that is the sum of the bit widths of the members, based on the definition of S1, as described below.

Wire S1[15:0]// defines a signal of 16-bit width size

It will be appreciated that in the case where the bundle includes F4, F2 and F3, the bit widths of F4, F2 and F3 are 8 bits, 4 bits and 4 bits, respectively. Thus, the bit width of bundle S1 may be defined by the API as the sum of the bit widths of F4, F2, and F3, i.e., 16 bits. The above scenario is only an example and does not limit the scope of the present disclosure. In a high-level language such as Chisel or spindle, the meaning of bundles is similar to a structure in a programming language (struct) that can bundle different domain segments together as one data stream while being transmitted via different bits of a circuit interface. In contrast, the complex does not require different domain segments to be transmitted simultaneously via different bits of the circuit interface. For example, the first domain segment and the second domain segment in the complex may be transmitted sequentially via the same bits of the circuit interface.

In one embodiment, the bundle S1 may be defined by the user by means of an API. In other embodiments, the circuit design software may also provide default complex definitions for use by the user, which is not limiting of the present disclosure. Although examples of designer input source indications in a source language environment are shown here as examples of bundles, this is merely illustrative and not limiting of the scope of the disclosure. For example, in other embodiments, the complex and bundle may nest into one another as a new data structure to increase ease of use for the designer. For example, for the cases S0 and S1 shown in FIG. 2, there may be the following definitions in a source language environment such as Chisel.

The above illustrates the case where bundles are nested within a complex, which is merely illustrative and not limiting on the scope of the present disclosure. In other embodiments, the complex may be nested within the bundle. For example, for the case of S2, a complex of F6A and F6B may be defined and nested in bundle S2. It will be appreciated that the above-described complexes, bundles, and nesting of the two may be defined by a designer using an API, or default structures may be provided by circuit design software, which is not limited by this disclosure.

When a designer designs using a first source indication in a source language, the individual domain segments may be represented, for example, using the following expressions.

u.SC0.F0＝＝＝>u[3:0]

u.SC0.F1＝＝＝>u[7:4]

u.SC0.F2＝＝＝>u[11:8]

u.SC0.F3＝＝＝>u[15:12]

u.SC1.F4＝＝＝>u[7:0]

u.SC1.F2＝＝＝>u[11:8]

u.SC1.F3＝＝＝>u[15:12]

In one embodiment, the method 300 may further include modifying the complex by adding another source element to the complex, the bit width corresponding to the complex being the maximum of at least one bit width corresponding to each first source element in the modified complex, the first source indication being associated with the modified complex. In one embodiment, the method 300 further comprises: the bundle is modified by adding another source element to the complex, the bit width corresponding to the bundle being the sum of the second source elements in the modified bundle, the first source indication being associated with the modified bundle.

By adding new elements to the complex or bundle, when the newly added scene is subsequently added, the data structure of the newly added scene is only needed to be added to the complex or bundle, and the scheme can automatically calculate the maximum bit width in the compiling stage without recalculating all scenes and refreshing documents. In this regard, the implementation is better backward compatibility than conventional schemes, which significantly reduces the cognitive burden on the designer and improves programming efficiency, as the designer does not need to know the condition of the individual domain segments of the circuit interface at any time.

At 304, the electronic device converts the first source indication into a first intermediate representation. The intermediate representation is a general description in the field of compilation, is an intermediate representation for facilitating the compiler to make a compilation optimization, is used for converting a source language and a final target language, and can be optimized and transformed on top of the intermediate representation. In the case of adding a complex definition in the source language environment, intermediate representations corresponding to the complex may be added to the circuit design software to facilitate conversion from the source language to the target language, such as from Chisel to VHDL or Verilog. Specifically, in one embodiment, a first intermediate representation of the complex may be defined that may carry the variable names of the complex variables themselves, as well as the variable names and corresponding bit widths of all elements thereof, such as:

DefineUnion(u,{F0:4bit,F4:8bit,F5:4bit})

Where u is the name of the complex named by the designer, F0, F4 or F5 represents an element in the complex, i.e., each field segment. F0, F4 or F5 describe the respective bit widths. Furthermore, a first intermediate representation within the access complex may also be defined, such as: visitUnion (u, F0), and the like.

At 306, a first target indication in a target language is determined based on the first intermediate representation. The first target indication represents a range of bits of the first portion of data in a data set transmitted via the circuit interface. In one embodiment, determining the first target indication in the target language based on the first intermediate representation comprises: converting the first intermediate representation into an intermediate representation of the target language; and converting the intermediate representation of the target language into a first target indication. For example, the electronic device automatically counts the bit widths of all members of DefineUnion above to determine the maximum bit width w_max of u. The electronic device further converts DefineUnion into a generic verilog signal with bit width DefineUnion (u, { F0:4bit, F4:8bit, F5:4bit }) = = = = > DEFINESIGNAL (u, 8 bit). In addition, the electronic device also automatically calculates and converts VisitUnion signals of HDL semantics accessing the Union element semantics corresponding hardware to intercept bit semantics:

VisitUnion(u,F0)＝>u[w_max:w_max–w_F0+1]

VisitUnion(u,F4)＝>u[w_max:w_max–w_F4+1]

VisitUnion(u,F5)＝>u[w_max:w_max–w_F5+1]

Wherein w_f0, w_f4, w_f5 are the bit widths of F0, F4, F5, respectively. Although a specific bit width intercept is illustrated herein, this is merely illustrative and is not limiting of the scope of the present disclosure. Other bit width truncation may be used, such as [ w_F0:0], [ w_F4:0], or [ w_F5:0].

It follows that the electronic device may automatically calculate the bit widths of all elements of the intermediate representation of the complex, and determine a maximum bit width based on the bit widths of all elements, and determine the maximum bit width as the bit width of the complex. The method further includes converting the intermediate representation of the complex to a signal with bit width in a target language such as HDL. The method further includes automatically calculating and federating a range of signal interception bits for a target language, such as HDL, corresponding to each element in the access intermediate representation.

After that, the method 300 may convert the intermediate representation of the target language into a first target indication. In particular, intermediate representations such as Verilog or VHDL may be converted to specific HDL code. The mapping of the intermediate representation of the target language to the specific target language code may be directly implemented using conventional mapping rules, and will not be described in detail herein.

Although illustrated herein as a complex example, this is merely illustrative and is not intended to limit the scope of the present disclosure. It will be appreciated that there may be intermediate representations of other data structures, intermediate representations of the target language, and conversions from the intermediate representations of the target language to the target language code. In one embodiment, for example, an intermediate representation of the bundle may be constructed; and constructing a second access intermediate representation for accessing the element within the bundle. In one embodiment, the method further comprises: determining the position width of the beam body based on the beam body; and determining bit ranges corresponding to the elements within the bundle based on the bit widths of the bundle and the second access intermediate representation. By building and accessing the intermediate representation of the bundle, the electronic device can automatically map the domain segments of the high-level language input by the designer through the API to the individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy. Specifically, the bit widths of all elements of the intermediate representation of the bundle are automatically calculated, and the bit width of the bundle is determined based on the sum of the bit widths of all elements. The method further includes converting the intermediate representation of the bundle to a signal with bit width in a target language such as HDL. The method further includes automatically calculating and bundles accessing a range of signal interception bits for a target language, such as HDL, corresponding to each element in the intermediate representation.

In one embodiment, the method 300 further includes implementing a circuit design based on the first target indication. For example, the connection of the circuit interface to the corresponding circuit component, the specific configuration of the circuit interface, etc. are determined based on the transmission of the individual field segments of the signal at the circuit interface.

In this embodiment, the designer accesses the data transferred by the circuit interface through a source indication of a source language representation, such as Chisel or spindle, which can be automatically converted to a target indication of a target language representation, such as Verilog or VHDL. In this way, the designer does not need to know the bit range corresponding to each domain segment in the signal transmitted through the circuit interface, but only needs to know the name of the domain segment to access the data corresponding to the domain segment. Therefore, compared with the situation that in the conventional scheme, a designer needs to know each bit range of each domain segment in the hardware description language in advance to correctly access the data corresponding to the domain segment, the scheme according to the present disclosure can reduce the cognitive burden of the designer and improve the design efficiency.

Fig. 4 shows a schematic flow diagram of a method 400 for designing a circuit according to further embodiments of the present disclosure. Method 400 is similar to method 300 and therefore the same or similar features are not described in detail herein, with particular reference to the description of method 300 of fig. 3. The method 400 differs from the method 300 in that: at 402, a complex and/or bundle is constructed. In some embodiments, a nest of the complex and bundle may also be constructed, such as where the bundle is nested in the complex, or where the complex is nested in the bundle. 402 may be implemented prior to 302, for example, a designer may define or build a conjunctive and/or bundle using an API. At 404, the method 400 includes building and accessing intermediate representations of the federation and/or bundles to facilitate automatic conversion from a high-level source language to an underlying target language.

In other embodiments, the complex and/or bundle and corresponding intermediate representations may be provided with default terms by the circuit design software without requiring prior user construction. The present disclosure is not limited herein.

Fig. 5 shows a schematic block diagram of an example device 500 that may be used to implement embodiments of the present disclosure. As shown, the device 500 includes a computing unit 501 that may perform various suitable actions and processes in accordance with computer program instructions stored in Random Access Memory (RAM) and/or Read Only Memory (ROM) 502 or loaded from a storage unit 508 into RAM 503 and/or ROM 502. In RAM 503 and/or ROM 502, various programs and data required for the operation of device 500 may also be stored. The computing unit 501 and the RAM 503 and/or the ROM 502 are connected to each other by a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.

Various components in the device 500 are connected to the I/O interface 505, including: an input unit 506 such as a keyboard, a mouse, etc.; an output unit 507 such as various types of displays, speakers, and the like; a storage unit 508 such as a magnetic disk, an optical disk, or the like; and a communication unit 509 such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The computing unit 501 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 501 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as method 400. For example, in some embodiments, the method 300 or 400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 500 via RAM and/or ROM and/or the communication unit 509. One or more of the steps of the methods 300 or 400 described above may be performed when a computer program is loaded into RAM and/or ROM and executed by the computing unit 501. Alternatively, in other embodiments, computing unit 501 may be configured to perform method 300 or 400 by any other suitable means (e.g., by means of firmware).

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Fig. 6 illustrates a block diagram of an example electronic device 600 for designing a circuit, according to an embodiment of the disclosure. The electronic device 600 may include a plurality of modules for performing corresponding steps in the methods 300 or 400 as discussed in fig. 3 or 4. As shown in fig. 6, the electronic device 600 includes a receiving unit 602, a converting unit 604, and a determining unit 606. The receiving unit 602 is configured to receive a first source indication for a first field segment of a set of field segments represented by a source language, the set of field segments representing a set of data transmitted via a circuit interface, the first field segment representing a first portion of data in the set of data. The conversion unit 604 is configured to convert the first source indication into a first intermediate representation. The determining unit 606 is configured to determine, based on the first intermediate representation, a first target indication in a target language, the first target indication representing a bit range of the first portion of data in the data set transmitted via the circuit interface. The designer accesses the data communicated by the circuit interface through a source indication of the source language expression, which can be automatically converted to a target indication of the target language expression, such as HDL. In this way, the designer does not need to know the bit range corresponding to each domain segment in the signal transmitted through the circuit interface, but only needs to know the name of the domain segment to access the data corresponding to the domain segment. Therefore, compared with the situation that in the conventional scheme, a designer needs to know each bit range of each domain segment in the hardware description language in advance to correctly access the data corresponding to the domain segment, the scheme according to the present disclosure can reduce the cognitive burden of the designer and improve the design efficiency.

In one embodiment, the source language may be a high-level language such as Chisel or SpinaHDL and the target language may be an underlying language such as Verilog or VHDL. The source language is a high-level language that is more designer-friendly than the target language, which is more underlying design. Since the source language is a high-level language, it is easier for the designer to understand and is also less prone to error. In this regard, coding and maintenance efficiency may be greatly improved.

In one embodiment, an API may be built to enable user programming of the circuit. That is, the API may be used to receive user input to the circuit, for example, a designer input of a first source indication of a first domain segment in a set of domain segments represented by a source language.

In one embodiment, the conversion unit 604 is further configured to: converting the first intermediate representation into an intermediate representation of the target language; and converting the intermediate representation of the target language into a first target indication. Further, in one embodiment, the method further comprises mapping intermediate representations of the target languages to target code of the target languages, wherein each intermediate representation of the target language is mapped to target code of the target language, e.g., rules of HDL grammar, which can be directly implemented using intermediate representation mapping rules of conventional HDLs. By compiling the code of the high-level language expression, and by converting the intermediate representation after compiling the conversion into an intermediate representation of the low-level language expression such as HDL, the code written in the high-level language can be optimized to obtain the target code of the low-level language expression.

In one embodiment, the first intermediate representation includes an intermediate representation for defining a complex or bundle that carries the variable names of the complex or bundle variables themselves, as well as the variable names and corresponding bit widths of all elements in the complex or bundle. Further, the first intermediate representation may also include an intermediate representation defining elements in the access complex or bundle.

In one embodiment, the electronic device further comprises: a building unit configured to build a complex comprising at least one first source element represented by a source language corresponding to each domain segment in the set of domain segments, the bit width corresponding to the complex being a maximum of the at least one bit width corresponding to the at least one first source element, the first source indication being associated with the complex. In one possible implementation, constructing the complex may be performed prior to the designer entering the first source indication. Alternatively, the API may also provide a default association without requiring the user to build the association. The complex is a data structure with a data hierarchy, and can be provided with a plurality of different data elements, wherein the data elements share the same memory, and the occupied size of the memory is the memory occupied by the largest data in the members.

In one embodiment, the building unit is further configured to: a bundle is constructed, the bundle including at least one second source element represented by a source language corresponding to each of the set of domain segments, the bit width corresponding to the bundle being a sum of at least one bit width corresponding to the at least one second source element, the first source indication being associated with the bundle. In one possible implementation, the build beam may be prior to the designer entering the first source indication. Alternatively, the API may also provide a default bundle without requiring the user to build the bundle. In a high-level language such as Chisel or spindle, the meaning of bundles is similar to a structure in a programming language (struct) that can bundle different domain segments together as one data stream while being transmitted via different bits of a circuit interface. In contrast, the complex does not require different domain segments to be transmitted simultaneously via different bits of the circuit interface. For example, the first domain segment and the second domain segment in the complex may be transmitted sequentially via the same bits of the circuit interface.

In one embodiment, the complex and bundle may nest with each other. In other words, in one possible implementation, the complex may be embedded in the bundle, and in another possible implementation, the bundle may be embedded in the complex. For example, in one embodiment, constructing the bundle includes constructing the bundle based on the association. In another possible implementation, constructing the association includes constructing the association based on the bundle. By nesting the complexes and bundles with one another, the flexibility of the designer in hardware programming can be significantly improved, and the programming efficiency can be significantly improved.

In an embodiment, the electronic device further comprises a modification unit. The modification unit is configured to modify the complex by adding another source element to the complex, the bit width corresponding to the complex being the maximum of the at least one bit width corresponding to each first source element in the modified complex, the first source indication being associated with the modified complex. In an embodiment, the modification unit is further configured to modify the bundle by adding another source element to the bundle, the bit width corresponding to the bundle being a sum of the second source elements in the modified bundle, the first source indication being associated with the modified bundle. By adding new elements to the complex or bundle, when the newly added scene is subsequently added, the data structure of the newly added scene is only needed to be added to the complex or bundle, and the scheme can automatically calculate the maximum bit width in the compiling stage without recalculating all scenes and refreshing documents. In this regard, the implementation is better backward compatibility than conventional schemes, which significantly reduces the cognitive burden on the designer and improves programming efficiency, as the designer does not need to know the condition of the individual domain segments of the circuit interface at any time.

In an embodiment, the building unit is further configured to build an intermediate representation of the complex; and constructing a first access intermediary representation for accessing the elements within the complex. In one embodiment, the determining unit 606 is further configured to determine a bit width of the complex based on the complex; and determining bit ranges corresponding to the elements within the complex based on the bit widths of the complex and the first access intermediate representation. By building and accessing the intermediate representation of the complex, domain segments of the high-level language input by the designer through the API can be automatically mapped to individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy.

In one embodiment, the electronic device further comprises a computing unit. The computing unit is configured to: the bit widths of all elements of the intermediate representation of the complex are automatically calculated, and a maximum bit width is determined based on the bit widths of all elements, and the maximum bit width is determined to be the bit width of the complex. The conversion unit 604 is further configured to convert the intermediate representation of the complex into a signal with bit width in a target language such as HDL. The computing unit is further configured to automatically compute and associate a range of signal interception bits of a target language, such as HDL, corresponding to each element in the access intermediate representation of the complex.

In an embodiment, the construction unit is further configured to construct the intermediate representation of the bundle; and constructing a second access intermediate representation for accessing the element within the bundle. In one embodiment, the determining unit 606 is further configured to: determining the position width of the beam body based on the beam body; and determining bit ranges corresponding to the elements within the bundle based on the bit widths of the bundle and the second access intermediate representation. By constructing and accessing the intermediate representation of the bundle, domain segments of the high-level language input by the designer through the API can be automatically mapped to individual domain segments of the underlying language description, such as HDL. This can significantly reduce the cognitive burden on the designer and improve programming efficiency and accuracy.

In one embodiment, the computing unit is configured to: the bit widths of all elements of the intermediate representation of the bundle are automatically calculated and the bit width of the bundle is determined based on the sum of the bit widths of all elements. The method further includes converting the intermediate representation of the bundle to a signal with bit width in a target language such as HDL. The method further includes automatically calculating and bundles accessing a range of signal interception bits for a target language, such as HDL, corresponding to each element in the intermediate representation.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims

A method for designing a circuit, comprising:

Receiving a first source indication for a first field segment in a set of field segments represented by a source language, the set of field segments being used to represent a set of data transmitted via a circuit interface, the first field segment being used to represent a first portion of data in the set of data;

converting the first source indication into a first intermediate representation; and

Based on the first intermediate representation, a first target indication in a target language is determined, the first target indication representing a range of bits of the first portion of data in the data set transmitted via the circuit interface.
The method of claim 1, wherein determining a first target indication in a target language based on the first intermediate representation comprises:

Converting the first intermediate representation into an intermediate representation of the target language; and

An intermediate representation of the target language is converted into the first target indication.
The method of claim 1 or 2, further comprising:

Constructing a complex comprising at least one first source element represented by the source language corresponding to each domain segment in the set of domain segments, the bit width corresponding to the complex being the maximum of the at least one bit width corresponding to the at least one first source element, the first source indication being associated with the complex.
A method according to any one of claims 1-3, further comprising:

A bundle is constructed, the bundle comprising at least one second source element represented by the source language corresponding to each domain segment in the set of domain segments, the bundle corresponding bit-width being a sum of at least one bit-width corresponding to the at least one second source element, the first source indication being associated with the bundle.
The method of claim 4, wherein constructing the bundle comprises constructing the bundle based on the association.
The method of claim 4, wherein constructing the complex comprises constructing the complex based on the bundle.
A method according to claim 3, further comprising:

modifying the complex by adding another source element to the complex, the bit width corresponding to the complex being the maximum of at least one bit width corresponding to each first source element in the modified complex, the first source indication being associated with the modified complex.
The method of claim 4, further comprising:

The bundle is modified by adding another source element to the complex, the bit width corresponding to the bundle being the sum of the second source elements in the modified bundle, the first source indication being associated with the modified bundle.
The method of claim 3 or 7, further comprising:

Constructing an intermediate representation of the complex; and

A first access intermediary representation is constructed for accessing elements within the complex.
The method of claim 9, further comprising:

Determining a bit width of the complex based on the complex; and

Based on the bit width of the complex and the first access intermediate representation, bit ranges corresponding to the elements within the complex are determined.
The method of claim 4 or 8, further comprising:

Constructing an intermediate representation of the bundle; and

A second access intermediate representation is constructed for accessing the elements within the bundle.
The method of claim 11, further comprising:

determining a bit width of the beam body based on the beam body; and

And determining bit ranges corresponding to elements in the bundle based on the bit width of the bundle and the second access intermediate representation.
An electronic device for designing a circuit, comprising:

A receiving unit configured to receive a first source indication for a first field segment of a set of field segments represented by a source language, the set of field segments representing a set of data transmitted via a circuit interface, the first field segment representing a first portion of data in the set of data;

A conversion unit configured to convert the first source indication into a first intermediate representation; and

A determining unit configured to determine, based on the first intermediate representation, a first target indication in a target language, the first target indication representing a range of bits of the first portion of data in the data set transmitted via the circuit interface.
The electronic device of claim 13, wherein the conversion unit is further configured to:

Converting the first intermediate representation into an intermediate representation of the target language; and

An intermediate representation of the target language is converted into the first target indication.
The electronic device of claim 13 or 14, further comprising:

A building unit configured to build a complex comprising at least one first source element represented by the source language corresponding to each domain segment in the set of domain segments, the bit width corresponding to the complex being a maximum of at least one bit width corresponding to the at least one first source element, the first source indication being associated with the complex.
The electronic device of any of claims 13-15, wherein the build unit is further configured to:

A bundle is constructed, the bundle comprising at least one second source element represented by the source language corresponding to each domain segment in the set of domain segments, the bundle corresponding bit-width being a sum of at least one bit-width corresponding to the at least one second source element, the first source indication being associated with the bundle.
The electronic device of claim 16, wherein the build unit is further configured to: the bundle is constructed based on the association.
An electronic device, comprising:

At least one processor;

At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions when executed by the at least one processor cause the apparatus to perform the method of any one of claims 1 to 12.
A computer readable storage medium storing a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 12.
A computer program product comprising computer executable instructions which, when executed by a processor, cause a computer to implement the method of any one of claims 1 to 12.