CN118157824A

CN118157824A - HARQ-based data cache management method, device and storage medium

Info

Publication number: CN118157824A
Application number: CN202410369279.4A
Authority: CN
Inventors: 刘博�
Original assignee: Shanghai Xingsi Semiconductor Co ltd
Current assignee: Shanghai Xingsi Semiconductor Co ltd
Priority date: 2024-03-28
Filing date: 2024-03-28
Publication date: 2024-06-07

Abstract

The embodiment of the application provides a data cache management method, equipment and a storage medium based on HARQ, wherein the method comprises the following steps: under the condition that first data corresponding to retransmission data needed by the HARQ process is stored in an off-chip memory, the first data is read from the off-chip memory and written into the on-chip memory; the first data is read from the on-chip memory to be combined with the retransmission data to obtain second data for decoding, wherein the start time of reading the first data from the on-chip memory is later than the start time of writing the first data into the on-chip memory. The application solves the problem of high data reading delay in HARQ retransmission in the related technology, thereby achieving the effect of reducing HARQ merging delay.

Description

HARQ-based data cache management method, device and storage medium

Technical Field

The embodiment of the application relates to the field of computers, in particular to a data cache management method, equipment and storage medium based on HARQ.

Background

In the field of data retransmission, a transmission strategy of error correction before retransmission is generally adopted, and when data retransmission is carried out, retransmission data and historical data are often required to be combined first, then the combined data are decoded, and previous data are required to be stored through an off-chip memory and an on-chip memory. However, due to the characteristics of the off-chip memory, the reading effect of the history data read from the off-chip memory is not good, and how to store more data to be combined through the on-chip memory, so as to improve the efficiency of the HARQ combining, and no effective solution has been proposed in the related art.

Disclosure of Invention

The embodiment of the application provides a data cache management method, equipment and a storage medium based on HARQ (hybrid automatic repeat request), which at least solve the problem of lower efficiency of HARQ combination in the related art.

According to an embodiment of the present application, there is provided a buffer management method for HARQ combining, including: under the condition that first data corresponding to retransmission data needed by an HARQ process are stored in an off-chip memory, reading the first data from the off-chip memory, and writing the first data into an on-chip memory; and reading the first data from the on-chip memory to be combined with retransmission data to obtain second data for decoding, wherein the starting time of reading the first data from the on-chip memory is later than the starting time of writing the first data into the on-chip memory.

According to another embodiment of the present application, there is provided a data buffer management apparatus based on HARQ, including: the device comprises a read-write controller and an on-chip memory, wherein the read-write controller is used for reading first data corresponding to retransmission data required by an HARQ process from the off-chip memory and writing the first data into the on-chip memory under the condition that the first data is stored in the off-chip memory, and reading the first data from the on-chip memory to be combined with the retransmission data so as to obtain second data for decoding, and the starting time of reading the first data from the on-chip memory is later than the starting time of writing the first data into the on-chip memory.

According to another embodiment of the present application, there is provided a data buffer management apparatus based on HARQ, including: the first reading module is used for reading the first data from the off-chip memory and writing the first data into the on-chip memory under the condition that the first data corresponding to the retransmission data needed by the HARQ process is stored in the off-chip memory; and the second reading module is used for reading the first data from the on-chip memory to be combined with retransmission data to obtain second data for decoding, wherein the starting time of reading the first data from the on-chip memory is later than the starting time of writing the first data into the on-chip memory.

According to another embodiment of the present application, there is provided an on-chip resource including the data cache management apparatus described above.

According to a further embodiment of the application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to a further embodiment of the application, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

According to the application, the first data stored in the off-chip memory is prestored in the on-chip memory before the HARQ combiner works, and the first data is directly read from the on-chip memory when the HARQ combiner starts to work so as to be combined with the retransmission data, so that the second data for decoding is obtained. The problem of low HARQ combining efficiency in the related art is solved.

Drawings

Fig. 1 is a block diagram of a hardware structure of a mobile terminal according to a data buffer management method based on HARQ according to an embodiment of the present application;

fig. 2 is a flowchart of a data buffer management method based on HARQ according to an embodiment of the present application;

fig. 3 is a block diagram of a structure of a HARQ-based data buffer management apparatus according to an embodiment of the present application;

Fig. 4 is a block diagram of a data buffer management unit of HARQ according to a specific embodiment of the present application;

FIG. 5 is a schematic diagram of the structure of an SRAM according to an embodiment of the present application;

fig. 6 is a data buffer management apparatus based on HARQ according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of a mobile terminal according to an embodiment of the present application. As shown in fig. 1, a mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.

The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to the HARQ-based data buffer management method in the embodiment of the present application, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

In this embodiment, a data buffer management method based on HARQ is provided, and fig. 2 is a flowchart of a data buffer management method based on HARQ according to an embodiment of the present application, as shown in fig. 2, where the flowchart includes the following steps:

Step S202, when first data corresponding to retransmission data needed by an HARQ process is stored in an off-chip memory, the first data is read from the off-chip memory and written into an on-chip memory;

Step S204, the first data is read from the on-chip memory to be combined with the retransmission data to obtain the second data for decoding, wherein the start time of reading the first data from the on-chip memory is later than the start time of writing the first data into the on-chip memory.

The main execution body of the above steps may be a processor having data processing and memory interaction capability with hardware, or may be other processing devices or processing units having similar processing capability, for example, but not limited to, a read-write controller in HARQ. According to the application, the first data stored in the off-chip memory is prestored in the on-chip memory before the HARQ combiner works, and the first data is directly read from the on-chip memory when the HARQ combiner starts to work so as to be combined with the retransmission data, so that the second data for decoding is obtained. The problem of low HARQ combining efficiency in the related art is solved, and the effect of improving the HARQ retransmission efficiency is achieved.

Alternatively, the on-chip memory comprises a static random access memory SRAM and the off-chip memory comprises a double rate synchronous dynamic random access memory DDR.

Optionally, the first data includes, but is not limited to HARQ process data. And combining the first data with the retransmission data, and then sending the combined first data and the retransmission data to a decoder for decoding again.

In an exemplary embodiment, after the first data is read from the on-chip memory to be combined with the retransmission data to obtain the second data for decoding, the method further includes: writing the second data into the off-chip memory if the data amount of the second data is greater than the free memory amount in the on-chip memory; and writing the second data into the on-chip memory in the case that the data amount of the second data is less than or equal to the free memory amount in the on-chip memory.

Alternatively, the second data may need to be written into off-chip memory because the amount of free memory in on-chip memory is insufficient to accommodate the second data. Off-chip memory typically has a larger storage capacity that can meet the storage requirements of large amounts of data. Thus, when the free memory in the on-chip memory is insufficient, data can be written to the off-chip memory to ensure that the data is not lost and can be accessed and processed as needed. If the data quantity of the second data is not larger than the free storage quantity in the on-chip memory, the second data is written into the on-chip memory, so that the reading time can be effectively reduced, and the retransmission efficiency is improved.

In an exemplary embodiment, the above method further comprises: and dynamically controlling the read-write priority of the bus through the cache waterline of the on-chip memory, wherein the priority of the bus is reduced under the condition that the first data is determined not to be read from the off-chip memory according to the cache waterline, and the bus is used for connecting the on-chip memory and the off-chip memory.

Optionally, the cache waterline is a series of steps for controlling and managing internal cache operations. These steps include reading data from main memory, writing data to cache, reading data from cache, and the like. The main purpose of the cache pipeline is to increase the speed and efficiency of data access. By performing operations such as prefetching, prewritting, and data transfer internally, the cache waterline can reduce the number of accesses to main memory, thereby reducing memory access latency and improving overall performance.

Optionally, the bus includes, but is not limited to, an AXI read bus. There is a relationship between the priority of the cache pipeline and the AXI read bus. For example, when the cache pipeline of an SRAM is set, it determines when the cache controller loads data into the SRAM. If the cache waterline is set higher, the cache controller may load data into the cache more frequently in order to increase the speed of reading the data. The priority of the AXI bus determines which read requests are prioritized when multiple read requests arrive at the same time. If the priority of a read request is higher, it will be processed faster, while other read requests may be delayed. Therefore, the relationship between the cache line of the SRAM and the priority of the AXI bus is that they both affect the read speed and priority of the data. In practical system design, these two factors need to be considered together in order to reasonably adjust the cache waterline and the priority of the read request to achieve optimal data processing performance.

In the pre-reading and data migration process, the priority of the AXI bus reading and writing can be adjusted according to the busy degree of the AXI bus and the SRAM cache line. When the AXI bus is busy, read and write priorities to the bus can be reduced to reduce contention and congestion to the bus. Meanwhile, the read-write priority of the SRAM cache can be improved, so that the read-write speed of data is increased, and the dependence on an AXI bus is reduced. In addition, in the data migration process, the read-write priority of the AXI bus and the SRAM cache can be dynamically adjusted according to the access mode and the access frequency of the data, so that more efficient data access and migration are realized. By reasonably adjusting the read-write priority, the efficiency and performance of data migration can be effectively improved.

Alternatively, the cache pipeline of the SRAM may be a multi-stage pipeline design, specifically including: and under the condition that the SRAM memory occupation reaches a target waterline, adjusting the priority of the action of reading the data stored in the DDR by the read-write controller in the AXI bus to be the target priority. The target waterline is used for representing the storage occupation condition of the SRAM, and includes, but is not limited to, a first waterline, a second waterline, a third waterline, a fourth waterline, and the like, where the waterline is used for representing different storage occupation thresholds, and corresponds to different preset priorities, for example, the first waterline may be 20%, or 50%, or 70%, or the like. Through the embodiment, the read-write controller can flexibly adjust the priority of the transfer operation when transferring the first data from the DDR to the SRAM, so that the first data is read in advance on the premise of not bringing excessive pressure to the AXI bus, and the HARQ merging efficiency is improved as a whole.

In one exemplary embodiment, the on-chip memory includes N sub-blocks, where N is a natural number greater than 1, the free amount of memory in the on-chip memory is determined according to the steps of: obtaining a bit map indicating whether each sub-block is free or not by scanning an on-chip memory; and determining the free storage amount in the on-chip memory according to the bit map.

Optionally, each sub-block contains a number of memory cells and associated control circuitry. For example, dividing the SRAM into N sub-blocks may improve the parallelism and access speed of the memory to meet the requirements of different applications. Each sub-block can independently perform read-write operation, so that the overall performance and reliability of the memory are improved.

Alternatively, the bit map is represented by 0/1, e.g., 0 for idle and 1 for occupied, one bit for each sub-block.

In an exemplary embodiment, the above method further comprises: and releasing the data in the target sub-block, wherein N sub-blocks comprise the target sub-block, and the time when the data in the target sub-block is not read is larger than a preset threshold value.

Alternatively, freeing a target sub-block of the N sub-blocks may free up space for other processes or applications. The method is beneficial to ensuring that resources are effectively managed and utilized, and simultaneously avoiding the problem of system performance degradation caused by long-time occupation of resources. Thus, for data that is not read for a long period of time, the SRAM will periodically release resources to ensure stability and efficiency of the system.

In an exemplary embodiment, the above method further comprises: and writing data which are not needed by the HARQ process in the on-chip memory into the off-chip memory.

There is also provided in this embodiment a data buffer management device based on HARQ, as shown in fig. 3, including: the second read-write controller is used for reading the first data from the off-chip memory and writing the first data into the on-chip memory under the condition that the first data corresponding to the retransmission data needed by the HARQ process is stored in the off-chip memory, and reading the first data from the on-chip memory to be combined with the retransmission data so as to obtain second data for decoding, wherein the starting time of reading the first data from the on-chip memory is later than the starting time of writing the first data into the on-chip memory. Optionally, the read-write controller includes a read-write controller 1 and a read-write controller 2.

By the device, the first data stored in the off-chip memory is prestored in the on-chip memory before the HARQ combiner works, and the first data is directly read from the on-chip memory when the HARQ combiner starts to work so as to be combined with the retransmission data, so that second data for decoding is obtained. The problem of low HARQ combining efficiency in the related art is solved.

In one exemplary embodiment, the on-chip memory comprises static random access memory, SRAM, and the off-chip memory comprises double rate synchronous dynamic random access memory, DDR; and/or the device further comprises a first read-write controller for writing the second data into the off-chip memory if the data amount of the second data is greater than the free memory amount in the on-chip memory; and writing the second data into the on-chip memory if the data amount of the second data is less than or equal to the free memory amount in the on-chip memory.

Optionally, the device further includes an AXI bus, where a read-write priority of the AXI bus is dynamically controlled by a cache line of the SRAM, where the cache line of the SRAM and an amount of free memory of the SRAM are required to meet a requirement of the first data on the memory space, and in a case that the first data is not read from the off-chip memory, the priority of the AXI read bus is reduced by the cache line of the SRAM, where the AXI bus is used to connect the SRAM and the DDR.

Optionally, the SRAM cache pipeline is a series of steps for controlling and managing internal cache operations. These steps include reading data from main memory, writing data to cache, reading data from cache, and the like. The main purpose of the cache pipeline is to increase the speed and efficiency of data access. By performing operations such as prefetching, prewritting, and data transfer internally, the cache waterline can reduce the number of accesses to main memory, thereby reducing memory access latency and improving overall performance.

Optionally, there is a relationship between the cache pipeline of the SRAM and the priority of the AXI read bus. For example, when the SRAM's cache pipeline is set, it determines when the cache controller loads data from the SRAM into the cache. If the cache waterline is set higher, the cache controller may load data into the cache more frequently in order to increase the speed of reading the data. The priority of the AXI bus determines which read requests are prioritized when multiple read requests arrive at the same time. If the priority of a read request is higher, it will be processed faster, while other read requests may be delayed. Therefore, the relationship between the cache line of the SRAM and the priority of the AXI bus is that they both affect the read speed and priority of the data. In practical system design, these two factors need to be considered together in order to reasonably adjust the cache waterline and the priority of the read request to achieve optimal data processing performance.

In one exemplary embodiment, the SRAM includes N sub-blocks, and whether the amount of free memory is included in each sub-block is indicated by a preset instruction, where N is a natural number greater than 1.

Optionally, each sub-block contains a number of memory cells and associated control circuitry. Dividing the SRAM into N sub-blocks can improve the parallelism and access speed of the memory to meet the requirements of different applications. Each sub-block can independently perform read-write operation, so that the overall performance and reliability of the memory are improved.

Alternatively, for example, the preset instruction may be: sub-block 1: including free storage; sub-block 2: excluding free memory; sub-block 3: including free storage; sub-block 4: excluding free memory.

The embodiment also provides an on-chip resource, which comprises the data cache management device in the embodiment.

The application is illustrated below with reference to specific examples:

In the scenario of a downlink hybrid automatic repeat request (Hybrid Automatic Repeat reQuest, abbreviated as NR) of a New air interface (New Radio) terminal, the buffering of soft bits includes two modes, namely SRAM buffering and DDR buffering. When the soft bits are cached in the SRAM, the area of the chip is increased; when the soft bits are buffered in DDR, DDR access latency is caused by the busyness of the AXI bus and the like.

Aiming at the problem of DDR access delay during HARQ merging, the embodiment provides a low-delay SRAM combined DDR cache management scheme, which can reduce the problem of DDR access delay while reducing chip overhead. The specific process is as follows:

Setting an SRAM buffer and a DDR buffer, wherein the aim is to enable the SRAM buffer to store soft bit data (corresponding to the first data in the above) needed by the current HARQ process, and enable the DDR buffer to store soft bit data (corresponding to the second data in the above) not needed by the current HARQ process; so that the read-write request of the current HARQ process occurs as much as possible inside the chip, thereby reducing the read-write delay problem. The method for improving the utilization rate of the on-chip resources can be realized through two modes of 'pre-reading' and 'early release'.

Wherein, "read ahead" includes: when the SRAM has spare resources, but soft bit data to be combined is at the DDR, the DDR data needs to be pre-read, and the data is written into the SRAM before being combined. The AXI bus priority when reading DDR can be adjusted according to the cache water limit of the current SRAM. "early release" includes: when the old data to be combined for retransmitting the data is not in the SRAM, the SRAM buffer can be moved out to DDR for storage, and the refreshed on-chip resources are used for pre-reading CB data of the current HARQ process; for data that takes up a long time unread in SRAM, resources are also released at regular time.

Alternatively, the unit structure of the SRAM combined with the DDR cache management scheme is composed of two read/write controllers and one SRAM as shown in fig. 4. The read-write controller 1 is used for writing SRAM or DDR to the combined data and writing DDR operation of non-current HARQ process data in the SRAM; the read-write controller 2 is used for reading SRAM and DDR, and pre-reading emergency data in DDR; the SRAM is connected with the read-write controller 1 and the read-write controller 2, and plays a role in buffering between the HARQ combiner and the DDR. The specific implementation steps are as follows:

S1, the output of the HARQ combiner firstly enters the read-write controller 1 to judge, if the SRAM has enough margin to write the soft bit data of the current CB, the soft bit data is directly written into the SRAM, otherwise, the soft bit data is written into the DDR. Waiting for the processing of the LDPC decoder, and if the decoding result is correct, releasing the corresponding CB resources in the SRAM; if the decoding is wrong, DDR moving of data can be carried out according to the current busy state of the AXI bus.

S2, when retransmission starts, judging whether the data of the corresponding HARQ process required by the current HARQ combiner is in DDR, if the data is in DDR and the SRAM has a margin, pre-reading the data can be carried out, the pre-reading data can be partially or completely moved into the SRAM before the HARQ combiner works, and when the HARQ combiner starts to work, the data can be rapidly input for the HARQ combiner. The pre-reading of data can also be carried out with priority adjustment according to the busy degree of the AXI bus.

Alternatively, as depicted in FIG. 5, the SRAM is divided into N sub-blocks, which are operated upon both when scanning for free resources and when freeing up resources. The SRAM is divided in a mode that address management is simpler, and whether each sub-block has cache resources or not can be represented by using a bitmap. Operations in sub-block units can greatly simplify address management logic. If the cache is not divided into sub-blocks, when the idle resources are scattered in the internal cache, the head address and idle length of each block of resources need to be recorded respectively, and the scattered operation can make the realization of the scanning logic more complex.

The embodiment uses two modes of pre-reading and dynamic release, and realizes a cache management scheme of cooperation of the SRAM and the DDR with low delay by using less chip resource. The utilization rate of chip resources is improved, and the access delay problem of DDR can be greatly reduced. Meanwhile, the data cached by the SRAM is more data required by the current HARQ process, so that the same low-delay effect can be achieved without arranging large SRAM resources in the chip. In addition, the subblock management can make the address control logic simpler and more convenient, and reduce the realization difficulty and area of the logic.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the above-mentioned methods of the various embodiments of the present application.

The embodiment also provides a data buffer management device based on HARQ, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 6 is a data buffer management apparatus based on HARQ according to an embodiment of the present application, as shown in fig. 6, the apparatus comprising:

A first reading module 62, configured to, when first data corresponding to retransmission data required by an HARQ process is stored in an off-chip memory, read the first data from the off-chip memory, and write the first data into the on-chip memory;

A second reading module 64, configured to read the first data from the on-chip memory to combine with the retransmission data to obtain second data for decoding, where a start time of reading the first data from the on-chip memory is later than a start time of writing the first data into the on-chip memory.

In an exemplary embodiment, the on-chip memory includes a static random access memory SRAM, and the off-chip memory includes a double rate synchronous dynamic random access memory DDR.

In an exemplary embodiment, the above apparatus further includes: a first writing module, configured to read the first data from the on-chip memory, combine the first data with retransmission data, and write the second data into the off-chip memory when a data size of the second data is greater than an idle memory size in the on-chip memory after obtaining the second data for decoding;

And the second writing module is used for writing the second data into the on-chip memory under the condition that the data volume of the second data is smaller than or equal to the free memory volume in the on-chip memory.

In an exemplary embodiment, the above apparatus further includes: and the control module is used for dynamically controlling the read-write priority of the bus through the cache waterline of the on-chip memory, wherein the idle storage capacity of the cache waterline is required to meet the requirement of the first data on the storage space, the priority of the bus is reduced under the condition that the first data is not read from the off-chip memory, and the bus is used for connecting the on-chip memory and the off-chip memory.

In an exemplary embodiment, the on-chip memory includes N sub-blocks, where N is a natural number greater than 1, and the apparatus determines the free memory in the on-chip memory according to the following steps: obtaining a bit map indicating whether each sub-block is free or not by scanning the on-chip memory; and determining the free storage amount in the on-chip memory according to the bit map.

In an exemplary embodiment, the above apparatus further includes: and the releasing module is used for releasing the data in the target sub-blocks, wherein the N sub-blocks comprise the target sub-blocks, and the time that the data in the target sub-blocks are not read is larger than a preset threshold value.

In an exemplary embodiment, the above apparatus further includes: and a third writing module, configured to write data in the on-chip memory, which is not needed by the HARQ process, into the off-chip memory.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; or the above modules may be located in different processors in any combination.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.

Claims

1. The data buffer management method based on HARQ is characterized by comprising the following steps:

Under the condition that first data corresponding to retransmission data needed by an HARQ process are stored in an off-chip memory, reading the first data from the off-chip memory, and writing the first data into an on-chip memory;

And reading the first data from the on-chip memory to be combined with retransmission data to obtain second data for decoding, wherein the starting time of reading the first data from the on-chip memory is later than the starting time of writing the first data into the on-chip memory.

2. The method of claim 1, wherein the on-chip memory comprises static random access memory, SRAM, and the off-chip memory comprises double rate synchronous dynamic random access memory, DDR.

3. The method of claim 1, wherein after reading the first data from the on-chip memory to combine with retransmission data to obtain second data for decoding, the method further comprises:

Writing the second data into the off-chip memory when the data amount of the second data is greater than the free memory amount in the on-chip memory;

and writing the second data into the on-chip memory under the condition that the data amount of the second data is smaller than or equal to the free storage amount in the on-chip memory.

4. The method according to claim 1, wherein the method further comprises:

And dynamically controlling the read-write priority of a bus through a cache waterline of the on-chip memory, wherein the priority of the bus is reduced under the condition that the first data is not read from the off-chip memory according to the cache waterline, and the bus is used for connecting the on-chip memory and the off-chip memory.

5. The method of claim 3, wherein the on-chip memory comprises N sub-blocks, wherein N is a natural number greater than 1, and wherein the amount of free memory in the on-chip memory is determined according to the steps of:

Obtaining a bit map indicating whether each sub-block is free or not by scanning the on-chip memory;

and determining the free storage amount in the on-chip memory according to the bit map.

6. The method of claim 5, wherein the method further comprises:

and releasing the data in the target sub-block, wherein N sub-blocks comprise the target sub-block, and the time when the data included in the target sub-block is not read is larger than a preset threshold value.

7. The method according to claim 1, wherein the method further comprises:

and writing data which is not needed by the HARQ process in the on-chip memory into the off-chip memory.

8. A HARQ-based data buffer management apparatus, comprising: a second read-write controller and an on-chip memory, wherein,

The second read-write controller is configured to, when first data corresponding to retransmission data required by an HARQ process is stored in an off-chip memory, read the first data from the off-chip memory, write the first data into an on-chip memory, and read the first data from the on-chip memory to combine with the retransmission data, so as to obtain second data for decoding, where a start time of reading the first data from the on-chip memory is later than a start time of writing the first data into the on-chip memory.

9. The apparatus of claim 8, wherein the on-chip memory comprises static random access memory, SRAM, and the off-chip memory comprises double rate synchronous dynamic random access memory, DDR;

And/or the number of the groups of groups,

The apparatus further includes a first read-write controller for writing the second data into the off-chip memory if the data amount of the second data is greater than the free memory amount in the on-chip memory; and writing the second data into the on-chip memory in the case that the data amount of the second data is less than or equal to the free memory amount in the on-chip memory.

10. An on-chip resource comprising a data cache management apparatus as claimed in claim 8 or 9.