CN118157462B

CN118157462B - Circuit structure for eliminating IO driver connection line capacitance

Info

Publication number: CN118157462B
Application number: CN202410584603.4A
Authority: CN
Inventors: 林云; 张冬青
Original assignee: Zhongyin Microelectronics Nanjing Co ltd
Current assignee: Zhongyin Microelectronics Nanjing Co ltd
Filing date: 2024-05-12
Publication date: 2024-08-02
Anticipated expiration: 2044-05-12

Abstract

The invention provides a circuit structure for eliminating IO driver connection capacitance, which relates to the technical field of IO driver end capacitance optimization.

Description

Circuit structure for eliminating IO driver connection line capacitance

Technical Field

The invention relates to the technical field of IO drive end capacitance optimization, in particular to a circuit structure for eliminating IO driver connection capacitance.

Background

The IO driving end in the high-speed circuit needs to be connected with a larger capacitive load at the output end because of the need of both driving the external wiring of the chip and setting ESD protection, so that a larger ISI effect is easily caused in the circuit.

In the prior art, the common solution is to increase the inductance to reduce the influence of capacitive load, optimize the layout design at the same time, reduce the parasitic capacitance of the IO driving end as much as possible, but the effect that the increase of the inductance can play is limited, and the optimization of the layout design is limited by the size of the component, so that the optimization amplitude is difficult to promote, and the optimization effect of the two is poor. Therefore, it is desirable to provide a system that substantially eliminates the effects of the IO driver side capacitive load.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The present invention is directed to a circuit structure for eliminating an IO driver link capacitor, so as to solve the problems set forth in the background art.

In order to achieve the above purpose, the present invention provides the following technical solutions:

a circuit structure for eliminating IO driver link capacitance, comprising:

The main driving module is electrically connected with the antistatic module and the load module, and is used for receiving an input signal, generating a first output signal according to the input signal and sending the first output signal to the load module;

The slave driving module is connected with the master driving module in parallel and is used for receiving an input signal, generating a second output signal according to the input signal and correcting the first output signal by using the second output signal;

The antistatic module is used for playing an antistatic role on the whole circuit;

and the load module is used for receiving the first output signal and executing the first output signal.

Preferably, a first inductor and a second inductor are electrically connected between the output end of the master driving module and the load module, and a first capacitor is electrically connected between the output end of the master driving module and the output end of the slave driving module.

Preferably, the first capacitor is disposed between the output terminal of the main driving module and the first inductor.

Preferably, the output end of the slave driving module is electrically connected with a second capacitor, and the other end of the second capacitor is grounded.

Preferably, the working logic of the master driving module and the working logic of the slave driving module are the same, and the phases of the first output signal and the second output signal are the same.

Preferably, the antistatic module is disposed between the first inductor and the second inductor.

Preferably, the master driving module, the slave driving module, the antistatic module, the load module, the first inductor, the second inductor, the first capacitor and the second capacitor are integrated on the PCB.

Preferably, the main driving module, the first capacitor, the first inductor, the second inductor, the antistatic module and the load module are all arranged on the top layer of the PCB, the auxiliary driving module and the second capacitor are arranged on the bottom layer of the PCB, and the top layer and the bottom layer of the PCB are connected through internal wiring.

Compared with the prior art, the invention has the beneficial effects that: the invention corrects the output of the main driving module by arranging a group of auxiliary driving modules which have the same logic as the main driving module and generating the output signals with the same phase as the main driving module by utilizing the auxiliary driving modules, thereby reducing the actual capacitance of the capacitive load at the output end of the main driving module, reducing the charge and discharge time of the capacitive load, accelerating the response speed of the output signals of the main driving module, optimizing the layout design, and isolating the main driving module from the auxiliary driving module in the layout design, further realizing the effects of reducing the ISI effect of an output circuit and improving the signal quality.

Drawings

FIG. 1 is a schematic diagram of a module structure of the present invention;

FIG. 2 is a circuit diagram of an IO driver end in the prior art;

FIG. 3 is a circuit diagram of the IO driver end of the present invention.

Detailed Description

The present invention will be further described in detail with reference to specific embodiments in order to make the objects, technical solutions and advantages of the present invention more apparent.

It is to be noted that unless otherwise defined, technical or scientific terms used herein should be taken in a general sense as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "up", "down", "left", "right" and the like are used only to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed accordingly.

Examples:

referring to fig. 1-3, the present invention provides a technical solution:

A circuit structure for eliminating IO driver connection capacitance comprises a master driving module driver, a slave driving module REPLICA DRIVE, an anti-static module ESD and a load module PAD.

The main driving module Drive is electrically connected with the anti-static module ESD and the load module PAD, and is used for receiving an input signal, generating a first output signal according to the input signal, sending the first output signal to the load module PAD, driving the IO end of the load module PAD, wherein the load module PAD is equipment with the IO end to be driven and is used for receiving the first output signal and executing, a first inductor L1 and a second inductor L2 are electrically connected between the output end of the main driving module and the load module, a first capacitor C1 is electrically connected between the output end of the main driving module and the output end of the auxiliary driving module, the first capacitor C1 is arranged between the output end of the main driving module Drive and the first inductor L1, and is used for enhancing the capacity of the main driving module Drive, so that the load module PAD can be driven conveniently, signal integrity can be improved, crosstalk and reflection between signals can be reduced, but larger capacitive load can cause a circuit to generate larger ISI effect, and therefore the influence of the ISI effect caused by the large capacitive load on the circuit can be reduced by using the first inductor L1 and the second inductor L2.

The slave driving module REPLICA DRIVE is connected in parallel with the master driving module Drive, and is configured to receive an input signal, generate a second output signal according to the input signal, and correct the first output signal by using the second output signal, where an output end of the slave driving module is electrically connected to a second capacitor C2, and the other end of the second capacitor C2 is grounded, where the slave driving module REPLICA DRIVE is the same as the working logic of the master driving module Drive and is a replica circuit of the master driving module Drive, so that phases of the second output signal and the first output signal are the same, and only differences of signal intensities exist.

The ESD (electrostatic discharge) module is an ESD diode, the positive electrode of the ESD diode is connected between the first inductor L1 and the second inductor L2, the negative electrode of the ESD diode is grounded, and when electrostatic discharge occurs outside, the ESD diode guides static to the ground so as to play a role of preventing static of the whole circuit.

As can be seen from the circuit diagram of the present invention, the voltages at two ends of the first capacitor C1 are the first output signal generated by the main driving module Drive and the second output signal generated by the slave driving module REPLICA DRIVE, and compared with the connection mode in the prior art that the other end of the first capacitor C1 is directly grounded, the potential difference at two ends of the first capacitor C1 is smaller, which is equivalent to reducing the actual capacitance of the first capacitor C1, so that the time required for charging and discharging the first capacitor C1 is shorter, and the response speed of the first output signal and the second output signal is faster, thereby playing a role in reducing the ISI effect of the circuit.

The main driving module Drive, the auxiliary driving module REPLICA DRIVE, the anti-static module ESD, the load module PAD, the first inductor L1, the second inductor L2, the first capacitor C1 and the second capacitor C2 are all integrated on the PCB, the main driving module Drive, the first capacitor C1, the first inductor L1, the second inductor L2, the anti-static module ESD and the load module PAD are all arranged on the top layer of the PCB, the auxiliary driving module REPLICA DRIVE and the second capacitor C2 are arranged on the bottom layer of the PCB, the top layer and the bottom layer of the PCB are connected through internal wires, through the layout mode, the output of the main driving module Drive and the output of the auxiliary driving module REPLICA DRIVE are isolated, the mutual interference between signals can be reduced, the potential difference of the two ends of the first capacitor C1 can be changed by adjusting the magnitude of the second output signal generated by the auxiliary driving module REPLICA DRIVE, and the actual capacitance is also equivalent to being changed, so that the capacitance of the main driving module Drive at the output end is convenient to dynamically adjust depending on the output of the auxiliary driving module REPLICA DRIVE.

The above formulas are all formulas with dimensions removed and numerical values calculated, the formulas are formulas with a large amount of data collected for software simulation to obtain the latest real situation, and preset parameters in the formulas are set by those skilled in the art according to the actual situation.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. Those of skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, may be located in one place, or may be distributed over multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.

Claims

1. A circuit structure for eliminating an IO driver link capacitor, comprising:

The load module is used for receiving the first output signal and executing the first output signal;

A first inductor and a second inductor are electrically connected between the output end of the main driving module and the load module, and a first capacitor is electrically connected between the output end of the main driving module and the output end of the auxiliary driving module;

one end of the first capacitor is connected between the output end of the master driving module and the first inductor, and the other end of the first capacitor is electrically connected with the output end of the slave driving module;

the output end of the slave driving module is electrically connected with one end of a second capacitor, and the other end of the second capacitor is grounded;

the working logic of the master driving module is the same as that of the slave driving module, and the phases of the first output signal and the second output signal are the same.

2. The circuit structure for eliminating the IO driver link capacitor of claim 1, wherein: the antistatic module is arranged between the first inductor and the second inductor.

3. The circuit structure for eliminating the IO driver link capacitor of claim 1, wherein: the main driving module, the auxiliary driving module, the antistatic module, the load module, the first inductor, the second inductor, the first capacitor and the second capacitor are integrated on the PCB.

4. A circuit structure for eliminating IO driver link capacitance as defined in claim 3, wherein: the main driving module, the first capacitor, the first inductor, the second inductor, the antistatic module and the load module are all arranged on the top layer of the PCB, the auxiliary driving module and the second capacitor are arranged on the bottom layer of the PCB, and the top layer and the bottom layer of the PCB are connected through internal wiring.