CN118156289A - Transistor and preparation method thereof - Google Patents

Transistor and preparation method thereof Download PDF

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Publication number
CN118156289A
CN118156289A CN202211558895.1A CN202211558895A CN118156289A CN 118156289 A CN118156289 A CN 118156289A CN 202211558895 A CN202211558895 A CN 202211558895A CN 118156289 A CN118156289 A CN 118156289A
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China
Prior art keywords
substrate
transistor
electrode
drain electrode
gate electrode
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CN202211558895.1A
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Chinese (zh)
Inventor
张乃千
裴轶
宋晰
张新川
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Dynax Semiconductor Inc
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Dynax Semiconductor Inc
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Priority to CN202211558895.1A priority Critical patent/CN118156289A/en
Publication of CN118156289A publication Critical patent/CN118156289A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a transistor and a preparation method thereof. The transistor comprises a substrate, a drain electrode, a source electrode and a gate electrode and a field plate structure, wherein the drain electrode and the source electrode are arranged on one side of the substrate; a first dielectric layer is arranged between the gate electrode and the field plate structure; the first dielectric layer is provided with a groove, a first non-groove part positioned between the gate electrode and the drain electrode and a second non-groove part positioned between the gate electrode and the source electrode; the part of the gate electrode, which is contacted with the first dielectric layer, comprises a first side wall, a top wall and a second side wall, wherein the first side wall and the top wall are close to the drain electrode, and the second side wall is close to the source electrode; vertical projection of the groove on the substrate, covering vertical projection of the first side wall on the substrate; the field plate structure fills the recess and covers a portion of the first non-recess portion. The invention can reduce the change rate of the gate-source capacitance when the state of the transistor is switched, and simultaneously ensures that the transistor has better bandwidth characteristics.

Description

Transistor and preparation method thereof
Technical Field
The invention relates to the technical field of microelectronics, in particular to a transistor and a preparation method thereof.
Background
Transistors have extremely important applications in the field of modern electronic technology, and the corresponding performance requirements for transistors are also increasing.
In order to improve breakdown voltage of the existing transistor, a field plate structure is generally added, a new depletion region can be formed below the field plate, which is equivalent to increasing the area of the depletion region in the barrier layer between the gate and the drain, and improving the source-drain voltage which can be borne by the depletion region, thereby increasing the breakdown voltage of the transistor. However, the existing transistor with a field plate structure has large gate-source capacitance change when switching between an on state and an off state, so that a power dispersion problem occurs, and the bandwidth characteristic is also poor.
Disclosure of Invention
The invention provides a transistor and a preparation method thereof, which are used for reducing the change rate of a gate-source capacitance during the state switching of the transistor and ensuring that the transistor has better bandwidth characteristics.
According to an aspect of the present invention, there is provided a transistor including a substrate, the transistor further including a drain electrode provided on one side of the substrate, a source electrode, and a gate electrode and a field plate structure arranged between the source electrode and the drain electrode;
a first dielectric layer is arranged between the gate electrode and the field plate structure along the thickness direction of the transistor;
The first dielectric layer is provided with a groove, a first non-groove part positioned between the gate electrode and the drain electrode and a second non-groove part positioned between the gate electrode and the source electrode; the part of the gate electrode, which is contacted with the first dielectric layer, comprises a first side wall, a top wall and a second side wall, wherein the first side wall is close to the drain electrode, and the second side wall is close to the source electrode; the vertical projection of the groove on the substrate covers the vertical projection of the first side wall on the substrate;
The field plate structure fills the recess and covers a portion of the first non-recess portion.
Optionally, the recess is located between a vertical projection of the first sidewall onto the substrate and a vertical projection of the source electrode onto the substrate, near a vertical projection of the sidewall of the source electrode onto the substrate.
Optionally, a vertical projection of a sidewall of the recess near the source electrode on the substrate does not overlap with a vertical projection of the second sidewall on the substrate.
Optionally, a perpendicular projection of the recess on the substrate covers a perpendicular projection of the second sidewall on the substrate, and the field plate structure covers a portion of the second non-recess portion.
Optionally, the groove is located between the gate electrode and the drain electrode near a sidewall of the drain electrode.
Optionally, a distance from a vertical projection of an edge of the gate electrode near the drain electrode on the substrate to a vertical projection of an edge of the recess near the drain electrode on the substrate is less than or equal to 0.9 times a distance from a vertical projection of an edge of the gate electrode near the drain electrode on the substrate to a vertical projection of an edge of the field plate structure near the drain electrode on the substrate.
Optionally, the depth of the groove is greater than 0.1 times the thickness of the portion of the first dielectric layer where the groove is not provided.
Optionally, the thickness of the portion of the first dielectric layer where the groove is not provided ranges from 30 nanometers to 500 nanometers.
Optionally, the transistor further comprises a buffer layer, a channel layer and a barrier layer sequentially stacked on the substrate;
The source electrode and the drain electrode are arranged on the barrier layer;
the transistor further comprises a second dielectric layer covering the barrier layer;
The gate electrode penetrates through the second dielectric layer and is in contact with the barrier layer;
the transistor further includes a third dielectric layer overlying the field plate structure.
According to another aspect of the present invention, there is provided a method for manufacturing a transistor, for manufacturing the transistor, the method comprising:
forming the source electrode, the drain electrode and the gate electrode;
forming a first dielectric preparation layer covering the gate electrode;
Forming a groove on the first medium preparation layer to form a first medium layer;
and forming a field plate structure filling the grooves and covering part of the first non-groove parts.
According to the technical scheme, the transistor comprises a substrate, a drain electrode, a source electrode, a gate electrode and a field plate structure, wherein the drain electrode and the source electrode are arranged on one side of the substrate; a first dielectric layer is arranged between the gate electrode and the field plate structure along the thickness direction of the transistor; the first dielectric layer is provided with a groove, a first non-groove part positioned between the gate electrode and the drain electrode and a second non-groove part positioned between the gate electrode and the source electrode; the part of the gate electrode, which is contacted with the first dielectric layer, comprises a first side wall, a top wall and a second side wall, wherein the first side wall and the top wall are close to the drain electrode, and the second side wall is close to the source electrode; vertical projection of the groove on the substrate, covering vertical projection of the first side wall on the substrate; the field plate structure fills the groove and covers part of the first non-groove part; the recess is adjacent to a vertical projection of a sidewall of the source electrode on the substrate, between a vertical projection of the first sidewall on the substrate and a vertical projection of the source electrode on the substrate. By arranging the grooves, the projection of the side wall of the groove close to the drain electrode is not overlapped with the projection of the side wall of the gate electrode close to the drain electrode, and the equivalent is that the distance between the field plate structure and the gate electrode is reduced, so that the gate-source capacitance is increased, and the power dispersion phenomenon is improved. And because the field plate structure covers partial first non-groove part, the distance between the field plate structure and the drain electrode is also far, and the source-drain capacitance cannot be increased, so that the device has better bandwidth characteristic.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a transistor according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a transistor according to a second embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing a transistor according to a third embodiment of the present invention;
fig. 4 is a schematic diagram of a product formed by the main steps of a method for manufacturing a transistor according to a third embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a schematic structural diagram of a transistor according to a first embodiment of the present invention, referring to fig. 1, the transistor includes a substrate 11, and further includes a drain electrode 15, a source electrode 16, and a gate electrode 19 and a field plate structure 20 disposed between the source electrode 16 and the drain electrode 15, which are disposed on one side of the substrate 11; a first dielectric layer 18 is arranged between the gate electrode 19 and the field plate structure 20 along the thickness direction X of the transistor; the first dielectric layer 18 has a recess 181, a first non-recess portion 182 located between the gate electrode 19 and the drain electrode 15, and a second non-recess portion 183 located at least between the gate electrode 19 and the source electrode 16; in the Y direction, the first dielectric layer 18 has a groove 181 between the first non-groove portion 182 and the second non-groove portion 183; the portion of gate electrode 19 in contact with first dielectric layer 18 includes a first sidewall 191 adjacent drain electrode 15, a top wall 192, and a second sidewall 193 adjacent source electrode 16; vertical projection of the groove 181 on the substrate 11, covering vertical projection of the first sidewall 191 on the substrate 11; the field plate structure 20 fills the recess 181 and covers part of the first non-recess portion 182; it should be noted that, in the embodiment where the field plate structure 20 fills the groove 181, the groove 181 may be completely covered, or the groove 181 may be partially covered, for example, at the edge of the groove 181, a certain interval may exist between the field plate structure 20 and the groove 181, and only the field plate structure 20 needs to be ensured to be filled in the groove 181 and the first non-groove portion 182 at the same time.
Further, the recess 181 is located close to the vertical projection of the sidewall of the source electrode 1811 on the substrate 11, between the vertical projection of the first sidewall 191 on the substrate 11 and the vertical projection of the source electrode 16 on the substrate 11.
Specifically, the transistor may be, for example, a high-power gallium nitride high electron mobility transistor (High Electron Mobility Transistor, HEMT), a Silicon-On-Insulator (SOI) structure transistor On an insulating substrate, a gallium arsenide (GaAs) based transistor, and a Metal-Oxide-semiconductor Field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), a Metal-Insulator-semiconductor Field effect transistor (Metal-Semiconductor Field-Effect Transistor, MISFET), a double heterojunction Field effect transistor (Double Heterojunction Field-Effect Transistor, DHFET), a Junction Field effect transistor (Junction-Effect Transistor, JFET), a Metal-semiconductor Field effect transistor (Metal-Semiconductor Field-Effect Transistor, fet), a Metal-Insulator-semiconductor heterojunction Field effect transistor (Metal-Semiconductor Heterojunction Field-Effect Transistor, MISFET), or other Field effect transistors, which are operated under a high-voltage and high-current environment. As shown in fig. 1, the transistor may include, for example, a substrate 11, a buffer layer 12, a channel layer 13, and a barrier layer 14, which are stacked in this order. The substrate 11 may be, for example, one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides. A multilayer epitaxial structure, that is, the buffer layer 12, the channel layer 13, and the barrier layer 14 described in this embodiment, is formed on the substrate 11. The material of the barrier layer 14 may be AlGaN, and the material of the channel layer 13 may be GaN, for example. The barrier layer 14 and the channel layer 13 form a heterojunction at which a 2DEG (Two-Dimensional Electron Gas ) channel is formed, wherein the channel layer 13 provides a channel for movement of the 2DEG, and the barrier layer 14 functions as a barrier.
After the first dielectric layer 18 is manufactured, the field plate structure is directly manufactured on the first dielectric layer 18, and the distance between the field plate structure and the gate electrode is far due to the fact that the first dielectric layer is thicker, so that the gate-source capacitance formed by the field plate structure and the gate electrode is small, the change rate of the gate-source capacitance is large when the transistor is switched between the on state and the off state, and therefore the power dispersion phenomenon is caused.
In this embodiment, as shown in fig. 1, the first dielectric layer 18 is formed with the groove 181, and when the first dielectric layer 18 is manufactured, the field plate structure 20 is not immediately manufactured, but the groove 181 is etched first, which is equivalent to reducing the thickness of the first dielectric layer 18. After the field plate structure 20 is manufactured, the field plate structure 20 fills the groove 181, specifically, as shown in fig. 1, taking the case that the field plate structure 20 completely covers the groove 181, the distance between the field plate structure 20 and the gate electrode 19 is smaller, so that the gate-source capacitance formed by the gate electrode 19 and the field plate structure 20 is larger, and the change rate of the gate-source capacitance is smaller when the on state and the off state of the transistor are switched, so that the power dispersion phenomenon can be avoided, and the transistor can be applied to the fields of radio frequency and the like.
In addition, the first sidewall 191 of the gate electrode 19 is generally an inclined sidewall, and the projection of the recess 181 is set to cover the projection of the first sidewall in this embodiment, so as to avoid a larger change of the gate-source capacitance at the first sidewall, thereby ensuring a smaller change rate of the gate-source capacitance when the transistor is switched between the on and off states.
The first dielectric layer 18 further includes a first non-recessed portion 182, where the first non-recessed portion 182 is located between the gate electrode 19 and the drain electrode 15, and it is understood that the projection of the first non-recessed portion 182 onto the substrate 11 is located between the projection of the gate electrode 19 onto the substrate 11 and the projection of the drain electrode 15 onto the substrate 11. The field plate structure 20 covers a part of the first non-groove portion 182, in other words, the field plate structure 20 extends from the groove 181 to the first non-groove portion 182, the thickness of the first non-groove portion 182 is thicker than that of the portion of the first dielectric layer 18 corresponding to the groove 181, the distance between one end of the field plate structure 182 close to the drain electrode 15 and the drain electrode 15 is also larger, and the source-drain capacitance of the transistor is not increased under the condition that the length of the field plate structure 182 is fixed, so that the device has better bandwidth characteristics.
According to the technical scheme, the transistor comprises a substrate, a drain electrode, a source electrode, a gate electrode and a field plate structure, wherein the drain electrode and the source electrode are arranged on one side of the substrate; a first dielectric layer is arranged between the gate electrode and the field plate structure along the thickness direction of the transistor; the first dielectric layer is provided with a groove, a first non-groove part positioned between the gate electrode and the drain electrode and a second non-groove part positioned between the gate electrode and the source electrode; the part of the gate electrode, which is contacted with the first dielectric layer, comprises a first side wall, a top wall and a second side wall, wherein the first side wall and the top wall are close to the drain electrode, and the second side wall is close to the source electrode; vertical projection of the groove on the substrate, covering vertical projection of the first side wall on the substrate; the field plate structure fills the groove and covers part of the first non-groove part; the recess is adjacent to a vertical projection of a sidewall of the source electrode on the substrate, between a vertical projection of the first sidewall on the substrate and a vertical projection of the source electrode on the substrate. By arranging the grooves, the projection of the side wall of the groove close to the drain electrode is not overlapped with the projection of the side wall of the gate electrode close to the drain electrode, and the equivalent is that the distance between the field plate structure and the gate electrode is reduced, so that the gate-source capacitance is increased, and the power dispersion phenomenon is improved. And because the field plate structure covers partial first non-groove part, the distance between the field plate structure and the drain electrode is also far, and the source-drain capacitance cannot be increased, so that the device has better bandwidth characteristic.
Optionally, with continued reference to fig. 1, a recess 181 is located between gate electrode 19 and drain electrode 15 proximate to a sidewall of drain electrode 15.
Specifically, in the present embodiment, the projection of the recess 181 on the substrate 11 near the sidewall of the drain electrode 15 is disposed between the projection of the gate electrode 19 on the substrate 11 and the projection of the drain electrode 15; in other words, the side wall of the recess 181 close to the drain electrode 15 does not overlap with the projection of the side wall of the gate electrode 19 close to the drain electrode 15. This arrangement ensures that the sidewall 1812 of the recess 181 adjacent to the drain electrode 15 does not overlap with the projection of the sidewall of the gate electrode 19 adjacent to the drain electrode 15 due to process errors when the recess 181 is formed, i.e. this arrangement ensures that the gate-source capacitance does not change significantly at the position of the sidewall of the gate electrode adjacent to the drain electrode.
Optionally, with continued reference to fig. 1, the distance from the vertical projection of the edge of gate electrode 19 near drain electrode 15 onto substrate 11 to the vertical projection of the edge of recess 181 near drain electrode 15 onto substrate 11 is less than or equal to the vertical projection of the edge of gate electrode 19 near drain electrode 15 onto substrate 11 to 0.9 times the distance from the vertical projection of the edge of field plate structure 20 near drain electrode 15 onto substrate 11.
Specifically, in the present embodiment, the direction in which the source electrode 16, the gate electrode 19, and the drain electrode 15 are arranged is defined as the direction Y, and the direction Y is parallel to the substrate 11; the edge of the gate electrode 19 near the drain electrode 15, that is, the portion of the gate electrode 19 closest to the drain electrode 15 in the direction Y, defines the portion as a first edge. The edge of the field plate structure 20 near the drain electrode 15 is defined as the second edge. The edge of the recess 181 adjacent to the drain electrode 15 is defined as a third edge. In the direction Y, the distance d1 between the first edge and the second edge may be greater than or equal to 0.1 micrometer, preferably may be 0.1 micrometer, 0.3 micrometer, etc. The distance d2 from the first edge to the third edge is less than or equal to 0.9 times, preferably 0.7 times or 0.5 times, the distance d1 from the first edge to the second edge, so that the portion of the field plate structure 20 corresponding to the unetched portion of the first dielectric layer is also larger, and the distance between the field plate structure 20 and the drain electrode 15 is ensured to be larger, thereby ensuring that the source-drain capacitance is not increased.
Optionally, the thickness of the portion of the first dielectric layer 18 where the recess 181 is not provided ranges from 30 nm to 500 nm, and may preferably be 100 nm, 200 nm or 300 nm. If the thickness of the portion of the first dielectric layer 18 where the recess is not provided is smaller, the distance between the gate electrode and the field plate structure will be too small after the recess is provided, which is easy to cause breakdown of the gate-source capacitance. If the thickness of the portion of the first dielectric layer 18 where the recess is not provided is relatively thick, material is wasted, and the capacitance between the gate electrode and the field plate structure is relatively small. Of course, it should be noted that, in the present embodiment, the portion of the first dielectric layer 18 where the recess 181 is not provided refers to the portion of the first dielectric layer where the recess 181 mentioned in the present embodiment is not provided, and the recess beyond the expected appearance of the product due to the process reason is not within the recess range described in the present embodiment.
Preferably, the depth of the recess 181 is greater than 0.1 times the thickness of the portion of the first dielectric layer 18 where the recess is not provided, or the thickness of the dielectric layer corresponding between the recess 181 and the gate electrode 19 is less than 0.9 times the thickness of the portion of the first dielectric layer 18 where the recess is not provided. If the depth of the groove 181 is larger, the distance between the field plate structure and the gate electrode will be too small, which is easy to cause gate-source capacitance breakdown, so the depth of the groove 181 is smaller than 0.9 times of the thickness of the non-groove part of the first dielectric layer 18; if the thickness of the groove is smaller, the groove is not easy to manufacture, and the depth of the groove can be preferably 0.5 times or 0.4 times of the depth of the part of the first dielectric layer where the groove is not arranged.
Optionally, with continued reference to fig. 1, in the present embodiment, the source electrode 16 and the drain electrode 15 are disposed on the barrier layer 14. The transistor further comprises a second dielectric layer 17 covering the barrier layer 14, and a gate electrode 19 extends through the second dielectric layer 17 and is in contact with the barrier layer 14. The gate electrode may be a T-shaped gate. In other embodiments, the gate electrode 19 may be directly disposed on the barrier layer 14 without disposing the second dielectric layer 17. The thickness of the second dielectric layer 17 may be, for example, 30 nm to 300 nm, and preferably may be 100 nm or 150 nm, etc. The transistor further comprises a third dielectric layer 21 covering the field plate structure 20. The first dielectric layer 18, the second dielectric layer 17 and the third dielectric layer 21 may all be SiN.
Example two
Fig. 2 is a schematic structural diagram of a transistor according to a second embodiment of the present invention, and in combination with fig. 1 and fig. 2, a vertical projection of a sidewall 1811 of the recess 181 near the source electrode 16 on the substrate 11 is not overlapped with a vertical projection of the second sidewall on the substrate 11.
Specifically, if the projection of the recess 181 near the sidewall 1811 of the source electrode 16 overlaps with the vertical projection of the second sidewall 193 on the substrate 11, which is equivalent to the portion of the first dielectric layer corresponding to the second sidewall 193, both the recess portion and the non-recess portion exist, so that after the field plate structure is disposed, the change rate of the portion of the gate-source capacitance corresponding to the second sidewall is relatively high, which is also unfavorable for reducing the change rate of the gate-source capacitance when the transistor is switched between the on and off states. In the first embodiment, the vertical projection of the side wall of the recess 181 near the source electrode 16 on the substrate 11 overlaps with the vertical projection of the top wall 192 on the substrate 11; in the present embodiment, the recess 181 is located near the vertical projection of the sidewall of the source electrode 16 on the substrate 11, and is located between the vertical projection of the second sidewall 193 on the substrate 11 and the vertical projection of the source electrode 16 on the substrate 11.
Optionally, along the thickness direction of the transistor, the projection of the recess 181 covers the projection of the gate electrode 19 close to the sidewall of the source electrode 16, and the first dielectric layer 18 further has a second non-recess portion 183 located between the source electrode 16 and the gate electrode, and the field plate structure 20 has a part of the second non-recess portion 183.
Specifically, the field plate structure 20 fills the recess 181 and extends toward the source electrode 16, and covers a portion of the second non-recess portion 183, which is more advantageous in reducing the difficulty of manufacturing the field plate structure 20.
In addition, in the present embodiment, the recess 181 may be disposed near the sidewall of the drain electrode 15 and between the gate electrode 19 and the drain electrode 15. Optionally, the distance from the vertical projection of the edge of the gate electrode 19 near the drain electrode 15 onto the substrate 11 to the vertical projection of the edge of the recess 181 near the drain electrode 15 onto the substrate 11 is less than or equal to 0.9 times the distance from the vertical projection of the edge of the gate electrode 19 near the drain electrode 15 onto the substrate 11 to the vertical projection of the edge of the field plate structure 20 near the drain electrode 15 onto the substrate 11. And optionally, the thickness of the portion of the first dielectric layer 18 where the recess 181 is not provided ranges from 30 nm to 500 nm. The relevant advantageous effects can be referred to the description of a part of the embodiments, and will not be repeated here.
Example III
The embodiment of the invention also provides a method for manufacturing a field plate structure, as shown in fig. 3, fig. 3 is a flowchart of a method for manufacturing a transistor provided by the third embodiment of the invention, and fig. 4 is a schematic product diagram formed by main steps of the method for manufacturing a transistor provided by the third embodiment of the invention, and the method for manufacturing a transistor includes, in combination with fig. 3 and fig. 4:
Step S101, forming a source electrode, a drain electrode and a gate electrode;
Specifically, the buffer layer 12, the channel layer 13, and the barrier layer 14 may be sequentially grown on the substrate 11; the source electrode 16 and the drain electrode 15 may be subsequently formed. Of course, the gate electrode may be formed at this step when the transistor does not include the second dielectric layer.
Subsequently, a second dielectric layer 17 is grown. Subsequently, a via hole is etched on the second dielectric layer 17, followed by formation of a gate electrode 19.
In step S102, a first dielectric preparation layer 184 is formed to cover the gate electrode. The first dielectric preparation layer 184 may be formed by, for example, growth.
Step S103, forming a groove on the first medium preparation layer to form a first medium layer;
the recess 181 may be formed, for example, by etching;
in step S104, a field plate structure 20 is formed that fills the recess and covers a portion of the first non-recess portion.
Finally, a third dielectric layer 21 covering the field plate structure 20 may be formed again.
The transistor manufactured by the manufacturing method of the embodiment is provided with the groove, and the projection of the side wall of the groove close to the drain electrode is not overlapped with the projection of the side wall of the gate electrode close to the drain electrode, which is equivalent to reducing the distance between the field plate structure and the gate electrode, thereby increasing the gate-source capacitance and improving the power dispersion phenomenon. And because the field plate structure covers partial first non-groove part, the distance between the field plate structure and the drain electrode is also far, and the source-drain capacitance cannot be increased, so that the device has better bandwidth characteristic.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. A transistor, wherein the transistor comprises a substrate, a drain electrode arranged on one side of the substrate, a source electrode, and a gate electrode and a field plate structure arranged between the source electrode and the drain electrode;
a first dielectric layer is arranged between the gate electrode and the field plate structure along the thickness direction of the transistor;
The first dielectric layer is provided with a groove, and the part of the first dielectric layer, which is not provided with the groove, comprises a first non-groove part positioned between the gate electrode and the drain electrode and a second non-groove part positioned between the gate electrode and the source electrode; the part of the gate electrode, which is contacted with the first dielectric layer, comprises a first side wall, a top wall and a second side wall, wherein the first side wall is close to the drain electrode, and the second side wall is close to the source electrode; the vertical projection of the groove on the substrate covers the vertical projection of the first side wall on the substrate;
The field plate structure fills the recess and covers a portion of the first non-recess portion.
2. The transistor of claim 1, wherein the recess is located proximate to a perpendicular projection of a sidewall of the source electrode onto the substrate between a perpendicular projection of the first sidewall onto the substrate and a perpendicular projection of the source electrode onto the substrate.
3. The transistor according to claim 1, wherein,
The vertical projection of the side wall of the groove, which is close to the source electrode, on the substrate is not overlapped with the vertical projection of the second side wall on the substrate.
4. The transistor of claim 1, wherein a perpendicular projection of the recess onto the substrate covers a perpendicular projection of the second sidewall onto the substrate, and the field plate structure covers a portion of the second non-recess portion.
5. The transistor of claim 1, wherein the recess is located between the gate electrode and the drain electrode proximate a sidewall of the drain electrode.
6. The transistor of claim 5, wherein a distance from a vertical projection of an edge of the gate electrode near the drain electrode onto the substrate to a vertical projection of an edge of the recess near the drain electrode onto the substrate is less than or equal to 0.9 times a distance from a vertical projection of an edge of the gate electrode near the drain electrode onto the substrate to a vertical projection of an edge of the field plate structure near the drain electrode onto the substrate.
7. The transistor of claim 1, wherein a depth of the recess is greater than 0.1 times a thickness of the first dielectric layer where the recess is not provided.
8. The transistor of claim 1, wherein the thickness of the portion of the first dielectric layer where the recess is not provided is in the range of 30 nm to 500 nm.
9. The transistor according to claim 1, further comprising a buffer layer, a channel layer, and a barrier layer sequentially stacked over the substrate;
The source electrode and the drain electrode are arranged on the barrier layer;
the transistor further comprises a second dielectric layer covering the barrier layer;
The gate electrode penetrates through the second dielectric layer and is in contact with the barrier layer;
the transistor further includes a third dielectric layer overlying the field plate structure.
10. A method of manufacturing a transistor for manufacturing the transistor according to any one of claims 1 to 9, characterized in that the method of manufacturing a transistor comprises:
forming the source electrode, the drain electrode and the gate electrode;
forming a first dielectric preparation layer covering the gate electrode;
Forming a groove on the first medium preparation layer to form a first medium layer;
and forming a field plate structure filling the grooves and covering part of the first non-groove parts.
CN202211558895.1A 2022-12-06 2022-12-06 Transistor and preparation method thereof Pending CN118156289A (en)

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CN118156289A true CN118156289A (en) 2024-06-07

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