CN1181559C - Voltage-withstanding layer consisting of high dielectric coefficient medium and semiconductor - Google Patents

Voltage-withstanding layer consisting of high dielectric coefficient medium and semiconductor Download PDF

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CN1181559C
CN1181559C CNB011399570A CN01139957A CN1181559C CN 1181559 C CN1181559 C CN 1181559C CN B011399570 A CNB011399570 A CN B011399570A CN 01139957 A CN01139957 A CN 01139957A CN 1181559 C CN1181559 C CN 1181559C
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semiconductor
layer
conduction type
district
contact
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CN1420569A (en
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陈星弼
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Tongji University
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Tongji University
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Priority to AU2002338003A priority patent/AU2002338003A1/en
Priority to US10/504,575 priority patent/US7230310B2/en
Priority to PCT/CN2002/000674 priority patent/WO2003044864A1/en
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract

The present invention relates to a voltage withstanding layer used between the characteristic layer and the contact layer of a high-voltage power device, which is composed of semiconductor of one (or two) kind of current conducting semiconductor (S) and two (or three)medium (HK) regions with high dielectric coefficients, which are parallel to the sectional planes of the voltage withstanding layer and the contact layer and are alternatively arranged.

Description

A kind of semiconductor device
Technical field
The invention belongs to semiconductor device, particularly the Withstand voltage layer of semiconductor power device.
Background technology
As everyone knows, in common power device, be added on n +District and p +Interval reverse voltage is to be born by a gently and thicker semiconductor layer of doping, is Withstand voltage layer (Voltage Sustaining Layer) to call this layer in the following text.For high voltage power device, conducting resistance R On(or conduction voltage drop) also mainly decided by Withstand voltage layer.This layer mixes lighter, or thickness is bigger, or the both is, then puncture voltage is higher, but conducting resistance (or conduction voltage drop) is also bigger.In many power devices, one of sixty-four dollar question is to have high puncture voltage that low conducting resistance is arranged again.Relation between the two becomes the obstacle of making the high-performance power device.What is more, above-mentioned R OnBe meant the resistance of the unit are of the conducting region in the Withstand voltage layer, and in fact in the Withstand voltage layer total some zone do not participate in conduction.For example, the zone under the source substrate zone of vertical-type (longitudinal type) MOSFET, the zone under the bipolar transistor base contact layer all is the zone of not participating in conduction.
The inventor's Chinese invention patent ZL91101845.X and U.S.'s patent of invention 5,216,275 have solved the problems referred to above.Its solution is at p +District and n +Interval next withstand voltage with a compound buffer layer (Composite Buffer Layer, or abbreviation CB layer).The zone of in the CB layer, containing two kinds of conductivity type opposite.These two kinds of zones are from being parallel to CB layer and n +Layer (or p +Layer) arbitrary section at interface all is alternately.And used before this Withstand voltage layer all is the semiconductor of single conduction type.In this invention, also announced the MOST that constitutes with this Withstand voltage layer, the conducting resistance R of unit are OnBe proportional to puncture voltage V B1.3 powers.This representative is to a breakthrough of common Withstand voltage layer relation, and other electrical property of MOST is also fine.
In the past few years, in the industrial quarters of semiconductor power device great change has taken place.Utilize the MOST of the structure (being CB layer structure) of super knot (Super Junction) device that high voltage and big electric current can be provided.
Fig. 1 (a) and Fig. 1 (b) represent the manufacture method of a super knot power device 1.Its process is earlier with the semiconductor chip of a substrate 2 first epitaxial loayer 3 of growing.Substrate 2 is heavily doped n in the figure +Layer, first epitaxial loayer 3 is light dope n layers, injects one deck p type district 4 at this floor intermediate ion.Generally speaking, per 50 to 100 volts epitaxial loayer of withstand voltage needs.Therefore,, 5,7,9,11 and 13 n type epitaxial loayer be among Fig. 1 (a) successively again, the p type ion implanted layer of 6,8,10,12 and 14 among Fig. 1 (a) will be done after each extension the transistor of a 600V.
The p type ion implanted layer 4,6,8,10,12 and 14 that forms is through having formed the p district 16 among Fig. 1 (b) after spreading, the zone that no ion injects influence is n district 15.This has just formed p district and n district alternately.And then do device layer or claim device feature layer 17.Contain ion in the device feature layer 17 and inject the n that forms + Source region 18, oxide layer 19 and on metal gate or polysilicon gate 20.At two n +Also has a p between the source region 18 + District 21, it also has the p of dark knot down + District 22, dark p +District 22 and p + District 21 links.
Obviously, repeatedly extension of above-mentioned manufacture method is very expensive.CB layer structure utilized the charge compensation principle, and wherein the doping in p district and n district will accurately be controlled, and this also makes manufacture difficulty increase, and device cost increases.
Another shortcoming of MOST that contains CB layer structure is when the conducting electric current is very big, and the electric charge of charge carrier itself can influence charge balance, causes puncture voltage to increase the secondary-breakdown phenomenon that descends with electric current, makes safety operation area (SOA) not ideal enough.
Another shortcoming that contains the MOST of CB floor structure is owing to there are two voltages between p district and the n district: one is built-in voltage, the auxiliary voltage that is produced by conducting resistance in this district when another is the conducting of Dang Yi district.These two voltages make between two districts and have depletion region, thereby the area of the effective cross-section in conducting district is reduced.In other words, conducting resistance increases with the increase of electric current.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device, it comprises a kind of Withstand voltage layer of new construction, the compound Withstand voltage layer that is called medium (High K) formation of semiconductor (Semiconductor) and high-dielectric coefficient, be called for short high half Withstand voltage layer or the high Jie's half storey (High K and Semiconductor Layer, or abbreviation HKS-Layer) of being situated between.It can avoid above-mentioned shortcoming, and makes conducting resistance R simultaneously OnWith puncture voltage V BRelation be improved, and have very high switching speed.
The invention provides a kind of semiconductor device, be included in the Withstand voltage layer between the device feature layer of the contact layer of conduction and conduction, described Withstand voltage layer comprises that at least one semiconductor region and at least one have the dielectric area of high-dielectric coefficient, described semiconductor region and dielectric area all contact with described device feature layer and the formed interface of contact layer, described semiconductor region and dielectric area are in contact with one another, and its formed contact-making surface is vertical or approximately perpendicular to described contact layer and device feature layer.
Described semiconductor region and dielectric area all contact with device feature layer and the formed interface of contact layer, and it can be direct contact, also can be by a thin semiconductor region or a thin dielectric area indirect contact.
Described semiconductor region and dielectric area are in contact with one another, and it can be direct contact, also can be by a thin dielectric area indirect contact with low-k.
Can constitute a cellular by at least one described semiconductor region and at least one described dielectric area, many described cellulars are closely arranged and have been constituted described Withstand voltage layer.
Described semiconductor region can be made of the semiconductor of first kind of conduction type, and the device feature layer is the semiconductor region that contains heavily doped second kind of conduction type, and contact layer is the semiconductor of heavily doped first kind of conduction type.
Described semiconductor region can be made of the semiconductor of first kind of conduction type, contact layer is to have the semiconductor of first kind of thin conduction type to constitute on the semiconductor of heavily doped first kind of conduction type, and the semiconductor of described thin first kind of conduction type directly contacts with Withstand voltage layer.
Described semiconductor region can both contain the semiconductor portions of first kind of conduction type, the semiconductor portions that also contains second kind of conduction type, wherein the semiconductor equalizing of the semiconductor of first kind of conduction type and second kind of conduction type directly contacts with device feature layer and contact layer, and the device feature layer is the semiconductor region that contains heavily doped second kind of conduction type.
Described semiconductor region can both contain the semiconductor portions of first kind of conduction type, the semiconductor portions that also contains second kind of conduction type, wherein the semiconductor of first kind of conduction type all directly contacts with device feature layer and contact layer, the semiconductor of second kind of conduction type directly contacts with the device feature layer, and by the dielectric layer of a thin high-dielectric coefficient or the dielectric layer and the contact layer indirect contact of a thin low-k, and the device feature layer is the semiconductor region that contains heavily doped second kind of conduction type.
The dielectric area that can have high-dielectric coefficient between the semiconductor of described two kinds of different conduction-types.
Described contact layer can be the semiconductor of heavily doped second kind of conduction type.
Described contact layer can have the semiconductor layer of first kind of thin conduction type on the semiconductor layer of heavily doped second kind of conduction type, the semiconductor layer of described thin first kind of conduction type directly contacts with Withstand voltage layer.
Description of drawings
Fig. 1 (a): make the method schematic diagram of the prior art of COOLMOST, represent that repeatedly extension and ion inject;
Fig. 1 (b): make the method schematic diagram of the prior art of COOLMOST, expression is the p district in n district around forming one through the diffusion back;
Fig. 2 (a): the explanation of Withstand voltage layer (in the W distance is Withstand voltage layer), expression pin diode;
Fig. 2 (b): the explanation of Withstand voltage layer (in the W distance is Withstand voltage layer), expression p +n -n +Diode;
Fig. 2 (c): the explanation of Withstand voltage layer (in the W distance is Withstand voltage layer), expression n-RMOST;
Fig. 2 (d): the explanation of Withstand voltage layer (in the W distance is Withstand voltage layer), expression n-VDMOST;
Fig. 2 (e): the explanation of Withstand voltage layer (in the W distance is Withstand voltage layer), expression Schottky diode;
Fig. 2 (f): the explanation of Withstand voltage layer (in the W distance is Withstand voltage layer), expression is near the IGBT of break-through;
Fig. 3 (a): common RMOST and Electric Field Distribution thereof, the structural representation of expression RMOST;
Fig. 3 (b): usually RMOST and Electric Field Distribution thereof, the Electric Field Distribution when being illustrated in bias voltage and closing on puncture voltage;
Fig. 3 (c): common RMOST and Electric Field Distribution thereof, a direct component of expression electric field;
Fig. 3 (d): common RMOST and Electric Field Distribution thereof, a component of expression electric field with variable in distance;
Fig. 4 (a): CB-RMOST and Electric Field Distribution thereof, the structural representation of expression CB-RMOST;
Fig. 4 (b): CB-RMOST and Electric Field Distribution thereof, the Electric Field Distribution when being illustrated in bias voltage and closing on puncture voltage;
Fig. 4 (c): CB-RMOST and Electric Field Distribution thereof, a direct component of expression electric field;
Fig. 4 (d): CB-RMOST and Electric Field Distribution thereof, a component of expression electric field with variable in distance;
Fig. 5 (a): the schematic diagram of the Withstand voltage layer (HKS Withstand voltage layer) that semiconductor and high-k material constitute, the Withstand voltage layer that expression high-k material and n N-type semiconductor N constitute;
Fig. 5 (b): the schematic diagram of the Withstand voltage layer (HKS Withstand voltage layer) that semiconductor and high-k material constitute, the Withstand voltage layer that expression high-k material and p N-type semiconductor N constitute;
Fig. 5 (c): the schematic diagram of the Withstand voltage layer (HKS Withstand voltage layer) that semiconductor and high-k material constitute, the Withstand voltage layer that expression high-k material and n N-type semiconductor N district and p N-type semiconductor N district constitute is p N-type semiconductor N district around the high-k material;
Fig. 5 (d): the schematic diagram of the Withstand voltage layer (HKS Withstand voltage layer) that semiconductor and high-k material constitute, the Withstand voltage layer that expression high-k material and n N-type semiconductor N district and p N-type semiconductor N district constitute, be p N-type semiconductor N district on one side around the high-k material, Yi Bian be n N-type semiconductor N district;
Fig. 6 (a):, represent interdigital figure along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5;
Fig. 6 (b): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, the box-shaped cellular figure of expression S district full-mesh;
Fig. 6 (c): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, the box-shaped cellular figure of expression HK district full-mesh;
Fig. 6 (d): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, the rectangle cellular figure of expression S district full-mesh;
Fig. 6 (e): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, the rectangle cellular figure of expression HK district full-mesh;
Fig. 6 (f): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, block pattern is inlayed in expression;
Fig. 6 (g): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, the hexagon closs packing figure of expression S district full-mesh;
Fig. 6 (h): along the various different structure schematic diagrames of the HKS Withstand voltage layer of II-II ' section among Fig. 5, the hexagon closs packing figure of expression HK district full-mesh.
Fig. 7 (a): with the schematic diagram of the n-RMOS of interdigital HKS Withstand voltage layer, the expression structural representation;
Fig. 7 (b): with the schematic diagram of the n-RMOS of interdigital HKS Withstand voltage layer, the expression opening feature;
Fig. 7 (c): with the schematic diagram of the n-RMOS of interdigital HKS Withstand voltage layer, the expression turn-off characteristic;
Fig. 8 (a):, represent interdigital figure along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d);
Fig. 8 (b): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), the box-shaped cellular figure of expression n district full-mesh;
Fig. 8 (c): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), the box-shaped cellular figure of expression p district full-mesh;
Fig. 8 (d): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), the rectangle cellular figure of expression n district full-mesh;
Fig. 8 (e): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), the rectangle cellular figure of expression p district full-mesh;
Fig. 8 (f): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), one of block pattern is inlayed in expression;
Fig. 8 (g): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), two of block pattern is inlayed in expression;
Fig. 8 (h): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), the hexagon closs packing figure of expression n district full-mesh;
Fig. 8 (i): along the various different structure schematic diagrames of the HKS Withstand voltage layer that contains p district and n district of III-III ' section among Fig. 5 (d), the hexagon closs packing figure of expression p district full-mesh;
Fig. 9: the SiO that a thin low-k is arranged between high-k material and the semi-conducting material 2The HKS Withstand voltage layer schematic diagram of layer;
Figure 10 (a): utilize the manufacture process of the VDMOST of HKS structure of voltage-sustaining layer, expression n +Have on the substrate and carved the groove that the degree of depth approaches epitaxy layer thickness on the silicon chip of n epitaxial loayer;
Figure 10 (b): utilize the manufacture process of the VDMOST of HKS structure of voltage-sustaining layer, be illustrated in the dielectric material that has filled up HK in the groove;
Figure 10 (c): utilize the manufacture process of the VDMOST of HKS structure of voltage-sustaining layer, the active area of device is done on the surface that is illustrated in n type district;
Figure 11: high-k material through a light dope n district again and n +The schematic diagram of the n-VDMOST that the drain region contact constitutes.
Figure 12: the schematic diagram of the n-VDMOST that HKS Withstand voltage layer that utilizes Fig. 5 (d) constitutes.
Figure 13: HKS Withstand voltage layer that utilizes Fig. 5 (d) but p district not with n +The drain region directly contacts and the schematic diagram of the n-VDMOST that constitutes.
Figure 14: one is utilized the HKS Withstand voltage layer of Fig. 5 (d) and constitutes the schematic diagram of IGBT.
Figure 15: one is utilized the HKS Withstand voltage layer of Fig. 5 (d) but has the schematic diagram of the IGBT of resilient coating.
Embodiment
In semiconductor power device, generally all there is one at p +The district (or is equivalent to p +Distinguish) and n +Withstand voltage layer between district's (or being equivalent to the nu district).Fig. 2 (a) is the schematic diagram of a pin diode, and it is by p +District 24, n +District 25 and i district 23 constitute, and wherein i district 23 is Withstand voltage layers.Here A is the anode of diode, and K is the negative electrode of diode.Fig. 2 (b) is a p +n -n +The schematic diagram of diode, wherein n -Depletion layer thickness is as being W when reverse bias is added to puncture voltage in district 26, and then thickness is that the zone of W is a Withstand voltage layer.Fig. 2 (c) is the schematic diagram of the n-RMOST of an electron conduction.Here S is the source electrode, and G is a gate electrode, and D is a drain electrode.Although on plane 31, be not p in gate oxide 32 parts +District, but because current potential and p during actual the use on the plane under the gate oxide 32 31 +Source substrate zone 29 is more or less the same with the current potential of n district 27 interfaces, and its difference is compared with the puncture voltage V of device BMuch smaller, therefore can be similar to and think an equipotential surface.Be discussed below when withstand voltage, the zone on the plane 31 is called device feature layer 33.The effect of 33 pairs of Electric Field Distribution of device feature layer can be used as p +Layer.Fig. 2 (d) is the schematic diagram of a VDMOST.Here plane 31 can be similar to and be used as and p +Source substrate zone 29 equipotentials.Therefore will arrive n district 27 and n below 31 with the plane among the present invention +Zone between the interface in drain region 28 is as Withstand voltage layer 34.And with the zone on the plane 31 as device feature layer 33.Here suppose that above-mentioned two kinds of MOST do not reach puncture voltage V adding reversed bias voltage BThe time depletion region the edge arrived n type district 27 and n +The interface in drain region 28.Therefore the thickness of Withstand voltage layer is the W shown in the figure, and this hypothesis meets common practical situation.
In above-mentioned situation, the both sides of Withstand voltage layer are p +District and n +The semiconductor in (or n) district.In fact, the device feature layer can not be p +The district, but metal, the n district formation Schottky of it and Withstand voltage layer contacts.Fig. 2 (e) illustrates the schematic diagram of a Schottky diode.Wherein replaced the p in the said circumstances with metal level 35 +Layer.Below the same reason, Withstand voltage layer also can not be and n +(or n) district contacts, but contacts with metal, forms the Schottky contact.Therefore, we claim that the district of the contact below the Withstand voltage layer is a contact layer.Fig. 2 (f) illustrates a situation near the IGBT of break-through.What Withstand voltage layer contacted below can think p +Layer 36.
For principle of the present invention is described, sketch conventional power MOS device electric breakdown strength V here earlier BWith conducting resistance R OnConcern unfavorable reason.Fig. 3 (a) is the schematic diagram of a RMOST.It is by n district 27, n +Source region 30, p + Source substrate zone 29 and n +Drain region 28 constitutes.Here G is a gate electrode, and S is the source electrode, and D is a drain electrode.Wherein Withstand voltage layer is that thickness shown in the figure is the depleted region 34 of W.Fig. 3 (b) illustrates the Electric Field Distribution when bias voltage closes on puncture voltage among the RMSOT, the electric field of E representative on reference axis y direction.According to the Poisson equation, the gradient of electric field is qN D/ ∈ SN wherein DRepresent the donor concentration in n district.When maximum field reaches breakdown critical electric field E CritThe time, avalanche breakdown just takes place.Breakdown critical electric field E CritNumerical value about 310 5About V/cm, the area in shadow region is represented the integration of electric field to the path, i.e. puncture voltage V between E and the y BObviously, puncture voltage V BHeight, must satisfy following two conditions: the gradient of (1) electric field is little, i.e. N DLittle; (2) width of depletion region W is big.But N DLittle, represent Withstand voltage layer carrier concentration when conducting little, the resistivity height.Depletion width W is big, represents the guiding path path length.Because conducting resistance is proportional to resistivity and path, this can make that conducting resistance increases greatly.For MOS T, best design is at n district 27 and n +Drain region 28 proximity electric fields are E Crit/ 3, then puncture voltage is 2E CritW/3.
Above-mentioned Electric Field Distribution can be thought the stack of two electric fields.One is applied voltage V BThe electric field that causes on a pin diode is shown in Fig. 3 (c).The value of electric field equals 2E Crit/ 3 and not with variable in distance.Another is to be-E from the electric field value of bottom Crit/ 3 electric field values to the top are+E CritThe electric field of/3 linear change, shown in Fig. 3 (d), its gradient is qN D/ ∈ S, its peak value is-qN DW/2 ∈ SAnd+qN DW/2 ∈ SThe electric field in back is to cause conducting resistance R OnWith puncture voltage V BIncrease and cause of increased.
The CB structure of voltage-sustaining layer (Chinese invention patent ZL91101845.X and U.S.'s patent of invention 5,216,275) that the inventor proposes has solved the problems referred to above.Why following brief description CB structure can improve conducting resistance R OnWith puncture voltage V BRelation.Fig. 4 (a) is the schematic diagram of a CB-RMOST.Its Withstand voltage layer 34 is alternately arranged by n district 27 and p district 37 and is formed, and its thickness is W.When CB-RMOST made n district 27 and p district 37 exhaust entirely adding reverse bias, the power line that the positive charge of ionized donor produces in the n district 27 ended on the negative electrical charge that ionization is led in its contiguous p district 37.Therefore the electric field of n district 27 center line I-I ' is shown in the solid line of Fig. 4 (b).It is constant basically, is just reaching near n near plane 31 +28 places, drain region slightly change.This electric field also can be decomposed into as Fig. 4 (c) and two electric fields shown in Fig. 4 (d).Fig. 4 (c) is equivalent to the situation of a pin diode, and is the same with Fig. 3 (c).Fig. 4 (d) then represents the longitudinal electric field by 27 generations of n district.This electric field is much smaller compared with the electric field of the Fig. 3 under the same doping content (d).In fact, N in the CB structure DCan be very big, and this electric field that produces is still much smaller.Because this does not begin constantly accumulation by the longitudinal electric field that the ionized donor positive charge produces in the middle of Withstand voltage layer, but the power line that is produced by near the ionized donor 27 tops, n district and the bottom is positioned at the negative electrical charge of top gate electrode G respectively and is positioned at following n +Drain region 28 negative electrical charges stop, and from 27 tops, n district and the electric field of bottom ionized donor at a distance all by around the ionization in p district 37 led stop.
Structure of voltage-sustaining layer proposed by the invention is with the material of high-dielectric coefficient and semiconductor alternately, constitutes situation as shown in Figure 5, and the HK among the figure represents the material of high-dielectric coefficient.
Principle of the present invention is as follows.
In Fig. 5 (a), if HK district 38 is all very narrow with n district 27,, be equivalent to a kind of material of mixing from taking it by and large, its dielectric coefficient is not the dielectric coefficient ∈ of semi-conducting material s, but it is more much bigger than its value, but than the dielectric coefficient ∈ of the material of high-dielectric coefficient DA little value.Say dielectric coefficient ∈ is arranged roughly as being used as after mixing M, then work as ∈ D＞＞∈ sThe time, ∈ M＞＞∈ sThis makes and to resemble slope qN Fig. 3 (d) D/ ∈ s, under same doping content, can become very little, become qN D/ ∈ MWith other in short, be exactly the N that can use bigger value DObtain same peak value electric field E Crit/ 3.
Make Withstand voltage layer with HKS layer of the present invention, because n type district 27 is when exhausting, the electric flux line that sends of ionized donor wherein, majority can laterally be gone in the medium 38 of contiguous high-dielectric coefficient and go, and go to the top by p by medium 38 inside of high-dielectric coefficient at last +Distinguish the negative electrical charge absorption that 24 internal inductions go out.Therefore, the value of the maximum field that ionized donor produces in the n type layer 27 can compare qN DW/2 ∈ sMuch smaller.And in the medium 38 of high-dielectric coefficient, the electric flux line that these are come in from n type district 27 is similar to and makes it produce many ionized donors.But because ∈ DVery big, the electric field that it self is produced is less.
Fig. 5 (c) and Fig. 5 (d) are the materials of having introduced high-dielectric coefficient HK in the CB structure of present inventor's Chinese invention patent ZL91101845.X and U.S.'s patent of invention 5,216,275.
In Fig. 5 (c), when p type district 37 and n type district 27 all exhaust.In desirable situation, the electric flux line that the ionized donor positive charge in n district 27 produces is all stopped by p type district 37 ionized donors just.The overweight undesirable situation of 27 doping in the n district, then unnecessary electric flux line can enter high dielectric coefficient medium 38 inside, flows to top p then + District 24 ends at p +On the induction negative electrical charge in district 24.The 27 undesirable situations of mixing and kicking the beam in the n district are then from bottom n +There is the electric flux line that sends in district 25, and flows to p district 37 again through the medium inside of high-dielectric coefficient, ends at unnecessary ionization and is subjected on the main negative electrical charge.
In Fig. 5 (d), when n type district 27 and p type district 37 exhaust entirely.In desirable situation, the electric flux line that n district 27 ionized donor positive charges produce flows to p district 37 again through the medium of high-dielectric coefficient, stopped by main negative electrical charge by ionization there.The overweight undesirable situation of 27 doping in the n district, its unnecessary electric flux line can flow to top p again through the medium 38 of high-dielectric coefficient +District 24 ends at p +On the induction negative electrical charge in district 24.The 27 undesirable situations of mixing and kicking the beam in the n district are then from bottom n +There is the electric flux line that sends in district 25, and medium 38 inside of process high-dielectric coefficient flow to p district 37 again, end at unnecessary ionization and are subjected on the main electric charge.
In sum, the semiconductor region in the Withstand voltage layer of the present invention can be that n type district also can be p type district, and also can be two kinds has.When therefore not needing to particularly point out below, will unify to represent with semiconductor region S.
In the HKS layer, the material of high-dielectric coefficient and the arrangement of semiconductor region have many structure graphs.Fig. 6 shows some edges as the material of many high-dielectric coefficients of II-II ' section of Fig. 5 (a) and the arrangement method of semiconductor region.Mark off many cellulars by dotted line among the figure.These figures comprise interdigital figure (Fig. 6 (a)), the box-shaped cellular figure of semiconductor region full-mesh (Fig. 6 (b)), the box-shaped cellular figure of HK district full-mesh (Fig. 6 (c)), the rectangle cellular figure of semiconductor region full-mesh (Fig. 6 (d)), the rectangle cellular figure of HK district full-mesh (Fig. 6 (e)), inlay block pattern (Fig. 6 (f)), the hexagon closs packing figure of semiconductor region full-mesh (Fig. 6 (g)), the hexagon closs packing figure of HK district full-mesh (Fig. 6 (h)).
Fig. 7 (a) is a structural representation of being RMOST of the HKS layer.Its superiority can be described with an exemplary value example calculation.If what adopt is interdigital figure, each cellular is wide to be 13.04 μ m, and n district 27 and HK district 38 respectively account for a half width, and the thickness of HKS layer is 65 μ m.The donor concentration in N district is 2.0710 15Cm -3,
The relative dielectric coefficient of high-k material equals 234 (than ten times of the relative dielectric coefficient Senior Two of silicon).Do analog computation with MEDICI software, adopted master pattern, the puncture voltage that obtains is 750 volts, and conduction resistance is 30m Ω cm 2And the conduction resistance of the traditional RMOST under the same puncture voltage is 123m Ω cm 2Fig. 7 (b) and Fig. 7 (c) are illustrated in 750 volts of power supply series resistances 5.7510 respectively 7Unlatching under the Ω μ m and the transient current characteristic of closing.Used grid voltage is to change to 20 volts and change to 0 volt from 20 volts from 0 volt, can see its rising and fall time respectively being 1ns that the opening time, the turn-off time was less than 80ns less than 2ns.
Obviously, there is not the COOLMOST problem that puncture voltage descends under big electric current here, thus the problem that promptly electron charge in n district 27 destruction charge balance descends puncture voltage when conducting.On the contrary, when n district electron number increased, the space charge density in n district can descend, thereby makes increase in breakdown voltage.This makes this device that bigger safety operation area be arranged, and electric current reaches 100A/cm 2And puncture voltage remains unchanged.
Another advantage is, do not exist here built-in voltage that p district and n district are arranged resembling among the MOST that the CB structure does or electric current by the time auxiliary voltage cause the tcam-exhaustion in n district 27.Therefore conducting resistance can not increase with drain-source voltage.Just when voltage is very big, caused the saturated of the middle velocity of electrons in n district 27 (also claiming the drift region), resistance increases to some extent.
Fig. 8 is illustrated in the many structural representations of Fig. 5 (d) along the arrangement in the material of the high-dielectric coefficient of III-III ' section and n N-type semiconductor N district and p N-type semiconductor N district.These figures comprise interdigital figure (Fig. 8 (a)), n district full-mesh box-shaped cellular figure (Fig. 8 (b)), p district full-mesh box-shaped cellular figure (Fig. 8 (c)), the rectangle cellular figure of n district full-mesh (Fig. 8 (d)), the rectangle cellular figure of p district full-mesh (Fig. 8 (e)), inlay one of block pattern (Fig. 8 (f)), inlay two (Fig. 8 (g)) of block pattern, the hexagon closs packing figure of n district full-mesh (Fig. 8 (h)), the hexagon closs packing figure of p district full-mesh (Fig. 8 (i)).
Above-mentioned high-k material is not limited to a kind of single material.It in addition can be a kind of compound material.For example, in Fig. 6 (a),, between it and the high-k material a thin SiO can be arranged if semiconductor is Si 2Layer 40 separates, as shown in Figure 9.SiO is represented in shadow region among the figure 2Layer 40.Although SiO 2Dielectric coefficient very little, but as long as SiO 2Layer 40 is enough thin, do not hinder the electric flux line of semiconductor S to enter among the medium HK of high-dielectric coefficient and go, or the electric flux line enters the semiconductor S from the medium HK of high-dielectric coefficient and goes.
Figure 10 utilizes the present invention to make one of examples of implementation of VDMOST.The n that n type epitaxial loayer 42 is arranged +The silicon chip of substrate 41 obtains the situation shown in Figure 10 (a) with anisotropic caustic solution cutting.This groove has abutment wall and bottom land.Use the material filling slot of high-dielectric coefficient again, make it such shown in Figure 10 (b).In n district 27, inject formation p then through diffusion or ion + Source substrate zone 29 and n +Source region 30.Do metal electrode again, obtain the VDMOST structure shown in Figure 10 (c).
Figure 11 illustrates the another kind of n-VDMOST that utilizes the present invention to constitute.Its feature be high-dielectric coefficient material not with n +Drain region 28 directly contacts, but contacts through a n district 45.Because the existence in this n district 45, VDMOST is close n when conducting +The resistance in drain region 28 can further reduce.Although when drain D and source S added reverse voltage, also there was fraction voltage in 44 districts and 45 districts among the figure, device withstand voltage main by 43 districts, so we are n district 45 and n +Drain region 28 is as contact layer.
Figure 12 illustrates the schematic diagram of the cellular of the n-VDMOST that utilizes Fig. 5 of the present invention (d) structure to make Withstand voltage layer.
Figure 13 illustrates schematic diagram that utilize that the present invention constitutes and a cellular similar another n-VDMOST of Figure 12.Here, be with the difference of Figure 12, p district 37 not with bottom n +Drain region 28 directly links, but by a thin dielectric layer HK38 and bottom n +Drain region 28 links indirectly.Certainly, this connects p district 37 and n +The dielectric layer in drain region 28 also can not be the material of high-dielectric coefficient, but the material of thin low-k.
Figure 14 illustrates a kind of IGBT that utilizes the present invention to constitute.The main distinction of the VDMOST of it and Figure 12 is that contact layer is not n +Distinguish but a p +District 36.
Figure 15 illustrates a kind of IGBT that has resilient coating (46 district) that utilizes the present invention to constitute.The main distinction of it and Figure 14 is in contact layer, and removing has p +Substrate 36 outside, also have at p +A n on the substrate 36 + Resilient coating 46.
Above to utilizing the present invention to do many example explanations.Its described n type can be regarded the material of first kind of conduction type as, and the p type can be regarded the material of second kind of conduction type as, and obviously, according to principle of the present invention, the n type of each embodiment and p type can be exchanged and not influence content of the present invention.For the ordinary skill in the art, can also under thought guidance of the present invention, make multiple variation and multiple device.

Claims (11)

1, a kind of semiconductor device, be included in the Withstand voltage layer between the device feature layer of the contact zone of conduction and conduction, it is characterized in that described Withstand voltage layer comprises that at least one semiconductor region and at least one have the dielectric area of high-dielectric coefficient, described semiconductor region and dielectric area all contact with described device feature layer and the formed interface of contact layer, described semiconductor region and dielectric area are in contact with one another, and its formed contact-making surface is perpendicular to described contact layer and device feature layer.
2, a kind of semiconductor device as claimed in claim 1, it is characterized in that described semiconductor region and dielectric area all contact with device feature layer and the formed interface of contact layer, this contact can be direct contact, also can be by a thin semiconductor region or a thin dielectric area indirect contact.
3, a kind of semiconductor device as claimed in claim 1 is characterized in that described semiconductor region and dielectric area are in contact with one another, and this contact can be direct contact, also can be by a thin dielectric area indirect contact with low-k.
4, a kind of semiconductor device as claimed in claim 1 is characterized in that at least one described semiconductor region and at least one described dielectric area have constituted a cellular, and many described cellulars are closely arranged and constituted described Withstand voltage layer.
5, semiconductor device according to claim 1, it is characterized in that described semiconductor region is that semiconductor by first kind of conduction type constitutes, the device feature layer is that the semiconductor region that contains heavily doped second kind of conduction type constitutes, and contact layer is the semiconductor formation of heavily doped first kind of conduction type.
6, semiconductor device according to claim 1, it is characterized in that described semiconductor region is that semiconductor by first kind of conduction type constitutes, contact layer is to have the semiconductor of first kind of thin conduction type to constitute on the semiconductor of heavily doped first kind of conduction type, and the semiconductor of described thin first kind of conduction type directly contacts with Withstand voltage layer.
7, semiconductor device according to claim 1, it is characterized in that described semiconductor region had both contained the semiconductor portions of first kind of conduction type, the semiconductor portion that also contains second kind of conduction type contains the semiconductor portions of first kind of conduction type, the semiconductor portions that also contains second kind of conduction type, wherein the semiconductor equalizing of the semiconductor of first kind of conduction type and second kind of conduction type directly contacts with device feature layer and contact layer, and the device feature layer is the semiconductor region that contains heavily doped second kind of conduction type.
8, semiconductor device according to claim 1, it is characterized in that described semiconductor region had both contained the semiconductor portions of first kind of conduction type, the semiconductor portions that also contains second kind of conduction type, wherein the semiconductor of first kind of conduction type all directly contacts with device feature layer and contact layer, the semiconductor of second kind of conduction type directly contacts with the device feature layer, and by the dielectric layer of a thin high-dielectric coefficient or the dielectric layer and the contact layer indirect contact of a thin low-k, and the device feature layer is the semiconductor region that contains heavily doped second kind of conduction type.
9,, it is characterized in that between the semiconductor of described two kinds of different conduction-types be the dielectric area with high-dielectric coefficient according to claim 7 or 8 described semiconductor device.
10, semiconductor device according to claim 1 is characterized in that described contact layer is the semiconductor of heavily doped second kind of conduction type.
11, semiconductor device according to claim 1, it is characterized in that described contact layer is the semiconductor layer that first kind of thin conduction type is arranged on the semiconductor layer of heavily doped second kind of conduction type, the semiconductor layer of described thin first kind of conduction type directly contacts with Withstand voltage layer.
CNB011399570A 2001-11-21 2001-11-21 Voltage-withstanding layer consisting of high dielectric coefficient medium and semiconductor Expired - Fee Related CN1181559C (en)

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US10/504,575 US7230310B2 (en) 2001-11-21 2002-09-24 Super-junction voltage sustaining layer with alternating semiconductor and High-K dielectric regions
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