CN118138042A - Analog-to-digital converter device and analog foreground correction method - Google Patents
Analog-to-digital converter device and analog foreground correction method Download PDFInfo
- Publication number
- CN118138042A CN118138042A CN202410115779.5A CN202410115779A CN118138042A CN 118138042 A CN118138042 A CN 118138042A CN 202410115779 A CN202410115779 A CN 202410115779A CN 118138042 A CN118138042 A CN 118138042A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- corrected
- bit
- quantization
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012937 correction Methods 0.000 title claims abstract description 158
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 422
- 238000013139 quantization Methods 0.000 claims abstract description 143
- 101100134058 Caenorhabditis elegans nth-1 gene Proteins 0.000 claims description 3
- 229910002056 binary alloy Inorganic materials 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 16
- 238000004088 simulation Methods 0.000 description 10
- 230000007423 decrease Effects 0.000 description 5
- 238000004422 calculation algorithm Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 101100523544 Schizosaccharomyces pombe (strain 972 / ATCC 24843) raf1 gene Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010845 search algorithm Methods 0.000 description 3
- 101100467517 Schizosaccharomyces pombe (strain 972 / ATCC 24843) raf2 gene Proteins 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 101150007692 DOA4 gene Proteins 0.000 description 1
- 101100387924 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DOS2 gene Proteins 0.000 description 1
- 238000003705 background correction Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The present disclosure provides an analog-to-digital converter apparatus and an analog front end correction method. The device comprises: the capacitor array comprises a quantized capacitor array and a capacitor array to be corrected; a comparator circuit configured to compare an output voltage of the capacitor array with a predetermined voltage and output a comparison result; logic control circuitry configured to: in the correction period, controlling the ground voltage to be sequentially and electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low level to high level; generating error codes of each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and in the quantization period, controlling the common-mode voltage to be input into the capacitor array, and obtaining a correction code according to the corresponding comparison result and the error code output by the comparator circuit; and controlling a plurality of target quantization capacitors in the quantization capacitor array to be electrically connected with the ground voltage or the reference voltage according to the correction code, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code.
Description
Technical Field
The present disclosure relates to the field of analog-to-digital converters, and more particularly, to an analog-to-digital converter apparatus and an analog front end correction method.
Background
When the SAR ADC (Successive Approximation Register Analog to Digital Converter, successive approximation type analog-digital converter) works, due to the capacitance mismatch problem of CDAC (CAPACITANCE DIGITAL to Analog Converter, capacitance digital-analog converter) in the SAR ADC, the actual capacitance weight can deviate from an ideal value, and the generated error is larger than 1LSB (LEAST SIGNIFICANT Bit ) and even reaches tens of LSBs, so that the precision of SARADC is affected. The correction algorithm aims to reduce the influence of capacitance mismatch and improve the effective bit of the SAR ADC. Correction algorithms generally have two classification methods: one is classified according to the amount of change of correction, and can be classified into analog correction and digital correction; the other is classified according to the working phase of correction, and can be classified into foreground correction and background correction.
The conventional analog front end correction is directed to the CDAC mismatch of the binary search algorithm, comprising two CDACs, one being the master CDAC of the conventional SAR ADC and the other being the correction CDAC. The corrected CDAC is used to store a range of capacitance mismatch and is connected to the master CDAC via a series capacitance. The correction method is only suitable for SAR ADC of binary search algorithm, and requires additional correction capacitor array, and the correction algorithm is complex and consumes large power.
Disclosure of Invention
In view of the above, the present disclosure provides an analog-to-digital converter apparatus and an analog foreground correction method.
According to a first aspect of the present disclosure, there is provided an analog-to-digital converter apparatus comprising: the capacitor array comprises a quantized capacitor array and a capacitor array to be corrected; the input end of the comparator circuit is electrically connected with the upper polar plate of the capacitor array and is configured to compare the output voltage of the capacitor array with a preset voltage and output a comparison result; logic control circuitry configured to: in the correction period, controlling the ground voltage to be sequentially and electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low level to high level; generating error codes of each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and in the quantization period, controlling the common-mode voltage to be input into the capacitor array, and obtaining a correction code according to the corresponding comparison result and the error code output by the comparator circuit; and controlling a plurality of target quantization capacitors in the quantization capacitor array to be electrically connected with the ground voltage or the reference voltage according to the correction code, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code.
According to an embodiment of the disclosure, a capacitive upper plate of the capacitive array is connected to the signal input to be quantized via a bootstrap switch, and a lower plate of the capacitive array is electrically connected to the logic control circuit, so that the logic control circuit controls one of a reference voltage, a common mode voltage and a ground voltage to be electrically connected to the lower plate of each capacitor in the capacitive array, wherein the voltage value of the common mode voltage is one half of the voltage value of the reference voltage.
According to an embodiment of the present disclosure, the capacitance array to be corrected includes N capacitances to be corrected, and the weight from the 1 st capacitance to the nth capacitance to be corrected gradually decreases; the quantization capacitor array comprises M quantization capacitors, the weight of the quantization capacitor from the 1 st bit to the Mth bit is gradually reduced, the weight of the capacitor to be corrected at the N bit is larger than that of the quantization capacitor at the 1 st bit, and N and M are integers larger than 1; the correction period includes 1 st to nth correction periods; the logic control circuit is further configured to: in an nth correction period, N is greater than or equal to 1 and less than or equal to N, a control ground voltage is electrically connected with a lower electrode plate of an nth-n+1th capacitor to be corrected, and M+1th comparison results are sequentially obtained from an output end of a comparator circuit, wherein one of the control ground voltage and a reference voltage is electrically connected with the lower electrode plate of the mth quantization capacitor under the condition that the mth comparison result is obtained, and the mth+1th comparison result is obtained after the control of the mth quantization capacitor according to the mth comparison result is completed in electrical connection, and M is greater than or equal to 1 and less than or equal to M; calculating the actual weight of the N-n+1 bit capacitor to be corrected based on the weights of the M quantized capacitors and M+1 comparison results; and calculating an error code of the N-n+1 bit to-be-corrected capacitor based on the actual weight and the ideal weight of the N-n+1 bit to-be-corrected capacitor.
According to an embodiment of the present disclosure, a logic control circuit is configured to: a reset operation is performed before the nth correction period, the reset operation including electrically connecting the lower plates of all of the capacitors in the capacitor array and the comparator input to a common mode voltage.
According to an embodiment of the present disclosure, a logic control circuit is configured to: in the nth correction period, under the condition that the output voltage of the capacitor array is lower than a preset voltage, the mth output result of the comparator circuit is 0, and the reference voltage is controlled to be connected with the lower polar plate of the mth quantized capacitor; when the output voltage of the capacitor array is higher than the preset voltage, the m-th output result of the comparator circuit is 1, and the control ground voltage is connected with the lower electrode plate of the m-th quantized capacitor.
According to an embodiment of the present disclosure, a logic control circuit is configured to: under the condition that an error code of an N-n+1 bit capacitor to be corrected is obtained in an nth correction period, taking the N-n+1 bit capacitor to be corrected as a new 1 st bit quantization capacitor to obtain an M+n bit quantization capacitor; and under the condition that the error code of the 1 st bit to-be-corrected capacitor is obtained in the N correction period, recovering the 1 st bit to N-1 st bit quantized capacitor to the 2 nd bit to-be-corrected capacitor to the N th bit to-be-corrected capacitor.
According to an embodiment of the present disclosure, the quantization period includes 1 st to nth quantization periods, and the logic control circuit is further configured to control one of the ground voltage and the reference voltage to be electrically connected to a lower plate of the nth bit capacitance to be corrected in accordance with the nth bit comparison result obtained from the comparator circuit in the nth quantization period; calculating the correction code of the nth capacitance to be corrected based on the error code of the nth capacitance to be corrected, the correction code of the nth-1 capacitance to be corrected and the comparison result of the nth bit; and controlling the ground voltage to be electrically connected with the lower polar plates of a plurality of target quantized capacitors in the quantized capacitor array according to the correction code, and correcting the nth capacitor to be corrected, wherein the sum of the weights of the plurality of target quantized capacitors is equal to the correction code.
According to an embodiment of the present disclosure, the logic control circuit is configured to acquire a 1 st bit comparison result from the comparator circuit in a 1 st quantization period, and to control one of the ground voltage and the reference voltage to be electrically connected to a lower plate of the 1 st bit capacitance to be corrected; and calculating the correction code of the 1 st bit capacitor to be corrected based on the error code of the 1 st bit capacitor to be corrected and the 1 st bit comparison result.
According to an embodiment of the present disclosure, a logic control circuit is configured to: in the nth quantization period, under the condition that the output voltage of the capacitor array is lower than a preset voltage, the nth bit output result of the comparator circuit is 0, and the control reference voltage is connected with the lower polar plate of the nth bit capacitor to be corrected; and under the condition that the output voltage of the capacitor array is higher than the preset voltage, the nth bit output result of the comparator circuit is 1, and the control ground voltage is connected with the lower electrode plate of the nth bit capacitor to be corrected.
According to an embodiment of the present disclosure, the capacitor array includes a first capacitor array and a second capacitor array, and specifications of the first capacitor array and the second capacitor array are completely consistent; the upper electrode plate of the first capacitor array is electrically connected to the positive input end of the comparator circuit, and the upper electrode plate of the second capacitor array is electrically connected to the negative input end of the comparator circuit;
According to an embodiment of the present disclosure, a logic control circuit is configured to: sequentially acquiring error codes of the first capacitor array and the second capacitor array in a correction period; in the quantization period, the first capacitor array and the second capacitor array are sequentially corrected based on the error code and the comparison result output from the comparator circuit.
A second aspect of the present disclosure provides an analog foreground correction method, comprising: the logic control circuit controls the ground voltage to be electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low to high in sequence; the logic control circuit generates error codes of each capacitor to be corrected according to the comparison result output by the comparator circuit, wherein the comparator circuit compares the output voltage of the capacitor array with a preset voltage and outputs the comparison result, and the capacitor array comprises a capacitor array to be corrected and a quantized capacitor array; the logic control circuit controls the common mode voltage to be input into the capacitor array; the logic control circuit obtains a correction code according to the comparison result output by the comparator circuit and the error code; the logic control circuit controls a plurality of target quantization capacitances in the quantization capacitance array to be electrically connected to a ground voltage or a reference voltage based on the correction code, wherein a sum of weights of the plurality of target quantization capacitances is equal to the correction code.
Drawings
The foregoing and other objects, features and advantages of the disclosure will be more apparent from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:
fig. 1A schematically illustrates a block diagram of an analog-to-digital converter apparatus according to an embodiment of the present disclosure;
Fig. 1B schematically illustrates yet another block diagram of an analog-to-digital converter apparatus according to an embodiment of the present disclosure;
fig. 1C schematically illustrates a block diagram of a capacitor array in an analog-to-digital converter apparatus according to an embodiment of the disclosure;
fig. 2 schematically illustrates a flow chart of a capacitive array of an analog-to-digital converter apparatus during a correction period according to an embodiment of the present disclosure;
fig. 3A schematically illustrates a block diagram of a capacitor array of an analog-to-digital converter apparatus during a quantization period according to an embodiment of the present disclosure;
fig. 3B schematically illustrates a flow chart of an analog-to-digital converter apparatus during a quantization period according to an embodiment of the present disclosure;
FIG. 4A schematically illustrates a simulation result diagram of an analog-to-digital converter apparatus without correction according to an embodiment of the present disclosure;
FIG. 4B schematically illustrates a simulation result diagram of an analog-to-digital converter apparatus with digital correction in accordance with an embodiment of the present disclosure;
Fig. 4C schematically illustrates a simulation result diagram in the case where an analog-to-digital converter apparatus according to an embodiment of the present disclosure is corrected by an analog foreground correction method;
FIG. 5 schematically illustrates a flow chart of an analog foreground correction method according to an embodiment of the disclosure;
Fig. 6 schematically illustrates yet another flow chart of an analog foreground correction method according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a convention should be interpreted in accordance with the meaning of one of skill in the art having generally understood the convention (e.g., "a system having at least one of A, B and C" would include, but not be limited to, systems having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).
Embodiments of the present disclosure provide an analog-to-digital converter apparatus including: the capacitor array comprises a quantized capacitor array and a capacitor array to be corrected; the input end of the comparator circuit is electrically connected with the upper polar plate of the capacitor array and is configured to compare the output voltage of the capacitor array with a preset voltage and output a comparison result; logic control circuitry configured to: in the correction period, controlling the ground voltage to be sequentially and electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low level to high level; generating error codes of each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and in the quantization period, controlling the common-mode voltage to be input into the capacitor array, and obtaining a correction code according to the corresponding comparison result and the error code output by the comparator circuit; and controlling a plurality of target quantization capacitors in the quantization capacitor array to be electrically connected with the ground voltage or the reference voltage according to the correction code, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code.
Fig. 1A-1C schematically illustrate block diagrams of the architecture of an analog-to-digital converter apparatus according to an embodiment of the present disclosure.
As shown in fig. 1A, the analog-digital converter apparatus 10 of this embodiment includes a capacitor array 11, a comparator circuit 12, and a logic control circuit 13.
The capacitor array 11 includes a quantization capacitor array and a capacitor array to be corrected.
The positive input terminal of the comparator circuit 12 is electrically connected to the upper plate of the capacitor array 11, the negative input terminal of the comparator circuit has an input of a predetermined voltage, and the comparator circuit compares the output voltage of the capacitor array with the predetermined voltage and outputs the comparison result.
The logic control circuit receives the comparison result of the comparator circuit and controls the connection of the capacitor array according to the comparison result. In the correction period, controlling the ground voltage to be sequentially and electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low level to high level; generating error codes of each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and in the quantization period, controlling the common-mode voltage to be input into the capacitor array, and obtaining a correction code according to the corresponding comparison result and the error code output by the comparator circuit; and controlling a plurality of target quantization capacitors in the quantization capacitor array to be connected with the ground voltage according to the correction code, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code.
The analog to digital converter device in the present disclosure includes two phases of operation: a correction phase and a quantization phase. In the correction stage, the SAR ADC measures and stores the mismatch quantity of the high-order capacitor array through the low-order capacitor array; in the normal working stage, the mismatch quantity stored in the correction stage is converted into analog quantity through the correction CDAC and is overlapped in the quantization process of the high-order capacitor array, so that the mismatch of the high-order capacitor array is eliminated. Compared with the traditional correction method, the correction method does not need an extra correction capacitor array, saves the area, omits the step of generating error voltage by switching the switch back and forth, and has simple correction logic and low power consumption.
Fig. 1B schematically illustrates yet another block diagram of an analog-to-digital converter apparatus according to an embodiment of the present disclosure.
As shown in fig. 1B, the upper plate of the capacitor array is connected to a common-mode voltage V CM through a bootstrap switch, the lower plate of the capacitor array is electrically connected to a logic control circuit 13 through a multiplexer, and the logic control circuit controls one of a signal to be sampled V IN, a reference voltage V REF, a ground voltage GND and a common-mode voltage V CM through the multiplexer based on a comparison result output by the comparator circuit, and is electrically connected to the lower plate of each capacitor in the capacitor array, wherein the voltage value of the common-mode voltage V CM is one half of the voltage value of the reference voltage V REF.
Fig. 1C schematically illustrates a block diagram of a capacitor array in an analog-to-digital converter apparatus according to an embodiment of the disclosure.
As shown in fig. 1C, the capacitor array 11 includes a quantization capacitor array 11_1 and a capacitor array 11_2 to be corrected.
The capacitance array 11_2 to be corrected may include N capacitances to be corrected, the weight of which gradually decreases from the 1 st capacitance to the nth capacitance to be corrected; the quantization capacitor array 11_1 may include M quantization capacitors, the weights of the 1 st quantization capacitor to the M quantization capacitor gradually decrease, and the weight of the nth quantization capacitor to be corrected is greater than the 1 st quantization capacitor, and the weights of all the capacitors to be corrected and the quantization capacitors satisfy the sub-binary condition, where N and M are integers greater than 1. Wherein the sub-binary condition is that the sum of the weight values of the first i-bit capacitors is larger than the weight value of the (i+1) -th capacitor in the arrangement sequence from small to large.
All the capacitors in the capacitor array 11 are divided into a high-order capacitor and a low-order capacitor according to the capacitor weight, the high-order capacitor and the low-order capacitor are separated by a bridge capacitor C BR, the capacitor positioned at the left side of C BR is the low-order capacitor, and the capacitor positioned at the right side of C BR is the high-order capacitor. All the capacitances in the capacitor array gradually decrease from the right to the left, where the capacitor array 11_2 to be corrected is selected and composed of a plurality of high-order capacitances with the largest capacitance weights, and the high-order capacitances have a larger influence on ENOB (EFFECTIVE NUMBER OF BITS, effective bit number) due to the large weight and the occurrence of capacitance mismatch, so that correction is required. The number of bits of the capacitor to be corrected is not a fixed value, modeling can be performed by using simulation tools such as Matlab, capacitance mismatch is added as an influence factor, and the correction effect is good when the number of bits of the capacitor to be corrected is judged through simulation verification.
For example, in 14bit 20step SAR ADC used in the embodiment of the present disclosure, the first five bits with the highest weight value in the high-order capacitors are selected as the capacitor array to be corrected, and the remaining high-order capacitors and all low-order capacitors are selected as the quantized capacitor array. The weighting arrangement for all capacitances is shown in the following table:
where MSB refers to the high-order capacitance and LSB refers to the low-order capacitance. CM10-CM6 are the 1 st to 5 th to correct the electric capacity, CM5-CM1, CL9-CL1 total 14 electric capacity are the 1 st to 14 th quantized electric capacity separately. Since CDAC in 14bit 20stepSAR ADC is 8+6 structure, where 8bit refers to the effective number of high-order capacitor, 6bit refers to the effective number of low-order capacitor, and VCM-based switching mode is adopted, the most significant number of capacitors is omitted, so that the unit number of capacitors used in the high Duan Dianrong array is 2 7 =128, the unit number of capacitors used in the low-order capacitor is 2 6 -1=63, the bridge capacitor is 1 unit capacitor, and the total is 128+63+1=192 capacitors. On the distribution of capacitance values, split recombination is performed on a binary basis.
For example, the sum of the capacitance values of the nine low-order capacitances CL1 to CL9 in the table is 63, and the allocations are made based on 1,2,4,8, 16, 32 represented by the 6 significant digits in the binary, with 2 being broken down into 1 and 1, 8 being broken down into 2 and 6, and 32 being broken down into 10 and 22. And recombining the undetached number and the dismantling result to obtain 1,1,1,2,4,6, 10, 16 and 22 as capacitance values of the nine-bit low-order capacitor. The allocation method of the high-order capacitor is the same as that of the low-order capacitor, and will not be described here again.
As shown in the above table, the high-order capacitance differs less from the low-order capacitance in capacitance value, but the weight value differs more. The adjustment of the weight value can be realized by a bridging capacitor, and the bridging capacitor has the function of adding a weight coefficient to the weight of the low-stage capacitorC LSB refers to the sum of the capacitance values of the low-order capacitors, C BR refers to the capacitance value of the bridge capacitor, so in the present disclosure, the weighting coefficient of the low-order capacitance weighting value is 1/64, and in the case that the high-order capacitance corresponds to 64 weighting values per 1 unit capacitance value, the low-order capacitance corresponds to 1 weighting value per 1 unit capacitance value.
The comparator circuit 12 is configured to compare an output voltage of the capacitor array with a predetermined voltage and output a comparison result.
And when the output voltage is smaller than the preset voltage, the comparison result is 0, and when the output voltage is larger than the preset voltage, the comparison result is 1. The preset voltage may be the common-mode voltage V CM or may be preset.
As shown in fig. 1A, the comparator circuit may be a differential comparator circuit, including a dual-end input, where two input ends are respectively connected to an output end of the capacitor array and a preset voltage.
As shown in fig. 1B, in the embodiment of the disclosure, two input ends of the comparator circuit are respectively electrically connected with the P-end and the N-end of the capacitor array, and when the capacitor array of the P-end is corrected and quantized, the lower plates of all capacitors of the N-end are electrically connected with the common mode voltage, so that the output voltage of the N-end can be equivalent to a constant value and the same as the common mode voltage. The comparator circuit may further include a double-ended output, the comparison results of the two output terminals OUTP and OUTN being different each time, and when the comparison result of one output terminal is 1, the comparison result of the other output terminal is 0. When the input voltage of the end of the capacitor array P is input, the comparator circuit takes the output of the output end OUTP as a comparison result.
The logic control circuit 13 may be divided into a correction period and a quantization period.
During the correction period, the logic control circuit is configured to: the ground voltage is controlled to be electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low to high in sequence; and generating error codes of each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit.
During the quantization period, the logic control circuit is configured to: controlling common-mode voltage to be input into a capacitor array, and obtaining a correction code according to a corresponding comparison result and an error code output by a comparator circuit; and controlling a plurality of target quantization capacitors in the quantization capacitor array to be connected with the ground voltage according to the correction code, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code.
In some embodiments of the present disclosure, the capacitive array may include a first capacitive array and a second capacitive array. As shown in fig. 1B and 1C, the capacitor array is divided into a first capacitor array P end and a second capacitor array N end, where the P end is the upper half of the capacitor array and the N end is the lower half of the capacitor array, and the specifications of the first capacitor array and the second capacitor array are completely consistent. The upper plate of the first capacitor array is electrically connected to the positive input of the comparator circuit, and the upper plate of the second capacitor array is electrically connected to the negative input of the comparator circuit. The logic control circuit is configured to: sequentially acquiring error codes of the first capacitor array and the second capacitor array in a correction period; in the quantization period, the first capacitor array and the second capacitor array are sequentially corrected based on the error code and the comparison result output from the comparator circuit.
The two output ends of the comparator circuit respectively output a comparison result OUTP of the first capacitor array end and a comparison result OUTN of the second capacitor array section. When the first capacitor array is quantized and corrected, the lower polar plates of all capacitors in the second capacitor array are electrically connected with the common-mode voltage V CM, which is equivalent to comparing the output voltage of the first capacitor array with the common-mode voltage V CM, and the comparison result output by the comparator circuit is consistent with the OUTP; and when the second capacitor array is quantized and corrected, the lower electrode plates of all the capacitors in the first capacitor array are electrically connected with the common-mode voltage V CM, which is equivalent to comparing the output voltage of the second capacitor array with the common-mode voltage V CM, and the comparison result output by the comparator circuit is consistent with the OUTN. The correction principles of the first capacitor array and the second capacitor array are completely consistent and can be respectively and independently performed.
The analog-to-digital converter device in this disclosure employs a SAR ADC of a segmented capacitive array. After the chip is electrified and before normal operation, the capacitor mismatch is eliminated in an analog domain, the method is suitable for SAR ADC of a non-binary search algorithm, no requirement is required for specific weight distribution of the capacitor, and the flexibility is high. Compared with the traditional method, the method does not need an extra correction capacitor array, saves the area, omits the step of generating error voltage by switching the switch back and forth, and has simple correction logic and low power consumption.
Fig. 2 schematically illustrates a flow chart of a capacitive array of an analog-to-digital converter apparatus during a correction period according to an embodiment of the present disclosure.
The correction period includes 1 st to nth correction periods. And measuring and storing error codes of the N-n+1-bit capacitors to be corrected in the nth correction period, and obtaining error codes of N capacitors to be corrected in the correction period.
In an embodiment of the present disclosure, the logic control circuit is further configured to: in an nth correction period, N is greater than or equal to 1 and less than or equal to N, a control ground voltage is electrically connected with a lower electrode plate of an nth-n+1th capacitor to be corrected, and M+1th comparison results are sequentially obtained from an output end of a comparator circuit, wherein one of the control ground voltage and a reference voltage is electrically connected with the lower electrode plate of the mth quantization capacitor under the condition that the mth comparison result is obtained, and the mth+1th comparison result is obtained after the control of the mth quantization capacitor according to the mth comparison result is completed in electrical connection, and M is greater than or equal to 1 and less than or equal to M; calculating the actual weight of the N-n+1 bit capacitor to be corrected based on the weights of the M quantized capacitors and M+1 comparison results; and calculating an error code of the N-n+1 bit to-be-corrected capacitor based on the actual weight and the ideal weight of the N-n+1 bit to-be-corrected capacitor.
For example, the apparatus of the present disclosure includes a 5-bit to-be-corrected capacitance and a 14-bit quantized capacitance. In the 1 st correction period, the control ground voltage GND is electrically connected with the lower pole plate of the 5 th capacitor to be corrected, at this time, the input voltage of the input end electrically connected with the capacitor array in the comparator circuit changes, so that the two input ends generate a voltage difference, the comparator circuit outputs a1 st comparison result based on the voltage of the two input ends, and the logic control circuit controls the multiplexer to selectively electrically connect the reference voltage or the ground voltage with the lower pole plate of the 1 st quantization capacitor based on the 1 st comparison result. And repeating the two steps of obtaining the comparison result and controlling the connection of the quantization capacitors until M comparison results are obtained in total, and obtaining the M+1st bit comparison result after the connection of the M-bit quantization capacitors is completed, wherein the 1 st correction period is ended. Under the condition that the output voltage of the capacitor array is lower than a preset voltage, the m-th output result of the comparator circuit is 0, and the control reference voltage is connected with the lower polar plate of the m-th quantized capacitor; when the output voltage of the capacitor array is higher than the preset voltage, the m-th output result of the comparator circuit is 1, and the control ground voltage is connected with the lower electrode plate of the m-th quantized capacitor.
In the embodiment of the disclosure, the specific process of calculating the actual weight of the N-n+1-th to-be-corrected capacitor based on the weight of the M quantized capacitors and the m+1 comparison results, and calculating the error code of the N-n+1-th to-be-corrected capacitor based on the actual weight of the N-n+1-th to-be-corrected capacitor and the ideal weight is as follows:
Actual weight = Σ (1-2×d i) ×ith quantized capacitance weight+d M+1
Wherein D i is the ith bit of comparison result, and D M+1 is the (M+1) th bit of comparison result. Taking the 5 th quantized capacitor as an example, the comparison result determines the positive and negative of the corresponding quantized capacitor weight value. For example, the quantized capacitance array weights are [256, 128, 64, 64, 64, 22, 16, 10,6,4,2,1,1,1], and the comparison result is [0,0,1,0,1,0,0,0,0,0,0,0,1,1,1]. The actual weight of the 5 th bit capacitor is 379. Obtaining a weight sequence [256, 128, -64, 64, -64, 22, 16, 10,6,4,2, -1, -1, -1], summing the weight sequence and the M+1th bit comparison result to obtain an error code of the 5 th bit capacitor equal to the actual weight minus the ideal weight: 379-384= -5, the logic control circuit stores the error code in the form of a binary code.
In the embodiment of the disclosure, under the condition that an error code of an N-n+1 bit capacitor to be corrected is obtained in an nth correction period, taking the N-n+1 bit capacitor to be corrected as a new 1 st bit quantization capacitor to obtain an M+n bit quantization capacitor; and under the condition that the error code of the 1 st bit to-be-corrected capacitor is obtained in the N correction period, recovering the 1 st bit to N-1 st bit quantized capacitor to the 2 nd bit to-be-corrected capacitor to the N th bit to-be-corrected capacitor.
For example, after calculating the error code of the 5 th bit capacitor to be corrected in the 1 st correction period, the 5 th bit capacitor to be corrected becomes a new 1 st bit quantized capacitor in the quantized capacitor array, the calculated actual weight is used as the weight of the 1 st bit quantized capacitor, and the weight of the 14 th bit quantized capacitor in the original quantized capacitor array is unchanged, and becomes the 2 nd bit to 15 th bit quantized capacitor. When quantizing the 4 th quantization capacitor, the weight of each quantization capacitor in the quantization capacitor array is respectively: [379, 256, 128, 64, 64, 64, 22, 16, 10,6,4,2,1,1,1].
The logic control circuit is configured to: a reset operation is performed before the nth correction period, the reset operation including electrically connecting the lower plates of all of the capacitors in the capacitor array and the comparator input to a common mode voltage.
As shown in fig. 2, in the correction period, the first step is to electrically connect the lower plates of all the capacitors in the capacitor array with the common mode voltage to change to the reset state; the second step is that the correction period 1 is that the lower polar plate of the 5 th capacitor to be corrected is connected with the ground voltage, and the actual weight and the error code of the 5 th capacitor to be corrected are calculated according to the comparison result and the weight of the quantized capacitor; the third step is to continue to electrically connect the lower polar plates of all the capacitors in the capacitor array with common mode voltage and restore to a reset state; the fourth step is the 2 nd correction period, the 5 th capacitor to be corrected is used as a quantization capacitor, and the 4 th capacitor to be corrected is connected with the ground voltage for correction; and repeating the reset operation and the correction operation until the actual capacitance and the error code of the 1 st bit capacitance to be corrected are obtained through calculation.
Fig. 3A schematically illustrates a block diagram of a capacitor array of an analog-to-digital converter apparatus during a quantization period according to an embodiment of the present disclosure.
Fig. 3B schematically illustrates a flowchart of an analog-to-digital converter apparatus during a quantization period according to an embodiment of the present disclosure.
As shown in fig. 3A, the lower capacitor in the capacitor array is quantized in the frame, and the capacitor to be corrected is corrected and compensated by the lower capacitor by controlling the lower plate of the capacitor in the frame in the quantization period.
The quantization period includes 1 st quantization period to nth quantization period. The logic control circuit is further configured to control one of the ground voltage and the reference voltage to be electrically connected to the lower plate of the n-th bit capacitance to be corrected in accordance with the n-th bit comparison result obtained from the comparator circuit in the n-th quantization period; calculating the correction code of the nth capacitance to be corrected based on the error code of the nth capacitance to be corrected, the correction code of the nth-1 capacitance to be corrected and the comparison result of the nth bit; and controlling ground voltage or reference voltage to be electrically connected with lower polar plates of a plurality of target quantization capacitors in the quantization capacitor array according to the correction code, and correcting the nth capacitor to be corrected, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code, and N is an integer greater than 0 and less than or equal to N.
In addition, in the 1 st quantization period, a1 st bit comparison result is obtained from the comparator circuit, and one of the ground voltage and the reference voltage is controlled to be electrically connected with the lower electrode plate of the 1 st bit capacitor to be corrected; and calculating the correction code of the 1 st bit capacitor to be corrected based on the error code of the 1 st bit capacitor to be corrected and the 1 st bit comparison result.
In the embodiment of the disclosure, the quantization period is performed in the normal working period of the SAR ADC, the lower plates of the first capacitor array and the second capacitor array are electrically connected to the input voltages V INN and V INP, respectively, after the SAR ADC acquires the input signal and finishes the sampling processing of the signal, the lower plates of all the capacitors are electrically connected to the common mode voltage V CM, and enter the quantization period to quantize the sampled input signal, and at this time, in the first capacitor array and the second capacitor array, the capacitors are electrically connected to the ground voltage and the reference voltage in opposite conditions. For example, when the first bit comparison result is1, as shown in fig. 3A, the 1 st bit to-be-corrected capacitor of the first capacitor array is grounded, and the 1 st bit to-be-corrected capacitor of the second capacitor array is grounded; the logic control circuit controls the lower plate of the target quantization capacitor in the first capacitor array to be electrically connected with the reference voltage when the correction code of the first capacitor array is positive, and controls the lower plate of the target quantization capacitor in the second capacitor array to be electrically connected with the ground voltage when the correction code of the second capacitor array is positive.
As shown in fig. 3B, the analog-to-digital converter apparatus of this embodiment includes operations S301 to S311 in the quantization period.
In operation S301, the comparator circuit outputs a first comparison result. One of the control ground voltage and the reference voltage is electrically connected with the lower polar plate of the 1 st capacitance to be corrected.
In operation S302, a correction code DOS1 of the 1 st bit capacitance to be corrected is calculated according to the 1 st bit comparison result. Operation S303 or operation S304 is selected based on the comparison result.
In operation S303, in the case that the comparison result is 1, the correction code dos1=diff1, and the control ground voltage is electrically connected to the lower plate of the 1 st bit capacitance to be corrected.
In operation S304, in the case that the comparison result is 0, the correction code dos1= -Diff1, the control reference voltage is electrically connected to the lower plate of the 1 st bit capacitor to be corrected.
In operation S305, the 1 st bit capacitance to be corrected is corrected and compensated according to the 1 st bit correction code. The logic control circuit selects part of the capacitors in the quantization capacitor array as target quantization capacitors based on the correction codes, and realizes quantization of the capacitors to be corrected by controlling the lower polar plate of the target quantization capacitors to be electrically connected with the ground voltage or the reference voltage. The correction code and the lower polar plate access state of each quantization capacitor in the quantization capacitor array are in one-to-one correspondence, the correction code is stored in the logic control circuit in advance, the quantization capacitor needing to be electrically connected with the ground voltage or the reference voltage is selected as the target quantization capacitor under the condition of obtaining the correction code, the target quantization capacitor is directly controlled by the logic control circuit, and the weight sum of the target quantization capacitor is equal to the calibration code. The target quantization capacitor is electrically connected with the reference voltage when the correction code is positive, and the target quantization capacitor is electrically connected with the ground voltage when the correction code is negative.
In operation S306, the comparator circuit outputs the comparison result of the nth time, N being an integer greater than 1 and less than or equal to N.
In operation S307, the correction code DOSn of the n-th capacitance to be corrected is calculated according to the n-th comparison result, and the n+1-th comparison result is output. Operation S308 or operation S309 is selected to be performed based on the n-th bit comparison result.
In operation S308, in the case that the comparison result of the nth bit is 1, the control ground voltage is electrically connected to the lower plate of the nth bit to be corrected capacitor, and the correction code DOSn =dos (n-1) + Diffn of the nth bit to be corrected capacitor.
In operation S309, in the case where the n-th bit comparison result is 0, the control ground voltage is electrically connected to the lower plate of the n-th bit to-be-corrected capacitor, and the correction code DOSn =dos (n-1) -Diffn of the n-th bit to-be-corrected capacitor.
For example, after quantizing the 1 st bit capacitance to be corrected, the comparator circuit outputs the 2 nd comparison result. The error code of the 2 nd capacitor to be corrected is Diff2, and under the condition that the comparison result is 1, the control ground voltage is electrically connected with the lower polar plate of the 2 nd capacitor to be corrected, and the correction code DOS2=DOS·+diff2 of the 2 nd capacitor to be corrected; and under the condition that the comparison result is 0, the control reference voltage is electrically connected with the lower electrode plate of the 2 nd bit capacitor to be corrected, and the correction code dos2=dos1-diff2.
In operation S310, the nth capacitance to be corrected is quantized according to the nth correction code DOSn. Operations S307 to S310 are repeated until the n+1th bit comparison result is output, at which time the N-bit capacitance to be corrected completes the quantization of the input signal.
In operation S311, the comparison result from the n+2th bit to the n+m+1 th bit is continuously obtained, and the input signal is quantized by the quantization capacitor array. And controlling the lower electrode plates of M quantization capacitors in the quantization capacitor array to be electrically connected with the ground voltage or the reference voltage according to the N+I bit comparison result and the N+2 bit to N+M bit comparison result output in the operation S310, acquiring the N+M+1 bit comparison result after determining the access state of the M quantization capacitors, finishing the quantization of the input signals by the M quantization capacitors, and ending the quantization period. When the ith bit comparison result is obtained (i is an integer greater than N and less than or equal to N+M), if the corresponding quantization capacitor is the target quantization capacitor, determining the access state of the target quantization capacitor again based on the comparison result, and determining whether to change the access state of the target quantization capacitor according to the current access state of the target quantization capacitor. The target quantization capacitor is electrically connected with the ground voltage when the comparison result is 1, and the target quantization capacitor is electrically connected with the reference voltage when the comparison result is 0. If the corresponding quantization capacitor is not the target quantization capacitor, the access state is not changed.
For example, if the comparison result is 1, and the lower plate of the corresponding target quantization capacitor is electrically connected with the reference voltage at this time, the lower plate of the corresponding target quantization capacitor is controlled to be connected with the ground voltage instead; if the comparison result is 1 and the lower polar plate of the corresponding target quantization capacitor is connected with the ground voltage, the access state is not changed.
In the embodiment of the disclosure, after the quantization capacitor is quantized based on the correction code of the 2 nd to-be-corrected capacitor, the 3 rd to 5 th comparison results are continuously obtained, the 3 rd to 5 th to-be-corrected capacitor is quantized according to the correction code of the 3 rd to 5 th, the 6 th to 19 th comparison results are obtained, the 1 st to 14 th quantization capacitor is quantized, and the quantization period is ended.
Fig. 4A schematically shows a simulation result diagram of the analog-digital converter apparatus in the case where correction is not performed.
As shown in fig. 4A, in the case where correction is not performed, as the capacitance mismatch coefficient increases, the effective bit number ENOB of the SAR ADC tends to decrease, and the larger the capacitance mismatch coefficient is, the greater the influence on the accuracy of the SAR ADC is, and therefore, in order to reduce the influence of capacitance mismatch on the SAR ADC, the correction is required.
Fig. 4B schematically shows a simulation result diagram of the analog-digital converter apparatus in the case of performing only digital correction.
Fig. 4C schematically illustrates a simulation result diagram in the case where the analog-to-digital converter apparatus according to the embodiment of the present disclosure is corrected by the analog foreground correction method. In the result diagrams of fig. 4A to 4C, the abscissa indicates the capacitance mismatch coefficient, and the ordinate indicates the effective number ENOB of the SAR ADC.
As shown in fig. 4B and 4C, comparing the simulation result graphs of fig. 4B for digital correction and fig. 4C for analog front-end correction by the apparatus of the present disclosure, it can be found that the effective number of bits for analog front-end correction by the present disclosure is significantly higher than that for digital correction in the first half of the broken line in the graph with a capacitance mismatch coefficient of 0.01 or less. This is because the ideal case of analog correction is a case that can be corrected to approach 0 mismatch, which means that the significant bit number ENOB reaches the ideal value of 13.78bit, whereas in the simulation diagram of fig. 4C subjected to analog front-end correction of the present disclosure, the corrected ENOB can approach 13.78bit when the capacitance mismatch coefficient is lower than 0.01. Thus the analog front end correction scheme using the present design is superior to using digital correction with a capacitance mismatch of 1% or less.
Fig. 5 schematically illustrates a flow chart of an analog foreground correction method according to an embodiment of the present disclosure.
As shown in fig. 5, the analog foreground correction method of this embodiment includes operations S501 to S504.
In operation S501, the logic control circuit performs a reset operation on the capacitor array.
In operation S502, the logic control circuit calculates an error code of a capacitance to be corrected based on the comparison result and the quantized capacitance array.
In operation S503, the logic control circuit updates the weight of the capacitor to be corrected, uses the capacitor to be corrected as the 1 st bit quantization capacitor of the quantization capacitor array, and repeats operations S501-S503 until the error codes of all the capacitors to be corrected are obtained.
In operation S504, the logic control circuit performs weight compensation on the capacitance to be corrected by controlling the low-order capacitance in the quantized capacitance array based on the error code.
Fig. 6 schematically illustrates yet another flow chart of an analog foreground correction method according to an embodiment of the present disclosure.
As shown in fig. 6, the analog foreground correction method of this embodiment includes operations S610 to S650.
In operation S610, the logic control circuit controls to electrically connect the ground voltage with each capacitance to be corrected in the array of capacitances to be corrected in sequence from a low order to a high order.
In operation S620, the logic control circuit generates an error code for each capacitor to be corrected according to the comparison result output by the comparator circuit, wherein the comparator circuit compares the output voltage of the capacitor array with the preset voltage, and outputs the comparison result, and the capacitor array includes the capacitor array to be corrected and the quantized capacitor array.
In operation S630, the logic control circuit controls the input of the common mode voltage to the capacitor array.
In operation S640, the logic control circuit obtains a correction code according to the comparison result output from the comparator circuit and the error code.
In operation S650, the logic control circuit controls a plurality of target quantization capacitances in the quantization capacitance array to be electrically connected to the ground voltage or the reference voltage based on the correction code, wherein a sum of weights of the plurality of target quantization capacitances is equal to the correction code.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the description and the claims to modify a corresponding element does not by itself connote any ordinal number of elements or the order of manufacturing or use of the ordinal numbers in a particular claim, merely for enabling an element having a particular name to be clearly distinguished from another element having the same name.
Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.
It should be noted that, unless there is an execution sequence between different operations or an execution sequence between different operations in technical implementation, the execution sequence between multiple operations may be different, and multiple operations may also be executed simultaneously in the embodiment of the disclosure.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present disclosure is not directed to any particular programming language. It will be appreciated that the disclosure described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present disclosure.
The disclosure may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. Various component embodiments of the present disclosure may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a related device according to embodiments of the present disclosure may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present disclosure may also be embodied as a device or apparatus program (e.g., computer program and computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present disclosure may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
All of the modules of the embodiments of the present disclosure may be hardware structures, the physical implementation of which includes, but is not limited to, physical devices including, but not limited to, transistors, memristors.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also, in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (12)
1. An analog to digital converter apparatus comprising:
The capacitor array comprises a quantized capacitor array and a capacitor array to be corrected;
the input end of the comparator circuit is electrically connected with the upper polar plate of the capacitor array and is configured to compare the output voltage of the capacitor array with a preset voltage and output a comparison result;
Logic control circuitry configured to:
In the correction period, controlling the ground voltage to be sequentially and electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low level to high level; generating error codes of each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and
In the quantization period, controlling common-mode voltage to be input to the capacitor array, and obtaining a correction code according to a corresponding comparison result output by the comparator circuit and the error code; and controlling a plurality of target quantization capacitors in the quantization capacitor array to be electrically connected with the ground voltage or the reference voltage according to the correction code, wherein the sum of weights of the plurality of target quantization capacitors is equal to the correction code.
2. The apparatus of claim 1, wherein the capacitive upper plates of the capacitive array are connected to a common mode voltage via a bootstrap switch, and the lower plates of the capacitive array are electrically connected to the logic control circuit through a multiplexer such that the logic control circuit is electrically connected to the lower plates of each of the capacitors in the capacitive array according to one of a multiplexer control signal to be sampled, a reference voltage, a ground voltage, and the common mode voltage, wherein a voltage value of the common mode voltage is one-half a voltage value of the reference voltage.
3. The apparatus according to claim 1 or 2, wherein the capacitance array to be corrected includes N capacitances to be corrected, the weight of the capacitances to be corrected gradually decreasing from the 1 st bit to the nth bit; the quantization capacitor array comprises M quantization capacitors, the weights of the quantization capacitors from the 1 st quantization capacitor to the Mth quantization capacitor are gradually reduced, the weight of the N-th capacitor to be corrected is larger than that of the 1 st quantization capacitor, the weights of all the capacitors to be corrected and the quantization capacitors meet the condition of sub-binary system, and N and M are integers larger than 1; the correction period includes 1 st to nth correction periods;
the logic control circuit is further configured to: in the N correction period, N is 1 or more and N or less,
Controlling the ground voltage to be electrically connected with a lower polar plate of an N-n+1 bit capacitor to be corrected, and sequentially acquiring M+1 bit comparison results from the output end of the comparator circuit, wherein under the condition that an mth bit comparison result is acquired, one of the ground voltage and the reference voltage is controlled to be electrically connected with the lower polar plate of the mth bit quantization capacitor, and the M+1 bit comparison result is acquired after the mth bit quantization capacitor is controlled to be electrically connected according to the mth bit comparison result, wherein M is more than or equal to 1 and less than or equal to M;
calculating the actual weight of the N-n+1 bit capacitor to be corrected based on the weights of the M quantized capacitors and the M+1 comparison results; and
And calculating an error code of the N-n+1 bit capacitor to be corrected based on the actual weight and the ideal weight of the N-n+1 bit capacitor to be corrected.
4. The apparatus of claim 3, wherein,
The logic control circuit is configured to:
And performing a reset operation before the nth correction period, wherein the reset operation comprises the step of electrically connecting the lower polar plates of all capacitors in the capacitor array and the comparator input end with the common mode voltage.
5. The apparatus of claim 3, wherein the logic control circuit is configured to: in the n-th correction period of time,
When the output voltage of the capacitor array is lower than the preset voltage, the m-th output result of the comparator circuit is 0, and the control reference voltage is connected with the lower polar plate of the m-th quantized capacitor;
And under the condition that the output voltage of the capacitor array is higher than the preset voltage, the m-th output result of the comparator circuit is 1, and the control ground voltage is connected with the lower polar plate of the m-th quantized capacitor.
6. The apparatus of claim 3, wherein the logic control circuit is configured to: under the condition that an error code of an N-n+1 bit capacitor to be corrected is obtained in an nth correction period, taking the N-n+1 bit capacitor to be corrected as a new 1 st bit quantization capacitor to obtain an M+n bit quantization capacitor; and
And under the condition that the error code of the 1 st bit to-be-corrected capacitor is obtained in the N correction period, recovering the 1 st bit to N-1 st bit quantized capacitor to the 2 nd bit to-be-corrected capacitor to the N th bit to-be-corrected capacitor.
7. The apparatus of claim 1 or 3, wherein the quantization period comprises 1 st quantization period through nth quantization period,
The logic control circuit is further configured to,
According to the comparison result of the nth bit obtained from the comparator circuit, one of the ground voltage and the reference voltage is controlled to be electrically connected with the lower polar plate of the capacitor to be corrected of the nth bit;
calculating the correction code of the nth to-be-corrected capacitor based on the error code of the nth to-be-corrected capacitor, the correction code of the nth-1 to-be-corrected capacitor and the nth comparison result;
And controlling ground voltage to be electrically connected with lower polar plates of a plurality of target quantized capacitors in the quantized capacitor array according to the correction code, wherein the ground voltage is used for correcting the nth capacitor to be corrected, and the sum of weights of the plurality of target quantized capacitors is equal to the correction code.
8. The apparatus of claim 7, wherein the logic control circuit is configured to obtain a1 st bit comparison result from the comparator circuit during a1 st quantization period, one of a control ground voltage and a reference voltage being electrically connected to a lower plate of the 1 st bit capacitance to be corrected;
And calculating the correction code of the 1 st bit capacitor to be corrected based on the error code of the 1 st bit capacitor to be corrected and the 1 st bit comparison result.
9. The apparatus of claim 7, wherein the logic control circuit is configured to: in the n-th quantization period,
When the output voltage of the capacitor array is lower than the preset voltage, the n-th output result of the comparator circuit is 0, and the control reference voltage is connected with the lower polar plate of the n-th capacitor to be corrected;
And under the condition that the output voltage of the capacitor array is higher than the preset voltage, the n-th output result of the comparator circuit is 1, and the control ground voltage is connected with the lower polar plate of the n-th capacitor to be corrected.
10. The apparatus of any of claims 1-9, wherein the capacitive array comprises a first capacitive array and a second capacitive array, the first capacitive array and the second capacitive array being of substantially identical gauge; the upper plate of the first capacitor array is electrically connected to the positive input of the comparator circuit, and the upper plate of the second capacitor array is electrically connected to the negative input of the comparator circuit.
11. The apparatus of claim 10, wherein the logic control circuit is configured to:
sequentially acquiring error codes of the first capacitor array and the second capacitor array in a correction period;
and in a quantization period, correcting the first capacitor array and the second capacitor array in sequence based on the error code and a comparison result output by the comparator circuit.
12. An analog foreground correction method applied to the apparatus according to one of claims 1 to 11, the method comprising:
the logic control circuit controls the ground voltage to be electrically connected with each capacitor to be corrected in the capacitor array to be corrected from low to high in sequence;
The logic control circuit generates an error code of each capacitor to be corrected according to a comparison result output by the comparator circuit, wherein the comparator circuit compares the output voltage of the capacitor array with a preset voltage and outputs a comparison result, and the capacitor array comprises the capacitor array to be corrected and a quantized capacitor array;
a logic control circuit controls the common mode voltage to be input to the capacitor array;
the logic control circuit obtains a correction code according to the comparison result output by the comparator circuit and the error code;
A logic control circuit controls a plurality of target quantization capacitances in the quantization capacitance array to be electrically connected to the ground voltage or the reference voltage based on the correction code, wherein a sum of weights of the plurality of target quantization capacitances is equal to the correction code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410115779.5A CN118138042A (en) | 2024-01-26 | 2024-01-26 | Analog-to-digital converter device and analog foreground correction method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410115779.5A CN118138042A (en) | 2024-01-26 | 2024-01-26 | Analog-to-digital converter device and analog foreground correction method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118138042A true CN118138042A (en) | 2024-06-04 |
Family
ID=91239329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410115779.5A Pending CN118138042A (en) | 2024-01-26 | 2024-01-26 | Analog-to-digital converter device and analog foreground correction method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118138042A (en) |
-
2024
- 2024-01-26 CN CN202410115779.5A patent/CN118138042A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5946443B2 (en) | Successive approximation register analog-to-digital converter with integral nonlinearity correction | |
| US8416116B2 (en) | Successive approximation analog-to-digital converter having auxiliary prediction circuit and method thereof | |
| EP2579464B1 (en) | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter | |
| US8599059B1 (en) | Successive approximation register analog-digital converter and method for operating the same | |
| US8441386B2 (en) | Method to reduce voltage swing at comparator input of successive-approximations-register analog-to-digital converters | |
| US9362939B1 (en) | Reduction of input dependent capacitor DAC switching current in flash-SAR analog-to-digital converters | |
| US8902092B2 (en) | Analog-digital conversion circuit and method | |
| US10020816B1 (en) | Hybrid successive approximation register analog to digital converter | |
| US9654127B1 (en) | Method for adaptively regulating coding mode and digital correction circuit thereof | |
| CN111130550B (en) | Successive approximation register type analog-to-digital converter and signal conversion method thereof | |
| US10886937B1 (en) | Method to embed ELD DAC in SAR quantizer | |
| US10491232B1 (en) | Successive approximation register (SAR) analog to digital converter (ADC) dynamic range extension | |
| CN114614821B (en) | SAR ADC offset error correction method and circuit based on differential structure | |
| CN115099182B (en) | Integral design method for segmented CDAC (capacitor-to-capacitor converter) bridge capacitor and analog-to-digital converter | |
| US8508398B1 (en) | Systems for comparator offset cancellation in successive-approximation-register analog-to-digital converters | |
| US20200007143A1 (en) | Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with Switchable Reference Voltage | |
| CN111510146B (en) | Analog-to-digital converter quantization method based on code word recombination | |
| Li et al. | Digital foreground calibration methods for SAR ADCs | |
| US11984904B2 (en) | Analog-to-digital converter (ADC) having calibration | |
| CN118138042A (en) | Analog-to-digital converter device and analog foreground correction method | |
| Choi et al. | A low energy two-step successive approximation algorithm for ADC design | |
| CN109936370B (en) | Low-power-consumption switching algorithm applied to SAR ADC | |
| CN113708763A (en) | Analog-to-digital conversion system and method with offset and bit weight correction mechanism | |
| KR102552752B1 (en) | Successive-Approximation-Register Analog-to-Digital-Converter Using Redundant Capacitor And Operating Method thereof | |
| US9413371B1 (en) | ADC and analog-to-digital converting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |