CN118138026A

CN118138026A - Delay buffer unit, electronic device, delay buffer array and operation method thereof

Info

Publication number: CN118138026A
Application number: CN202311842660.XA
Authority: CN
Inventors: 吴华强; 卫松涛; 潘思宁; 姚鹏; 郭欣颖; 揭路; 伍冬; 高滨; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-06-04

Abstract

The disclosure provides a delay buffer unit, a delay buffer array, an electronic device and an operation method of the delay buffer array, wherein the delay buffer unit comprises a first delay buffer subunit and a second delay buffer subunit which are connected in series, wherein the first delay buffer subunit and the second delay buffer subunit are respectively configured to have opposite influence on the edge slope of a pulse signal passing through the delay buffer unit, the delay buffer unit can be used for integrating calculation so as to realize matrix vector multiplication operation, and can ensure that an output delay signal still has a falling edge and a rising edge with ideal slope while reducing hardware expenditure of an integrated circuit.

Description

Delay buffer unit, electronic device, delay buffer array and operation method thereof

Technical Field

Embodiments of the present disclosure relate to a delay buffer unit, a delay buffer unit array, an electronic device, and an operation method of the delay buffer unit array.

Background

Memristors (e.g., resistive random access memories, phase change memories, conductive bridge memories, etc.) are nonvolatile devices whose conductance state can be adjusted by application of an external stimulus. Memristors, which are two-terminal devices, have the characteristics of adjustable resistance and non-volatility, and are therefore widely used in memory and computing. According to kirchhoff's current law and ohm's law, an array of memristors can perform multiply-accumulate calculations in parallel, with both storage and calculation occurring in each device of the array.

The integrated calculation architecture can realize higher calculation power and energy efficiency because the problem of a storage wall is avoided. The non-volatile memory unified system can reduce the complexity of matrix vector multiplication from o (n 2) to o (1) by using the cross array structure.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

Some embodiments of the present disclosure provide a delay buffer unit including a first delay buffer subunit and a second delay buffer subunit connected in series, the first delay buffer subunit including a first-stage inverter, a second-stage inverter, and a first delay adjustment subunit, an input of the first-stage inverter serving as an input of the delay buffer unit, an input of the second-stage inverter being connected to an output of the first-stage inverter, the first-stage delay adjustment subunit being connected to a first end, a first operating voltage end, and a second operating voltage end of the first-stage inverter, the second delay buffer subunit including a third-stage inverter, a fourth-stage inverter, and a second delay adjustment subunit, an input of the third-stage inverter being connected to an output of the second-stage inverter, the input end of the fourth-stage inverter is connected with the output end of the third-stage inverter, the output end of the fourth-stage inverter is used as the output end of the delay buffer unit, the second-stage delay adjustment subunit is connected with the second end, the third operation voltage end and the fourth operation voltage end of the third-stage inverter, wherein the first delay adjustment subunit comprises a first memristor and a first control switch, the first control switch is configured to determine whether to use the first memristor to adjust the first delay of the first delay buffer subunit, the second delay adjustment subunit comprises a second memristor and a second control switch, the second control switch is configured to determine whether to use the second memristor to adjust the second delay of the second delay buffer subunit, the first delay buffer subunit and the second delay buffer subunit are respectively configured to have opposite effects on edge slopes of pulse signals passing through the delay buffer units.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, voltages of the first operating voltage terminal and the second operating voltage terminal are lower than voltages of the third operating voltage terminal and the fourth operating voltage terminal, at least one of the first operating voltage terminal and the second operating voltage terminal functions as a discharge voltage terminal when the first delay buffer subunit is operated, and at least one of the third operating voltage terminal and the fourth operating voltage terminal functions as a charge voltage terminal when the second delay buffer subunit is operated.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the type of the first control switch is different from the type of the second control switch.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the first control switch includes a first pole, a second pole, and a first control pole, the first control pole receives a first control signal to turn on or off the first pole and the second pole of the first control switch according to the first control signal, the first pole of the first control switch is electrically connected to a first end of the first stage inverter, the second pole of the control switch is electrically connected to the first operating voltage end, the first end of the first memristor is electrically connected to the first pole of the first control switch and the first end of the first stage inverter, and the second end of the first memristor is electrically connected to the second operating voltage end; the second control switch comprises a first pole, a second pole and a second control pole, the second control pole receives a second control signal to conduct or cut off the first pole and the second pole of the second control switch according to the second control signal, the first pole of the second control switch is electrically connected with the second end of the third-stage inverter, the second pole of the second control switch is electrically connected with the third operating voltage end, the first end of the second memristor is electrically connected with the first pole of the second control switch and the second end of the third-stage inverter, and the second end of the second memristor is electrically connected with the fourth operating voltage end; the first control signal and the second control signal are inverted from each other.

For example, in one delay buffer unit provided by some embodiments of the present disclosure, the first delay adjustment subunit includes a first adjustment capacitance and is configured to adjust a delay of the first delay buffer subunit using the first memristor and the first adjustment capacitance according to the first control signal, and the second delay adjustment subunit includes a second adjustment capacitance and is configured to adjust a delay of the second delay buffer subunit using the second memristor and the second adjustment capacitance according to a second control signal.

For example, in some embodiments of the present disclosure, a delay buffer unit is provided in which a capacitance of the first adjustment capacitor is the same as a capacitance of the second adjustment capacitor.

Some embodiments of the present disclosure further provide a delay buffer array, including a plurality of delay buffer units according to any one of the embodiments above, where the plurality of delay buffer units are arranged as an array having a plurality of rows, and the delay buffer units in each row are serially connected in turn to form a delay chain.

For example, in a delay buffer array provided in some embodiments of the present disclosure, the delay buffer array further includes: the time pulse input module is configured to respectively provide time pulse signals at the input ends of the delay chains; the programming voltage generation module is configured to perform memristor programming on the target delay buffer unit; an input loading module configured to provide a first control signal and a second control signal as input signals for each delay buffer unit; the output quantization module is configured to quantize the outputs of the delay chains respectively to obtain digital output signals; the data storage module is configured to store data when the delay buffer array performs calculation; and the mode control module is configured to control an operation mode executed by the delay buffer array.

Some embodiments of the present disclosure also provide an electronic device comprising a delay buffer array as described in any one of the above embodiments.

Some embodiments of the present disclosure further provide a method for operating a delay buffer array, which is applied to the delay buffer array described in any one of the foregoing embodiments, where the method for operating a delay buffer array includes: providing a time pulse signal at an input of a delay chain selected for a computational operation in the delay buffer array; applying a first control signal and a second control signal as input data signals to each delay buffer unit in a delay chain selected for calculation operation in the delay buffer array, wherein the input data signals control the first control switch and the second control switch of the delay buffer unit corresponding to the input data signals to be switched on or off; the output of the delay chain selected for the computational operation in the delay buffer array obtains an object output signal.

For example, in one method of operation of a delay buffer array provided by some embodiments of the present disclosure, the input data signal applied to each delay buffer cell in the same delay chain selected for a computational operation is 1 bit of multi-bit data, respectively.

For example, in an operation method of a delay buffer array provided in some embodiments of the present disclosure, after an output end of a delay chain selected for a calculation operation in the delay buffer array obtains an output signal, the operation method of the delay buffer array further includes: acquiring a time delay between the time pulse signal and the object output signal; quantizing the delay to obtain a digital output signal; and subtracting the check data from the digital output signal to obtain a check output of the delay buffer array.

Some embodiments of the present disclosure further provide another operation method of a delay buffer array, which is applied to the delay buffer array described in any one of the foregoing embodiments, and the operation method includes: selecting one delay buffer unit in the delay buffer array as a unit to be programmed; applying the first control signal to control a first control switch in the unit to be programmed, and applying a first programming voltage to two ends of a first memristor in the unit to be programmed to change the resistance value of the first memristor; or applying the second control signal to control a second control switch in the unit to be programmed, and applying a second programming voltage to two ends of a second memristor in the unit to be programmed to change the resistance value of the second memristor.

For example, in an operation method of a delay buffer array provided in some embodiments of the present disclosure, after changing a resistance value of the first memristor or changing a resistance value of the second memristor, the operation method further includes: providing a time pulse signal at the input end of a delay chain corresponding to the unit to be programmed; the method comprises the steps of controlling a first control switch and a second control switch of a unit to be programmed to be turned off and turned on, controlling the first control switch and the second control switch of a delay buffer unit except the unit to be programmed in a delay chain corresponding to the unit to be programmed to be turned on, and obtaining an output signal of the delay chain corresponding to the unit to be programmed to be used as a first programming output; or the first control switch and the second control switch of the unit to be programmed are controlled to be on and off, the first control switch and the second control switch of the delay buffer units except the unit to be programmed in the delay chain corresponding to the unit to be programmed are controlled to be on, and the output signal of the delay chain corresponding to the unit to be programmed is obtained to be used as the second programming output; and determining whether the resistance value of the first memristor or the resistance value of the second memristor of the unit to be programmed meets programming requirements according to the first programming output or the second programming output.

Some embodiments of the present disclosure further provide another operation method of a delay buffer array, which is applied to the delay buffer array described in any one of the foregoing embodiments, and the operation method includes: providing a time pulse signal at an input of a delay chain selected for a verify operation in the delay buffer array; respectively applying a first control signal and a second control signal which are used as input signals to each delay buffer unit in a delay chain selected for verification operation in the delay buffer array so as to control the first control switch and the second control switch of each delay buffer unit to be conducted; the output end of the delay chain selected for verification operation in the delay buffer array acquires an output signal as an intrinsic output; and quantifying the delay between the intrinsic output and the time pulse signal to obtain verification data of a delay chain selected for verification operation in the delay buffer array.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A is a schematic diagram of an exemplary delay buffer unit;

FIG. 1B is a schematic diagram of another exemplary delay buffer unit;

FIG. 1C is a schematic diagram of an exemplary delay chain;

FIG. 1D is a schematic diagram of an exemplary computing device;

Fig. 2 is a schematic structural diagram of a delay buffer unit according to at least one embodiment of the present disclosure;

Fig. 3A is a schematic diagram of a working principle of a delay buffer unit according to at least one embodiment of the present disclosure;

fig. 3B is a schematic diagram of a working principle of a delay buffer unit according to at least one embodiment of the present disclosure;

Fig. 4 is a schematic diagram of a series structure of delay buffer units according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a delay buffer array according to at least one embodiment of the present disclosure;

FIG. 6 is a flow chart of a method of operating a delay buffer array according to at least one embodiment of the present disclosure;

FIG. 7 is a flow chart of yet another method of operation of a delay buffer array according to at least one embodiment of the present disclosure;

FIG. 8A is a schematic diagram illustrating a program verification of a delay buffer unit according to at least one embodiment of the present disclosure;

FIG. 8B is a schematic diagram of yet another delay buffer unit programming verification provided in at least one embodiment of the present disclosure; and

FIG. 9 is a flow chart of yet another method of operation of a delay buffer array according to at least one embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical solutions of the present disclosure, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings, and the specific embodiments and the accompanying drawings described herein are only for explaining the present disclosure and not limiting the disclosed embodiments, and the embodiments of the present disclosure and the features of the embodiments may be combined with each other without conflict.

For convenience of description, only parts related to the embodiments of the present disclosure are shown in the drawings, and parts unrelated to the embodiments of the present disclosure are not shown in the drawings. Each unit, module referred to in the embodiments of the present disclosure may correspond to only one physical structure, may be composed of a plurality of physical structures, or may be integrated into one physical structure. In the absence of conflict, the functions noted in the flowcharts and block diagrams of the disclosed embodiments may occur out of the order noted in the figures.

The architecture, functionality, and operation of possible implementations of systems, apparatuses, devices, methods according to various embodiments of the present disclosure are shown in the flowcharts and block diagrams of the disclosed embodiments. Each block in the flowchart or block diagrams may represent a unit, module, segment, or code, which comprises executable instructions for implementing the specified functions. Moreover, each block or combination of blocks in the block diagrams and flowchart illustrations can be implemented by hardware-based systems that perform the specified functions, or by combinations of hardware and computer instructions.

Detailed descriptions of known functions and known parts (elements) may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is denoted by the same or similar reference numeral in each drawing.

The memristor is a novel information processing device, has the function of memory computation fusion, and can realize computation operation in situ on stored data, so that huge expenditure of data movement is eliminated. In addition, the memristor can directly perform operation on an analog domain (for example, the memristor can complete multiplication operation based on ohm's law and addition operation based on kirchhoff's current law), so that matrix vector multiplication operation is realized in one step, and digital-to-analog conversion cost is not needed in the operation process. In recent years, memristor-based memory integration has made significant progress. However, since the power supply support of the terminal device is limited, memristor-based integrated storage devices are required to have not only higher precision of computation but also lower energy consumption and higher energy efficiency. Therefore, the memristor memory integrated design is improved in the aspects of array structure, peripheral circuit design and the like.

For example, one improvement is a voltage domain quantization scheme, employing voltage precharge type reading instead of current type reading scheme with excessive quiescent current overhead, but the output range of the scheme is limited. For example, another improvement is a time domain quantization method, which transfers the output result to a time domain to increase the output range, thereby more simply and efficiently distinguishing different output states, etc., but the output of the time domain quantization has a nonlinear problem. In addition, the quantization schemes of the voltage domain and the time domain are required to handle large current flowing through the memristor array when the memristor array is opened in parallel, and large current on the memristor array and a peripheral circuit of the memristor array can generate large power consumption. For example, another improvement is a current-mode analog computation scheme based on a 2T2R array structure, which alleviates the problem of IR drop (IR drop) of the wiring by reducing the accumulated output current, and is a computation mode with high parallelism and high computation power. However, in order to ensure the calculation accuracy, this calculation method requires a large input power consumption and a clamp circuit power consumption, and when the array size is large, a large power consumption is also generated.

The memristor integrated array and circuit design scheme can not meet the extremely low-power consumption and high-energy efficiency requirements during parallel processing due to the limitation of a calculation mechanism. The inventor of the present disclosure proposes a calculation array using a memristor delay structure as a calculation basic unit, and further implementing a calculation-integrated matrix vector multiplication operation by using delay accumulation of each unit, where the calculation array can avoid a need of processing a large current in a calculation process, and lower a working power supply voltage, thereby implementing high energy efficiency.

FIG. 1A illustrates a schematic diagram of an exemplary delay buffer unit; fig. 1B shows a schematic diagram of another exemplary delay buffer unit.

For example, one scheme adopts a delay buffer unit as shown in fig. 1A and 1B to control delay between input and output, so that transmission delay of the delay buffer unit can be changed according to whether a memristor is used, and the transmission delay of the delay buffer unit can be changed by controlling resistance value change of the memristor, thereby realizing dynamic regulation and control of the delay buffer unit, and flexibly and efficiently regulating and controlling the delay according to actual requirements.

As in the example shown in fig. 1A and 1B, the delay buffer unit 10 includes a first-stage inverter P1, a second-stage inverter P2, and a delay adjustment subunit 11.

For example, the input terminal of the first-stage inverter P1 serves as the input terminal INT of the delay buffer unit 10. The input signal of the delay buffer unit may be received from the input terminal of the first stage inverter P1, and the input signal may be, for example, a rising edge trigger signal (as shown in fig. 1A) or a falling edge trigger signal (as shown in fig. 1B). For example, the first stage inverter P1 includes two transistors T1 and T2, where T1 is, for example, an NMOS transistor, T2 is, for example, a PMOS transistor, and gate terminals of the transistors T1 and T2 may be used as input terminals, that is, the input terminal INT of the delay buffer unit 10 to receive an input signal. For example, when the input signal is at a high level, the transistor T1 is turned on, the transistor T2 is turned off, and when the input signal is at a low level, the transistor T1 is turned off, and the transistor T2 is turned on. The drain terminals of the transistors T1 and T2 are electrically connected to each other and serve as the output terminal of the first-stage inverter P1, and the source terminal of the transistor T1 or T2 may be connected to the ground terminal or the power source terminal or may serve as the first terminal of the first-stage inverter P1.

For example, the input terminal of the second-stage inverter P2 is connected to the output terminal of the first-stage inverter P1, and the output terminal of the second-stage inverter P2 serves as the output terminal OUT of the delay buffer unit 10. The circuit structure of the second-stage inverter P2 is similar to that of the first-stage inverter P1.

For example, the output signal of the delay buffer unit 10, which corresponds to the input signal and has a certain delay with respect to the input signal, may be output from the output terminal of the second-stage inverter P2, the delay being composed of the transmission delays of the first-stage inverter P1 and the second-stage inverter P2. For example, as shown in fig. 1A, when the input signal received from the input terminal INT of the delay buffer unit 10 is a rising edge trigger signal, the output signal outputted from the output terminal OUT of the delay buffer unit 10 has a certain delay t with respect to the rising edge trigger signal (the rising edge trigger signal and the output signal are respectively represented by gray lines and black lines at the output terminal OUT in fig. 1A). For example, as shown in fig. 1B, when the input signal received from the input terminal INT of the delay buffer unit 10 is a falling edge trigger signal, the output signal outputted from the output terminal OUT of the delay buffer unit 10 has a certain delay t with respect to the falling edge trigger signal (the falling edge trigger signal and the output signal are respectively represented by gray lines and black lines at the output terminal OUT in fig. 1B).

For example, the delay adjustment subunit 11 is connected between the first end of the first-stage inverter P1 and the first operating voltage end 1, and the delay adjustment subunit 11 comprises a memristor (here exemplified by a Resistive Random Access Memory (RRAM)), the delay adjustment subunit 11 being configured to control the transmission delay of the first-stage inverter P1 using the memristor RRAM in accordance with the first input signal NWL. For example, the first input signal NWL is used to control whether the delay adjustment subunit 11 adjusts the transmission delay of the first-stage inverter P1 using the memristor RRAM, thereby adjusting the delay difference (delay t) between the output signal and the input signal of the delay buffer unit 10.

For example, the delay adjustment subunit 11 further includes a control switch, which may be an N-type transistor or a P-type transistor. The control switch, here exemplified by an N-type transistor (NM 1), comprises a first pole, a second pole and a control pole, which first pole, second pole and control pole of the first control switch NM1 may be, for example, the source, drain and gate of the N-type transistor, respectively. The control electrode of the first control switch NM1 is connected to the first input signal NWL, and turns on or off the first electrode and the second electrode of the first control switch NM1 according to the first input signal NWL. For example, a first pole of the first control switch NM1 is electrically connected to a first end of the first-stage inverter P1, a second pole of the first control switch NM1 is electrically connected to the first operation voltage end 1, the first-stage inverter P1 is connected to the first operation voltage end 1 when the first control switch NM1 is turned on, and the first-stage inverter P1 is disconnected from the first operation voltage end 1 when the first control switch NM1 is turned off. The first control switch NM1 may be an N-type transistor (as shown in fig. 1A) or a P-type transistor.

For example, the memristor RRAM in the delay adjustment subunit 11 includes a first terminal electrically connected to the first pole of the first control switch NM1 and the first terminal of the first-stage inverter P1, and a second terminal. The second terminal of the memristor RRAM and the second terminal of the first control switch NM1 may be connected to the same or different operation voltage terminals. Here, the connection of the second terminal of the memristor RRAM and the second terminal of the first control switch NM1 to different operation voltage terminals means that both obtain voltage signals from the different operation voltage terminals, respectively.

For example, in one example, the second terminal of the memristor RRAM may be electrically connected to the first operating voltage terminal 1, i.e. the second terminal of the memristor RRAM is connected to the first operating voltage terminal together with the second terminal of the first control switch NM1, and the first operating voltage terminal 1 may be, for example, a power supply terminal or a ground terminal. For example, in another example, the second terminal of the memristor RRAM is electrically connected to the second operating voltage terminal 2, the second terminal of the first control switch NM1 is electrically connected to the first operating voltage terminal 1, and the voltage signals provided by the first operating voltage terminal 1 and the second operating voltage terminal 2 are different. For example, in yet another example, the second terminal of the memristor RRAM is electrically connected to the first operating voltage terminal 1, the second terminal of the first control switch NM1 is electrically connected to the second operating voltage terminal 2, and the first operating voltage terminal 1 and the second operating voltage terminal 2 are different.

The delay adjustment subunit 11 is connected to the first terminal of the first-stage inverter P1, for example, to the source terminal of the first-stage inverter P1. For example, as shown in fig. 1A, the delay adjustment subunit 11 is connected between the NMOS transistor T1 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in the delay adjustment subunit 11 shown in fig. 1A, a first pole (e.g., drain) of the first control switch NM1 is connected to the source of the NMOS transistor T1 in the first-stage inverter P1, and a first end of the memristor RRAM is connected to the source of the NMOS transistor T1 in the first-stage inverter P1. For example, as shown in fig. 1B, the delay adjustment subunit 11 is connected between the PMOS transistor T2 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in the delay adjustment subunit 11 shown in fig. 1B, a first pole (e.g., a source) of the first control switch NM1 is connected to a source of the PMOS transistor T2 in the first-stage inverter P1, and a first end of the memristor RRAM is connected to a source of the PMOS transistor T2 in the first-stage inverter P1.

For example, the delay buffer unit 10 further includes a capacitor C1, where a first pole of the capacitor C1 is connected between the output terminal of the first-stage inverter P1 and the input terminal of the second-stage inverter P2, and a second pole of the capacitor C1 is grounded. The capacitor C1 may be, for example, a specially prepared capacitor element or a parasitic capacitor or the like.

For example, in the delay buffer unit 10 shown in fig. 1A, when the input signal received from the input terminal INT of the delay buffer unit 10 is a low level signal, the NMOS transistor T1 in the first-stage inverter P1 is turned off, and the PMOS transistor T2 is turned on, thereby disconnecting the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1. In this case, the delay adjustment subunit 11 may be connected to the first operating voltage terminal 1 and the second operating voltage terminal 2 to perform the first processing operation on the memristor RRAM according to the signal provided by the second operating voltage terminal 2. For example, the first processing operation performed on the memristor RRAM may be a set operation, a reset operation, or an initialization operation to change the resistance value of the memristor.

For memristors (e.g., resistive random access memories), an additional initialization (Forming) process is typically required, and after initialization is completed, the resistance value of the memristor may vary with the applied voltage signal. Since there is no conductive filament inside the memristor when its fabrication is completed, it is necessary to form a conductive filament inside the memristor by an initialization operation. The initialization operation typically only needs to be performed once during the life cycle of the memristor.

For example, in the delay buffer unit 10 shown in fig. 1A, after the conduction path between the delay adjustment subunit 11 and the first-stage inverter P1 is disconnected, an initialization voltage may be applied between the first operating voltage terminal 1 and the second operating voltage terminal 2 to perform an initialization operation on the memristor, so that a conductive filament is formed inside the memristor. For example, after being initialized such that conductive filaments are formed inside the memristor RRAM, the memristor RRAM has a threshold voltage.

For example, it is a mainstream practice that the resistance value (or conductance value) of the memristor RRAM is not changed when the magnitude of the input voltage applied between the first and second terminals of the memristor RRAM is smaller than the threshold voltage of the memristor RRAM. In this case, a read voltage may be applied between the first and second operating voltage terminals to read the current resistance value of the memristor RRAM. The read voltage is less than the threshold voltage of the memristor RRAM, so that the current resistance value of the memristor can be read without changing the resistance value of the memristor.

For example, when the magnitude of the input voltage applied between the first and second terminals of the memristor RRAM is greater than the threshold voltage of the memristor RRAM, the resistance value (or conductance value) of the memristor RRAM may be changed according to a Set (Set) voltage or a Reset (Reset) voltage applied between the first and second terminals of the memristor RRAM. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. For example, applying a set voltage to the memristor RRAM may cause the resistance value of the memristor RRAM to become small, applying a reset voltage to the memristor RRAM may cause the resistance value of the memristor RRAM to become large, the application of the set voltage to the memristor is referred to as a set operation, and the application of the reset voltage to the memristor is referred to as a reset operation.

Fig. 1C shows a schematic diagram of an exemplary delay chain. As shown in fig. 1C, a plurality of delay buffer units 10 are cascaded to form a row of delay chain 20, and an input signal KEEP is received from an input terminal INT of a first delay buffer unit 10 of the delay chain 20, where the input signal KEEP may be, for example, a rising edge trigger signal or a falling edge trigger signal. Such delay chains may be arranged side by side to provide a delay buffer array.

For convenience of description, the matrix vector multiplication operation is described below by taking the delay buffer unit 10 as shown in fig. 1A as an example, and when performing calculation, the input signal KEEP is a rising edge trigger signal, and the first control switch NM1 and the memristor RRAM in the delay adjustment subunit 11 of the delay buffer unit 10 are grounded.

For example, in the operation array, each delay buffer unit 10 performs multiplication as one calculation unit, and the accumulated delays of the plurality of delay buffer units 10 are outputted from the output end of the delay chain 20 as the result of the multiplication and addition operation as the output of the delay chain.

For example, before performing the calculation, the elements of the matrix G (or the calculation weights in the neural network) need to be mapped into the delays of the delay buffer unit 10, and the magnitude of the delays can be obtained by adjusting the magnitude of the resistance values of memristors in the delay buffer unit 10, for example. For example, a column of elements G11, G21, …, gm1 of the matrix G are mapped to memristor-regulated delays W <0>, W <1>, …, W < m-1>, respectively, of m delay buffer cells 10.

Then, when performing computation, the elements of the input vector V are mapped into the first input signals of the delay buffer unit 10, for example, the input element V1 of the input vector V is used as the first input signals NWL <0>, NWL <1>, …, NWL < m-1> of the plurality of delay buffer units 10 in cascade connection, and the plurality of first input signals NWL <0>, NWL <1>, …, NWL < m-1> can be input in parallel, for example, so as to improve the computation efficiency. The first input signals NWL <0>, NWL <1>, …, NWL < m-1>, corresponding to the input element V1, control whether the memristor-regulated delays W <0>, W <1>, …, W < m-1> of the delay buffer cells 10 are strung into the delay chain 20. The accumulated delay NWL < m-1:0 >. W < m-1:0> at the output of the delay chain 20 is the result of the vector inner product operation (multiply-accumulate operation).

For example, for each delay buffer unit 10 in fig. 1A or fig. 1B, when the first control signal is at a low level (corresponding to the input element V1 being 1), the memristor RRAM is connected between the first-stage inverter P1 and the first operating voltage terminal 1, and at this time, the delay t of the delay buffer unit is the delay regulated by the resistance value of the memristor, that is, the delay regulated by the memristor is strung into the delay chain; when the first control signal is at a high level (corresponding to the input element V1 being 0), the memristor RRAM is bypassed, and the memristor RRAM is not connected between the first-stage inverter P1 and the first operation voltage terminal 1, at this time, the delay t of the delay buffer unit is an intrinsic delay, that is, only the intrinsic delay is connected in series to the delay chain.

Through the calculation operation, the delay chain may implement a vector inner product operation (multiply-accumulate operation) of one (e.g., 1 bit) input data and m weight elements.

FIG. 1D illustrates a schematic diagram of an exemplary computing device. As shown in fig. 1D, the computing device includes a delay computing array 100, and the delay computing array 100 includes delay buffer units 10 of 2M rows and N columns (only 4 rows and 2 columns are shown in the figure).

For example, N delay buffer units 10 in each row are connected in series with each other to form one row of delay chains 20, and each two adjacent rows of delay chains 20 constitute one delay processing combination 30. The difference in the delays of two delay buffer units 10 on the same column in each delay processing combination 30 may correspond to a signed weight element, e.g., by configuring the resistance values of memristors in the two delay buffer units 10, the difference in the delays of the two delay buffer units 10 may be made to represent a positive, negative, or zero weight element. That is, two delay buffer units 10 on the same column in each delay processing combination 30 may be used as a differential unit, and the delay of each differential unit may be used to represent a weight element of a positive value, a negative value, or a zero value.

For example, the two delay chains 20 in each delay processing combination 30 receive the same input signal KEEP, e.g. via the input terminal INT of the first delay buffer unit 10 in the two delay chains 20, respectively. The input signal KEEP may be used to control the mode of operation of the delay computing array 100. For example, the input signal KEEP may control whether the delay computing array 100 is in the first mode of operation or the second mode of operation. When the input signal KEEP remains at a normally low level (or a normally high level), the delay computing array 100 is in the first operation mode; when the input signal KEEP is a rising edge trigger signal (or a falling edge trigger signal), the delay computing array 100 is in the second operation mode.

In the first operation mode, the input signal KEEP is, for example, at a low level, so as to control the delay adjusting subunit 11 in the delay buffer unit 10 to be electrically disconnected from the first-stage inverter P1, where the aforementioned first processing operation may be performed on the memristor RRAM, for example, performing a set operation, a reset operation, or the like on the memristor RRAM. In the second operation mode, the input signal KEEP inputs an edge signal, so as to control the delay adjusting subunit 11 in the delay buffer unit 10 to be electrically connected to the first-stage inverter P2, and at this time, a calculation operation or a calibration reading operation may be performed on the delay calculation array 100, for example, a delay calculation result or a delay reading result is obtained from an output end of the delay chain.

For example, the outputs of the two-row delay chains 20 in each delay processing combination 30 output the cumulative delays of the plurality of delay buffer units 10 of the two rows, respectively. For example, as shown in fig. 1D, the first row delay chain 20 in the first delay processing combination 30 outputs the cumulative delay t_dlp <0> of the N delay buffer units 10 of the first row from the output terminal DLP <0>, and the second row delay chain 20 outputs the cumulative delay t_dln <0> of the N delay buffer units 10 of the second row from the output terminal DLN <0>.

For example, in one example, when a computation operation is performed on delay compute array 100, the difference Δt=t_dlp <0> -t_dln <0> of the cumulative delays of the two rows of delay chains in delay processing combination 30 may represent the result of the vector inner product of the input data and the signed weight element.

For example, two delay buffer units 10 located on the same column in each delay processing combination 30 are respectively connected to two word lines corresponding to the same column. For example, as shown in FIG. 1D, two adjacent delay buffer cells 10 on a first column in a first row delay processing combination 30 are connected to word lines WLP <0> and WLN <0>, respectively.

For example, two delay buffer units 10 on the same column in each delay processing combination 30 are connected to the corresponding bit lines on the same column. For example, as shown in FIG. 1D, two adjacent delay buffer cells 10 on a first column in the first row delay processing combination 30 are each connected to bit line BL <0 >.

For example, in each delay processing combination 30, N delay buffer units 10 located on the same row are connected to the source lines of the same row. For example, N delay buffer units 10 in the first row delay processing combination 30 are connected to the source line SLP <0>, and N delay buffer units 10 in the second row are connected to the source line SLN <0 >.

For example, for the delay buffer unit 10 in the delay calculation array 100, the delay adjustment subunit 11 of the delay buffer unit 10 is connected to a first end (e.g., a source end) of the first-stage inverter, and the delay adjustment subunit 11 is connected to different operation voltage ends, such as the first operation voltage end or the second operation voltage end, through a source line corresponding to the present row, a bit line corresponding to the present column, and a word line corresponding to the present column.

For example, as shown in fig. 1D, in the delay buffer unit 10 on the first column of the first row, the control electrode of the control switch NM1 in the delay adjustment subunit 11 is connected to the word line WLP <0>, the first electrode of the control switch NM1 is connected to the first end of the first-stage inverter P1 and the first end of the memristor RRAM, the second electrode of the control switch NM1 is connected to the source line SLP <0>, and the second end of the memristor is connected to the bit line BL <0 >. The connection between the delay buffer units 10 and the word lines, bit lines and source lines in other rows and columns is similar, and will not be described here again.

In the delay buffer unit, since the delay buffer unit is controlled to delay the rising edge (or the falling edge) of the input signal KEEP by the memristor, a loss is generated on the slope of the rising edge (or the falling edge) of the input signal KEEP, so the second-stage inverter P2 as shown in fig. 1A and 1B usually uses three parallel inverters to compensate the lost slope, i.e. one delay buffer unit needs an overhead of 9T1R, and the input signal KEEP generally includes both the rising edge and the falling edge, one delay buffer unit in the delay processing combination delays the rising edge of the input signal KEEP, the other delay buffer unit delays the falling edge of the input signal KEEP, and a corresponding group of differential units in the two delay buffer units needs an overhead of 2×9t1r to represent the delay generated on the whole input signal KEEP.

The first delay buffer unit comprises a first delay buffer subunit and a second delay buffer subunit which are connected in series, the first delay buffer subunit comprises a first-stage inverter, a second-stage inverter and a first delay regulating subunit, the input end of the first-stage inverter is used as the input end of the delay buffer unit, the input end of the second-stage inverter is connected with the output end of the first-stage inverter, the first-stage delay regulating subunit is connected with the first end, the first operation voltage end and the second operation voltage end of the first-stage inverter, the second delay buffer subunit comprises a third-stage inverter, a fourth-stage inverter and a second delay regulating subunit, the input end of the third-stage inverter is connected with the output end of the second-stage inverter, the output end of the fourth-stage inverter is used as the output end of the delay buffer unit, the second-stage delay regulating subunit is connected with the second end, the third operation voltage end and the fourth delay regulating subunit of the second-stage inverter, the second delay regulating subunit is configured according to the first delay buffer subunit, the second delay buffer subunit is controlled by the first delay buffer subunit, the second delay buffer subunit is configured to be controlled by the second delay buffer subunit, the second delay buffer subunit is controlled by the second delay buffer subunit, and the second delay buffer subunit is configured to be the second delay buffer subunit, and the second buffer subunit is controlled by the second delay buffer subunit is controlled by the second buffer unit, and the second buffer subunit is configured to be affected by the second delay buffer unit.

For example, the first delay may be a delay caused by a rising edge of an input pulse signal, the second delay may be a delay caused by a falling edge of the input pulse signal, and by the two-stage series structure, it is possible to simultaneously delay the rising edge and the falling edge of the input pulse signal in one row of delay buffer units without generating delays in the two rows of delay buffer units respectively.

For example, the first delay buffer subunit causes a loss of the rising edge slope of the pulse signal passing through the delay buffer unit, and the second delay buffer subunit causes a loss of the falling edge slope of the pulse signal passing through the delay buffer unit.

Fig. 2 is a schematic structural diagram of a delay buffer unit according to at least one embodiment of the present disclosure. In fig. 1A and fig. 1B, when the second-stage inverter P2 is a single inverter, the first delay buffer subunit may be, for example, a delay buffer unit as shown in fig. 1A, where a transistor type of the first control switch NM1 in fig. 1B is replaced by a transistor type different from that of the first control switch NM1 in fig. 1A, and may be used as a second delay buffer subunit, in this case, the first delay buffer subunit NCELL includes a first-stage inverter PM1, a second-stage inverter PM2, a first regulating capacitor C1, a first control switch NM0, and a first memristor R1, and the second delay buffer subunit PCELL includes a third-stage inverter PM3, a fourth-stage inverter PM4, a second regulating capacitor C2, a second control switch PM0, and a second resistor R2, where the second-stage inverter PM2 and the fourth-stage inverter PM4 are connected to an operation terminal of the second buffer subunit K at an input terminal of the second buffer subunit PM2 by a voltage operation terminal of the first buffer subunit PM2, and the second buffer subunit PCELL is connected to an operation terminal of the second buffer subunit PM2 at a second-stage voltage input terminal of the second buffer subunit PM 2.

For example, the voltages of the first operation voltage terminal K1 and the second operation voltage terminal K2 are lower than the voltages of the third operation voltage terminal K3 and the fourth operation voltage terminal K4, and at least one of the first operation voltage terminal K1 and the second operation voltage terminal K2 functions as a discharge voltage terminal when the first delay buffer subunit NCELL operates, for example, is connected to each other so as to jointly function as a discharge voltage terminal; at least one of the third operating voltage terminal K3 and the fourth operating voltage terminal K4 functions as a charging voltage terminal when the second delay buffer subunit PCELL is operating, for example, both are connected to each other so as to jointly function as a charging voltage terminal. For example, the first operating voltage terminal K1 and the second operating voltage terminal K2 are grounded, the third operating voltage terminal K3 and the fourth operating voltage terminal K4 are connected to the power supply voltage, and the memristor exists not only in the discharging path (NM 0 and the adjacent R1 in fig. 2) but also in the charging path (PM 0 and the adjacent R2 in fig. 2);

For example, the type of the first control switch NM0 is different from the type of the second control switch PM0, for example, the first control switch NM0 is an N-type transistor, and the second control switch PM0 is a P-type transistor.

For example, the first control switch NM0 includes a first pole, a second pole, and a first control pole, the first control pole receives the first control signal nwl_n to turn on or off the first pole and the second pole of the first control switch NM0 according to the first control signal nwl_n, the first pole of the first control switch NM0 is electrically connected to the first end of the first-stage inverter, the second pole of the first control switch NM0 is electrically connected to the first operation voltage end K1, the first end of the first memristor R1 is electrically connected to the first pole of the first control switch NM0 and the first end of the first-stage inverter, and the second end of the first memristor R1 is electrically connected to the second operation voltage end K2; the second control switch PM0 includes a first pole, a second pole and a second control pole, the second control pole receives a second control signal nwl_p to turn on or off the first pole and the second pole of the second control switch PM0 according to the second control signal nwl_p, the first pole of the second control switch PM0 is electrically connected to the second end of the third-stage inverter, the second pole of the second control switch PMO is electrically connected to the third operating voltage end K3, the first end of the second memristor R2 is electrically connected to the first pole of the second control switch PM0 and the second end of the third-stage inverter, and the second end of the second memristor R2 is electrically connected to the fourth operating voltage end K4; the first control signal nwl_n and the second control signal nwl_p are inverted to each other to control the first control switch NM0 and the second control switch PM0 to be turned on or off at the same time.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The first pole (electrode) and the second pole (electrode) of the transistor employed herein may be a source and a drain or a drain and a source, respectively. It is understood that the source and drain may be symmetrical in structure, so that the source and drain may be indistinguishable in structure. Embodiments of the present disclosure are not limited in the type of transistor employed.

For example, the first delay adjustment subunit comprises a first adjustment capacitance C1 and is configured to adjust the delay of the first delay buffer subunit NCELL using the first memristor R1 and the first adjustment capacitance C1 according to the first control signal nwl_n, the second delay adjustment subunit comprises a second adjustment capacitance C2 and is configured to adjust the delay of the second delay buffer subunit PCELL using the second memristor R2 and the second adjustment capacitance C2 according to the second control signal nwl_p, e.g. the first adjustment capacitance may utilize a parasitic capacitance of the circuit structure itself or an external capacitance.

For example, the capacitance of the first adjusting capacitor C1 is the same as the capacitance of the second adjusting capacitor C2, so that the delays generated by the first delay adjusting subunit and the second delay adjusting subunit on the rising edge and the falling edge of the input pulse signal are consistent when the resistances of the first memristor R1 and the second memristor R2 are equal.

As described above, in the structure shown in fig. 1D, a delay buffer unit of one line generates delay only for the rising edge (or falling edge) of the input pulse signal, two delay buffer units of two lines are needed to form a differential structure to calculate the delay generated by the input pulse signal passing through the delay buffer unit, and in order to output an ideal rising edge (or falling edge), the second inverter P2 in the delay buffer unit shown in fig. 1A or fig. 1B needs to compensate the slope of the rising edge (or falling edge) loss by using three inverters connected in series, in this case, the overhead required for one differential unit is 2×9t1r.

Fig. 3A and fig. 3B are schematic diagrams illustrating a working principle of a delay buffer unit according to at least one embodiment of the present disclosure. In the following, description will be made on how to reduce the circuit overhead with reference to fig. 3A and 3B, wherein the delay buffer unit structure shown in fig. 3A is the same as the delay buffer unit structure shown in fig. 2, and it should be noted that, for example, in the calculation mode, the first operation voltage terminal K1 and the second operation voltage terminal K2 of the delay buffer unit shown in fig. 2 are grounded, the third operation voltage terminal K3 and the fourth operation voltage terminal K4 are connected to the power supply voltage, and the positions of the first delay buffer unit and the second delay buffer unit in the delay buffer unit structure shown in fig. 3B are opposite to those in fig. 2.

As shown in fig. 3A, when the delay buffer unit receives the rising edge, the N-type transistors of the first stage inverter PM1 and the third stage inverter PM3 and the P-type transistors of the second stage inverter PM2 and the fourth stage inverter are turned on (indicated by black in the figure), but at this time, the output X of the first delay buffer subunit ncl also passes through the two-stage ell of the second delay buffer subunit ll, and the P-type transistor of the third stage inverter PM3 turns off (indicated by gray in the figure), so that the output of the first delay buffer subunit NCELL is X, and the RC delay formed by the first regulating capacitor C1 and the first memristor R1 only passes through the second stage inverter PM2, so that the slope of the rising edge of the output X of the first delay buffer subunit ncel is lost, but the output X of the first delay buffer subunit ncl also passes through the two-stage elll of the second delay buffer subunit ll, and the second RC connected with the third stage inverter RC 3 is turned off, so that the output X of the second delay buffer subunit PM2 is not restored to the ideal slope of the rising edge, and the output X of the second delay buffer subunit RC is not restored.

As shown in fig. 3B, when the delay buffer unit receives the falling edge, the N-type transistors of the first stage inverter PM1 and the third stage inverter PM3 and the P-type transistors of the second stage inverter PM2 and the fourth stage inverter are turned off (shown in gray in the figure), but at this time, the output Y of the first delay buffer unit PCELL also passes through the two-stage inverters of the second delay buffer subunit NCELL, and the N-type transistors of the third stage inverter PM3 are turned on (shown in black in the figure), so that the output of the first delay buffer subunit PCELL is Y, and the RC delay formed by the second regulating capacitor C2 and the second memristor R2 only passes through the second stage inverter PM2, and therefore the slope of the falling edge of the output Y of the first delay buffer subunit PCELL is lost.

When the input is 0 (i.e., nwl_n=1, nwl_p=0), the gate of the first control switch NM0 is connected to the high level, the first control switch NM0 is turned on, the gate of the second control switch PM0 is connected to the low level, the second control switch PM0 is turned on, the first memristor R1 and the second memristor R2 are bypassed, and the delay passing through the rising edge and the falling edge of the delay buffer unit is the intrinsic delay of the 4-stage inverter, so that the pulse widths of the input and the output are consistent; when the input is 1 (i.e., nwl_n=0, nwl_p=1), the gate of the first control switch NM0 is connected to the low level, the first control switch NM0 is turned off, the gate of the second control switch PM0 is connected to the high level, the second control switch PM0 is turned off, the rising edge delay is dominated by the RC delay formed by the first memristor R1, the falling edge is dominated by the RC delay formed by the first adjustment capacitance C1 and the second memristor R2, and thus the width of the output pulse is inconsistent with the input pulse width, and the degree of the inconsistency is determined by the sizes of the first memristor R1 and the second memristor R2.

In the above embodiment, the two-stage delay buffer subunit forms a differential unit, only the overhead of 2×5t1r is needed, and the rising edge or the falling edge is the edge slope recovered by the intrinsic delay of the three-stage inverter after RC delay, so that the hardware overhead is reduced while the output delay signal is ensured to still have the falling edge and the rising edge with ideal slope. The parasitic capacitance in the dynamic switching process of the circuit is smaller due to the fact that fewer transistors are used, and therefore lower dynamic switching power consumption can be achieved through the unit structure.

Fig. 4 is a schematic diagram of a serial structure of a delay buffer unit according to at least one embodiment of the present disclosure, where the delay buffer unit according to at least one embodiment of the present disclosure can implement a product of a 1-bit (bit) input and a signed weight, and is described below with reference to fig. 4.

As shown in fig. 4, m delay buffer units according to any of the above embodiments are connected in series to form a series structure, where m is an integer greater than 1, and the series structure forms a delay chain. The input pulse W1 is input to the input end of the delay chain, and the control signal IN < m-1> is input to each corresponding delay buffer unit (for example, the control signal of the first delay buffer unit is IN <0 >), so that the output pulse W2 can be obtained at the output end of the delay chain, wherein the delay generated by the single delay buffer subunit is W < m-1> (for example, the delay generated by the first delay buffer subunit is W <0 >).

The delay difference NW of the output pulse W2 with respect to the rising edge of the input pulse W1 is dominated by the RC delay accumulation of all the first delay buffer subunits NCELL, the delay difference PW of the output pulse with respect to the falling edge of the input pulse is dominated by the RC delay accumulation of all the second delay buffer subunits PCELL, thus completing the inner product of the 1bit input vector (IN <0>, IN <1> … IN < m-1 >) and the signed weight vector (W <0>, W <1> … W < m-1 >), this result being represented by the difference (W2-W1) of the output and input pulse widths, i.e.:

At least one embodiment of the present disclosure further provides a delay buffer array, where the delay buffer array includes a plurality of delay buffer units according to any one of the embodiments above.

Fig. 5 is a schematic structural diagram of a delay buffer array according to at least one embodiment of the present disclosure, as shown in fig. 5, where the delay buffer array includes a plurality of delay buffer units according to any one of the embodiments described above, and the delay buffer units in each row are sequentially connected in series to form a delay chain, for example, each delay buffer unit includes a first delay buffer subunit NCELL and a second delay buffer subunit PCELL connected in series.

The delay buffer array may further include a time pulse input module 101, a programming voltage generation module 102, an input loading module 103, an output quantization module 104, a data storage module 105, a mode control module 106, a column selection module 107, a row selection module 108, and a quantization control module 109. Wherein, the time pulse input module 101 is configured to provide time pulse signals to the input ends of the delay chains respectively; the programming voltage generation module 102 is configured to memristor program the target delay buffer unit; the input loading module 103 is configured to provide a first control signal and a second control signal as input signals for each delay buffer unit; the output quantization module 104 is configured to quantize the outputs of the plurality of delay chains to obtain digital output signals, respectively; the data storage module 105 is configured to store data when the delay buffer array performs calculations.

The mode control module 106 is configured to control an operation mode of the delay buffer array, such as a calculation mode, a programming mode, and a verification mode, the column selection module 107 and the row selection module 108 are configured to determine a selected delay buffer unit position during weight mapping, and the quantization control module 109 is configured to generate a timing signal for outputting the operation of the quantization module 104 to control the operation of the quantization output module, for example, the quantization control module may be a TDC (Time-to-Digital Converter ) array.

Since in practice it may happen that the intrinsic delays of the rising edges of all the first delay buffer subunits NCELL and the second delay buffer subunits PCELL do not match exactly, the difference in width between the input pulse and the output pulse will not be equal to 0 even when all 0 s are input at this time, which is a systematic error for the calculation, the calculation under all 0 s can be performed before the calibration and the calculation, so that the systematic error is extracted by the output quantization module 104 and stored in the data storage module 105 as calibration data, and then the calibration data is subtracted from the quantized output results of the calibration and the calculation, so as to achieve the elimination of the systematic error.

During weight mapping, determining the position of a selected delay buffer unit through a column selection module 107 and a row selection module 108, checking through an output quantization module 104, and programming a selected unit RRAM through a programming voltage generation module 102; the input loading module 103 applies an input vector to the vertical direction of the array during calculation, obtains an output vector result of matrix vector multiplication in the horizontal direction, and quantizes the output vector result into digital output through the output quantization module 104. It should be noted that, whether checking or calculating is performed, a calibration phase PH0 is required before the calibration phase PH0 starts, so as to quantize and store the systematic error DOUT0 at the input of all 0, and then quantize the digital output DOUT1 through the output quantization module 104 in the normal checking or calculating process PH 1. The digital outputs obtained by the two phases are subtracted in the digital domain to obtain output vectors DOUT1-DOUT0 which can truly reflect the result.

The operation of the delay buffer array of the present disclosure in the calculate, verify and program modes is described below in connection with some embodiments.

Fig. 6 is a flowchart of a method for operating a delay buffer array according to at least one embodiment of the present disclosure, where the method is applied to the delay buffer array according to any one of the above embodiments, and as shown in fig. 6, the method includes steps S201 to S203.

S201, providing a time pulse signal at the input end of a delay chain selected for calculation operation in the delay buffer array.

For example, the time pulse signal may be provided by the time pulse input module 101 as shown in fig. 5, and the delay chain corresponding to the delay buffer unit for the calculation operation may be selected by the column selection module 107 and the row selection module 108.

S202, respectively applying a first control signal and a second control signal which are input data signals to each delay buffer unit in a delay chain selected for calculation operation in a delay buffer array, wherein the input data signals control the first control switch and the second control switch of the delay buffer unit corresponding to the input data signals to be switched on or off.

For example, the first control signal and the second control signal may be provided by the input loading module 103 as shown in fig. 5.

S203, the output end of the delay chain selected for calculation operation in the delay buffer array acquires an object output signal, wherein the object output signal is a time signal delayed from the input time pulse signal.

For example, the input data signals applied to each delay buffer cell in the same delay chain selected for a computing operation are each 1 bit of multi-bit data. For example, m delay buffer units exist in the delay chain, the input data signal has m bits, each bit of input signal is input into the corresponding delay buffer unit, for example, two delay buffer units exist in the delay chain, the input signal at the moment is 10, the corresponding input signal of the first delay buffer unit is 1, and the corresponding input signal of the second delay buffer unit is 0; for a single delay buffer unit, input signals are 0 and 1, when the input is 0, the corresponding first control signal and second control signal control the first control switch and the second control switch to be conducted, the memristor in the delay buffer unit is bypassed, and when the input is 1, the corresponding first control signal and second control signal control the first control switch and the second control switch to be turned off, so that the memristor in the delay buffer unit participates in RC delay.

For example, after the object output signal is obtained, the object output signal may be quantized, and the time signal may be converted into a digital signal, which specifically includes the following steps:

S204, acquiring time delay between the time pulse signal and the object output signal;

s205, quantizing the delay to obtain a digital output signal;

S206, subtracting the check data from the digital output signal to obtain a check output of the delay buffer array.

The check data is the systematic error DOUT0 of the delay buffer array under the input of all 0. For example, the delay may be quantized by the output quantization module 104 as shown in fig. 5

Fig. 7 is a flowchart of another method for operating a delay buffer array according to at least one embodiment of the present disclosure, where the method is applied to the delay buffer array according to any one of the above embodiments, as shown in fig. 7, and the method includes steps S301 to S302.

S301, selecting one delay buffer unit in the delay buffer array as a unit to be programmed;

S302, applying a first control signal to control a first control switch in a unit to be programmed, and applying a first programming voltage to two ends of a first memristor in the unit to be programmed to change the resistance value of the first memristor; or applying a second control signal to control a second control switch in the unit to be programmed, and applying a second programming voltage to two ends of a second memristor in the unit to be programmed to change the resistance value of the second memristor.

For example, a delay buffer unit as a unit to be programmed may be selected by a column selection module 107 and a row selection module 108 as shown in fig. 5. As described above, the time pulse input module 101 inputs, for example, a low level, and the programming voltage generating module 102 performs the first processing operation on the memristor to implement programming of the memristor, and the specific process is not described herein.

It should be noted that, the initializing operation of the memristor is only required to be performed once, the programming operation of the memristor may be performed multiple times to adjust (program) the resistance value of the memristor until the programming requirement is met, for example, after performing a set operation or a reset operation on the memristor, in a conventional manner, a read operation may also be performed on the memristor to verify whether the resistance value of the memristor reaches the expected resistance value, and if the resistance value of the memristor does not reach the expected resistance value, the set operation or the reset operation may be performed on the memristor again until the resistance value of the memristor reaches the expected resistance value, so as to determine whether the resistance value of the memristor reaches the expected specific step:

s303, providing a time pulse signal at the input end of a delay chain corresponding to the unit to be programmed;

S304, a first control switch and a second control switch of a unit to be programmed are controlled to be turned off, the first control switch and the second control switch of a delay buffer unit except the unit to be programmed in a delay chain corresponding to the unit to be programmed are controlled to be turned on, and an output signal of the delay chain corresponding to the unit to be programmed is obtained to be used as a first programming output; or the first control switch and the second control switch of the unit to be programmed are controlled to be turned on and turned off, the first control switch and the second control switch of the delay buffer units except the unit to be programmed in the delay chain corresponding to the unit to be programmed are controlled to be turned on, and the output signal of the delay chain corresponding to the unit to be programmed is obtained to be used as the second programming output;

S305, determining whether the resistance value of the first memristor or the resistance value of the second memristor of the unit to be programmed meets programming requirements according to the first programming output or the second programming output.

Fig. 8A and fig. 8B are schematic diagrams illustrating a program verification of a delay buffer unit according to at least one embodiment of the present disclosure.

As shown in fig. 8A, m delay buffer units according to any one of the embodiments are connected in series to form a delay chain, each delay buffer unit includes a first delay buffer subunit NCELL and a second delay buffer subunit PCELL connected in series, an input pulse W1 is poured into an input end of the delay chain, an output end obtains an output pulse W2, one delay buffer unit in the delay chain is selected as a unit to be programmed (first delay subunit NCELL in the figure), delay generated by each delay buffer unit on the input pulse is W < m-1> (for example, delay generated by the first delay buffer unit on the input pulse is W <0 >), intrinsic delay generated by all delay buffer subunits in the delay chain on a rising edge of the input pulse W1 is tr_int, intrinsic delay generated on a falling edge of the input pulse W1 is tf_int, a first control switch in the first delay subunit NCELL to be programmed is controlled by a control signal, delay time is W < m-1> (the rest delay subunits NCELL in the figure), delay generated by each delay buffer unit on the input pulse is W < m > (for example, delay generated by the first delay buffer subunit on the input pulse is W <0 >), and the intrinsic delay generated by all delay buffer subunits in the delay chain on the input pulse W1 on the rising edge is tr_int, and the first delay buffer subunit NCELL is controlled by the control signal.

As shown in fig. 8B, the second control switch in the second delay sub-unit PCELL of the unit to be programmed in fig. 8A is controlled to be turned on by the control signal, and the first control switches in all the first delay sub-units NCELL in the delay chain and the second control switch in the Yu Dier delay sub-unit PCELL thereof are controlled to be turned on by the control signal, so that the other configurations are the same as those in fig. 8A and are not repeated here. At this time, only the memristors in the second delay subunit PCELL of the cells to be programmed in the delay chain participate in RC delay, and the influence on the falling edge delay of the input pulse W1 is R0 ^- C. Therefore, whether the resistance values of two memristors in the unit to be programmed meet the requirements can be judged according to the sizes of R0 ⁺ C and R0 ^- C.

The above is a process of performing program verification on a single cell before performing the calculation mode, that is, a process of writing weights; the programming verification of the weights is also performed in the time domain, i.e. the criterion for the weight programming is the delay rather than the conductance in the conventional sense. When the positive weight is programmed, as shown in fig. 8A, only the NCELL of the selected cell is input 1, and the PCELL in the cell and the PCELL and NCELL of the other cells are both input 0, so that only the NCELL tribute rising edge RC delay of the selected cell is input on the whole delay chain, and therefore, the weight definition and correction of the NCELL of the selected cell can be performed according to the relative width of the input and output pulses; for programming of negative weights, as shown in fig. 8B, only PCELL of the selected cell is input 1, and PCELLs and NCELLs of other cells in the cell are input 0, so that only PCELLs of the selected cell contribute to the falling edge RC delay over the whole delay chain, and thus weight definition and correction of PCELLs of the selected cell can be performed according to the relative width of input/output pulses.

Fig. 9 is a flowchart of another method for operating a delay buffer array according to at least one embodiment of the present disclosure, where the method is applied to the delay buffer array according to any one of the above embodiments, as shown in fig. 9, and the method includes steps S401 to S404.

S401, providing a time pulse signal at the input end of a delay chain selected for verification operation in a delay buffer array;

S402, respectively applying a first control signal and a second control signal which are used as input signals to each delay buffer unit in a delay chain selected for verification operation in a delay buffer array so as to control the first control switch and the second control switch of each delay buffer unit to be conducted;

S403, the output end of the delay chain selected for verification operation in the delay buffer array acquires an output signal to be used as an intrinsic output;

S404, quantifying the delay between the intrinsic output and the time pulse signal to obtain verification data of a delay chain selected for verification operation in the delay buffer array.

For example, a time pulse signal may be provided by the time pulse input module 101 as shown in fig. 5, a delay chain corresponding to a delay buffer unit for verification operation is selected by the column selection module 107 and the row selection module 108, a first control signal and a second control signal which are all 0 are provided by the input loading module 103 to control all the first control switches and the second control switches in the delay chain to be turned on, and delay between an intrinsic output and an input time pulse signal is quantized by the output quantization module 104 to obtain a systematic error DOUT0 as verification data.

At least one embodiment of the present disclosure further provides an electronic device, which includes the delay buffer array according to any one of the embodiments, and the delay conversion array may be, for example, a structure as shown in fig. 5.

The electronic device may be, for example, a processor or any other product or component that includes the processor in combination with the processor. For another example, the electronic device may be a server device or a terminal device, and for example, the terminal device may be a mobile phone, a notebook computer, or the like.

According to the delay buffer unit, the array, the electronic device and the operation method of the array, which are provided by the embodiment of the disclosure, the calculation precision can be ensured under the condition that the unit area is reduced and fewer transistors are used, delay signals with ideal slopes and rising edges are output, and the dynamic power consumption is reduced.

For example, in at least one embodiment, the forward computation paradigm of an array of delay buffer units may support fully parallel matrix vector multiplication within a row; for example, systematic errors due to non-ideal factors such as process can be counteracted by checking the data.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

In addition to the exemplary descriptions above, for the present disclosure, the following points are described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A delay buffer unit comprises a first delay buffer subunit and a second delay buffer subunit which are connected in series,

The first delay buffer subunit comprises a first-stage inverter, a second-stage inverter and a first delay regulating subunit, wherein the input end of the first-stage inverter is used as the input end of the delay buffer unit, the input end of the second-stage inverter is connected with the output end of the first-stage inverter, the first-stage delay regulating subunit is connected with the first end, the first operating voltage end and the second operating voltage end of the first-stage inverter,

The second delay buffer subunit comprises a third-stage inverter, a fourth-stage inverter and a second delay regulating subunit, wherein the input end of the third-stage inverter is connected with the output end of the second-stage inverter, the input end of the fourth-stage inverter is connected with the output end of the third-stage inverter, the output end of the fourth-stage inverter is used as the output end of the delay buffer unit, the second delay regulating subunit is connected with the second end, the third operating voltage end and the fourth operating voltage end of the third-stage inverter,

Wherein the first delay adjustment subunit comprises a first memristor and a first control switch configured to determine whether to adjust a first delay of the first delay buffer subunit using the first memristor in accordance with the first control switch, the second delay adjustment subunit comprises a second memristor and a second control switch configured to determine whether to adjust a second delay of the second delay buffer subunit using the second memristor in accordance with the second control switch,

The first delay buffer subunit and the second delay buffer subunit are respectively configured to have opposite effects on edge slopes of pulse signals passing through the delay buffer units.

2. The delay buffer cell of claim 1, wherein the first and second operating voltage terminals have voltages lower than the third and fourth operating voltage terminals, at least one of the first and second operating voltage terminals acting as a discharge voltage terminal when the first delay buffer subunit is operating,

At least one of the third operating voltage terminal and the fourth operating voltage terminal is used as a charging voltage terminal when the second delay buffer subunit works.

3. The delay buffer unit of claim 1, wherein the type of the first control switch is different from the type of the second control switch.

4. The delay buffer unit of claim 1, wherein the first control switch comprises a first pole, a second pole and a first control pole, the first control pole receiving a first control signal to turn on or off the first pole and the second pole of the first control switch according to the first control signal, the first pole of the first control switch being electrically connected to a first end of the first stage inverter, the second pole of the first control switch being electrically connected to the first operating voltage end,

A first end of the first memristor is electrically connected with a first pole of the first control switch and a first end of the first stage inverter, and a second end of the first memristor is electrically connected with the second operation voltage end;

The second control switch comprises a first pole, a second pole and a second control pole, the second control pole receives a second control signal to conduct or cut off the first pole and the second pole of the second control switch according to the second control signal, the first pole of the second control switch is electrically connected with the second end of the third-stage inverter, the second pole of the second control switch is electrically connected with the third operation voltage end,

The first end of the second memristor is electrically connected with the first pole of the second control switch and the second end of the third-stage inverter, and the second end of the second memristor is electrically connected with the fourth operation voltage end;

The first control signal and the second control signal are inverted from each other.

5. The delay buffer cell of claim 4, wherein the first delay adjustment subunit comprises a first adjustment capacitance and is configured to adjust a delay of the first delay buffer subunit using the first memristor and the first adjustment capacitance in accordance with the first control signal,

The second delay adjustment subunit includes a second adjustment capacitance and is configured to adjust a delay of the second delay buffer subunit using the second memristor and the second adjustment capacitance in accordance with a second control signal.

6. The delay buffer cell of claim 5, wherein the capacitance of the first adjustment capacitance is the same as the capacitance of the second adjustment capacitance.

7. A delay buffer array comprising a plurality of delay buffer cells as claimed in any one of claims 1 to 6, wherein the plurality of delay buffer cells are arranged in an array having a plurality of rows, and the delay buffer cells in each row are serially connected in turn to form a delay chain.

8. The delay buffer array of claim 7, wherein the delay buffer array further comprises:

the time pulse input module is configured to respectively provide time pulse signals at the input ends of the delay chains;

the programming voltage generation module is configured to perform memristor programming on the target delay buffer unit;

An input loading module configured to provide a first control signal and a second control signal as input signals for each delay buffer unit;

The output quantization module is configured to quantize the outputs of the delay chains respectively to obtain digital output signals;

the data storage module is configured to store data when the delay buffer array performs calculation;

and the mode control module is configured to control an operation mode executed by the delay buffer array.

9. An electronic device comprising a delay buffer array as claimed in any one of claims 7 or 8.

10. A method of operation of a delay buffer array, applied to the delay buffer array of any of claims 7-8, the method of operation of the delay buffer array comprising:

Providing a time pulse signal at an input of a delay chain selected for a computational operation in the delay buffer array;

applying a first control signal and a second control signal as input data signals to each delay buffer unit in a delay chain selected for calculation operation in the delay buffer array, wherein the input data signals control the first control switch and the second control switch of the delay buffer unit corresponding to the input data signals to be switched on or off;

The output of the delay chain selected for the computational operation in the delay buffer array obtains an object output signal.

11. The method of claim 10, wherein the input data signal applied to each delay buffer cell in the same delay chain selected for the computational operation is 1 bit of multi-bit data, respectively.

12. The method of operation of a delay buffer array of claim 10, wherein the method of operation of a delay buffer array after the output of the delay chain selected for computational operations acquires an output signal further comprises:

Acquiring a time delay between the time pulse signal and the object output signal;

quantizing the delay to obtain a digital output signal;

And subtracting the check data from the digital output signal to obtain a check output of the delay buffer array.

13. A method of operation of a delay buffer array as claimed in any one of claims 7 to 8, the method of operation comprising:

selecting one delay buffer unit in the delay buffer array as a unit to be programmed;

Applying the first control signal to control a first control switch in the unit to be programmed, and applying a first programming voltage to two ends of a first memristor in the unit to be programmed to change the resistance value of the first memristor; or applying the second control signal to control a second control switch in the unit to be programmed, and applying a second programming voltage to two ends of a second memristor in the unit to be programmed to change the resistance value of the second memristor.

14. The method of operation of a delay buffer array of claim 13, wherein after changing the resistance of the first memristor or changing the resistance of the second memristor, the method of operation further comprises:

Providing a time pulse signal at the input end of a delay chain corresponding to the unit to be programmed;

The method comprises the steps of controlling a first control switch and a second control switch of a unit to be programmed to be turned off and turned on, controlling the first control switch and the second control switch of a delay buffer unit except the unit to be programmed in a delay chain corresponding to the unit to be programmed to be turned on, and obtaining an output signal of the delay chain corresponding to the unit to be programmed to be used as a first programming output; or the first control switch and the second control switch of the unit to be programmed are controlled to be on and off, the first control switch and the second control switch of the delay buffer units except the unit to be programmed in the delay chain corresponding to the unit to be programmed are controlled to be on, and the output signal of the delay chain corresponding to the unit to be programmed is obtained to be used as the second programming output;

and determining whether the resistance value of the first memristor or the resistance value of the second memristor of the unit to be programmed meets programming requirements according to the first programming output or the second programming output.

15. A method of operation of a delay buffer array as claimed in any one of claims 7 to 8, the method of operation comprising:

Providing a time pulse signal at an input of a delay chain selected for a verify operation in the delay buffer array;

Respectively applying a first control signal and a second control signal which are used as input signals to each delay buffer unit in a delay chain selected for verification operation in the delay buffer array so as to control the first control switch and the second control switch of each delay buffer unit to be conducted;

The output end of the delay chain selected for verification operation in the delay buffer array acquires an output signal as an intrinsic output;

and quantifying the delay between the intrinsic output and the time pulse signal to obtain verification data of a delay chain selected for verification operation in the delay buffer array.