CN118138026A - Delay buffer unit, electronic device, delay buffer array and operation method thereof - Google Patents

Abstract

The present disclosure provides a delay buffer unit, a delay buffer array, an electronic device and an operation method of the delay buffer array, wherein the delay buffer unit comprises a first delay buffer sub-unit and a second delay buffer sub-unit connected in series, wherein the first delay buffer sub-unit and the second delay buffer sub-unit are respectively configured to have opposite effects on the edge slope of a pulse signal passing through the delay buffer unit. Through the delay buffer unit, it can be used for storage and calculation in one to realize matrix-vector multiplication operations, and can reduce the hardware overhead of the storage and calculation in one circuit while ensuring that the output delay signal still has a falling edge and a rising edge with a relatively ideal slope.

Description

Delay buffer unit, electronic device, delay buffer array and operation method thereof

Technical Field

Embodiments of the present disclosure relate to a delay buffer unit, a delay buffer unit array, an electronic device, and an operating method of the delay buffer unit array.

Background technique

Memristors (e.g., resistive random access memory, phase change memory, conductive bridge memory, etc.) are non-volatile devices whose conductance state can be adjusted by applying external stimuli. Memristors are two-terminal devices with adjustable resistance and non-volatility, so they are widely used in storage and computing. According to Kirchhoff's current law and Ohm's law, an array composed of memristors can perform multiplication and accumulation calculations in parallel, and both storage and calculation occur in each device in the array.

The storage-computing integrated computing architecture can achieve higher computing power and energy efficiency by avoiding the storage wall problem. The non-volatile memory storage-computing integrated system can reduce the complexity of matrix-vector multiplication from O(n2) to O(1) by using its cross-array structure.

Public Content

Some embodiments of the present disclosure provide a delay buffer unit, the delay buffer unit comprising a first delay buffer subunit and a second delay buffer subunit connected in series, the first delay buffer subunit comprising a first-stage inverter, a second-stage inverter and a first delay adjustment subunit, the input end of the first-stage inverter serving as the input end of the delay buffer unit, the input end of the second-stage inverter connected to the output end of the first-stage inverter, the first-stage delay adjustment subunit connected to the first end, the first operating voltage end and the second operating voltage end of the first-stage inverter, the second delay buffer subunit comprising a third-stage inverter, a fourth-stage inverter and a second delay adjustment subunit, the input end of the third-stage inverter connected to the output end of the second-stage inverter, the input end of the fourth-stage inverter connected to the output end of the third-stage inverter, The output end of the fourth-stage inverter serves as the output end of the delay buffer unit, and the second-stage delay adjustment subunit is connected to the second end, the third operating voltage end and the fourth operating voltage end of the third-stage inverter, wherein the first delay adjustment subunit includes a first memristor and a first control switch, and is configured to determine whether to use the first memristor to adjust the first delay of the first delay buffer subunit according to the first control switch, and the second delay adjustment subunit includes a second memristor and a second control switch, and is configured to determine whether to use the second memristor to adjust the second delay of the second delay buffer subunit according to the second control switch, and the first delay buffer subunit and the second delay buffer subunit are respectively configured to have opposite effects on the edge slope of the pulse signal passing through the delay buffer unit.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the voltages of the first operating voltage terminal and the second operating voltage terminal are lower than the voltages of the third operating voltage terminal and the fourth operating voltage terminal, and at least one of the first operating voltage terminal and the second operating voltage terminal serves as a discharge voltage terminal when the first delay buffer sub-unit is working, and at least one of the third operating voltage terminal and the fourth operating voltage terminal serves as a charging voltage terminal when the second delay buffer sub-unit is working.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the type of the first control switch is different from the type of the second control switch.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the first control switch includes a first pole, a second pole and a first control pole, the first control pole receives a first control signal to turn on or off the first pole and the second pole of the first control switch according to the first control signal, the first pole of the first control switch is electrically connected to the first end of the first-stage inverter, the second pole of the control switch is electrically connected to the first operating voltage end, the first end of the first memristor is electrically connected to the first pole of the first control switch and the first end of the first-stage inverter, and the second end of the first memristor is electrically connected to the second operating voltage end; the second control switch includes a first pole, a second pole and a second control pole, the second control pole receives a second control signal to turn on or off the first pole and the second pole of the second control switch according to the second control signal, the first pole of the second control switch is electrically connected to the second end of the third-stage inverter, the second pole of the second control switch is electrically connected to the third operating voltage end, the first end of the second memristor is electrically connected to the first pole of the second control switch and the second end of the third-stage inverter, and the second end of the second memristor is electrically connected to the fourth operating voltage end; the first control signal and the second control signal are inverted to each other.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the first delay adjustment subunit includes a first adjustment capacitor, and is configured to adjust the delay of the first delay buffer subunit using the first memristor and the first adjustment capacitor according to the first control signal, and the second delay adjustment subunit includes a second adjustment capacitor, and is configured to adjust the delay of the second delay buffer subunit using the second memristor and the second adjustment capacitor according to the second control signal.

For example, in a delay buffer unit provided in some embodiments of the present disclosure, the capacitance of the first adjustment capacitor is the same as the capacitance of the second adjustment capacitor.

Some embodiments of the present disclosure further provide a delay buffer array, comprising a plurality of delay buffer units as described in any of the above embodiments, wherein the plurality of delay buffer units are arranged in an array having a plurality of rows, and the delay buffer units in each row are sequentially connected in series to form a delay chain.

For example, in a delay buffer array provided in some embodiments of the present disclosure, the delay buffer array also includes: a time pulse input module, configured to provide time pulse signals to the input ends of multiple delay chains respectively; a programming voltage generation module, configured to perform memristor programming on the target delay buffer unit; an input loading module, configured to provide a first control signal and a second control signal as input signals for each delay buffer unit; an output quantization module, configured to quantize the outputs of the multiple delay chains respectively to obtain digital output signals; a data storage module, configured to store data when the delay buffer array performs calculations; and a mode control module, configured to control the operation mode executed by the delay buffer array.

Some embodiments of the present disclosure further provide an electronic device, comprising a delay buffer array as described in any of the above embodiments.

Some embodiments of the present disclosure also provide an operating method for a delay buffer array, which is applied to the delay buffer array described in any of the above embodiments, and the operating method of the delay buffer array includes: providing a time pulse signal at the input end of the delay chain selected for computing operations in the delay buffer array; applying a first control signal and a second control signal as input data signals to each delay buffer unit in the delay chain selected for computing operations in the delay buffer array, respectively, wherein the input data signal controls the first control switch and the second control switch of the delay buffer unit corresponding to the input data signal to be turned on or off; and obtaining an object output signal at the output end of the delay chain selected for computing operations in the delay buffer array.

For example, in a method for operating a delay buffer array provided in some embodiments of the present disclosure, the input data signal applied to each delay buffer unit in the same delay chain selected for computing operation is 1 bit of multi-bit data.

For example, in an operating method of a delay buffer array provided in some embodiments of the present disclosure, after obtaining an output signal at the output end of the delay chain selected for calculation operation in the delay buffer array, the operating method of the delay buffer array further includes: obtaining the delay between the time pulse signal and the object output signal; quantizing the delay to obtain a digital output signal; and subtracting verification data from the digital output signal to obtain a verification output of the delay buffer array.

Some embodiments of the present disclosure also provide another method for operating a delay buffer array, which is applied to the delay buffer array described in any of the above embodiments, and the operating method includes: selecting a delay buffer unit in the delay buffer array as a unit to be programmed; applying the first control signal to control the first control switch in the unit to be programmed, and applying a first programming voltage to both ends of a first memristor in the unit to be programmed to change the resistance value of the first memristor; or, applying the second control signal to control the second control switch in the unit to be programmed, and applying a second programming voltage to both ends of a second memristor in the unit to be programmed to change the resistance value of the second memristor.

For example, in an operation method of a delay buffer array provided in some embodiments of the present disclosure, after changing the resistance value of the first memristor or changing the resistance value of the second memristor, the operation method also includes: providing a time pulse signal at the input end of the delay chain corresponding to the unit to be programmed; controlling the first control switch of the unit to be programmed to be turned off and the second control switch to be turned on, and controlling the first control switch and the second control switch of the delay buffer unit other than the unit to be programmed in the delay chain corresponding to the unit to be programmed to be turned on, and obtaining the output signal of the delay chain corresponding to the unit to be programmed as the first programming output; or, controlling the first control switch of the unit to be programmed to be turned on and the second control switch to be turned off, and controlling the first control switch and the second control switch of the delay buffer unit other than the unit to be programmed in the delay chain corresponding to the unit to be programmed to be turned on, and obtaining the output signal of the delay chain corresponding to the unit to be programmed as the second programming output; determining whether the resistance value of the first memristor or the resistance value of the second memristor of the unit to be programmed meets the programming requirements according to the first programming output or the second programming output.

Some embodiments of the present disclosure also provide another operation method of a delay buffer array, which is applied to the delay buffer array described in any of the above embodiments, and the operation method includes: providing a time pulse signal at the input end of the delay chain selected for the verification operation in the delay buffer array; applying a first control signal and a second control signal as input signals to each delay buffer unit in the delay chain selected for the verification operation in the delay buffer array, respectively, to control the conduction of the first control switch and the second control switch of each delay buffer unit; obtaining an output signal at the output end of the delay chain selected for the verification operation in the delay buffer array as an intrinsic output; and quantifying the delay between the intrinsic output and the time pulse signal to obtain verification data of the delay chain selected for the verification operation in the delay buffer array.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

FIG1A is a schematic diagram of the structure of an exemplary delay buffer unit;

FIG1B is a schematic diagram of the structure of another exemplary delay buffer unit;

FIG1C is a schematic diagram of the structure of an exemplary delay chain;

FIG1D is a schematic diagram of the structure of an exemplary computing device;

FIG2 is a schematic diagram of a delay buffer unit structure provided by at least one embodiment of the present disclosure;

FIG3A is a schematic diagram of the working principle of a delay buffer unit provided by at least one embodiment of the present disclosure;

FIG3B is a schematic diagram of the working principle of a delay buffer unit provided by at least one embodiment of the present disclosure;

FIG4 is a schematic diagram of a series structure of delay buffer units provided by at least one embodiment of the present disclosure;

FIG5 is a schematic diagram of a delay buffer array structure provided by at least one embodiment of the present disclosure;

FIG6 is a flow chart of a delay buffer array operation method provided by at least one embodiment of the present disclosure;

FIG7 is a flow chart of another delay buffer array operation method provided by at least one embodiment of the present disclosure;

FIG8A is a schematic diagram of a delay buffer unit programming verification provided by at least one embodiment of the present disclosure;

FIG8B is a schematic diagram of another delay buffer unit programming verification provided by at least one embodiment of the present disclosure; and

FIG. 9 is a flow chart of another delay buffer array operation method provided by at least one embodiment of the present disclosure.

Detailed ways

In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings. The specific embodiments and drawings described herein are only used to explain the present disclosure rather than to limit the disclosed embodiments. In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

For ease of description, the drawings of the embodiments of the present disclosure only show the parts related to the embodiments of the present disclosure, while the parts unrelated to the embodiments of the present disclosure are not shown in the drawings. Each unit and module involved in the embodiments of the present disclosure may correspond to only one entity structure, or may be composed of multiple entity structures, or multiple units and modules may be integrated into one entity structure. In the absence of conflict, the functions and steps marked in the flowcharts and block diagrams of the embodiments of the present disclosure may occur in an order different from that marked in the drawings.

The flowcharts and block diagrams of the embodiments of the present disclosure illustrate the possible architectures, functions, and operations of the systems, devices, equipment, and methods according to the embodiments of the present disclosure. Each box in the flowchart or block diagram may represent a unit, module, program segment, or code, which contains executable instructions for implementing the specified functions. Moreover, each box or combination of boxes in the block diagram and flowchart may be implemented by a hardware-based system that implements the specified functions, or may be implemented by a combination of hardware and computer instructions.

In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components (elements) may be omitted. When any component (element) of the embodiments of the present disclosure appears in more than one drawing, the component (element) is represented by the same or similar reference numerals in each drawing.

Memristor is a new type of information processing device with the function of storage and computing fusion. It can perform computing operations on stored data in situ, thereby eliminating the huge overhead of data movement. In addition, memristors can perform operations directly in the analog domain (for example, memristors can complete multiplication operations based on Ohm's law and addition operations based on Kirchhoff's current law), thereby realizing matrix-vector multiplication operations in one step, and there is no need for the overhead of digital-to-analog conversion during the operation process. In recent years, memristor-based storage and computing have made significant progress. However, since the power supply support of terminal equipment is limited, the memristor-based storage and computing device is required to have not only higher-precision calculations, but also lower energy consumption and higher energy efficiency. To this end, the memristor storage and computing design has made many improvements in array structure and peripheral circuit design.

For example, one improved solution is a voltage domain quantization solution, which uses voltage precharge type reading to replace the current type reading solution with excessive static current overhead, but the output range of this solution is limited. For example, another improved solution is a time domain quantization method, which transfers the output result to the time domain to increase the output range, so as to distinguish different output states more simply and efficiently, etc., but the output of time domain quantization has nonlinear problems. In addition, whether it is a voltage domain or a time domain quantization solution, it is necessary to deal with the large current flowing through the memristor array when it is opened in parallel. The large current on the memristor array and its peripheral circuits will generate large power consumption. For example, another improved solution is a current type analog calculation solution based on a 2T2R array structure, which alleviates the IR drop problem of the routing by reducing the cumulative output current. It is a high parallel and high computing power calculation method. However, in order to ensure the calculation accuracy, this calculation method requires a large input power consumption and clamping circuit power consumption, and when the array scale is large, it will also generate large power consumption.

The above-mentioned memristor storage-computation integrated array and circuit design scheme cannot meet the requirements of extreme low power consumption and high energy efficiency in parallel processing due to the limitation of its computing mechanics. The inventor of the present disclosure proposes a computing array that uses a memristor delay structure as a basic computing unit, and then uses the delay accumulation of each unit to realize the storage-computation integrated matrix-vector multiplication operation. The computing array can avoid the need to process large currents during the calculation process, and lower the working power supply voltage to achieve high energy efficiency.

FIG. 1A is a schematic diagram showing the structure of an exemplary delay buffer unit; FIG. 1B is a schematic diagram showing the structure of another exemplary delay buffer unit.

For example, one solution uses a delay buffer unit as shown in Figure 1A and Figure 1B to control the delay between input and output. The transmission delay of the delay buffer unit can be changed according to whether a memristor is used. The transmission delay of the delay buffer unit can also be changed by controlling the change in the resistance value of the memristor, thereby realizing dynamic regulation of the delay buffer unit and being able to flexibly and efficiently regulate the size of the delay according to actual needs.

As shown in the example of FIG. 1A and FIG. 1B , the delay buffer unit 10 includes a first-stage inverter P1 , a second-stage inverter P2 , and a delay adjustment subunit 11 .

For example, the input end of the first-stage inverter P1 serves as the input end INT of the delay buffer unit 10. The input signal of the delay buffer unit can be received from the input end of the first-stage inverter P1, and the input signal can be, for example, a rising edge trigger signal (as shown in FIG. 1A ) or a falling edge trigger signal (as shown in FIG. 1B ). For example, the first-stage inverter P1 includes two transistors T1 and T2, T1 is, for example, an NMOS tube, and transistor T2 is, for example, a PMOS tube. The gate ends of transistors T1 and T2 can serve as input ends, that is, as the input end INT of the delay buffer unit 10 to receive input signals. For example, when the input signal is at a high level, transistor T1 is turned on and transistor T2 is turned off. When the input signal is at a low level, transistor T1 is turned off and transistor T2 is turned on. The drain ends of transistors T1 and T2 are electrically connected to each other and serve as the output end of the first-stage inverter P1. The source end of transistor T1 or T2 can be connected to the ground end or the power supply end, or can serve as the first end of the first-stage inverter P1.

For example, the input of the second inverter P2 is connected to the output of the first inverter P1, and the output of the second inverter P2 serves as the output OUT of the delay buffer unit 10. The circuit structure of the second inverter P2 is similar to that of the first inverter P1.

For example, the output signal of the delay buffer unit 10 can be output from the output terminal of the second-stage inverter P2, and the output signal corresponds to the input signal and has a certain delay relative to the input signal, and the delay is composed of the transmission delay of the first-stage inverter P1 and the second-stage inverter P2. For example, as shown in FIG1A, when the input signal received from the input terminal INT of the delay buffer unit 10 is a rising edge trigger signal, the output signal output from the output terminal OUT of the delay buffer unit 10 has a certain delay t relative to the rising edge trigger signal (the rising edge trigger signal and the output signal are represented by a gray line and a black line at the output terminal OUT in FIG1A, respectively). For example, as shown in FIG1B, when the input signal received from the input terminal INT of the delay buffer unit 10 is a falling edge trigger signal, the output signal output from the output terminal OUT of the delay buffer unit 10 has a certain delay t relative to the falling edge trigger signal (the falling edge trigger signal and the output signal are represented by a gray line and a black line at the output terminal OUT in FIG1B, respectively).

For example, the delay adjustment subunit 11 is connected between the first end of the first-stage inverter P1 and the first operating voltage terminal 1, and the delay adjustment subunit 11 includes a memristor (here, a resistive random access memory (RRAM) is used as an example), and the delay adjustment subunit 11 is configured to control the use of the memristor RRAM to adjust the transmission delay of the first-stage inverter P1 according to the first input signal NWL. For example, the first input signal NWL is used to control whether the delay adjustment subunit 11 uses the memristor RRAM to adjust the transmission delay of the first-stage inverter P1, thereby adjusting the delay difference (delay t) between the output signal and the input signal of the delay buffer unit 10.

For example, the delay adjustment subunit 11 also includes a control switch, which can be an N-type transistor or a P-type transistor. The control switch (here taking the N-type transistor (NM1) as an example) includes a first electrode, a second electrode and a control electrode, and the first electrode, the second electrode and the control electrode of the first control switch NM1 can be, for example, the source, the drain and the gate of the N-type transistor, respectively. The control electrode of the first control switch NM1 is connected to the first input signal NWL, and the first electrode and the second electrode of the first control switch NM1 are turned on or off according to the first input signal NWL. For example, the first electrode of the first control switch NM1 is electrically connected to the first end of the first-stage inverter P1, and the second electrode of the first control switch NM1 is electrically connected to the first operating voltage terminal 1. When the first control switch NM1 is turned on, the first-stage inverter P1 is connected to the first operating voltage terminal 1, and when the first control switch NM1 is turned off, the first-stage inverter P1 is disconnected from the first operating voltage terminal 1. The first control switch NM1 can be an N-type transistor (as shown in FIG. 1A) or a P-type transistor.

For example, the memristor RRAM in the delay adjustment subunit 11 includes a first end and a second end, and the first end of the memristor RRAM is electrically connected to the first pole of the first control switch NM1 and the first end of the first-stage inverter P1. The second end of the memristor RRAM and the second pole of the first control switch NM1 can be connected to the same operating voltage terminal or different operating voltage terminals. Here, the second end of the memristor RRAM and the second pole of the first control switch NM1 are connected to different operating voltage terminals, indicating that the two obtain voltage signals from different operating voltage terminals, respectively.

For example, in one example, the second end of the memristor RRAM can be electrically connected to the first operating voltage terminal 1, that is, the second end of the memristor RRAM and the second pole of the first control switch NM1 are connected to the first operating voltage terminal, and the first operating voltage terminal 1 can be, for example, a power supply terminal or a ground terminal. For example, in another example, the second end of the memristor RRAM is electrically connected to the second operating voltage terminal 2, the second pole of the first control switch NM1 is electrically connected to the first operating voltage terminal 1, and the voltage signals provided by the first operating voltage terminal 1 and the second operating voltage terminal 2 are different. For example, in yet another example, the second end of the memristor RRAM is electrically connected to the first operating voltage terminal 1, the second pole of the first control switch NM1 is electrically connected to the second operating voltage terminal 2, and the first operating voltage terminal 1 and the second operating voltage terminal 2 are different.

The delay adjustment subunit 11 is connected to the first end of the first-stage inverter P1, for example, connected to the source end of the first-stage inverter P1. For example, as shown in FIG1A , the delay adjustment subunit 11 is connected between the NMOS tube T1 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in the delay adjustment subunit 11 shown in FIG1A , the first pole (for example, the drain) of the first control switch NM1 is connected to the source end of the NMOS tube T1 in the first-stage inverter P1, and the first end of the memristor RRAM is connected to the source end of the NMOS tube T1 in the first-stage inverter P1. For example, as shown in FIG1B , the delay adjustment subunit 11 is connected between the PMOS tube T2 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in the delay adjustment subunit 11 shown in Figure 1B, the first pole (for example, the source) of the first control switch NM1 is connected to the source end of the PMOS tube T2 in the first-stage inverter P1, and the first end of the memristor RRAM is connected to the source end of the PMOS tube T2 in the first-stage inverter P1.

For example, the delay buffer unit 10 further includes a capacitor C1, a first electrode of which is connected between the output of the first inverter P1 and the input of the second inverter P2, and a second electrode of which is grounded. The capacitor C1 may be a specially prepared capacitor element or a parasitic capacitor.

For example, in the delay buffer unit 10 shown in FIG1A , when the input signal received from the input terminal INT of the delay buffer unit 10 is a low-level signal, the NMOS tube T1 in the first-stage inverter P1 is turned off, and the PMOS tube T2 is turned on, thereby disconnecting the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1. In this case, the delay adjustment subunit 11 can be connected to the first operating voltage terminal 1 and the second operating voltage terminal 2 to perform a first processing operation on the memristor RRAM according to the signal provided by the second operating voltage terminal 2. For example, the first processing operation performed on the memristor RRAM can be a set operation, a reset operation, or an initialization operation to change the resistance value of the memristor.

For memristors (e.g., resistive random access memory), an additional initialization process is usually required. After the initialization is completed, the resistance value of the memristor can change with the applied voltage signal. Since there are no conductive filaments inside the memristor when it is prepared, it is necessary to form conductive filaments inside the memristor through an initialization operation. The initialization operation usually only needs to be performed once in the life cycle of the memristor.

For example, in the delay cache unit 10 shown in FIG1A , after the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1 is disconnected, an initialization voltage may be applied between the first operating voltage terminal 1 and the second operating voltage terminal 2 to initialize the memristor so that a conductive filament is formed inside the memristor. For example, after the conductive filament is formed inside the memristor RRAM through initialization, the memristor RRAM has a threshold voltage.

For example, the mainstream approach is that when the input voltage amplitude applied between the first terminal and the second terminal of the memristor RRAM is less than the threshold voltage of the memristor RRAM, the resistance value (or conductance value) of the memristor RRAM will not be changed. In this case, a read voltage can be applied between the first operating voltage terminal and the second operating voltage terminal to read the current resistance value of the memristor RRAM. The read voltage is less than the threshold voltage of the memristor RRAM, so that the current resistance value of the memristor can be read without changing the resistance value of the memristor.

For example, when the input voltage amplitude applied between the first end and the second end of the memristor RRAM is greater than the threshold voltage of the memristor RRAM, the resistance value (or conductance value) of the memristor RRAM can be changed according to the set voltage or reset voltage applied between the first end and the second end of the memristor RRAM. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. For example, applying a set voltage to the memristor RRAM can reduce the resistance value of the memristor RRAM, and applying a reset voltage to the memristor RRAM can increase the resistance value of the memristor RRAM. Applying a set voltage to the memristor is called a set operation, and applying a reset voltage to the memristor is called a reset operation.

FIG1C shows a schematic diagram of the structure of an exemplary delay chain. As shown in FIG1C , a plurality of delay buffer units 10 are cascaded to form a row of delay chains 20, and an input signal KEEP is received from an input terminal INT of a first delay buffer unit 10 of the delay chain 20. The input signal KEEP may be, for example, a rising edge trigger signal or a falling edge trigger signal. Such delay chains may be arranged side by side to provide a delay buffer array.

For ease of description, the matrix-vector multiplication operation is introduced below using the delay buffer unit 10 shown in FIG1A as an example. When performing the calculation, the input signal KEEP is a rising edge trigger signal, and the first control switch NM1 and the memristor RRAM in the delay adjustment subunit 11 of the delay buffer unit 10 are both grounded.

For example, in the operation array, each delay buffer unit 10 performs a multiplication operation as a calculation unit, and the accumulated delay of multiple delay buffer units 10 is output from the output end of the delay chain 20 as the result of the multiplication and addition operation as the output of the delay chain.

For example, before performing calculations, it is necessary to first map the elements of the matrix G (or the calculation weights in the neural network) to the delay of the delay buffer unit 10, and the size of the delay can be obtained, for example, by adjusting the resistance value of the memristor in the delay buffer unit 10. For example, a column of elements G11, G21, ..., Gm1 of the matrix G are respectively mapped to the delays W<0>, W<1>, ..., W<m-1> of m delay buffer units 10 that are controlled by the memristors.

Then, when performing calculations, the elements of the input vector V are mapped to the first input signals of the delay buffer unit 10. For example, the input element V1 of the input vector V is used as the first input signals NWL<0>, NWL<1>, ..., NWL<m-1> of the cascaded multiple delay buffer units 10. The multiple first input signals NWL<0>, NWL<1>, ..., NWL<m-1> can be input in parallel, for example, to improve the calculation efficiency. The first input signals NWL<0>, NWL<1>, ..., NWL<m-1> corresponding to the input element V1 control whether the multiple delays W<0>, W<1>, ..., W<m-1> of the multiple delay buffer units 10 controlled by the memristors are connected in series to the delay chain 20. The accumulated delay NWL<m-1:0>·W<m-1:0> at the output end of the delay chain 20 is the calculation result of the vector inner product operation (multiplication-accumulation operation).

For example, for each delay buffer unit 10 in Figure 1A or Figure 1B, when the first control signal is at a low level (the corresponding input element V1 is 1), the memristor RRAM is connected between the first-stage inverter P1 and the first operating voltage terminal 1. At this time, the delay t of the delay buffer unit is the delay after being adjusted by the resistance value of the memristor, that is, the delay adjusted by the memristor is connected in series to the delay chain; when the first control signal is at a high level (the corresponding input element V1 is 0), the memristor RRAM is bypassed, and the memristor RRAM is not connected between the first-stage inverter P1 and the first operating voltage terminal 1. At this time, the delay t of the delay buffer unit is the intrinsic delay, that is, only the intrinsic delay is connected in series to the delay chain.

Through the above calculation operation, the above delay chain can realize a vector inner product operation (multiplication-accumulation operation) of one (for example, 1 bit) input data and m weight elements.

Fig. 1D shows a schematic diagram of the structure of an exemplary computing device. As shown in Fig. 1D, the computing device includes a delay computing array 100, and the delay computing array 100 includes delay buffer units 10 with 2M rows and N columns (only 4 rows and 2 columns are shown in the figure).

For example, N delay buffer units 10 in each row are connected in series to form a row of delay chains 20, and each two adjacent rows of delay chains 20 constitute a delay processing combination 30. The difference in delay between two delay buffer units 10 on the same column in each delay processing combination 30 can correspond to a signed weight element. For example, by configuring the resistance value of the memristor in the two delay buffer units 10, the difference in delay between the two delay buffer units 10 can represent a positive, negative or zero weight element. That is, the two delay buffer units 10 on the same column in each delay processing combination 30 can be used as a differential unit, and the delay of each differential unit can be used to represent a positive, negative or zero weight element.

For example, the two rows of delay chains 20 in each delay processing combination 30 receive the same input signal KEEP, for example, the input signal KEEP is received through the input terminal INT of the first delay buffer unit 10 in the two rows of delay chains 20. The input signal KEEP can be used to control the operation mode of the delay calculation array 100. For example, the input signal KEEP can control whether the delay calculation array 100 is in the first operation mode or the second operation mode. When the input signal KEEP maintains a normally low level (or a normally high level), the delay calculation array 100 is in the first operation mode; when the input signal KEEP is a rising edge trigger signal (or a falling edge trigger signal), the delay calculation array 100 is in the second operation mode.

In the first operation mode, the input signal KEEP is, for example, at a low level, thereby controlling the delay adjustment subunit 11 in the delay buffer unit 10 to be electrically disconnected from the first-stage inverter P1, and at this time, the first processing operation described above can be performed on the memristor RRAM, such as performing a set operation, a reset operation, etc. on the memristor RRAM. In the second operation mode, the input signal KEEP inputs an edge signal, thereby controlling the delay adjustment subunit 11 in the delay buffer unit 10 to be electrically connected to the first-stage inverter P2, and at this time, a calculation operation or a calibration read operation can be performed on the delay calculation array 100, for example, a delay calculation result or a delay read result can be obtained from the output end of the delay chain.

For example, the output ends of the two rows of delay chains 20 in each delay processing combination 30 respectively output the accumulated delays of the two rows of multiple delay buffer units 10. For example, as shown in FIG1D , the first row of delay chains 20 in the first delay processing combination 30 outputs the accumulated delay t_DLP<0> of the N delay buffer units 10 in the first row from the output end DLP<0>, and the second row of delay chains 20 outputs the accumulated delay t_DLN<0> of the N delay buffer units 10 in the second row from the output end DLN<0>.

For example, in one example, when a calculation operation is performed on the delay calculation array 100 , the difference ΔT=t_DLP<0>−t_DLN<0> between the accumulated delays of two delay chains in the delay processing combination 30 may represent the vector inner product result of the input data and the signed weight element.

For example, two delay buffer units 10 located in the same column in each delay processing assembly 30 are respectively connected to two word lines corresponding to the same column. For example, as shown in FIG1D , two adjacent delay buffer units 10 in the first column of the first row delay processing assembly 30 are respectively connected to word lines WLP<0> and WLN<0>.

For example, two delay buffer units 10 on the same column in each delay processing combination 30 are connected to the bit line corresponding to the same column. For example, as shown in FIG1D , two adjacent delay buffer units 10 on the first column in the first row delay processing combination 30 are connected to the bit line BL<0>.

For example, in each delay processing assembly 30, the N delay buffer units 10 located in the same row are connected to the source line of the same row. For example, in the first row delay processing assembly 30, the N delay buffer units 10 located in the first row are all connected to the source line SLP<0>, and the N delay buffer units 10 located in the second row are all connected to the source line SLN<0>.

For example, for the delay buffer unit 10 in the delay calculation array 100, the delay adjustment subunit 11 of the delay buffer unit 10 is connected to the first end (for example, the source end) of the first-stage inverter, and the delay adjustment subunit 11 is connected through the source line corresponding to the row, the bit line corresponding to the column, and the word line corresponding to the column, so as to be connected to different operating voltage ends, for example, the first operating voltage end or the second operating voltage end, through the source line, the bit line, and the word line.

For example, as shown in FIG1D , in the delay buffer unit 10 on the first row and the first column, the control electrode of the control switch NM1 in the delay adjustment subunit 11 is connected to the word line WLP<0>, the first electrode of the control switch NM1 is connected to the first end of the first-stage inverter P1 and the first end of the memristor RRAM, the second electrode of the control switch NM1 is connected to the source line SLP<0>, and the second end of the memristor is connected to the bit line BL<0>. The connection method of the delay buffer units 10 on other rows and columns with the word lines, bit lines and source lines is similar, and will not be repeated here.

In the above-mentioned delay buffer unit, since the slope of the rising edge (or falling edge) of the input signal KEEP is lost in the process of controlling the switch to be cut off to delay the rising edge (or falling edge) of the input signal KEEP by adjusting the delay buffer unit through the memristor, the second-stage inverter P2 as shown in Figures 1A and 1B usually uses three parallel inverters to compensate for the lost slope, that is, one delay buffer unit requires an overhead of 9T1R, and the input signal KEEP generally includes both a rising edge and a falling edge. In the delay processing combination, one row of delay buffer units delays the rising edge of the input signal KEEP, and another row of delay buffer units delays the falling edge of the input signal KEEP. A corresponding group of differential units in the two rows of delay buffer units requires an overhead of 2×9T1R to represent the delay generated for the entire input signal KEEP.

At least one embodiment of the present disclosure provides a delay buffer unit, which includes a first delay buffer subunit and a second delay buffer subunit connected in series, the first delay buffer subunit includes a first-stage inverter, a second-stage inverter and a first delay adjustment subunit, the input end of the first-stage inverter serves as the input end of the delay buffer unit, the input end of the second-stage inverter is connected to the output end of the first-stage inverter, the first-stage delay adjustment subunit is connected to the first end, the first operating voltage end and the second operating voltage end of the first-stage inverter, the second delay buffer subunit includes a third-stage inverter, a fourth-stage inverter and a second delay adjustment subunit, the input end of the third-stage inverter is connected to the output end of the second-stage inverter, the input end of the fourth-stage inverter is connected to the third-stage inverter The output end of the fourth-stage inverter serves as the output end of the delay buffer unit, and the second-stage delay adjustment subunit is connected to the second end, the third operating voltage end and the fourth operating voltage end of the third-stage inverter, wherein the first delay adjustment subunit includes a first memristor and a first control switch, and is configured to determine whether to use the first memristor to adjust the first delay of the first delay buffer subunit according to the first control switch, and the second delay adjustment subunit includes a second memristor and a second control switch, and is configured to determine whether to use the second memristor to adjust the second delay of the second delay buffer subunit according to the second control switch, and the first delay buffer subunit and the second delay buffer subunit are respectively configured to have opposite effects on the edge slope of the pulse signal passing through the delay buffer unit.

For example, the first delay may be a delay caused to the rising edge of the input pulse signal, and the second delay may be a delay caused to the falling edge of the input pulse signal. Through the two-stage series structure, it is possible to simultaneously delay the rising edge and the falling edge of the input pulse signal in one row of delay buffer units without delaying the rising edge and the falling edge separately in two rows of delay buffer units.

For example, the first delay buffer subunit causes a loss in the rising edge slope of the pulse signal passing through the delay buffer unit, and the second delay buffer subunit causes a loss in the falling edge slope of the pulse signal passing through the delay buffer unit.

FIG2 is a schematic diagram of a delay buffer unit structure provided by at least one embodiment of the present disclosure. When the second-stage inverter P2 in FIG1A and FIG1B uses a single inverter, the first delay buffer subunit can adopt, for example, the delay buffer unit shown in FIG1A. At this time, the transistor type of the first control switch NM1 in FIG1B is replaced with a transistor different from the transistor type of the first control switch NM1 in FIG1A, and then the second delay buffer subunit can be used. In this case, the structure of any embodiment of the present disclosure can be as shown in FIG2, and the first delay buffer subunit NCELL includes a first-stage inverter PM1, a second-stage inverter PM2, a first adjustment capacitor C1, a first control switch NM0 and a first memristor R1, and the second delay buffer subunit P CELL includes a third-stage inverter PM3, a fourth-stage inverter PM4, a second adjustment capacitor C2, a second control switch PM0 and a second memristor R2, wherein the second-stage inverter PM2 and the fourth-stage inverter PM4 are both single inverters, the second pole of the first control switch NM0 is connected to the first operating voltage terminal K1, the second end of the first memristor R1 is connected to the second operating voltage terminal K2, the second pole of the second control switch PM0 is connected to the third operating voltage terminal K3, the second end of the second memristor R2 is connected to the fourth operating voltage terminal K4, and the output of the first delay buffer subunit NCELL is connected to the input of the second delay buffer subunit PCELL.

For example, the voltages of the first operating voltage terminal K1 and the second operating voltage terminal K2 are lower than the voltages of the third operating voltage terminal K3 and the fourth operating voltage terminal K4. When the first delay buffer subunit NCELL is working, at least one of the first operating voltage terminal K1 and the second operating voltage terminal K2 serves as a discharge voltage terminal, for example, the two are connected to each other so as to serve as a discharge voltage terminal together; when the second delay buffer subunit PCELL is working, at least one of the third operating voltage terminal K3 and the fourth operating voltage terminal K4 serves as a charge voltage terminal, for example, the two are connected to each other so as to serve as a charge voltage terminal together. For example, the first operating voltage terminal K1 and the second operating voltage terminal K2 are grounded, and the third operating voltage terminal K3 and the fourth operating voltage terminal K4 are connected to the power supply voltage. At this time, the memristor exists not only in the discharge path (NM0 and the adjacent R1 in FIG. 2 ), but also in the charge path (PM0 and the adjacent R2 in FIG. 2 );

For example, the type of the first control switch NM0 is different from the type of the second control switch PM0. For example, the first control switch NM0 uses an N-type transistor, and the second control switch PM0 uses a P-type transistor.

For example, the first control switch NM0 includes a first electrode, a second electrode and a first control electrode, the first control electrode receives a first control signal NWL_N to turn on or off the first electrode and the second electrode of the first control switch NM0 according to the first control signal NWL_N, the first electrode of the first control switch NM0 is electrically connected to the first end of the first-stage inverter, the second electrode of the first control switch NM0 is electrically connected to the first operating voltage terminal K1, the first end of the first memristor R1 is electrically connected to the first electrode of the first control switch NM0 and the first end of the first-stage inverter, and the second end of the first memristor R1 is electrically connected to the second operating voltage terminal K2; the second control switch PM0 includes a first electrode, a second electrode and a second control electrode, the second The control electrode receives the second control signal NWL_P to turn on or off the first electrode and the second electrode of the second control switch PM0 according to the second control signal NWL_P, the first electrode of the second control switch PM0 is electrically connected to the second end of the third-stage inverter, the second electrode of the second control switch PMO is electrically connected to the third operating voltage terminal K3, the first end of the second memristor R2 is electrically connected to the first electrode of the second control switch PM0 and the second end of the third-stage inverter, and the second end of the second memristor R2 is electrically connected to the fourth operating voltage terminal K4; the first control signal NWL_N and the second control signal NWL_P are inverted to each other to control the first control switch NM0 and the second control switch PM0 to be turned on or off at the same time.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics. The first pole (electrode) and the second pole (electrode) of the transistor used here may be the source and the drain or the drain and the source, respectively. It is understandable that the source and the drain may be symmetrical in structure, so the source and the drain may be indistinguishable in structure. The embodiments of the present disclosure do not limit the type of transistor used.

For example, the first delay adjustment subunit includes a first adjustment capacitor C1, and is configured to adjust the delay of the first delay buffer subunit NCELL using the first memristor R1 and the first adjustment capacitor C1 according to the first control signal NWL_N, and the second delay adjustment subunit includes a second adjustment capacitor C2, and is configured to adjust the delay of the second delay buffer subunit PCELL using the second memristor R2 and the second adjustment capacitor C2 according to the second control signal NWL_P. For example, the first adjustment capacitor can utilize the parasitic capacitance of the circuit structure itself or an external capacitor.

For example, the capacitance of the first adjustment capacitor C1 is the same as the capacitance of the second adjustment capacitor C2, so that when the resistance values of the first memristor R1 and the second memristor R2 are equal, the delays generated by the first delay adjustment subunit and the second delay adjustment subunit for the rising edge and falling edge of the input pulse signal are consistent.

As mentioned above, in the structure shown in FIG1D , a row of delay buffer units only delays the rising edge (or falling edge) of the input pulse signal, and two rows of delay buffer units are required to form a differential structure to calculate the delay generated by the input pulse signal passing through the delay buffer unit, and to output an ideal rising edge (or falling edge). The second-stage inverter P2 in the delay buffer unit shown in FIG1A or FIG1B needs to use three inverters in series to compensate for the slope loss of the rising edge (or falling edge). In this case, the overhead required for a differential unit is 2×9T1R.

FIG3A and FIG3B are schematic diagrams of the working principle of the delay buffer unit provided by at least one embodiment of the present disclosure. The following will be combined with FIG3A and FIG3B to illustrate how the present disclosure reduces circuit overhead, wherein the delay buffer unit structure shown in FIG3A is the same as the delay buffer unit structure shown in FIG2. It should be noted that, for example, in the calculation mode, the first operating voltage terminal K1 and the second operating voltage terminal K2 of the delay buffer unit shown in FIG2 are grounded, and the third operating voltage terminal K3 and the fourth operating voltage terminal K4 are connected to the power supply voltage. In the delay buffer unit structure shown in FIG3B, the positions of the first delay buffer unit and the second delay buffer unit are opposite to those in FIG2, and the present application does not limit this.

As shown in FIG3A , when the delay buffer unit receives a rising edge, the N-type transistors of the first-stage inverter PM1 and the third-stage inverter PM3 and the P-type transistors of the second-stage inverter PM2 and the fourth-stage inverter are turned on (indicated in black in the figure), the P-type transistors of the first-stage inverter PM1 and the third-stage inverter PM3 and the N-type transistors of the second-stage inverter PM2 and the fourth-stage inverter are turned off (indicated in gray in the figure), and the output of the first delay buffer subunit NCELL is X. Since the RC delay formed by the first adjustment capacitor C1 and the first memristor R1 has only passed The second-stage inverter PM2 is formed, and thus the slope of the rising edge of the output X of the first delay buffer subunit NCELL will be lost. However, at this time, the output X of the first delay buffer subunit NCELL will still pass through the two-stage inverter of the second delay buffer subunit PCELL. Since the P-type transistor of the third-stage inverter PM3 is cut off, the second memristor R2 connected to the third-stage inverter PM3 is isolated, and the second memristor R2 does not participate in the RC delay, so the undesirable rising edge of the output X is restored. Therefore, the output of the entire two-stage structure still has a rising edge with a relatively ideal slope.

As shown in FIG3B , when the delay buffer unit receives a falling edge, the N-type transistors of the first-stage inverter PM1 and the third-stage inverter PM3 and the P-type transistors of the second-stage inverter PM2 and the fourth-stage inverter are turned off (indicated in gray in the figure), the P-type transistors of the first-stage inverter PM1 and the third-stage inverter PM3 and the N-type transistors of the second-stage inverter PM2 and the fourth-stage inverter are turned on (indicated in black in the figure), and the output of the first delay buffer subunit PCELL is Y. Since the RC delay formed by the second adjustment capacitor C2 and the second memristor R2 has only passed The second-stage inverter PM2, therefore, the slope of the falling edge of the output Y of the first delay buffer sub-unit PCELL will be lost, but at this time the output Y of the first delay buffer sub-unit PCELL will still pass through the two-stage inverter of the second delay buffer sub-unit NCELL. At this time, since the N-type transistor of the third-stage inverter PM3 is cut off, the first memristor R1 connected to the third-stage inverter PM3 is isolated, and the first memristor R1 does not participate in the RC delay, so the undesirable falling edge of the output Y is restored, and the output of the two-stage structure still has a falling edge with a relatively ideal slope.

When the input is 0 (i.e., NWL_N=1, NWL_P=0), the gate of the first control switch NM0 is connected to a high level, the first control switch NM0 is turned on, the gate of the second control switch PM0 is connected to a low level, the second control switch PM0 is turned on, the first memristor R1 and the second memristor R2 are bypassed, and the delays of the rising edge and the falling edge passing through the delay buffer unit are the intrinsic delays of the 4-stage inverter, so the pulse widths of the input and output are consistent; when the input is 1 (i.e., NWL_N=0, NWL_P=1), the gate of the first control switch NM0 is connected to a low level, the first control switch NM0 is turned off, the gate of the second control switch PM0 is connected to a high level, the second control switch PM0 is turned off, the rising edge delay is dominated by the RC delay composed of the first memristor R1 and the first adjustment capacitor C1, and the falling edge is dominated by the RC delay composed of the second memristor R2 and the second adjustment capacitor C2, so the width of the output pulse is inconsistent with the input pulse width, and the degree of inconsistency is determined by the size of the first memristor R1 and the second memristor R2.

In the above embodiment, the two-stage delay buffer subunit has formed a differential unit, which only requires 2*5T1R overhead, and the rising edge or falling edge is restored to the edge slope after the RC delay through the intrinsic delay of the three-stage inverter, thereby reducing the hardware overhead while ensuring that the output delay signal still has a falling edge and a rising edge with a relatively ideal slope. Since fewer transistors are used, the parasitic capacitance during the dynamic flipping process of the circuit is smaller, so the unit structure can achieve lower dynamic flipping power consumption.

FIG4 is a schematic diagram of a series structure of a delay buffer unit provided in at least one embodiment of the present disclosure. The delay buffer unit provided in at least one embodiment of the present disclosure can realize the product of 1-bit input and signed weight, which is explained below in conjunction with FIG4 .

As shown in FIG4 , m delay buffer units as described in any of the above embodiments are connected in series to form a series structure, where m is an integer greater than 1, and the series structure forms a delay chain. An input pulse W1 is input at the input end of the delay chain, and a control signal IN<m-1> is input to each corresponding delay buffer unit (for example, the control signal of the first delay buffer unit is IN<0>), then an output pulse W2 can be obtained at the output end of the delay chain, wherein the delay generated by a single delay buffer subunit is W<m-1> (for example, the delay generated by the first delay buffer subunit is W<0>).

The delay difference NW of the output pulse W2 relative to the rising edge of the input pulse W1 is dominated by the RC delay accumulation of all the first delay buffer sub-units NCELL, and the delay difference PW of the output pulse relative to the falling edge of the input pulse is dominated by the RC delay accumulation of all the second delay buffer sub-units PCELL. In this way, the inner product of the 1-bit input vector (IN<0>, IN<1>…IN<m-1>) and the signed weight vector (W<0>, W<1>…W<m-1>) is completed. This result is reflected by the difference in the output and input pulse widths (W2-W1), that is:

At least one embodiment of the present disclosure further provides a delay buffer array, which includes a plurality of delay buffer units as described in any of the above embodiments.

Figure 5 is a schematic diagram of a delay buffer array structure provided by at least one embodiment of the present disclosure. As shown in Figure 5, the delay buffer array includes a plurality of delay buffer units as described in any of the above embodiments, wherein the plurality of delay buffer units are arranged in an array having a plurality of rows, and the delay buffer units in each row are connected in series in sequence to form a delay chain. For example, each delay buffer unit includes a first delay buffer sub-unit NCELL and a second delay buffer sub-unit PCELL connected in series.

The delay buffer array may further include a time pulse input module 101, a programming voltage generation module 102, an input loading module 103, an output quantization module 104, a data storage module 105, a mode control module 106, a column selection module 107, a row selection module 108, and a quantization control module 109. The time pulse input module 101 is configured to provide time pulse signals to the input ends of multiple delay chains respectively; the programming voltage generation module 102 is configured to perform memristor programming on the target delay buffer unit; the input loading module 103 is configured to provide a first control signal and a second control signal as input signals for each delay buffer unit; the output quantization module 104 is configured to quantize the outputs of multiple delay chains respectively to obtain digital output signals; and the data storage module 105 is configured to store data when the delay buffer array performs calculations.

The mode control module 106 is configured to control the working mode of the delay buffer array, such as calculation mode, programming mode and verification mode, etc. The column selection module 107 and the row selection module 108 are configured to determine the selected delay buffer unit position during weight mapping, and the quantization control module 109 is configured to generate a timing signal for the output quantization module 104 to control the operation of the quantization output module. For example, the quantization control module can be a TDC (Time-to-Digital Converter) array.

In practice, it may happen that the rising edge intrinsic delay of all the first delay buffer subunits NCELL and the intrinsic delay of the second delay buffer subunit PCELL do not completely match each other. Therefore, even when all 0s are input, the width difference between the input pulse and the output pulse will not be equal to 0. This is a systematic error for calculation. Before verification and calculation, calculation under all-0 input can be performed to extract the system error as verification data through the output quantization module 104 and save it in the data storage module 105. Afterwards, the verification data is subtracted from the quantized output results of the verification and calculation to eliminate the systematic error.

During weight mapping, the position of the selected delay buffer unit is determined by the column selection module 107 and the row selection module 108 and verified by the output quantization module 104, and the programming voltage generation module 102 is used to program the selected unit RRAM; during calculation, the input loading module 103 applies the input vector to the vertical direction of the array, and obtains the output vector result of the matrix vector multiplication in the horizontal direction, which is quantized into a digital output by the output quantization module 104. It should be noted that, whether it is verification or calculation, a calibration phase PH0 is required before it starts, the purpose of which is to quantize and store the system error DOUT0 under all-0 input, and then quantize it into a digital output DOUT1 by the output quantization module 104 in the normal verification or calculation process PH1. The digital outputs obtained by the two phases are subtracted in the digital domain to obtain the output vector DOUT1-DOUT0 that can truly reflect the result.

The working process of the delay buffer array in the calculation, verification and programming modes of the present disclosure is described below in conjunction with some embodiments.

FIG6 is a flow chart of a delay buffer array operation method provided by at least one embodiment of the present disclosure. The operation method is applied to the delay buffer array described in any of the above embodiments. As shown in FIG6 , the operation method includes steps S201 - S203 .

S201 . Provide a time pulse signal at an input end of a delay chain selected for a computing operation in a delay buffer array.

For example, the time pulse input module 101 shown in FIG. 5 may provide a time pulse signal, and the column selection module 107 and the row selection module 108 may select a delay chain corresponding to a delay buffer unit used for a calculation operation.

S202. Apply a first control signal and a second control signal as input data signals to each delay buffer unit in the delay chain selected for computing operations in the delay buffer array, wherein the input data signal controls the first control switch and the second control switch of the delay buffer unit corresponding to the input data signal to be turned on or off.

For example, the first control signal and the second control signal may be provided by the input loading module 103 as shown in FIG. 5 .

S203 . Obtain an object output signal at an output end of a delay chain selected for a calculation operation in a delay buffer array, wherein the object output signal is a time signal delayed with respect to an input time pulse signal.

For example, the input data signal applied to each delay buffer unit in the same delay chain selected for computing operation is 1 bit of the multi-bit data. For example, if there are m delay buffer units in the delay chain, the input data signal has m bits, and each input signal is input into the corresponding delay buffer unit. For example, if there are two delay buffer units in the delay chain, and the input signal at this time is 10, the corresponding input signal of the first delay buffer unit is 1, and the corresponding input signal of the second delay buffer unit is 0; for a single delay buffer unit, the input signals are 0 and 1. When the input is 0, the corresponding first control signal and the second control signal control the first control switch and the second control switch to turn on, bypassing the memristor in the delay buffer unit. When the input is 1, the corresponding first control signal and the second control signal control the first control switch and the second control switch to turn off, so that the memristor in the delay buffer unit participates in RC delay.

For example, after obtaining the object output signal, the object output signal can also be quantized to convert the time signal into a digital signal. Specifically, the following steps are performed:

S204, obtaining the delay between the time pulse signal and the object output signal;

S205, quantifying the delay to obtain a digital output signal;

S206: Subtract the verification data from the digital output signal to obtain the verification output of the delay buffer array.

The verification data is the system error DOUT0 of the delay buffer array under the all-0 input. For example, the delay can be quantized by the output quantization module 104 shown in FIG. 5

FIG7 is a flow chart of another delay buffer array operation method provided by at least one embodiment of the present disclosure. The operation method is applied to the delay buffer array described in any of the above embodiments. As shown in FIG7 , the operation method includes steps S301 - S302 .

S301, selecting a delay buffer unit in the delay buffer array as a unit to be programmed;

S302, applying a first control signal to control a first control switch in the unit to be programmed, and applying a first programming voltage to both ends of a first memristor in the unit to be programmed to change the resistance value of the first memristor; or, applying a second control signal to control a second control switch in the unit to be programmed, and applying a second programming voltage to both ends of a second memristor in the unit to be programmed to change the resistance value of the second memristor.

For example, the delay buffer unit as the unit to be programmed can be selected by the column selection module 107 and the row selection module 108 as shown in FIG5 . As described above, the programming of the memristor is realized by inputting, for example, a normally low level through the time pulse input module 101 and performing the first processing operation on the memristor through the programming voltage generation module 102, and the specific process is not repeated here.

It should be noted that the initialization operation of the memristor only needs to be performed once, and the programming operation of the memristor can be performed multiple times to adjust (program) the resistance value of the memristor until it meets the programming requirements. For example, after the memristor is set or reset, in the traditional practice, the memristor can also be read to verify whether the resistance value of the memristor reaches the expected resistance value. If the resistance value of the memristor does not reach the expected resistance value, the memristor can be set or reset again until the resistance value of the memristor reaches the expected resistance value. Determining whether the resistance value of the memristor reaches the expected resistance value specifically includes the following steps:

S303, providing a time pulse signal at the input end of the delay chain corresponding to the unit to be programmed;

S304, control the first control switch of the unit to be programmed to be turned off and the second control switch to be turned on, and control the first control switch and the second control switch of the delay buffer unit other than the unit to be programmed in the delay chain corresponding to the unit to be programmed to be turned on, and obtain the output signal of the delay chain corresponding to the unit to be programmed as the first programming output; or control the first control switch of the unit to be programmed to be turned on and the second control switch to be turned off, and control the first control switch and the second control switch of the delay buffer unit other than the unit to be programmed in the delay chain corresponding to the unit to be programmed to be turned on, and obtain the output signal of the delay chain corresponding to the unit to be programmed as the second programming output;

S305 , determining whether the resistance value of the first memristor or the resistance value of the second memristor of the unit to be programmed meets programming requirements according to the first programming output or the second programming output.

8A and 8B are schematic diagrams of a delay buffer unit programming verification according to at least one embodiment of the present disclosure.

As shown in FIG8A , m delay buffer units as described in any of the above embodiments are connected in series to form a delay chain, each delay buffer unit includes a first delay buffer subunit NCELL and a second delay buffer subunit PCELL connected in series, an input pulse W1 is input into the input end of the delay chain, and an output pulse W2 is obtained at the output end, one of the delay buffer units in the delay chain is selected as the unit to be programmed (the first one in the figure), and the delay generated by each delay buffer unit to the input pulse is W<m-1> (for example, the delay generated by the first delay buffer unit to the input pulse is W<0>), and the intrinsic delay generated by all the delay buffer subunits in the delay chain to the rising edge of the input pulse W1 is tr_int, which is The intrinsic delay generated by the falling edge of the input pulse W1 is tf_int. The first control switch in the first delay subunit NCELL of the unit to be programmed is cut off by the control signal (the first delay subunit NCELL with an input of 1 in the figure), and the first control switches in the remaining first delay subunits NCELL in the delay chain and the second control switches in all second delay subunits PCELL are turned on by the control signal (the first delay subunit NCELL and the second delay subunit PCELL with an input of 0 in the figure). At this time, only the memristor in the first delay subunit NCELL of the unit to be programmed in the delay chain participates in the RC delay, and the delay effect on the rising edge of the input pulse W1 is R0 ⁺ C.

As shown in FIG8B, the second control switch in the second delay subunit PCELL of the unit to be programmed in FIG8A is turned on by controlling the control signal, and the first control switches in all the first delay subunits NCELL in the delay chain and the second control switches in the remaining second delay subunits PCELL are turned on by the control signal, and the remaining configurations are the same as FIG8A and will not be repeated here. At this time, only the memristor in the second delay subunit PCELL of the unit to be programmed in the delay chain participates in the RC delay, and the effect on the falling edge delay of the input pulse W1 is R0 ^- C. Therefore, it can be judged whether the resistance values of the two memristors in the unit to be programmed meet the requirements according to the size of R0 ⁺ C and R0 ^- C.

The above is the process of programming and verifying a single cell before executing the calculation mode, that is, the process of writing the weight; the programming and verification of the weight is also performed in the time domain, that is, the criterion for weight programming is delay rather than conductivity in the traditional sense. When programming positive weights, as shown in FIG8A , only the NCELL of the selected cell inputs 1, and the PCELL in the cell and the PCELL and NCELL of other cells all input 0, so that only the NCELL of the selected cell contributes to the rising edge RC delay in the entire delay chain, so the weight definition and correction of the NCELL of the selected cell can be performed based on the relative width of the input and output pulses; similarly for negative weight programming, as shown in FIG8B , only the PCELL of the selected cell inputs 1, and the NCELL in the cell and the PCELL and NCELL of other cells all input 0, so that only the PCELL of the selected cell contributes to the falling edge RC delay in the entire delay chain, so the weight definition and correction of the PCELL of the selected cell can be performed based on the relative width of the input and output pulses.

FIG9 is a flow chart of another delay buffer array operation method provided by at least one embodiment of the present disclosure. The operation method is applied to the delay buffer array described in any of the above embodiments. As shown in FIG9 , the operation method includes steps S401 - S404 .

S401, providing a time pulse signal at the input end of the delay chain selected for the verification operation in the delay buffer array;

S402, applying a first control signal and a second control signal as input signals to each delay buffer unit in a delay chain selected for a verification operation in the delay buffer array, so as to control a first control switch and a second control switch of each delay buffer unit to be turned on;

S403, obtaining an output signal as an intrinsic output at an output end of a delay chain selected for a verification operation in a delay buffer array;

S404 , quantify the delay between the intrinsic output and the time pulse signal to obtain verification data of the delay chain selected for verification operation in the delay buffer array.

For example, a time pulse signal can be provided through the time pulse input module 101 as shown in Figure 5, the delay chain corresponding to the delay buffer unit used for the verification operation can be selected through the column selection module 107 and the row selection module 108, the first control signal and the second control signal that are all 0 are provided through the input loading module 103 to control all the first control switches and the second control switches in the delay chain to be turned on, and the delay between the intrinsic output and the input time pulse signal is quantized through the output quantization module 104 to obtain the system error DOUT0 as the verification data.

At least one embodiment of the present disclosure further provides an electronic device, which includes a delay buffer array as described in any of the above embodiments. The delay conversion array may be, for example, a structure as shown in FIG. 5 .

The electronic device may be, for example, a processor or any other product or component including the processor and used in conjunction with the processor. For another example, the electronic device may be a server device or a terminal device, such as a mobile phone, a laptop computer, or the like.

The delay buffer unit, array, electronic device and array operation method provided by the embodiments of the present disclosure can ensure calculation accuracy while reducing the unit area and using fewer transistors, output delay signals with falling and rising edges with relatively ideal slopes, and reduce dynamic power consumption.

For example, in at least one embodiment, the forward computing paradigm of the array of delay buffer units can support fully parallel matrix-vector multiplication within a row; for example, system errors caused by non-ideal factors such as process can be offset by verifying data.

It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

In addition to the above exemplary description, the following points need to be explained for the present disclosure:

(1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

(3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims (15)

1. A delay buffer unit comprises a first delay buffer subunit and a second delay buffer subunit which are connected in series,

The first delay buffer subunit comprises a first-stage inverter, a second-stage inverter and a first delay regulating subunit, wherein the input end of the first-stage inverter is used as the input end of the delay buffer unit, the input end of the second-stage inverter is connected with the output end of the first-stage inverter, the first-stage delay regulating subunit is connected with the first end, the first operating voltage end and the second operating voltage end of the first-stage inverter,

The second delay buffer subunit comprises a third-stage inverter, a fourth-stage inverter and a second delay regulating subunit, wherein the input end of the third-stage inverter is connected with the output end of the second-stage inverter, the input end of the fourth-stage inverter is connected with the output end of the third-stage inverter, the output end of the fourth-stage inverter is used as the output end of the delay buffer unit, the second delay regulating subunit is connected with the second end, the third operating voltage end and the fourth operating voltage end of the third-stage inverter,

Wherein the first delay adjustment subunit comprises a first memristor and a first control switch configured to determine whether to adjust a first delay of the first delay buffer subunit using the first memristor in accordance with the first control switch, the second delay adjustment subunit comprises a second memristor and a second control switch configured to determine whether to adjust a second delay of the second delay buffer subunit using the second memristor in accordance with the second control switch,

The first delay buffer subunit and the second delay buffer subunit are respectively configured to have opposite effects on edge slopes of pulse signals passing through the delay buffer units.

2. The delay buffer cell of claim 1, wherein the first and second operating voltage terminals have voltages lower than the third and fourth operating voltage terminals, at least one of the first and second operating voltage terminals acting as a discharge voltage terminal when the first delay buffer subunit is operating,

At least one of the third operating voltage terminal and the fourth operating voltage terminal is used as a charging voltage terminal when the second delay buffer subunit works.

3. The delay buffer unit of claim 1, wherein the type of the first control switch is different from the type of the second control switch.

4. The delay buffer unit of claim 1, wherein the first control switch comprises a first pole, a second pole and a first control pole, the first control pole receiving a first control signal to turn on or off the first pole and the second pole of the first control switch according to the first control signal, the first pole of the first control switch being electrically connected to a first end of the first stage inverter, the second pole of the first control switch being electrically connected to the first operating voltage end,

A first end of the first memristor is electrically connected with a first pole of the first control switch and a first end of the first stage inverter, and a second end of the first memristor is electrically connected with the second operation voltage end;

The second control switch comprises a first pole, a second pole and a second control pole, the second control pole receives a second control signal to conduct or cut off the first pole and the second pole of the second control switch according to the second control signal, the first pole of the second control switch is electrically connected with the second end of the third-stage inverter, the second pole of the second control switch is electrically connected with the third operation voltage end,

The first end of the second memristor is electrically connected with the first pole of the second control switch and the second end of the third-stage inverter, and the second end of the second memristor is electrically connected with the fourth operation voltage end;

The first control signal and the second control signal are inverted from each other.

5. The delay buffer cell of claim 4, wherein the first delay adjustment subunit comprises a first adjustment capacitance and is configured to adjust a delay of the first delay buffer subunit using the first memristor and the first adjustment capacitance in accordance with the first control signal,

The second delay adjustment subunit includes a second adjustment capacitance and is configured to adjust a delay of the second delay buffer subunit using the second memristor and the second adjustment capacitance in accordance with a second control signal.

6. The delay buffer cell of claim 5, wherein the capacitance of the first adjustment capacitance is the same as the capacitance of the second adjustment capacitance.

7. A delay buffer array comprising a plurality of delay buffer cells as claimed in any one of claims 1 to 6, wherein the plurality of delay buffer cells are arranged in an array having a plurality of rows, and the delay buffer cells in each row are serially connected in turn to form a delay chain.

8. The delay buffer array of claim 7, wherein the delay buffer array further comprises:

the time pulse input module is configured to respectively provide time pulse signals at the input ends of the delay chains;

the programming voltage generation module is configured to perform memristor programming on the target delay buffer unit;

An input loading module configured to provide a first control signal and a second control signal as input signals for each delay buffer unit;

The output quantization module is configured to quantize the outputs of the delay chains respectively to obtain digital output signals;

the data storage module is configured to store data when the delay buffer array performs calculation;

and the mode control module is configured to control an operation mode executed by the delay buffer array.

9. An electronic device comprising a delay buffer array as claimed in any one of claims 7 or 8.

10. A method of operation of a delay buffer array, applied to the delay buffer array of any of claims 7-8, the method of operation of the delay buffer array comprising:

Providing a time pulse signal at an input of a delay chain selected for a computational operation in the delay buffer array;

applying a first control signal and a second control signal as input data signals to each delay buffer unit in a delay chain selected for calculation operation in the delay buffer array, wherein the input data signals control the first control switch and the second control switch of the delay buffer unit corresponding to the input data signals to be switched on or off;

The output of the delay chain selected for the computational operation in the delay buffer array obtains an object output signal.

11. The method of claim 10, wherein the input data signal applied to each delay buffer cell in the same delay chain selected for the computational operation is 1 bit of multi-bit data, respectively.

12. The method of operation of a delay buffer array of claim 10, wherein the method of operation of a delay buffer array after the output of the delay chain selected for computational operations acquires an output signal further comprises:

Acquiring a time delay between the time pulse signal and the object output signal;

quantizing the delay to obtain a digital output signal;

And subtracting the check data from the digital output signal to obtain a check output of the delay buffer array.

13. A method of operation of a delay buffer array as claimed in any one of claims 7 to 8, the method of operation comprising:

selecting one delay buffer unit in the delay buffer array as a unit to be programmed;

Applying the first control signal to control a first control switch in the unit to be programmed, and applying a first programming voltage to two ends of a first memristor in the unit to be programmed to change the resistance value of the first memristor; or applying the second control signal to control a second control switch in the unit to be programmed, and applying a second programming voltage to two ends of a second memristor in the unit to be programmed to change the resistance value of the second memristor.

14. The method of operation of a delay buffer array of claim 13, wherein after changing the resistance of the first memristor or changing the resistance of the second memristor, the method of operation further comprises:

Providing a time pulse signal at the input end of a delay chain corresponding to the unit to be programmed;

The method comprises the steps of controlling a first control switch and a second control switch of a unit to be programmed to be turned off and turned on, controlling the first control switch and the second control switch of a delay buffer unit except the unit to be programmed in a delay chain corresponding to the unit to be programmed to be turned on, and obtaining an output signal of the delay chain corresponding to the unit to be programmed to be used as a first programming output; or the first control switch and the second control switch of the unit to be programmed are controlled to be on and off, the first control switch and the second control switch of the delay buffer units except the unit to be programmed in the delay chain corresponding to the unit to be programmed are controlled to be on, and the output signal of the delay chain corresponding to the unit to be programmed is obtained to be used as the second programming output;

and determining whether the resistance value of the first memristor or the resistance value of the second memristor of the unit to be programmed meets programming requirements according to the first programming output or the second programming output.

15. A method of operation of a delay buffer array as claimed in any one of claims 7 to 8, the method of operation comprising:

Providing a time pulse signal at an input of a delay chain selected for a verify operation in the delay buffer array;

Respectively applying a first control signal and a second control signal which are used as input signals to each delay buffer unit in a delay chain selected for verification operation in the delay buffer array so as to control the first control switch and the second control switch of each delay buffer unit to be conducted;

The output end of the delay chain selected for verification operation in the delay buffer array acquires an output signal as an intrinsic output;

and quantifying the delay between the intrinsic output and the time pulse signal to obtain verification data of a delay chain selected for verification operation in the delay buffer array.