CN118136518B - Preparation method of power module - Google Patents

Preparation method of power module Download PDF

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Publication number
CN118136518B
CN118136518B CN202410563845.5A CN202410563845A CN118136518B CN 118136518 B CN118136518 B CN 118136518B CN 202410563845 A CN202410563845 A CN 202410563845A CN 118136518 B CN118136518 B CN 118136518B
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Prior art keywords
substrate
conductive
region
signal connection
area
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CN118136518A (en
Inventor
张学伦
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Geely Technology Group Co ltd
Zhejiang Jingneng Microelectronics Co ltd
Zhejiang Geely Holding Group Co Ltd
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Geely Technology Group Co ltd
Zhejiang Jingneng Microelectronics Co ltd
Zhejiang Geely Holding Group Co Ltd
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Priority to CN202410563845.5A priority Critical patent/CN118136518B/en
Publication of CN118136518A publication Critical patent/CN118136518A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Inverter Devices (AREA)

Abstract

The application provides a preparation method of a power module. The method comprises the following steps: providing a substrate, wherein a first conductive area, a second conductive area, a third conductive area and a plurality of signal connection areas are arranged on the substrate, the first conductive area comprises a positive electrode connection area, the second conductive area comprises an alternating current connection area, and the third conductive area comprises a negative electrode connection area; connecting a plurality of upper and lower bridge chips to the first and second conductive regions, respectively; connecting the front surface of each upper bridge chip and the front surface of each lower bridge chip to the second and third conductive areas through independent metal sheets respectively; the grid electrode of each upper bridge chip and the grid electrode of each lower bridge chip are correspondingly connected to the signal connection area through conductive wires respectively; and plastic packaging the substrate, and exposing at least one part of each of the positive electrode connection region, the negative electrode connection region, the alternating current connection region and the signal connection region on the substrate to obtain the half-bridge structure after plastic packaging. The application can reduce parasitic inductance and volume of the prepared power module.

Description

Preparation method of power module
Technical Field
The embodiment of the application relates to the technical field of power electronics, in particular to a preparation method of a power module.
Background
With the development of power electronics technology, power modules have attracted more and more attention. The power module is a device which combines a plurality of semiconductor chips into a whole according to certain functions and modes, is mainly applied to a power loop of a power electronic system, and is core hardware for realizing electric energy conversion.
Currently, silicon carbide (SiC) power modules are increasingly being used in new energy automotive applications. Compared with an IGBT (Insulate Gate Bipolar Transistor, insulated gate bipolar transistor), a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has a faster switching speed and lower switching loss, and therefore, the high-speed switching process becomes sensitive to parasitic parameters, and high-frequency oscillation and voltage overshoot are more likely to occur. However, the power module prepared at present still has the problem of larger parasitic inductance of the power loop and has larger volume.
Disclosure of Invention
The embodiment of the application aims to provide a preparation method of a power module, which can reduce parasitic inductance and volume of the prepared power module.
One aspect of the embodiments of the present application provides a method for manufacturing a power module. The preparation method comprises the following steps:
providing a substrate, wherein a first conductive area, a second conductive area, a third conductive area and a plurality of signal connection areas are arranged on the substrate, the first conductive area comprises a positive electrode connection area, the second conductive area comprises an alternating current connection area, and the third conductive area comprises a negative electrode connection area;
connecting a plurality of upper bridge chips and a plurality of lower bridge chips to the first conductive region and the second conductive region, respectively;
Connecting the front surface of each upper bridge chip and the front surface of each lower bridge chip to the second conductive area and the third conductive area through independent metal sheets respectively;
The grid electrode of each upper bridge chip and the grid electrode of each lower bridge chip are correspondingly connected to the signal connection area through conducting wires respectively; and
And carrying out plastic packaging on the substrate, and exposing at least one part of each of the positive electrode connection region, the negative electrode connection region, the alternating current connection region and the signal connection region on the substrate to obtain a half-bridge structure after plastic packaging.
Further, the providing a substrate includes:
Providing a first substrate and a second substrate, wherein the first substrate is provided with the first conductive region, the second conductive region and the signal connection region, the second substrate is provided with the third conductive region,
The preparation method further comprises the following steps:
The second substrate is electrically connected to the first substrate.
Further, the first substrate comprises a first upper conductive layer, a first lower conductive layer and a first intermediate insulating layer positioned between the first upper conductive layer and the first lower conductive layer, the second substrate comprises a second upper conductive layer, a second lower conductive layer and a second intermediate insulating layer positioned between the second upper conductive layer and the second lower conductive layer, wherein the first upper conductive layer of the first substrate comprises the first conductive region, the second conductive region and the signal connection region, the second upper conductive layer of the second substrate comprises the third conductive region,
The electrically connecting the second substrate to the first substrate includes:
The second lower conductive layer of the second substrate is electrically connected to the second conductive region of the first substrate.
Further, the connecting the plurality of upper bridge chips and the plurality of lower bridge chips to the first conductive region and the second conductive region, respectively, includes:
Symmetrically connecting a plurality of upper bridge chips to the first conductive areas on two opposite sides of the positive electrode connection area respectively; and
And respectively and symmetrically connecting a plurality of lower bridge chips to the second conductive areas on two opposite sides of the negative electrode connection area, wherein the number of chips in the two symmetrically arranged areas is the same.
Further, the signal connection region includes a signal connection region located at a first side and a second side opposite to each other of the substrate, and the correspondingly connecting the gate of each upper bridge chip and the gate of each lower bridge chip to the signal connection region through conductive wires includes:
Correspondingly connecting the grid electrode of each upper bridge chip to the signal connection area positioned on the first side edge of the substrate through a first upper conductive wire; and
And correspondingly connecting the grid electrode of each lower bridge chip to the signal connection area positioned on the second side edge of the substrate through a first lower conductive wire.
Further, the signal connection region includes a gate signal connection region, wherein,
The signal connection area for correspondingly connecting the grid electrode of each upper bridge chip to the first side edge of the substrate through the first upper conductive wire comprises: grouping a plurality of upper bridge chips positioned on each side of the positive electrode connection region as an independently controlled upper bridge chip and connecting the grid electrode of each upper bridge chip to a grid electrode signal connection region of the first side edge through a first upper conductive wire;
The signal connection area for correspondingly connecting the grid electrode of each lower bridge chip to the second side edge of the substrate through the first lower conductive wire comprises: and grouping a plurality of lower bridge chips positioned on each side of the negative electrode connection region as an independently controlled lower bridge chip, and connecting the grid electrode of each lower bridge chip to one grid electrode signal connection region of the second side edge through a first lower conductive wire.
Further, the preparation method further comprises the following steps:
The positions of a plurality of connection landing points of the first upper conductive line and the first lower conductive line on the gate signal connection region are determined in advance through simulation and corresponding marks are made on the periphery of the landing point positions by laser,
Wherein, the grid electrodes of all upper bridge chips in all upper bridge chip groups are correspondingly connected to all connection drop points on the grid signal connection area of the first side edge through a first upper conductive wire;
and correspondingly connecting the grid electrode of each lower bridge chip in each lower bridge chip group to each connection drop point under the grid electrode signal connection area of the second side edge through a first lower conductive wire.
Further, the preparation method further comprises the following steps:
and arranging the temperature-sensitive resistor in a signal connection area which is positioned in the central connecting line of the positive electrode connection area and the negative electrode connection area.
Further, the preparation method further comprises the following steps:
and connecting the three half-bridge structures after plastic packaging to the heat dissipation substrate to form the full-bridge module.
Further, the preparation method further comprises the following steps:
and connecting the signal terminals to the signal connection areas exposed out of the plastic package shell of the half-bridge structure after plastic package.
Further, the preparation method further comprises the following steps:
providing a positive direct current busbar and a negative direct current busbar, wherein the positive direct current busbar is provided with a first connecting part and a first plane main body part, and the negative direct current busbar is provided with a second connecting part and a second plane main body part;
The first connecting part of the positive direct current busbar and the second connecting part of the negative direct current busbar are respectively connected with the positive connecting area and the negative connecting area exposed outside the plastic package shell of the half-bridge structure after plastic package, and the first plane main body part of the positive direct current busbar and the second plane main body part of the negative direct current busbar are mutually overlapped and extend out of one end of the plastic package shell at intervals; and
And connecting an alternating current busbar to the alternating current connection area outside the plastic package shell, and extending from the other end opposite to the plastic package shell.
The power module prepared by the preparation method of the power module of one or more embodiments of the application can have lower parasitic inductance of a power loop; in addition, in the preparation process, the power connection area and the signal connection area are exposed outside the plastic package shell, so that the volume of the whole module can be greatly reduced, and the signal terminal and the power busbar can be very conveniently installed from the outside of the plastic package shell; in addition, the mounting time of the signal terminals and the power busbar can be selected according to the actual application requirements, and the proper type of signal terminals can be conveniently changed according to the requirements of application ends after the module is molded.
Drawings
Fig. 1 is a schematic perspective view of a half-bridge structure according to an embodiment of the present application.
Fig. 2 is a side view of the half-bridge structure shown in fig. 1.
Fig. 3 is a top view of the half-bridge structure shown in fig. 1.
Fig. 4 is a partially exploded schematic view of the half-bridge structure shown in fig. 1.
Fig. 5 is a top view of a first substrate according to an embodiment of the application.
Fig. 6 is a schematic top view of an upper bridge chip and a lower bridge chip mounted on a first substrate according to an embodiment of the application.
Fig. 7 is a schematic diagram of one example of a half-bridge commutation path formed in accordance with the present application.
Fig. 8 is a schematic perspective view of a half-bridge structure according to another embodiment of the present application.
Fig. 9 is a schematic perspective view of a half-bridge structure according to yet another embodiment of the present application.
Fig. 10 is a schematic perspective view of a half-bridge structure according to still another embodiment of the present application.
Fig. 11 is a schematic perspective view of a positive dc busbar and a negative dc busbar according to an embodiment of the present application.
Fig. 12 is a schematic diagram of the overall structure of a power module according to an embodiment of the application.
Fig. 13 is a full-bridge circuit topology of a power module according to an embodiment of the application.
Fig. 14 is a flowchart of a method for manufacturing a power module according to an embodiment of the application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with aspects of the application as detailed in the accompanying claims.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
The application provides a half-bridge structure of a power module. The half-bridge structure of various embodiments of the present application will be described in detail below with reference to the accompanying drawings. The features of the examples and embodiments described below may be combined with each other without conflict.
Fig. 1 to 4 disclose illustrations of a half-bridge structure 100 of a power module according to an embodiment of the present application, wherein fig. 1 is a perspective view of the half-bridge structure 100; FIG. 2 is a side view of the half-bridge structure 100 shown in FIG. 1; FIG. 3 is a top view of the half-bridge structure 100 shown in FIG. 1; fig. 4 is a partially exploded schematic view of the half-bridge structure 100 shown in fig. 1. As shown in fig. 1 to 4, a half-bridge structure 100 according to an embodiment of the present application includes a substrate and a chipset disposed on the substrate. The substrate may include, for example, but is not limited to, a ceramic substrate.
The substrate is provided with a power connection area for connecting the power busbar and a plurality of signal connection areas for connecting a plurality of signal terminals. The power connection areas include a positive connection area dc+ for connecting the positive DC busbar 81, a negative connection area DC-for connecting the negative DC busbar 82, and an AC connection area AC for connecting the AC busbar 83.
The chip sets include an upper bridge chip set 31 and a lower bridge chip set 32. The upper bridge chipset 31 may include a plurality of upper bridge chips 310 connected in parallel, and the lower bridge chipset 32 may include a plurality of lower bridge chips 320 connected in parallel. For example, in the illustrated embodiment, upper bridge chipset 31 includes eight upper bridge chips 310 connected in parallel, and lower bridge chipset 32 includes eight lower bridge chips 320 connected in parallel. Of course, the number of chips included in the upper bridge chip 310 and the lower bridge chip 320 of the present application is not limited to eight as shown in the drawings, and may include any number of chips according to practical application requirements. In one embodiment, upper bridge chips 310 in upper bridge chipset 31 and lower bridge chips 320 in lower bridge chipset 32 may include, for example, but are not limited to, silicon carbide (SiC) chips.
The upper bridge chips 310 in the upper bridge chipset 31 are symmetrically disposed on opposite sides of the positive electrode connection region dc+, the lower bridge chips 320 in the lower bridge chipset 32 are symmetrically disposed on opposite sides of the negative electrode connection region DC-, and the number of chips in the two symmetrically disposed regions is the same. For example, in fig. 3, eight upper bridge chips 310 in the upper bridge chip group 31 are symmetrically disposed on opposite sides of the positive electrode connection region dc+ respectively, and the number of upper bridge chips 310 on opposite sides of the positive electrode connection region dc+ is the same, that is, four upper bridge chips 310 are symmetrically disposed on each of the upper side and the lower side of the positive electrode connection region dc+; eight lower bridge chips 320 in the lower bridge chip set 32 are symmetrically disposed on opposite sides of the anode connection region DC-, respectively, and the number of lower bridge chips 320 on opposite sides of the anode connection region DC-, respectively, is the same, i.e., four lower bridge chips 320 are symmetrically disposed on upper and lower sides of the anode connection region DC-, respectively.
The half-bridge structure 100 of the present application can greatly shorten the commutation path and reduce the noise of the commutating current while realizing parallel shunting by symmetrically disposing the upper bridge chip set 31/the lower bridge chip set 32 on opposite sides of the positive electrode connection region dc+/the negative electrode connection region DC-and the layout manner that the positive electrode connection region dc+ and the negative electrode connection region DC-are located in the middle of the chip.
Referring to fig. 2 and 4 in combination, in some embodiments, the substrate of the present application may include a first substrate 1 and a second substrate 2 disposed on the first substrate 1. The first substrate 1 includes a first upper conductive layer 11, a first lower conductive layer 12, and a first intermediate insulating layer 13 between the first upper conductive layer 11 and the first lower conductive layer 12; the second substrate 2 includes a second upper conductive layer 21, a second lower conductive layer 22, and a second intermediate insulating layer 23 between the second upper conductive layer 21 and the second lower conductive layer 22. The first substrate 1 and the second substrate 2 may include, for example, but not limited to, ceramic substrates. The first upper conductive layer 11 and the first lower conductive layer 12 of the first substrate 1, and the second upper conductive layer 21 and the second lower conductive layer 22 of the second substrate 2 may be copper layers, for example, and the first intermediate insulating layer 13 of the first substrate 1 and the second intermediate insulating layer 23 of the second substrate 2 may be ceramic layers, for example.
Fig. 5 discloses a top view of the first substrate 1 according to an embodiment of the application. As shown in fig. 5 in combination with reference to fig. 4, the upper bridge chip set 31, the lower bridge chip set 32, the positive electrode connection region dc+, the alternating current connection region AC, and the plurality of signal connection regions are provided on the first substrate 1. The first upper conductive layer 11 of the first substrate 1 includes a first conductive region 111 and a second conductive region 112 spaced apart from each other. Wherein the positive electrode connection region dc+ is located in the first conductive region 111 of the first substrate 1.
As shown in fig. 4, the negative electrode connection region DC-is provided on the second substrate 2. Fig. 6 discloses a schematic top view of an upper bridge chip 310 and a lower bridge chip 320 mounted on a first substrate 1 according to an embodiment of the present application. Referring to fig. 6 in combination, the back surfaces of the plurality of upper bridge chips 310 are connected to the first conductive region 111 as the drain d, and the back surfaces of the plurality of lower bridge chips 320 are connected to the second conductive region 112 as the drain d. Alternatively, the back surfaces of the plurality of upper bridge chips 310 and the plurality of lower bridge chips 320 may be sintered to the first conductive region 111 and the second conductive region 112 of the first substrate 1, respectively, through the sintered layers. The negative electrode connection region DC-is located in the second upper conductive layer 21 of the second substrate 2, and the second lower conductive layer 22 of the second substrate 2 is connected to the second conductive region 112 of the first substrate 1. Alternatively, the second lower conductive layer 22 of the second substrate 2 may be soldered to the second conductive region 112 of the first substrate 1 through a soldering/sintering process.
As shown in fig. 1,3 and 4, the front surfaces of the plurality of upper bridge chips 310 are electrically connected to the second conductive regions 112 as source electrodes s through the plurality of independent upper metal sheets 41, respectively, and the front surfaces of the plurality of lower bridge chips 320 are electrically connected to the second upper conductive layer 21 of the second substrate 2 as source electrodes s through the plurality of independent lower metal sheets 42, respectively. The separate upper metal sheet 41 and the separate lower metal sheet 42 may include, for example, but are not limited to, copper foil or the like. The number of independent upper metal sheets 41 and independent lower metal sheets 42 is equal to the number of upper bridge chips 310 and lower bridge chips 320, respectively. In the illustrated embodiment of the application, the plurality of individual upper metal sheets 41 are eight identical upper copper foils and the plurality of individual lower metal sheets 42 are eight identical lower copper foils. In one embodiment, both ends of the upper copper foil may be electrically connected to the copper layer (i.e., the second conductive region 112) where the front side of the upper bridge chip 310 and the lower bridge chip 320 are located, respectively, by a soldering or sintering process, and both ends of the lower copper foil may be electrically connected to the copper layer (i.e., the second upper conductive layer 21) where the front side of the lower bridge chip 320 and the negative electrode connection region DC-are located, respectively, by a soldering or sintering process.
Fig. 7 discloses a schematic diagram of one example of a half-bridge commutation path formed in accordance with the present application. As shown in fig. 7, the current from the positive electrode connection region dc+ sequentially passes through the first conductive region 111 of the first substrate 1 where the positive electrode connection region dc+ is located, enters the plurality of upper bridge chips 310 connected in parallel, passes through the upper bridge chips 310 as the back surface of the drain d and the upper bridge chips 310 as the front surface of the source s, then flows through the second conductive region 112 of the first substrate 1 by means of the independent upper metal sheet 41, enters the plurality of lower bridge chips 320 connected in parallel, passes through the back surface of the lower bridge chip 320 as the drain d and the front surface of the lower bridge chip 320 as the source s, then flows through the second upper conductive layer 21 of the second substrate 2 by means of the independent lower metal sheet 42, and finally is outputted to the negative electrode connection region DC-through the second upper conductive layer 21 where the negative electrode connection region DC-is located, thereby completing the current conversion. The application can greatly shorten the current conversion path and reduce the noise of the current conversion path.
The half-bridge structure 100 of the present application enables the current of the lower bridge chipset 32 to flow into the second upper conductive layer 21 of the second substrate 2 by means of the independent lower metal sheet 42 by independently disposing the negative electrode connection region DC-on the second substrate 2, so that the region of the second conductive region 112 of the first substrate 1 is more complete, and the second conductive region 112 may have a larger area as shown in fig. 5, so that the path noise can be further reduced; in addition, by adopting such a 3D structure, the structure of the entire half-bridge structure 100 can be made more compact.
Of course, it is understood that the half-bridge structure 100 of the present application is not limited to disposing the positive electrode connection region dc+ and the negative electrode connection region DC-on two substrates (i.e., the first substrate 1 and the second substrate 2), respectively. In other embodiments, the half-bridge structure 100 of the present application may also have the positive electrode connection region dc+ and the negative electrode connection region DC-respectively disposed on the same substrate, which may also have the beneficial technical effects of shortening the current converting path and reducing the noise of the current converting path shown in fig. 5.
With continued reference to fig. 3, the plurality of signal connection regions may include a plurality of signal connection regions 113 of the upper bridge chipset, a plurality of signal connection regions 114 of the lower bridge chipset 32, the plurality of signal connection regions 113, 114 including a plurality of gate signal connection regions 1131, 1141, respectively.
The plurality of parallel-connected upper bridge chips 310 distributed at each side of the positive electrode connection region dc+ constitute upper bridge chip groups, and the upper bridge chip groups distributed at opposite sides of the positive electrode connection region dc+ are independently controlled, respectively. Accordingly, a plurality of parallel-connected lower bridge chips 320 distributed at each side of the negative electrode connection region DC-constitute lower bridge chip groups, and upper bridge chip groups distributed at opposite sides of the negative electrode connection region DC-are independently controlled, respectively.
Wherein, each group of upper bridge chips corresponds to one gate signal connection region 1131, and the gates g of the upper bridge chips 310 in each group of upper bridge chips are connected to the gate signal connection region 1131 through the first upper conductive lines 51. Accordingly, each group of lower bridge chips corresponds to one gate signal connection region 1141, and the gates g of the respective lower bridge chips 320 in each group of lower bridge chips are correspondingly connected to the gate signal connection region 1141 through the first lower conductive lines 52.
In some embodiments, the gate signal connection region 1131 has a plurality of connection drop points 1136, each connection drop point 1136 is correspondingly connected to the gate g of one upper bridge chip 310 through the first upper conductive line 51, and the gate driving noise of each upper bridge chip 310 can be adjusted by adjusting the length of the first upper conductive line 51 and the position of the connection drop point 1136 between the upper bridge chips 310 in each group of upper bridge chips. Accordingly, the gate signal connection region 1141 has a plurality of connection drop points 1146, each connection drop point 1146 is correspondingly connected to the gate g of one lower bridge chip 320 through the first lower conductive line 52, and the gate driving noise of each lower bridge chip 320 can be adjusted by adjusting the length of the first lower conductive line 52 and the position of the connection drop point 1146 between each lower bridge chip 320 in each group of lower bridge chips.
In order to distinguish the positions of the connection landing points 1136 of the first upper conductive lines 51 connecting the respective upper bridge chips 310 on the gate signal connection region 1131 from the positions of the connection landing points 1146 of the first lower conductive lines 52 connecting the respective lower bridge chips 320 on the gate signal connection region 1141, the positions of the plurality of connection landing points 1136 on the gate signal connection region 1131 and the positions of the plurality of connection landing points 1146 on the gate signal connection region 1141 may be determined in advance by simulation, and corresponding marks may be made on the periphery of the landing point positions by, for example, laser light. Thus, during the manufacturing process, it is convenient to properly connect each upper bridge chip 310 to the corresponding connection drop 1136 using the first upper conductive line 51, and to properly connect each lower bridge chip 320 to the corresponding connection drop 1146 using the first lower conductive line 52.
The half-bridge structure 100 of the present application can shorten the path of each gate connection line in each chip group by independently controlling each upper bridge chip group and each lower bridge chip group, thereby reducing the gate driving circuit stray inductance, and can reduce the gate driving circuit stray inductance variability by adjusting the length and connection landing point of the first conductive line (specifically, including the first upper conductive line 51 and the first lower conductive line 52).
With continued reference to fig. 3, the plurality of signal connection regions 113 further includes a plurality of source signal connection regions 1132, and each group of upper bridge chips corresponds to one source signal connection region 1132. Accordingly, the plurality of signal connection regions 114 further includes a plurality of source signal connection regions 1142, and each group of lower bridge chips corresponds to one source signal connection region 1142.
In some embodiments, the sources s of one of the upper bridge chips 310 in each upper bridge chip group are correspondingly connected to the source signal connection region 1132 through the second upper conductive line 53, and the sources s of every adjacent two of the upper bridge chips 310 are connected through the third upper conductive line 55, so that the sources s of the upper bridge chips 310 in each upper bridge chip group are connected to the same source signal connection region 1132. Accordingly, the sources s of one of the lower bridge chips 320 in each lower bridge chip group are correspondingly connected to the source signal connection region 1142 through the second lower conductive lines 54, and the sources s of every adjacent two lower bridge chips 320 are connected through the third lower conductive lines 56, so that the sources s of the lower bridge chips 320 in each lower bridge chip group are connected to the same source signal connection region 1142.
The conductive wires may include, for example, but not limited to, aluminum wires, and the like. The conductive wires may be electrically connected to the corresponding structures through a bonding process.
In some embodiments, the half-bridge structure 100 of the present application may further include a temperature sensitive resistor R, where the temperature sensitive resistor R is disposed on the substrate and may be used to detect the overall chip temperature in the half-bridge structure 100. The temperature sensitive resistor R may comprise, for example, an NTC (Negative Temperature Coefficient ) temperature sensitive resistor. The plurality of signal connection regions 113 further includes signal connection regions 1133, 1134 of the temperature sensitive resistor 4, the temperature sensitive resistor R is connected to the signal connection region 1133, and the temperature sensitive resistor R is further connected to the signal connection region 1134 through the fourth conductive wire 57.
As shown in fig. 3, in some embodiments, temperature sensitive resistor R is located at the center line of positive electrode connection region dc+ and negative electrode connection region DC-.
According to the half-bridge structure 100, the temperature-sensitive resistor R is arranged on the central connecting line of the positive electrode connecting region DC+ and the negative electrode connecting region DC-, so that the temperature-sensitive resistor R is positioned closer to the central axis of the distribution of the upper bridge chip set 31 and the lower bridge chip set 32, and the arrangement mode of the temperature-sensitive resistor R, which is close to the symmetrical central axis of the distribution of the chips, can be beneficial to improving the junction temperature monitoring accuracy.
In some embodiments, the plurality of signal connection regions further includes monitor signal connection regions 1135, 1145 for connecting monitor signal terminals, the monitor signal connection region 1135 may be located at the first conductive region 111, and the monitor signal connection region 1145 may be located at the second conductive region 112.
As shown in fig. 3,4 and 5, the positive electrode connection region dc+ and the negative electrode connection region DC-are located substantially in the middle region of the substrate, and the alternating current connection region AC is disposed near the first end of the substrate.
In the embodiment where the substrates comprise a first substrate 1 and a second substrate 2, the positive connection region dc+ and the negative connection region DC-are located substantially in a middle region of the first substrate 1, the AC connection region AC is located near a first end of the first substrate 1, and the AC connection region AC is located in a second conductive region 112 of the first substrate 1.
In some embodiments, the signal connection regions 113 of the plurality of upper bridge chipsets 31 and the signal connection regions 1133, 1134 of the temperature-sensitive resistor R are distributed on a first side of the first substrate 1, and the signal connection region 114 of the lower bridge chipset 32 is distributed on a second side of the first substrate 1, where the first side is opposite to the second side and is adjacent to the first end.
Fig. 8 discloses a perspective view of a half-bridge structure 100 according to another embodiment of the present application. As shown in fig. 8, in some embodiments, the half-bridge structure 100 of the present application further includes a plastic enclosure 6. The plastic package 6 may be used to encapsulate the substrate and the chipset. After the half-bridge structure 100 is molded, at least a portion of each of the positive electrode connection region dc+, the negative electrode connection region DC-, the alternating current connection region AC, and the signal connection regions 113 and 114 is exposed outside the molded case 6, so that the power busbar and/or the signal terminal can be conveniently mounted from the outside.
In addition, the signal connection area is exposed outside the plastic package shell 6, so that convenience in selecting signal terminals is provided, different signal terminal shapes can be selected according to actual application requirements, and various connection modes are provided.
Fig. 9 discloses a schematic perspective view of a half-bridge structure 100 according to a further embodiment of the application. As shown in fig. 9, in some embodiments, the half-bridge structure 100 of the present application may further include a plurality of signal terminals 71, 72. The plurality of signal terminals 71, 72 are respectively connected to a plurality of signal connection areas 113, 114 exposed outside the plastic package 6.
Fig. 10 discloses a schematic perspective view of a half-bridge structure 100 according to yet another embodiment of the present application. As shown in fig. 10, in some embodiments, the half-bridge structure 100 of the present application may further include a positive dc bus 81, a negative dc bus 82, and an ac bus 83. The positive and negative DC bus bars 81 and 82 may be externally connected to the positive and negative electrode connection regions dc+ and DC-exposed outside the plastic package case 6, and the AC bus bar 83 may be externally connected to the AC connection region AC exposed outside the plastic package case 6.
Fig. 11 discloses a schematic perspective view of a positive dc busbar 81 and a negative dc busbar 82 according to an embodiment of the present application. As shown in fig. 11, in some embodiments, the positive dc busbar 81 has a first connection portion 811 and a first planar body portion 812, and the negative dc busbar 82 has a second connection portion 821 and a second planar body portion 822. The first connection portion 811 is for connection to the positive electrode connection region dc+, the second connection portion 821 is for connection to the negative electrode connection region DC-, the first planar main body portion 812 and the second planar main body portion 822 are overlapped with each other and are disposed at a distance, and an insulating material may be used for the distance region.
According to the half-bridge structure 100, the upper bridge chips 310 in the upper bridge chip set 31 are symmetrically arranged on the opposite sides of the positive electrode connection area DC+ respectively, the lower bridge chips 320 in the lower bridge chip set 32 are symmetrically arranged on the opposite sides of the negative electrode connection area DC-, and the middle layout mode of the positive electrode connection area DC+ and the negative electrode connection area DC-enables the positive direct current busbar 81 and the negative direct current busbar 82 to better realize lamination, so that the positive direct current busbar 81 and the negative direct current busbar 82 realize mutual inductance, and the system-level stray inductance is reduced.
In some embodiments, the first planar body portion 812 and the second planar body portion 822 have opposite first and second sides at the same end. The positive dc busbar 81 further has a first transition portion 813, and the first transition portion 813 connects the first connection portion 811 and the first side of the first planar main body portion 812; the negative dc bus 82 also has a second transition 823, the second transition 823 connecting the second connection 821 to a second side of the second planar body 822. The first transition portion 813 of the positive dc bus 81 and the second transition portion 823 of the negative dc bus 82 have different heights, so that the first planar body portion 812 of the positive dc bus 81 and the second planar body portion 822 of the negative dc bus 82 may be spaced apart from each other, and an insulating material may be used in the spaced apart region.
In some embodiments, the ac busbar 83 extends from a first end of the substrate, and the first planar body portion 812 of the positive dc busbar 81 and the second planar body portion 822 of the negative dc busbar 82 extend from a second end of the substrate, the second end being opposite the first end. That is, as shown in fig. 10, the ac busbar 83 extends from one end of the plastic package 6, and the first planar body portion 812 of the positive dc busbar 81 and the second planar body portion 822 of the negative dc busbar 82 extend from the opposite end of the plastic package 6.
It should be noted that, the product manufacturing end of the half-bridge structure 100 of the present application may only provide a module structure, such as the module structure shown in fig. 8, in which the signal terminals and the power bus bars are not yet mounted after plastic packaging, and the signal terminals and the power bus bars may be mounted again at the application end. Of course, the module structure shown in fig. 9 or fig. 10 may also be provided according to the requirements of the client at the application end, which is not limited herein.
The application also provides a power module 200. Fig. 12 discloses an overall structure of a power module 200 according to an embodiment of the application. As shown in fig. 12, the power module 200 of the present application includes three half-bridge structures 100 and a heat dissipation substrate 9 as described in the above embodiments, and the three half-bridge structures 100 are connected to the heat dissipation substrate 9.
Fig. 13 discloses a full-bridge circuit topology of a power module 200 according to one embodiment of the application. As shown in fig. 13, three chipsets L1, L2, L3 in the three half-bridge structures 100 form a full-bridge circuit. In each chipset, the positive electrode connection region dc+ is electrically connected to the drain d of the upper bridge chip 310, the source s of the upper bridge chip 310 is electrically connected to the drain d of the lower bridge chip 320, the negative electrode connection region DC-is electrically connected to the source s of the lower bridge chip 320, and the AC connection region AC is electrically connected to the source s of the upper bridge chip 310 and the drain d of the lower bridge chip 320, respectively.
The power module 200 of the present application may have substantially similar advantageous effects to the half-bridge structure 100 described above by adopting the half-bridge structure 100 and the vehicle having the power module 200 according to the embodiments described above, and thus, will not be described herein.
The application also provides a preparation method of the power module. Fig. 14 discloses a flowchart of a method for manufacturing a power module according to an embodiment of the present application. As shown in fig. 14, the method for manufacturing a power module according to an embodiment of the present application may include steps S1 to S5.
In step S1, a substrate is provided, on which a first conductive region 111, a second conductive region 112, a third conductive region and a plurality of signal connection regions are provided, the first conductive region 111 including a positive connection region dc+, the second conductive region 112 including an alternating current connection region AC, and the third conductive region including a negative connection region DC-.
In step S2, the plurality of upper bridge chips 310 and the plurality of lower bridge chips 320 are connected to the first conductive region 111 and the second conductive region 112, respectively.
In step S3, the front surface of each upper bridge chip 310 and the front surface of each lower bridge chip 320 are respectively connected to the second conductive region 112 and the third conductive region by the independent metal sheets (specifically, the independent upper metal sheet 41 and the independent lower metal sheet 42).
In step S4, the gate g of each upper bridge chip 310 and the gate g of each lower bridge chip 320 are respectively connected to the signal connection regions by conductive lines.
In step S5, the substrate is subjected to plastic packaging, and at least a portion of each of the positive electrode connection region dc+, the negative electrode connection region DC-, the alternating current connection region AC, and the signal connection region on the substrate is exposed, so as to obtain the half-bridge structure 100 after plastic packaging.
The power module prepared by the preparation method of the power module can have lower parasitic inductance of a power loop; in addition, in the preparation process, the power connection area and the signal connection area are exposed outside the plastic package shell 6, so that the volume of the whole module can be greatly reduced, and the signal terminals and the power busbar can be very conveniently installed from the outside of the plastic package shell 6; in addition, the mounting time of the signal terminals and the power busbar can be selected according to the actual application requirements, and the proper type of signal terminals can be conveniently changed according to the requirements of application ends after the module is molded.
In some embodiments, the providing substrate of step S1 includes: a first substrate 1 and a second substrate 2 are provided, wherein a first conductive region 111, a second conductive region 112 and a signal connection region are provided on the first substrate 1, and a third conductive region is provided on the second substrate 2. In this case, step S6 may further include: the second substrate 2 is electrically connected to the first substrate 1. Thus, the patterned metal structure of the first substrate 1 can be reduced.
In some embodiments, the first substrate 1 includes a first upper conductive layer 11, a first lower conductive layer 12, and a first intermediate insulating layer 13 between the first upper conductive layer 11 and the first lower conductive layer 12, the second substrate 2 includes a second upper conductive layer 21, a second lower conductive layer 22, and a second intermediate insulating layer 23 between the second upper conductive layer 21 and the second lower conductive layer 22, wherein the first upper conductive layer 11 of the first substrate 1 includes a first conductive region 111, a second conductive region 112, and a signal connection region, and the second upper conductive layer 21 of the second substrate 2 includes a third conductive region. In step S3, the second lower conductive layer 22 of the second substrate 2 may be electrically connected to the second conductive region 112 of the first substrate 1. Therefore, the second conductive region 112 on the first substrate 1 can be more complete, so that the second conductive region 112 can have a large area, and the path noise can be further reduced.
In some embodiments, connecting the plurality of upper bridge chips 310 and the plurality of lower bridge chips 320 to the first conductive region 111 and the second conductive region 112 of step S2 may include step S21 and step S22, respectively. In step S21, the upper bridge chips 310 are symmetrically connected to the first conductive regions 111 on opposite sides of the positive electrode connection region dc+. In step S22, a plurality of lower bridge chips 320 are symmetrically connected to the second conductive regions 112 on opposite sides of the negative electrode connection region DC-respectively, wherein the number of chips in the symmetrically arranged two regions is the same. Therefore, the current converting path can be greatly shortened, and the noise of the current converting path is reduced. Moreover, the variability between different parallel circuits can also be reduced.
In some embodiments, the signal connection regions include signal connection regions 113, 114 located on opposite first and second sides of the substrate. The step S4 of correspondingly connecting the gate g of each upper bridge chip 310 and the gate g of each lower bridge chip 320 to the signal connection region through the conductive lines may include the steps S41 and S42, respectively. In step S41, the gate g of each upper bridge chip 310 may be correspondingly connected to the signal connection region 113 located at the first side of the substrate through the first upper conductive line 51. In step S42, the gate g of each lower bridge chip 320 may be correspondingly connected to the signal connection region 114 located at the second side of the substrate through the first lower conductive line 52.
The signal connection region 113 includes a gate signal connection region 1131, and the signal connection region 114 includes a gate signal connection region 1141. In some embodiments, the signal connection region 113 correspondingly connecting the gate g of each upper bridge chip 310 to the first side of the substrate through the first upper conductive line 51 includes: grouping a plurality of upper bridge chips 310 located at each side of the positive electrode connection region dc+ as one independently controlled upper bridge chip 310 and connecting the gate g of each upper bridge chip 310 thereof to one gate signal connection region 1131 of the first side through the first upper conductive line 51; accordingly, the signal connection region 114 correspondingly connecting the gate g of each lower bridge chip 320 to the second side of the substrate through the first lower conductive line 52 includes: the plurality of lower bridge chips 320 located at each side of the negative electrode connection region DC-are grouped as one independently controlled lower bridge chip 320 and the gate g of each lower bridge chip 320 thereof is connected to one gate signal connection region 1141 of the second side through the first lower conductive line 52. Thus, independent control of each upper bridge chip 310 grouping and each lower bridge chip 320 grouping can be achieved.
In some embodiments, the method for manufacturing a power module of the present application further includes: the positions of a plurality of connection landing points 1136 of the first upper conductive lines 51 on the gate signal connection region 1131 and the positions of a plurality of connection landing points 1146 of the first lower conductive lines 52 on the gate signal connection region 1141 are determined in advance through simulation and corresponding marks are made on the periphery of the landing point positions by laser, so that the gates g of the upper bridge chips 310 in each upper bridge chip 310 group can be accurately correspondingly connected to the connection landing points 1136 on the gate signal connection region 1131 through the first upper conductive lines 51; and the gates g of the lower bridge chips 320 in the respective lower bridge chip 320 groups are correspondingly connected to the respective connection landing points 1146 under the gate signal connection region 1141 through the first lower conductive lines 52.
In some embodiments, the method for manufacturing a power module of the present application may further include: the temperature-sensitive resistor R is arranged in a signal connection region of a central line between the positive electrode connection region dc+ and the negative electrode connection region DC-. Therefore, the monitoring accuracy of the temperature of the chip inside the module can be improved.
In some embodiments, the method for manufacturing a power module of the present application may further include step S6. In step S9, the three half-bridge structures 100 after plastic packaging are connected to the heat dissipation substrate 9 to form a full-bridge module.
In some embodiments, the method for manufacturing a power module of the present application may further include step S7. In step S7, the signal terminals are connected to the signal connection areas exposed outside the plastic package 6 of the half-bridge structure 100 after plastic packaging.
In some embodiments, the method for manufacturing a power module of the present application may further include steps S81 to S83.
In step S81, a positive dc busbar 81 and a negative dc busbar 82 are provided, wherein the positive dc busbar 81 has a first connection portion 811 and a first planar body portion 812, and the negative dc busbar 82 has a second connection portion 821 and a second planar body portion 822.
In step S82, the first connection portion 811 of the positive DC busbar 81 and the second connection portion 821 of the negative DC busbar 82 are respectively connected to the positive connection region dc+ and the negative connection region DC "exposed outside the plastic package 6 of the half-bridge structure 100 after plastic packaging, and the first planar main body portion 812 of the positive DC busbar 81 and the second planar main body portion 822 of the negative DC busbar 82 overlap each other and extend from one end of the plastic package 6 at intervals.
In step S83, the AC busbar 83 is connected to the AC connection area AC outside the plastic package 6, and the AC busbar 83 extends from the opposite end of the plastic package 6.
The steps S7 and S81 to S83 may be performed before or after the step S6 according to the actual application requirement.
The steps of one specific example of the method for manufacturing a power module of the present application are described in detail below with reference to the drawings.
First, a first substrate 1 as shown in fig. 5 and a second substrate 2 as shown in fig. 4 are provided.
And (3) sintering: as shown in fig. 6, all the upper bridge chips 310 and all the lower bridge chips 320 are sintered to the first conductive region 111 and the second conductive region 112 of the first substrate 1, respectively, through a sintering process.
And (3) welding: as shown in fig. 7, the second lower conductive layer 22 of the second substrate 2 is welded to the second conductive region 112 of the first substrate 1, the independent upper metal sheets 41 are respectively welded to the surface of each upper bridge chip 310 and the second conductive region 112 of the first substrate 1, the independent lower metal sheets 42 are respectively welded to the surface of each lower bridge chip 320 and the second upper conductive layer 21 of the second substrate 2, and one end of the temperature-sensitive resistor R is welded to the signal connection region of the first substrate 1. In the welding step, each element to be welded and the welding flux can be placed at the corresponding welding position and fixed by the clamp, and then the elements to be welded and the welding flux can be placed in a welding furnace together to finish welding at one time.
And (3) wire bonding: as shown in fig. 3, the gates g of each upper bridge chip 310 and each lower bridge chip 320 are respectively bonded to the corresponding signal connection region through a bonding process, and the other end of the temperature sensitive resistor R is bonded to the other signal connection region through a bonding process.
And (3) plastic packaging: as shown in fig. 8, the substrate after the above steps is subjected to plastic packaging.
Terminal welding: as shown in fig. 9, each signal terminal is welded to a signal connection area exposed outside the plastic package case 6 after plastic packaging.
And welding the busbar: as shown in fig. 10, the power busbar is respectively welded to corresponding power pads exposed outside the plastic package case 6 after plastic packaging.
And (3) system welding: as shown in fig. 12, three half-bridge structures 100 are respectively welded to the heat dissipation substrate 9, and the welding is completed at one time.
Of course, the terminal welding step and the busbar welding step may be performed after the system welding step is completed, or may be performed by the customer at the application end.
It will be understood that the specific steps of the above method for manufacturing a power module are only one specific example of the present application, however, the method for manufacturing a power module of the present application is not limited to the specific steps described above, and in other embodiments, the steps may be split, combined, omitted, etc. appropriately, and in addition, the order of the steps and the specific process adopted by the steps may be appropriately adjusted according to the actual situation.
The method for preparing the power module provided by the embodiment of the application is described in detail. Specific examples are used herein to illustrate the method for manufacturing the power module according to the embodiments of the present application, and the description of the above embodiments is only for helping to understand the core idea of the present application, and is not intended to limit the present application. It should be noted that it will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the spirit and principles of the application, which should also fall within the scope of the appended claims.

Claims (9)

1. A preparation method of a power module is characterized by comprising the following steps: comprising the following steps:
providing a substrate, wherein a first conductive area, a second conductive area, a third conductive area and a plurality of signal connection areas are arranged on the substrate, the first conductive area comprises a positive electrode connection area, the second conductive area comprises an alternating current connection area, and the third conductive area comprises a negative electrode connection area;
connecting a plurality of upper bridge chips and a plurality of lower bridge chips to the first conductive region and the second conductive region, respectively;
Connecting the front surface of each upper bridge chip and the front surface of each lower bridge chip to the second conductive area and the third conductive area through independent metal sheets respectively;
The grid electrode of each upper bridge chip and the grid electrode of each lower bridge chip are correspondingly connected to the signal connection area through conducting wires respectively; and
The substrate is subjected to plastic packaging, and at least one part of each of the positive electrode connection region, the negative electrode connection region, the alternating current connection region and the signal connection region on the substrate is exposed to obtain a half-bridge structure after plastic packaging,
The providing substrate includes:
Providing a first substrate and a second substrate, wherein the first substrate is provided with the first conductive region, the second conductive region and the signal connection region, the second substrate is provided with the third conductive region,
The preparation method further comprises the following steps:
electrically connecting the second substrate to the first substrate,
The first substrate comprises a first upper conductive layer, a first lower conductive layer and a first middle insulating layer positioned between the first upper conductive layer and the first lower conductive layer, the second substrate comprises a second upper conductive layer, a second lower conductive layer and a second middle insulating layer positioned between the second upper conductive layer and the second lower conductive layer, wherein the first upper conductive layer of the first substrate comprises the first conductive region, the second conductive region and the signal connection region, the second upper conductive layer of the second substrate comprises the third conductive region,
The electrically connecting the second substrate to the first substrate includes:
The second lower conductive layer of the second substrate is electrically connected to the second conductive region of the first substrate.
2. The method of manufacturing according to claim 1, wherein: the connecting the plurality of upper bridge chips and the plurality of lower bridge chips to the first conductive region and the second conductive region, respectively, includes:
Symmetrically connecting a plurality of upper bridge chips to the first conductive areas on two opposite sides of the positive electrode connection area respectively; and
And respectively and symmetrically connecting a plurality of lower bridge chips to the second conductive areas on two opposite sides of the negative electrode connection area, wherein the number of chips in the two symmetrically arranged areas is the same.
3. The method of manufacturing as claimed in claim 2, wherein: the signal connection area comprises a signal connection area positioned on a first side edge and a second side edge which are opposite to each other of the substrate, and the corresponding connection of the grid electrode of each upper bridge chip and the grid electrode of each lower bridge chip to the signal connection area through conductive wires comprises the following steps:
Correspondingly connecting the grid electrode of each upper bridge chip to the signal connection area positioned on the first side edge of the substrate through a first upper conductive wire; and
And correspondingly connecting the grid electrode of each lower bridge chip to the signal connection area positioned on the second side edge of the substrate through a first lower conductive wire.
4. A method of preparation as claimed in claim 3, wherein: the signal connection region includes a gate signal connection region, wherein,
The signal connection area for correspondingly connecting the grid electrode of each upper bridge chip to the first side edge of the substrate through the first upper conductive wire comprises: grouping a plurality of upper bridge chips positioned on each side of the positive electrode connection region as an independently controlled upper bridge chip and connecting the grid electrode of each upper bridge chip to a grid electrode signal connection region of the first side edge through a first upper conductive wire;
The signal connection area for correspondingly connecting the grid electrode of each lower bridge chip to the second side edge of the substrate through the first lower conductive wire comprises: and grouping a plurality of lower bridge chips positioned on each side of the negative electrode connection region as an independently controlled lower bridge chip, and connecting the grid electrode of each lower bridge chip to one grid electrode signal connection region of the second side edge through a first lower conductive wire.
5. The method of manufacturing according to claim 4, wherein: further comprises:
The positions of a plurality of connection landing points of the first upper conductive line and the first lower conductive line on the gate signal connection region are determined in advance through simulation and corresponding marks are made on the periphery of the landing point positions by laser,
Wherein, the grid electrodes of all upper bridge chips in all upper bridge chip groups are correspondingly connected to all connection drop points on the grid signal connection area of the first side edge through a first upper conductive wire;
and correspondingly connecting the grid electrode of each lower bridge chip in each lower bridge chip group to each connection drop point under the grid electrode signal connection area of the second side edge through a first lower conductive wire.
6. The method of manufacturing as claimed in claim 2, wherein: further comprises:
and arranging the temperature-sensitive resistor in a signal connection area which is positioned in the central connecting line of the positive electrode connection area and the negative electrode connection area.
7. The method of manufacturing according to claim 1, wherein: further comprises:
and connecting the three half-bridge structures after plastic packaging to the heat dissipation substrate to form the full-bridge module.
8. The production method according to any one of claims 1 to 7, characterized in that: further comprises:
and connecting the signal terminals to the signal connection areas exposed out of the plastic package shell of the half-bridge structure after plastic package.
9. The production method according to any one of claims 1 to 7, characterized in that: further comprises:
providing a positive direct current busbar and a negative direct current busbar, wherein the positive direct current busbar is provided with a first connecting part and a first plane main body part, and the negative direct current busbar is provided with a second connecting part and a second plane main body part;
The first connecting part of the positive direct current busbar and the second connecting part of the negative direct current busbar are respectively connected with the positive connecting area and the negative connecting area exposed outside the plastic package shell of the half-bridge structure after plastic package, and the first plane main body part of the positive direct current busbar and the second plane main body part of the negative direct current busbar are mutually overlapped and extend out of one end of the plastic package shell at intervals; and
And connecting an alternating current busbar to the alternating current connection area outside the plastic package shell, and extending from the other end opposite to the plastic package shell.
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