CN118134749A - Data transmission rate updating method, device and equipment - Google Patents

Abstract

The application discloses a method, a device and equipment for updating a data transmission rate, and belongs to the technical field of image processing. The method comprises the following steps: acquiring the number of vertexes of the first image frame; determining a first data amount of first cache data corresponding to the first image frame according to the vertex number, wherein the first cache data is data required by the first image frame in the rendering process; determining a first rate according to a first data amount of the first cache data, and updating a data transmission rate between an image processing unit and a memory from an initial rate to the first rate before rendering the first image frame, wherein the image processing unit is used for rendering the first image frame, and the memory is used for storing the first cache data.

Description

Data transmission rate updating method, device and equipment

Technical Field

The application belongs to the technical field of image processing, and particularly relates to a method, a device and equipment for updating a data transmission rate.

Background

Conventional graphics rendering pipelines require a significant amount of memory bandwidth requirements during the rendering of images. To reduce bandwidth requirements, tiled-based (tiled) rendering techniques may be used. Through tiled-based rendering techniques, the image to be rendered can be divided into small blocks (tiles), each tile being rendered independently.

However, under the tiled-based architecture, since the small-piece rendering is performed, the graphics processing unit needs to frequently read and write the memory in the rendering process, when the graphics processing unit has a large amount of access requirements to the memory, the access time of the graphics processing unit to the memory is too long, which can cause the rendering time of a single image to be too long, thereby causing slow image rendering.

Disclosure of Invention

The embodiment of the application aims to provide a method, a device and equipment for updating a data transmission rate, which can solve the technical problem of slow image rendering in the prior art.

In a first aspect, an embodiment of the present application provides a method for updating a data transmission rate, where the method includes:

obtaining the number of vertexes of a first image frame, wherein the first image frame is an image frame to be rendered;

Determining a first data amount of first cache data corresponding to the first image frame according to the vertex number, wherein the first cache data is data required by the first image frame in the rendering process;

Determining a first rate according to a first data amount of the first cache data, and updating a data transmission rate between an image processing unit and a memory from an initial rate to the first rate before rendering the first image frame, wherein the image processing unit is used for rendering the first image frame, and the memory is used for storing the first cache data.

In a second aspect, an embodiment of the present application provides an apparatus for updating a data transmission rate, including:

the image processing device comprises a first acquisition module, a second acquisition module and a first display module, wherein the first acquisition module is used for acquiring the number of vertexes of a first image frame, and the first image frame is an image frame to be rendered;

The first determining module is used for determining a first data amount of first cache data corresponding to the first image frame according to the vertex number, wherein the first cache data is data required by the first image frame in the rendering process;

The first updating module is used for determining a first rate according to a first data amount of the first cache data, updating the data transmission rate between the image processing unit and the memory from an initial rate to the first rate before rendering the first image frame, wherein the image processing unit is used for rendering the first image frame, and the memory is used for storing the first cache data.

In a third aspect, an embodiment of the application provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as provided in the first aspect.

In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the method as provided in the first aspect.

In a fifth aspect, an embodiment of the present application provides a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to execute programs or instructions to implement a method as provided in the first aspect.

In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement a method as provided in the first aspect.

In the method, the device and the equipment for updating the data transmission rate, the vertex number of the image frame can be obtained in the process that each image is about to be rendered, the data amount of the cache data corresponding to the image frame is estimated based on the vertex number of the image frame, and then the data transmission rate between an image processing unit and a memory in the electronic equipment is adjusted according to the data amount. Therefore, before each image frame is subjected to image rendering, the buffer data volume of the image frame can be estimated in advance, and the data transmission rate between the image processing unit and the memory is adjusted to be matched with the transmission rate of the buffer data volume, so that the rendering time of the image processing unit to the memory in the image frame rendering process is ensured not to be too long, the image rendering is avoided to be too slow, and further the image display is prevented from being blocked.

Drawings

Fig. 1 is a flowchart of a method for updating a data transmission rate according to an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a data transmission rate updating device according to another embodiment of the present application;

Fig. 3 is a schematic structural diagram of an electronic device according to another embodiment of the present application;

fig. 4 is a schematic hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or otherwise described herein, and that the objects identified by "first," "second," etc. are generally of a type not limited to the number of objects, for example, the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

In order to solve the technical problems, the application provides a data transmission rate updating method. The method for updating the data transmission rate provided by the embodiment of the application is described in detail below through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

As shown in fig. 1, fig. 1 is a flowchart of a method for updating a data transmission rate according to an embodiment of the present application, where the method for updating a data transmission rate may include:

s101, obtaining the number of vertexes of a first image frame, wherein the first image frame is an image frame to be rendered;

In this embodiment, the video or the plurality of images may be rendered in an electronic device, where the electronic device at least includes an image processing unit and a memory, where the image processing unit is configured to render the images frame by frame, and the memory is configured to store data related to image rendering. Before the first image frame is received and rendered, all the vertices in the first image frame can be extracted according to the shape and structure of the geometric figure in the first image frame, and the number of the vertices in the first image frame is counted. Wherein the vertices are used to characterize corners and inflection points of the geometry in the image frames.

S102, determining a first data volume of first cache data corresponding to the first image frame according to the vertex number, wherein the first cache data is data required by the first image frame in the rendering process;

In this embodiment, the electronic device may render the image using tiled-based (tiled) rendering techniques. The first image frame may be divided into a plurality of image segments by tiled-based rendering techniques and each image segment may be rendered independently one by one using an image processing unit.

In the process of rendering the image frames through tiled-based rendering technology, cache data (FRAME DATA) for rendering are generated based on the image frames and stored in a memory of the electronic device, and in the process of sequentially rendering each image segment, the image processing unit can perform read-write interaction with the memory to acquire the cache data corresponding to the image segment and complete the rendering of the image segment by utilizing the data.

For example, in the tiled-based architecture, the geometry in the first image frame may be split into multiple triangles for rendering, and then the cached data may include raw vertex data, shading results, triangle indices, pixel states, and so on. The original vertex data may include vertex coordinates, normal vectors, texture coordinates, and the like of the triangles; the coloring result is the result of the vertex shader after processing the original vertex data; the pixel state then includes depth information and template information. These cached data are saved for use in a later rendering stage.

In addition, since the vertices are basic elements constituting the geometry in the image frame, the more the number of vertices, the more complex the geometry in the image frame, and thus the larger the data amount of the corresponding buffer data, the data amount of the corresponding buffer data can be estimated by the number of vertices.

S103, determining a first rate according to the first data amount of the first cache data, and updating the data transmission rate between an image processing unit and a memory from an initial rate to the first rate before rendering the first image frame, wherein the image processing unit is used for rendering the first image frame, and the memory is used for storing the first cache data.

In the embodiment of the application, since the first cache data exists in the memory of the electronic device, the image processing unit needs to frequently interact with the memory in the process of rendering the first image frame so as to read and write the first cache data in the memory. If the time for reading and writing is too long, the rendering time of the first image frame is too long, and thus the image display is blocked.

Therefore, the first rate matched with the first data amount can be determined based on the data amount of each image frame, then the data transmission rate between the image processing unit and the memory is adjusted, and the actual data transmission rate between the image processing unit and the memory is adjusted from the initial rate to the first rate matched with the first data amount, so that the rendering time of each frame is ensured to be within a proper time interval, and the blocking of image display is avoided.

In some embodiments, S103 may include:

Determining a half of the first rate as a second rate;

and adjusting the double data rate of the memory to the second rate so as to update the data transmission rate between the image processing unit and the memory to the first rate.

In this embodiment, if the electronic device uses the Double Data Rate (DDR) technology, after determining the first Rate, the Data transmission Rate between the image processing unit and the memory can be adjusted by adjusting the DDR (Double Data Rate) of the memory. DDR is a memory technology that allows data to be transferred twice per clock cycle, so if DDR technology is used in the memory of an electronic device, the corresponding DDR of the memory can be adjusted to half the first rate, and the actual data transfer rate between the image processing unit and the memory is correspondingly adjusted to the first rate.

Therefore, the half of the first rate can be determined as the second rate, and after the DDR of the memory is adjusted to the second rate, the data transmission rate between the image processing unit and the memory is automatically adjusted to the first rate.

In the application, the vertex number of the image frame can be obtained in the process that each image is about to be rendered, the data quantity of the cache data corresponding to the image frame is estimated based on the vertex number of the image frame, and then the data transmission rate between an image processing unit and a memory in the electronic equipment is adjusted according to the data quantity. Therefore, before each image frame is subjected to image rendering, the buffer data volume of the image frame can be estimated in advance, and the data transmission rate between the image processing unit and the memory is adjusted to be matched with the transmission rate of the buffer data volume, so that the rendering time of the image processing unit to the memory in the image frame rendering process is ensured not to be too long, the image rendering is avoided to be too slow, and further the image display is prevented from being blocked.

In some embodiments, S102 is preceded by:

Acquiring a second data amount of second cache data corresponding to a second image frame, wherein the second image frame is the last image frame of the first image frame;

determining a first difference of the first data amount minus the second data amount, and determining an absolute value of the first difference;

The step S102 includes:

and under the condition that the absolute value of the first difference value is larger than a first threshold value, determining the first rate according to the first data quantity, and updating the data transmission rate between the image processing unit and the memory from the initial rate to the first rate before rendering the first image frame.

In this embodiment, before determining the first data amount of the first buffer data corresponding to the first image frame, the second data amount corresponding to the last image frame adjacent to the first image frame, that is, the second image frame, may be acquired. An absolute value of a first difference between the first data amount and the second data amount is then calculated.

If the absolute value of the first difference value is larger than a preset first threshold value, the data quantity difference between the first cache data and the second cache data is larger, and the data transmission rate between the image processing unit and the memory needs to be redetermined and adjusted based on the first data quantity; if the absolute value of the first difference value is smaller than or equal to a preset first threshold value, the data quantity difference between the first cache data and the second cache data is smaller, and when the first image frame is subjected to data rendering, the data transmission rate when the second image frame is rendered can be used, and the data transmission rate between the image processing unit and the memory does not need to be readjusted.

In this embodiment, the difference in data amount between the first image frame and the second image frame may be determined by comparing the data amounts of the first image frame and the previous image frame adjacent to the first image frame, and the data transmission rate between the image processing unit and the memory may be updated only when the difference in data amount is large, so that the computational effort required for updating the data transmission rate may be saved while avoiding the image rendering from being too slow.

In some embodiments, the determining the first rate from the first data amount of the first buffered data includes:

Acquiring a preset total single-frame rendering time length;

And determining the first rate according to the single frame rendering total duration and the first data quantity.

In this embodiment, the total time length of single frame rendering is the total time length consumed for rendering one image frame, that is, the time from the start of rendering to the completion of the whole process of rendering. In order to provide a smooth visual experience, users often want to be able to maintain a certain frame rate during the rendering of a video or multiple image frames.

In addition, because the time consumption ratio between the processes of each stage of the rendering is usually fixed in the rendering process, the single-frame read-write time length allocated to the image processing unit for data interaction with the memory when one image frame is rendered can be estimated based on the single-frame rendering total time length, and then the quotient of the first data quantity divided by the single-frame read-write time length can be determined as the first rate.

For example, the total single-frame rendering duration may be set to 10ms, the first data amount may be 5000 bits, and the time consumption of data read-write in rendering may be 20%, so that when one image frame is rendered based on the total single-frame rendering duration, the single-frame read-write duration allocated to the image processing unit for performing data interaction with the memory may be estimated to be 2ms, that is, the data of the data amount of 5000 bits needs to be transmitted within 2ms, and therefore the first rate may be determined to be 5000 bits divided by 2ms, that is, 2.5Mbps.

By the method, the rendering time length of each image frame can be controlled to be the total rendering time length of a single frame by determining the first rate, and the smoothness of image display is ensured by enabling the rendering time length of each image frame to be nearly consistent.

In some embodiments, before determining the first data amount of the first buffered data corresponding to the first image frame according to the number of vertices, the method further includes:

Acquiring a plurality of historical vertex numbers of a plurality of historical image frames, wherein each historical image frame corresponds to one historical vertex number;

Acquiring a plurality of historical data amounts corresponding to the plurality of historical image frames, wherein each historical image frame corresponds to one historical data amount;

generating a first corresponding relation according to the plurality of historical vertex numbers and the plurality of historical data amounts, wherein the first corresponding relation is a corresponding relation between the vertex numbers and the data amounts of the image frames.

In this embodiment, for each historical image frame, a hardware counter in the image processing unit may be used to obtain the number of historical vertices in the historical image frame, and by querying a driver interface associated with the image processing unit, obtain the historical cache data in the historical image frame in the driver, and determine the historical data amount of the historical cache data.

After obtaining the plurality of historical vertex numbers and the historical data amount corresponding to each historical vertex number, a relationship curve between the vertex number and the data amount or a relationship table between the vertex number and the data amount can be generated through data fitting based on the plurality of historical vertex numbers and the plurality of historical data amounts. The first correspondence between the number of vertices and the amount of data in each image frame may also be extracted by a relationship curve and a relationship table.

By the method, the corresponding relation between the vertex number corresponding to the historical image frames and the cached data quantity can be summarized, so that the cached data quantity corresponding to each image frame can be accurately predicted based on the corresponding relation and the vertex number.

In some embodiments, after updating the data transfer rate between the image processing unit and the memory from the initial rate to the first rate before rendering the first image frame, the method includes:

After the first image frame is rendered, the data transmission rate is updated from the first rate to an initial rate.

In this embodiment, before each image frame performs image rendering, the data transmission rate between the image processing unit and the memory may be adjusted from the initial rate to a first rate, where the first rate is matched with the data size of the buffered data corresponding to the image frame, so that it can be ensured that the total duration occupied by the image processing unit performing data reading and writing from the memory at the first rate in the image rendering process accords with the expectation of the user.

And after the image frame is rendered, the data transfer rate may be adjusted from the first rate back to the default initial rate.

By the rate adjustment mode, the rate can be adjusted back to the default value after a certain image frame is rendered, so that the situation that data transmission is continuously performed at an excessively high or excessively low speed after the rendering is completed, and bandwidth resources are wasted is avoided.

Fig. 2 is a schematic structural diagram of a data transmission rate updating device according to another embodiment of the present application, and as shown in fig. 2, the data transmission rate updating device may include:

a first obtaining module 201, configured to obtain the number of vertices of a first image frame, where the first image frame is an image frame to be rendered;

a first determining module 202, configured to determine a first data amount of first buffered data corresponding to the first image frame according to the number of vertices, where the first buffered data is data required by the first image frame in a rendering process;

A first updating module 203, configured to determine a first rate according to a first data amount of the first buffered data, and update, before rendering the first image frame, a data transmission rate between an image processing unit and a memory from an initial rate to the first rate, where the image processing unit is configured to render the first image frame, and the memory is configured to store the first buffered data.

In the application, the vertex number of the image frame can be obtained in the process that each image is about to be rendered, the data quantity of the cache data corresponding to the image frame is estimated based on the vertex number of the image frame, and then the data transmission rate between an image processing unit and a memory in the electronic equipment is adjusted according to the data quantity. Therefore, before each image frame is subjected to image rendering, the buffer data volume of the image frame can be estimated in advance, and the data transmission rate between the image processing unit and the memory is adjusted to be matched with the transmission rate of the buffer data volume, so that the rendering time of the image processing unit to the memory in the image frame rendering process is ensured not to be too long, the image rendering is avoided to be too slow, and further the image display is prevented from being blocked.

In another optional example, the updating means of the data transmission rate further includes:

A second obtaining module, configured to obtain a second data amount of second buffered data corresponding to a second image frame, where the second image frame is a previous image frame of the first image frame;

a second determining module configured to determine a first difference value of the first data amount minus the second data amount, and determine an absolute value of the first difference value;

the first update module 203 further includes:

And the first determining unit is used for determining the first rate according to the first data amount and updating the data transmission rate between the image processing unit and the memory from the initial rate to the first rate before rendering the first image frame under the condition that the absolute value of the first difference value is larger than a first threshold value.

In another alternative example, the first update module 203 further includes:

the first acquisition unit is used for acquiring a preset total single-frame rendering duration;

and the second determining unit is used for determining the first rate according to the single frame rendering total duration and the first data volume.

In another optional example, the updating means of the data transmission rate further includes:

A third obtaining unit, configured to obtain a plurality of historical vertex numbers of a plurality of historical image frames, where each historical image frame corresponds to one historical vertex number;

a fourth obtaining unit, configured to obtain a plurality of historical data amounts corresponding to the plurality of historical image frames, where each historical image frame corresponds to one historical data amount;

And the generating unit is used for generating a first corresponding relation according to the plurality of historical vertex numbers and the plurality of historical data amounts, wherein the first corresponding relation is a corresponding relation between the vertex numbers and the data amounts of the image frames.

In another alternative example, the first update module 203 further includes:

And the second updating module is used for updating the data transmission rate from the first rate to an initial rate after the first image frame is rendered.

The updating device of the data transmission rate in the embodiment of the application can be electronic equipment or a component in the electronic equipment, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the electronic device may be a Mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile internet appliance (Mobile INTERNET DEVICE, MID), an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a robot, a wearable device, an ultra-Mobile personal computer (UMPC), a netbook or a personal digital assistant (personal DIGITAL ASSISTANT, PDA), etc., a server, a network attached storage (NetworkAttached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine, a self-service machine, etc., a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine, a self-service machine, etc., and the embodiments of the present application are not limited in particular.

The device for updating the data transmission rate in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an IOS operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.

The data transmission rate updating device provided by the embodiment of the present application can implement each process implemented by the method embodiment of fig. 1, and in order to avoid repetition, a description is omitted here.

Optionally, as shown in fig. 3, the embodiment of the present application further provides an electronic device 100, including a processor 110, a memory 119, and a program or an instruction stored in the memory 119 and capable of being executed on the processor 110, where the program or the instruction implements each process of the above embodiment of the method for updating a data transmission rate when executed by the processor 110, and the same technical effects are achieved, and for avoiding repetition, a detailed description is omitted herein.

The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

Referring to fig. 4 in combination, fig. 4 is a schematic hardware structure of an electronic device implementing an embodiment of the present application. The electronic device 100 includes, but is not limited to: radio frequency unit 121, network module 122, audio output unit 123, input unit 124, sensor 125, display unit 126, user input unit 127, interface unit 128, memory 129, and processor 120.

Those skilled in the art will appreciate that the electronic device 100 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 120 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 4 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.

The processor 120 is configured to obtain a number of vertices of a first image frame, where the first image frame is an image frame to be rendered;

The processor 120 is configured to determine a first data amount of first buffered data corresponding to the first image frame according to the number of vertices, where the first buffered data is data required by the first image frame in a rendering process;

The processor 120 is configured to determine a first rate according to a first data amount of the first buffered data, and update a data transmission rate between an image processing unit and a memory before rendering the first image frame from an initial rate to the first rate, where the image processing unit is configured to render the first image frame, and the memory is configured to store the first buffered data.

In the application, the vertex number of the image frame can be obtained in the process that each image is about to be rendered, the data quantity of the cache data corresponding to the image frame is estimated based on the vertex number of the image frame, and then the data transmission rate between an image processing unit and a memory in the electronic equipment is adjusted according to the data quantity. Therefore, before each image frame is subjected to image rendering, the buffer data volume of the image frame can be estimated in advance, and the data transmission rate between the image processing unit and the memory is adjusted to be matched with the transmission rate of the buffer data volume, so that the rendering time of the image processing unit to the memory in the image frame rendering process is ensured not to be too long, the image rendering is avoided to be too slow, and further the image display is prevented from being blocked.

In another optional example, the updating means of the data transmission rate further includes:

A processor 120, configured to obtain a second data amount of second buffered data corresponding to a second image frame, where the second image frame is a previous image frame to the first image frame;

A processor 120 for determining a first difference of the first data amount minus the second data amount and determining an absolute value of the first difference;

The processor 120 is further configured to: and under the condition that the absolute value of the first difference value is larger than a first threshold value, determining the first rate according to the first data quantity, and updating the data transmission rate between the image processing unit and the memory from the initial rate to the first rate before rendering the first image frame.

In another alternative example, the processor 120 is further configured to:

Acquiring a preset total single-frame rendering time length;

And determining the first rate according to the single frame rendering total duration and the first data quantity.

In another alternative example, the processor 120 is further configured to:

Acquiring a plurality of historical vertex numbers of a plurality of historical image frames, wherein each historical image frame corresponds to one historical vertex number;

Acquiring a plurality of historical data amounts corresponding to the plurality of historical image frames, wherein each historical image frame corresponds to one historical data amount;

generating a first corresponding relation according to the plurality of historical vertex numbers and the plurality of historical data amounts, wherein the first corresponding relation is a corresponding relation between the vertex numbers and the data amounts of the image frames.

In another alternative example, the processor 120 is further configured to:

After the first image frame is rendered, the data transmission rate is updated from the first rate to an initial rate.

It should be appreciated that in embodiments of the present application, the input unit 124 may include a graphics processor (Graphics Processing Unit, GPU) 1241 and a microphone 1242, with the graphics processor 1241 processing image data of still pictures or video obtained by an image capture device (e.g., a camera) in a video capture mode or an image capture mode. The display unit 126 may include a display panel 1261, and the display panel 1261 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 127 includes at least one of a touch panel 1271 and other input devices 1272. Touch panel 1271 is also referred to as a touch screen. Touch panel 1271 may include two parts, a touch detection device and a touch controller. Other input devices 1272 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.

The memory 129 may be used to store software programs and various data. The memory 129 may mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 129 may include volatile memory or nonvolatile memory, or the memory 129 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (RandomAccess Memory, RAM), static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate Synchronous dynamic random access memory (Double DATA RATE SDRAM, DDRSDRAM), enhanced Synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCH LINK DRAM, SLDRAM), and Direct random access memory (DRRAM). Memory 129 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

Processor 120 may include one or more processing units; optionally, the processor 120 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 120.

The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above-mentioned data transmission rate updating method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here.

The processor is a processor in the electronic device in the above embodiment. Readable storage media include computer readable storage media such as computer readable memory ROM, random access memory RAM, magnetic or optical disks, and the like.

The embodiment of the application further provides a chip, the chip comprises a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running programs or instructions, the processes of the data transmission rate updating method embodiment can be realized, the same technical effects can be achieved, and the repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the data transmission rate updating method embodiment, and achieve the same technical effects, and are not repeated herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (11)

1. A method for updating a data transmission rate, comprising:

obtaining the number of vertexes of a first image frame, wherein the first image frame is an image frame to be rendered;

Determining a first data amount of first cache data corresponding to the first image frame according to the vertex number, wherein the first cache data is data required by the first image frame in the rendering process;

Determining a first rate according to a first data amount of the first cache data, and updating a data transmission rate between an image processing unit and a memory from an initial rate to the first rate before rendering the first image frame, wherein the image processing unit is used for rendering the first image frame, and the memory is used for storing the first cache data.

2. The method of claim 1, wherein prior to determining the first rate from the first amount of data of the first buffered data, further comprising:

Acquiring a second data amount of second cache data corresponding to a second image frame, wherein the second image frame is the last image frame of the first image frame;

determining a first difference of the first data amount minus the second data amount, and determining an absolute value of the first difference;

The determining a first rate according to the first data amount of the first cache data, and updating the data transmission rate between the image processing unit and the memory from an initial rate to the first rate before rendering the first image frame, includes:

and under the condition that the absolute value of the first difference value is larger than a first threshold value, determining the first rate according to the first data quantity, and updating the data transmission rate between the image processing unit and the memory from the initial rate to the first rate before rendering the first image frame.

3. The method of claim 1, wherein the determining a first rate from the first amount of data of the first buffered data comprises:

Acquiring a preset total single-frame rendering time length;

And determining the first rate according to the single frame rendering total duration and the first data quantity.

4. The method according to claim 1, further comprising, before determining the first data amount of the first buffered data corresponding to the first image frame according to the number of vertices:

Acquiring a plurality of historical vertex numbers of a plurality of historical image frames, wherein each historical image frame corresponds to one historical vertex number;

Acquiring a plurality of historical data amounts corresponding to the plurality of historical image frames, wherein each historical image frame corresponds to one historical data amount;

generating a first corresponding relation according to the plurality of historical vertex numbers and the plurality of historical data amounts, wherein the first corresponding relation is a corresponding relation between the vertex numbers and the data amounts of the image frames.

5. The method of claim 1, wherein after updating the data transfer rate between the image processing unit and the memory from the initial rate to the first rate prior to rendering the first image frame, comprising:

After the first image frame is rendered, the data transmission rate is updated from the first rate to an initial rate.

6. An apparatus for updating a data transmission rate, comprising:

the image processing device comprises a first acquisition module, a second acquisition module and a first display module, wherein the first acquisition module is used for acquiring the number of vertexes of a first image frame, and the first image frame is an image frame to be rendered;

The first determining module is used for determining a first data amount of first cache data corresponding to the first image frame according to the vertex number, wherein the first cache data is data required by the first image frame in the rendering process;

The first updating module is used for determining a first rate according to a first data amount of the first cache data, updating the data transmission rate between the image processing unit and the memory from an initial rate to the first rate before rendering the first image frame, wherein the image processing unit is used for rendering the first image frame, and the memory is used for storing the first cache data.

7. The apparatus of claim 6, wherein the means for updating the data transmission rate further comprises:

A second obtaining module, configured to obtain a second data amount of second buffered data corresponding to a second image frame, where the second image frame is a previous image frame of the first image frame;

a second determining module configured to determine a first difference value of the first data amount minus the second data amount, and determine an absolute value of the first difference value;

the first update module further includes:

And the first determining unit is used for determining the first rate according to the first data amount and updating the data transmission rate between the image processing unit and the memory from the initial rate to the first rate before rendering the first image frame under the condition that the absolute value of the first difference value is larger than a first threshold value.

8. The apparatus of claim 6, wherein the first update module further comprises:

the first acquisition unit is used for acquiring a preset total single-frame rendering duration;

and the second determining unit is used for determining the first rate according to the single frame rendering total duration and the first data volume.

9. The apparatus of claim 6, wherein the means for updating the data transmission rate further comprises:

A third obtaining unit, configured to obtain a plurality of historical vertex numbers of a plurality of historical image frames, where each historical image frame corresponds to one historical vertex number;

a fourth obtaining unit, configured to obtain a plurality of historical data amounts corresponding to the plurality of historical image frames, where each historical image frame corresponds to one historical data amount;

And the generating unit is used for generating a first corresponding relation according to the plurality of historical vertex numbers and the plurality of historical data amounts, wherein the first corresponding relation is a corresponding relation between the vertex numbers and the data amounts of the image frames.

10. The apparatus of claim 6, wherein the means for updating the data transmission rate further comprises:

And the second updating module is used for updating the data transmission rate from the first rate to an initial rate after the first image frame is rendered.

11. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the data transfer rate updating method of any of claims 1-5.