CN118119181A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN118119181A CN118119181A CN202311772018.9A CN202311772018A CN118119181A CN 118119181 A CN118119181 A CN 118119181A CN 202311772018 A CN202311772018 A CN 202311772018A CN 118119181 A CN118119181 A CN 118119181A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title description 15
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 238000002161 passivation Methods 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims description 22
- 239000010410 layer Substances 0.000 description 165
- 230000002093 peripheral effect Effects 0.000 description 37
- 238000000034 method Methods 0.000 description 34
- 239000000463 material Substances 0.000 description 17
- 238000005530 etching Methods 0.000 description 16
- 125000006850 spacer group Chemical group 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- 239000013256 coordination polymer Substances 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- -1 silicon carbide nitride Chemical class 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor structure, which comprises a substrate; a first dielectric layer on the substrate; a contact structure in the first dielectric layer of the substrate; a second dielectric layer on the first dielectric layer and on both sides of the contact structure; an interconnect structure is located on the second dielectric layer; and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, a top surface of the first dielectric layer, and a sidewall of the interconnect structure.
Description
The application relates to a divisional application of Chinese patent application (application number: 202110697716.1, application name: semiconductor structure and manufacturing method thereof) filed in 2021, 6 and 23 days.
Technical Field
The invention relates to a semiconductor structure and a manufacturing method thereof. More particularly, the present invention relates to a Dynamic Random Access Memory (DRAM) including a memory region and a peripheral region, and a method of fabricating the same.
Background
Dynamic Random Access Memory (DRAM) is a type of volatile memory. DRAM devices typically include a memory region comprised of an array of memory cells, and a peripheral region comprised of control circuitry. The control circuit in the peripheral region may address each memory cell in the memory region by crossing a plurality of column word lines (word lines) and a plurality of row bit lines (bit lines) of the memory region and electrically connect with each memory cell to perform reading, writing or erasing of data. In advanced semiconductor manufacturing, the chip size of DRAM devices can be greatly reduced by employing an architecture of buried word lines or buried bit lines, by which the active regions of memory cells can be arranged at a dense pitch to obtain a higher cell density.
In the process of manufacturing a DRAM device, a memory cell and a semiconductor device of a peripheral circuit are simultaneously formed by the same manufacturing process. Therefore, it is important to provide peripheral semiconductor devices that are compatible with the manufacturing process of the memory cells.
Disclosure of Invention
One of the objectives of the present invention is to provide a semiconductor structure and a method for fabricating the same. The semiconductor structure has a memory region and a peripheral region, wherein a contact structure of the peripheral region of the semiconductor structure is formed simultaneously with a storage node contact of a memory cell in the memory region by the same manufacturing process. The contact structure provided by the invention can be used as an interconnection element of a peripheral circuit of the peripheral area of the semiconductor structure.
In one aspect, a semiconductor structure is provided that includes a substrate including a peripheral region and a memory region. A first dielectric layer is disposed on the substrate. A contact structure is located in the first dielectric layer over the peripheral region of the substrate. A second dielectric layer is disposed on the first dielectric layer and on both sides of the contact structure. An interconnect structure is located on the second dielectric layer. A passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure.
In another aspect, a semiconductor structure is provided that includes a substrate including a peripheral region and a memory region. A first dielectric layer is disposed on the substrate. A second dielectric layer is disposed on the first dielectric layer. An opening is located in the peripheral region of the substrate and includes a lower portion through the first dielectric layer and an upper portion through the second dielectric layer. An interconnect structure is located on the second dielectric layer and on both sides of the opening. A contact structure is located within the lower portion of the opening. A passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure.
In another aspect, the invention provides a semiconductor structure comprising a substrate, a first dielectric layer on the substrate, a contact structure in the first dielectric layer, a second dielectric layer on the first dielectric layer and on both sides of the contact structure, wherein a distance between the second dielectric layers on both sides of the contact structure is greater than a width of the contact structure, and a passivation layer covering a top surface of the contact structure and a sidewall of the second dielectric layer.
In yet another aspect, a semiconductor structure is provided that includes a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. An opening including a lower portion passing through the first dielectric layer and an upper portion passing through the second dielectric layer, wherein a width of the upper portion is greater than a width of the lower portion. A contact structure is located within the lower portion of the opening. A passivation layer covers a top surface of the contact structure and a sidewall of the second dielectric layer.
In another aspect, the invention provides a method for fabricating a semiconductor structure, which includes the following steps. First, a substrate is provided, which includes a peripheral region and a memory region. A first dielectric layer is then formed on the substrate, and a second dielectric layer is formed on the first dielectric layer. Then, an opening is formed in the peripheral region and through the second dielectric layer and the first dielectric layer. A conductive layer is formed on the second dielectric layer and fills the opening. Then, a recess process is performed to remove a portion of the conductive layer located at an upper portion of the opening to form a contact structure in a lower portion of the opening, wherein the second dielectric layer exposed from the upper portion of the opening is partially removed during the recess process. A passivation layer is formed to cover a top surface of the contact structure and a sidewall of the second dielectric layer.
Drawings
The accompanying drawings provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings and description serve to illustrate principles of some embodiments. It should be noted that all of the drawings are schematic and that relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.
Fig. 1 is a schematic top view of a semiconductor structure according to an embodiment of the present invention.
Fig. 2 to 10 are schematic views showing successive steps of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
Fig. 11 and 12 are schematic cross-sectional views of a semiconductor structure according to a second embodiment of the present invention, wherein fig. 11 and 12 correspond to the steps shown in fig. 7 and 8, respectively.
Fig. 13 is a schematic cross-sectional view of a semiconductor structure according to a third embodiment of the present invention, and corresponds to the steps shown in fig. 10.
Fig. 14 is a schematic cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention, and corresponds to the steps shown in fig. 10.
Wherein reference numerals are as follows:
100. Semiconductor structure
200. Semiconductor structure
300. Semiconductor structure
400. Semiconductor structure
10. Substrate and method for manufacturing the same
10A peripheral region
10B memory region
14. Isolation structure
22. Semiconductor part
24. Metal part
26. Hard mask portion
32. Spacer wall
34. A first dielectric layer
36. A second dielectric layer
38. Patterning mask layer
38A mask openings
42. First contact opening
42A lower part
42B upper part
44. Second contact opening
46. Storage node contact opening
52. Conductive layer
53A air gap
53B air gap
54. Passivation layer
62. Third dielectric layer
63A air gap
161. Doped regions
162. Doped regions
AA region
BB region
CC region
BL bit line
C1 Contact structure
C2 Contact structure
CP contact pad
E1 Etching process
E2 Recessing process
E3 Etching process
G2 Gate structure
M1 interconnect structure
S1 semiconductor portion
SNC storage node contact
SNCP contact pad
W1 width
W2 width
P air gap opening
Detailed Description
The following description of the preferred embodiments of the present invention will be presented to enable those skilled in the art to make and use the invention, and is provided in connection with the accompanying drawings. It should be understood that the following embodiments may be substituted, rearranged, and mixed with features of several different embodiments to achieve other embodiments without departing from the spirit of the disclosure.
Fig. 1 is a schematic top view of a semiconductor structure 100 according to an embodiment of the invention. As shown in fig. 1, the semiconductor structure 100 includes a substrate 10, and a peripheral region 10A and a memory region 10B are defined on the substrate 10. It should be noted that the shapes and arrangements of the peripheral region 10A and the memory region 10B shown in fig. 1 are for illustrative purposes and are not intended to limit the present invention.
The peripheral region 10A may be provided with peripheral circuits for controlling operations and input/output of the memory cells in the memory region 10B, for example, drivers, buffers, amplifiers, and decoders, but is not limited thereto. The peripheral region 10A may also include circuitry for repairing abnormal memory cells, such as fuse (fuse) circuitry. In accordance with an embodiment of the present invention, as shown in FIG. 1, the peripheral area 10A may include an area AA and an area BB for setting different types of circuits. Memory region 10B may include a region CC for setting a memory cell array, such as a DRAM cell. According to an embodiment of the present invention, the semiconductor devices of the peripheral circuits in the peripheral region 10A and the DRAM cells in the memory region 10B are formed simultaneously by the same manufacturing process integrally on the substrate 10.
Fig. 2 to 10 are schematic diagrams showing successive steps of a method for fabricating a semiconductor structure 100 according to a first embodiment of the present invention. The semiconductor structure 100 shown in fig. 2 to 10 may have a substrate 10 as shown in fig. 1 and a peripheral region 10A and a memory region 10B. The left-hand portion of fig. 2-10 is a cross-sectional schematic view of region AA of peripheral region 10A of semiconductor structure 100. The middle portion of fig. 2-10 is a cross-sectional schematic view of region BB of the peripheral region 10A of the semiconductor structure 100. The right-hand portion of fig. 2-10 is a cross-sectional schematic view of region CC of memory region 10B of semiconductor structure 100.
Referring to fig. 2, a substrate 10 is provided first, and then a plurality of isolation structures 14 such as Shallow Trench Isolation (STI) are formed in the substrate 10 to define a plurality of active regions (active regions) of a semiconductor device (not shown) in a peripheral region 10A of the substrate 10, and a plurality of active regions of memory cells (not shown) in a memory region 10B of the substrate 10. In addition, a plurality of buried word lines (not shown) may be formed in the substrate 10 through active areas (not shown) of the memory cells.
As shown in fig. 2, the gate structure G2 and the plurality of bit lines BL may be simultaneously formed on the peripheral region 10A and the memory region 10B of the substrate 10 through the same manufacturing process. For example, a semiconductor material layer (not shown), a metal material layer (not shown), and a hard mask material layer (not shown) may be sequentially formed on the peripheral region and the memory region of the substrate 10. Then, a patterning process (e.g., a photolithography and etching process) may be performed to pattern the hard mask material layer, and then an etching process may be performed using the patterned hard mask material layer as an etching mask to etch and remove the semiconductor material layer and the unnecessary portion of the metal material layer, thereby obtaining the gate structure G2 and the bit line BL.
As shown in fig. 2, the gate structure G2 and the bit line BL respectively include a semiconductor portion 22, a metal portion 24 on the semiconductor portion 22, and a hard mask portion 26 on the metal portion 24. According to an embodiment of the present invention, the material of the semiconductor portion 22 may include polysilicon. The material of the metal portion 24 may include aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium aluminum alloy (TiAl), or other low resistivity metal material. The material of the hard mask portion 26 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other suitable dielectric materials. A gate dielectric layer (not shown) may be provided between the substrate 10 and the semiconductor portion 22 of the gate structure G2.
Please refer to fig. 3. Spacers 32 may then be formed on the sidewalls of gate structure G2 and bit line BL, and doped regions 161 and 162 may be formed within active regions (not shown) in regions AA and BB of peripheral region 10A of substrate 10. It should be noted that the locations of the doped regions 161 and 162 shown in fig. 3 are exemplary and should not be taken as limitations of the present invention. Subsequently, a first dielectric layer 34 may be formed on the substrate 10, and the first dielectric layer 34 may be planarized to remove a portion of the first dielectric layer 34 until the top surfaces of the gate structure G2 and the bit line BL are exposed from the first dielectric layer 34. Next, a second dielectric layer 36 is formed on the first dielectric layer 34 and covers the exposed top surfaces of the gate structure G2 and the bit line BL. Materials of the first dielectric layer 34 and the second dielectric layer 36 may include silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable dielectric material, according to an embodiment of the present invention. According to an embodiment of the present invention, the first dielectric layer 34 may include silicon oxide (SiO 2), and the second dielectric layer 36 may include silicon nitride (SiN), but is not limited thereto.
In accordance with an embodiment of the present invention, the spacer 32 may be formed, for example, by first depositing at least one spacer material layer (not shown) on the substrate 10 and conformally covering the top surfaces and sidewalls of the gate structure G2 and the bit line BL. The spacer material layer may then be etched, for example, by a dry etching process, to anisotropically etch and remove the unwanted portions of the spacer material layer, while the remaining portions of the spacer material layer remaining on the sidewalls of the gate structure G2 and the bit line BL become the spacers 32. In accordance with an embodiment of the present invention, the material of the spacers 32 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable dielectric materials. According to an embodiment of the present invention, the spacers 32 on the sidewalls of the gate structure G2 and the bit line BL may have a single-layer structure or a multi-layer structure, respectively.
Please refer to fig. 4. Subsequently, a patterned masking layer 38 may be formed over the second dielectric layer 36. Patterned masking layer 38 may include a plurality of masking openings 38a exposing predetermined portions of second dielectric layer 36.
Please refer to fig. 5. Subsequently, an etching process E1, such as a dry etching process, is performed using the patterned mask layer 38 as an etching mask, and the exposed portions of the second dielectric layer 36 and the first dielectric layer 34 are etched through the mask opening 38a, thereby forming the first contact opening 42, the second contact opening 44, and the storage node contact opening 46. In detail, the first contact opening 42 is located on the region AA of the peripheral region 10A of the substrate 10, passes through the second dielectric layer 36 and the first dielectric layer 34 and exposes a portion of the doped region 161. The second contact opening 44 is located on the region BB of the peripheral region 10A of the substrate 10, through the second dielectric layer 36 and the first dielectric layer 34 and exposes a portion of the doped region 162 on both sides of the gate structure G2. The storage node contact opening 46 is located on the region CC of the memory region 10B of the substrate 10, through the first dielectric layer 34 between the second dielectric layer 36 and the bit line BL and exposes a portion of the active area of the memory cell (the exposed portion of the substrate 10 of region CC).
Please refer to fig. 6. After removal of the patterned masking layer 38, a semiconductor portion S1 is then selectively formed over the exposed active area of the memory cell (the exposed portion of the substrate 10 of region CC), such that the semiconductor portion S1 fills the lower portion of the storage node contact opening 46. Subsequently, a conductive layer 52 is formed on the second dielectric layer 36, and the conductive layer 52 fills the first contact opening 42, the second contact opening 44, and the storage node contact opening 46. The material of the conductive layer 52 may include a metal, such as tungsten (W). According to an embodiment of the present invention, as shown in fig. 6, when the widths of the first contact opening 42 and the second contact opening 44 are smaller, and/or by controlling the gap filling capability of the conductive layer 52, an air gap 53A and an air gap 53B sealed by the conductive layer 52 may be formed in the first contact opening 42 and the second contact opening 44, respectively.
Please refer to fig. 7. Subsequently, another patterning mask layer (not shown) is formed on the conductive layer 52 to cover a predetermined portion of the conductive layer 52, and then a recessing process E2 is performed using the patterning mask layer (not shown) as an etching mask to etch and pattern the conductive layer 52 on the second dielectric layer 36 while removing a portion of the conductive layer 52 located in the upper portion 42b of the first contact opening 42, thereby simultaneously forming a contact structure C1 located in the lower portion 42a of the first contact opening 42, a contact structure C2 located in the second contact opening 44, and a contact pad CP of the contact structure C2, a contact pad CP of the storage node contact SNC and the storage node contact SNC located in the storage node contact opening 46, and an interconnection structure M1 located over the second dielectric layer 36 on both sides of the first contact opening 42. It is noted that the portion of the second dielectric layer 36 exposed from the upper portion 42b of the first contact opening 42 is also removed in the recessing process E2, so that after the recessing process E2, the width W2 of the upper portion 42b of the first contact opening 42 is larger than the width W1 of the lower portion 42a of the first contact opening 42, as shown in fig. 7.
According to an embodiment of the present invention, the sidewalls of the interconnect structure M1 and the sidewalls of the second dielectric layer 36 on both sides of the upper portion 42b of the first contact opening 42 may be aligned with each other, as shown in fig. 7.
In accordance with an embodiment of the present invention, the recessing process E2 may remove a portion of the first dielectric layer 34 by etching down while widening the upper portion 42b of the first contact opening 42, resulting in concave sidewalls of the first dielectric layer 34 exposed from the upper portion 42b of the first contact opening 42. Because of the different etch rates of first dielectric layer 34 and conductive layer 52 during recessing process E2, the top surface of contact structure C1 may protrude from the concave sidewalls of first dielectric layer 34. According to an embodiment of the present invention, after the recessing process E2, the air gap 53A may remain sealed in the conductive layer 52 of the first contact opening 42 without being exposed.
Please continue to refer to fig. 7. The contact pads CP of the contact structure C2 protrude from the second contact opening 44 and extend laterally to cover portions of the second dielectric layer 36 located on both sides of the second contact opening 44. The contact pads SNCP of the storage node contact SNC protrude from the storage node contact opening 46 and extend laterally to cover portions of the second dielectric layer 36 located on both sides of the storage node contact opening 46. In accordance with an embodiment of the present invention, during the recessing process E2, the portions of the second dielectric layer 36 not covered by the interconnect structure M1, the contact pad CP of the contact structure C2, and the contact pad SNCP of the storage node contact SNC are also removed, thereby exposing portions of the upper surface of the first dielectric layer 34 around the second contact opening 44. According to an embodiment of the present invention, the exposed upper surface of the first dielectric layer 34 may have a concave profile.
Please refer to fig. 8. Subsequently, a passivation layer 54 is formed on the substrate 10, and the passivation layer 54 is made to cover the contact structure C1, the interconnection structure M1, and the sidewalls and top surfaces of the contact pad CP of the contact structure C2 and the contact pad SNCP of the storage node contact SNC. According to an embodiment of the present invention, the material of the passivation layer 54 may include silicon nitride (SiN).
Please refer to fig. 9. Subsequently, an etching process E3, such as an anisotropic dry etching process, may be performed to remove a portion of the passivation layer 54 until the top surface of the interconnect structure M1, the top surface of the contact pad CP of the contact structure C2, and the top surface of the contact pad SNCP of the storage node contact SNC are exposed.
It is noted that, as shown in the left portion of fig. 9, after the etching process E3, a portion of the remaining passivation layer 54 may become a sidewall of the second dielectric layer 36 exposed from the upper portion 42b of the first contact opening 42 along a portion of the top surface of the contact structure C1, and a spacer that is covered by the sidewall of the interconnect structure M1, and the bottom is lower than the bottom of the second dielectric layer 36. According to an embodiment of the present invention, the contact structure C1 may be partially removed in the etching process E3 such that a portion of the top surface of the contact structure C1 is exposed from the passivation layer 54 and the air gap 53A in the contact structure C1 is opened. In other words, the top of the air gap 53A may have an air gap opening P.
It is also noted that after the etching process E3, a portion of the remaining passivation layer 54 may become a spacer along the sidewalls of the contact pad CP of the contact structure C2 and the sidewalls of the second dielectric layer 36 under the contact pad CP, as shown in the middle portion of fig. 9. The hard mask portion 26 of the gate structure G2 and the surface of the first dielectric layer 34 may be exposed from the passivation layer 54. As shown in the right-hand portion of fig. 9, a portion of the remaining passivation layer 54 may fill in between the contact pads SNCP of the storage node contacts SNC and entirely cover the hard mask portion 26 of the bit line BL.
Please refer to fig. 10. Subsequently, a third dielectric layer 62 is formed on the interconnection structure M1, the contact pad CP and the contact pad SNCP, and the third dielectric layer 62 is made to completely fill the gap between the upper portion 42b of the first contact opening 42 and the contact pad CP and to be in direct contact with the contact structure C1. Notably, the air gap 53A opened by the etching process E3 is again sealed by the third dielectric layer 62. The material of the third dielectric layer 62 may include silicon oxide (SiO 2) or silicon nitride (SiN), but is not limited thereto. In a subsequent fabrication process (not shown), the third dielectric layer 62 may be planarized, and then an interconnection structure (not shown) electrically connected to the contact pads CP of the contact structures C1 and C2, and the contact pads SNCP of the storage node contacts SNC, respectively, may be formed in the third dielectric layer 62.
In view of the above, in one aspect, the present invention provides a semiconductor structure 100, comprising a substrate 10, the substrate 10 comprising a peripheral region 10A and a memory region 10B, a first dielectric layer 34 located on the substrate 10, and a contact structure C1 located in the first dielectric layer 34 on the peripheral region 10A. The second dielectric layer 36 is located on the first dielectric layer 34 and on both sides of the contact structure C1. Interconnect structure M1 is located on second dielectric layer 36. Passivation layer 54 covers a top surface of contact structure C1, a sidewall of second dielectric layer 36, and a sidewall of interconnect structure M1.
Another aspect of the invention provides a semiconductor structure 100 comprising a substrate 10, a first dielectric layer 34 on the substrate 10, a second dielectric layer 36 on the first dielectric layer 34, and an opening (first contact opening) 42 on the substrate 10, wherein the opening comprises a lower portion 42a extending through the first dielectric layer 34, and an upper portion 42b extending through the second dielectric layer 36. The semiconductor structure 100 further includes an interconnect structure M1 on the second dielectric layer 36 on both sides of the opening (first contact opening) 42, a contact structure C1 on a lower portion 42a of the opening (first contact opening) 42, and a passivation layer 54 covering the top surface of the contact structure C1, sidewalls of the second dielectric layer 36, and sidewalls of the interconnect structure M1.
According to an embodiment of the present invention, the width W2 of the upper portion 42b of the opening (first contact opening) 42 is larger than the width W1 of the lower portion 42a of the opening (first contact opening) 42. The distance between the second dielectric layers 36 on both sides of the contact structure C1 is substantially equal to the width W2, and the width of the contact structure C1 is substantially equal to the width W1, that is, the distance between the second dielectric layers 36 on both sides of the contact structure C1 is greater than the width of the contact structure.
According to an embodiment of the present invention, a portion of the top surface of the contact structure C1 may be exposed from the passivation layer 54. That is, the passivation layer 54 covers a portion of the top surface of the contact structure C1.
According to an embodiment of the present invention, the air gap 53A in the contact structure C1 may be exposed from the passivation layer 54. The top of the air gap 53A has an air gap opening P.
According to an embodiment of the present invention, the sidewalls of the second dielectric layer 36 and the sidewalls of the interconnect structure M1 are aligned with each other.
According to an embodiment of the present invention, passivation layer 54 covers a concave sidewall of first dielectric layer 34. The top surface of the contact structure C1 may protrude from the concave side wall of the first dielectric layer 34.
According to an embodiment of the present invention, the semiconductor structure 100 further includes a third dielectric layer 62 on the interconnect structure M1, filling in between the second dielectric layer 36 and the interconnect structure M1 on both sides of the contact structure C1, filling in the upper portion 42b of the opening (first contact opening) 42 and sealing the air gap 53A.
According to an embodiment of the present invention, the semiconductor structure 100 further comprises a plurality of bit lines BL on the substrate 10, and a plurality of storage node contacts SNC on the substrate 10 and between the bit lines BL, wherein a top surface of the interconnect structure M1 and a top surface of the storage node contacts SNC are level with each other.
Various embodiments of the invention are described in detail below. For simplicity of description, the same components are denoted by the same symbols in the following embodiments. In order to facilitate understanding of the differences between the embodiments, differences between the different embodiments will be described below, and the same features will not be described again.
Fig. 11 and 12 are schematic cross-sectional views of a semiconductor structure 200 according to a second embodiment of the present invention, wherein fig. 11 and 12 correspond to the steps shown in fig. 7 and 8, respectively. The second embodiment shown in fig. 11 and 12 is different from the first embodiment shown in fig. 7 and 8 in that the top of the air gap 53A in the contact structure C1 is opened to have an air gap opening P during the recessing process E2 by adjusting the position of the top of the air gap 53A and/or the over etching amount of the first dielectric layer 34 in the recessing process E2 as shown in fig. 11, and then the air gap 53A may be sealed again by the passivation layer 54 as shown in fig. 12, and then opened again by the etching process E3 (see fig. 9).
Fig. 13 is a schematic cross-sectional view of a semiconductor structure 300 according to a third embodiment of the present invention, and corresponds to the steps shown in fig. 10. The third embodiment shown in fig. 13 is different from the first embodiment shown in fig. 10 in that, as shown in fig. 13, the conductive layer 52 can completely fill the first contact opening 42 and the second contact opening 44 without forming an air gap in the first contact opening 42 and the second contact opening 44. Thereafter, a passivation layer 54 is formed to cover the top surface of the contact structure C1, the sidewalls of the second dielectric layer 36 and the sidewalls of the interconnect structure M1, and then a third dielectric layer 62 is formed on the interconnect structure M1 and the third dielectric layer 62 is made to completely fill the opening (first contact opening) 42.
Fig. 14 is a schematic cross-sectional view of a semiconductor structure 400 according to a fourth embodiment of the invention, and corresponds to the steps shown in fig. 10. The fourth embodiment shown in fig. 14 is different from the first embodiment shown in fig. 10 in that, as shown in fig. 14, the conductive layer 52 may completely fill the first contact opening 42 and the second contact opening 44 without forming an air gap in the first contact opening 42 and the second contact opening 44, and the third dielectric layer 62 filled in the upper portion 42b of the first contact opening 42 may form a sealed air gap 63A between the spacers (the remaining passivation layer 54).
In summary, the present invention provides a semiconductor structure having a contact structure formed in a peripheral region by the same manufacturing process as a memory node contact of a memory cell of a memory region, which can be used as an interconnection element of a peripheral circuit.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A semiconductor structure, comprising:
A substrate;
a first dielectric layer on the substrate;
a contact structure in the first dielectric layer of the substrate;
A second dielectric layer on the first dielectric layer and on both sides of the contact structure;
An interconnect structure is located on the second dielectric layer; and
A passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, a top surface of the first dielectric layer, and a sidewall of the interconnect structure.
2. The semiconductor structure of claim 1, wherein a distance between the second dielectric layers on both sides of the contact structure is greater than a width of the contact structure.
3. The semiconductor structure of claim 1, wherein the first dielectric layer comprises a concave sidewall covered by the passivation layer, and the top surface of the contact structure protrudes from the concave sidewall of the first dielectric layer.
4. The semiconductor structure of claim 1, wherein the contact structure comprises an air gap and a top of the air gap has an air gap opening.
5. The semiconductor structure of claim 1, wherein the sidewalls of the second dielectric layer and the sidewalls of the interconnect structure are aligned with each other.
6. The semiconductor structure of claim 1, further comprising a third dielectric layer on said interconnect structure and filling between said second dielectric layers on both sides of said contact structure.
7. A semiconductor structure, comprising:
A substrate;
a first dielectric layer on the substrate;
a contact structure in the first dielectric layer of the substrate;
A second dielectric layer on the first dielectric layer and on both sides of the contact structure;
An interconnect structure is located on the second dielectric layer; and
A passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure;
A third dielectric layer covers the top surface of the interconnect structure and the sidewalls of the passivation layer.
8. The semiconductor structure of claim 7, wherein said contact structure comprises an air gap and a top of said air gap has an air gap opening.
9. The semiconductor structure of claim 7, wherein the substrate comprises: a memory area;
The semiconductor structure further includes:
a plurality of bit lines on the memory region of the substrate;
A plurality of storage node contact structures on the substrate and between the bit lines, wherein the top surfaces of the interconnect structures and the top surfaces of the storage node contact structures are level with each other.
10. A semiconductor structure, comprising:
A substrate;
a first dielectric layer on the substrate;
a contact structure in the first dielectric layer of the substrate;
A second dielectric layer on the first dielectric layer and on both sides of the contact structure;
an interconnect structure is located on the second dielectric layer;
A passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure;
a third dielectric layer over the interconnect structure and the passivation layer; and
An air gap is defined by the contact structure and the third dielectric layer.
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| KR20040063299A (en) * | 2003-01-06 | 2004-07-14 | 삼성전자주식회사 | Method of forming a via contact structure using a dual damascene process |
| US20140209984A1 (en) * | 2013-01-31 | 2014-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd | Semiconductor Device With Multi Level Interconnects And Method Of Forming The Same |
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| CN109979940B (en) * | 2017-12-27 | 2021-03-26 | 长鑫存储技术有限公司 | Semiconductor memory device and method of manufacturing the same |
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