CN118116972A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate. The semiconductor substrate is provided with a well region, a first doped region and two second doped regions. The first doped region is located in the well region and between the two second doped regions. Two second doped regions are located in the well region. Each of the two second doped regions has a first side adjacent to the first doped region and a second side opposite to the first doped region. The distance between the second side of one of the two second doped regions and the edge of the well region is the same as the distance between the second side of the other of the two second doped regions and the other edge of the well region. The semiconductor structure can be used in a power metal oxide semiconductor field effect transistor (power MOSFET), and the distance is used as the channel length, so that the symmetrical power MOSFET with the same channel length is obtained, and the design of a circuit is easier.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background

In a power metal oxide semiconductor field effect transistor (power MOSFET), a channel length is related to an on-resistance between a drain and a source of a unit element, so that the power MOSFET having the same channel length and symmetry can make design of a circuit easier. In a conventional power MOSFET process, spacers are used as the hard mask for ion implantation and the thickness is used to define the channel length so that the devices have the same channel length. In shrinking device dimensions, the thickness of the hard mask must be reduced to reduce the channel length, so the ion implantation energy must be reduced due to the limitations, and the preferred channel length and ion implantation energy cannot be achieved at the same time. In addition, since the N-type doped region and the P-type doped region are formed in different regions in the power MOSFET process, two masks are conventionally used, wherein the two masks have to be designed with a space reserved to avoid overlapping displacement, thereby limiting the device size reduction.

Disclosure of Invention

One aspect of the present disclosure is a semiconductor structure.

According to some embodiments of the present disclosure, a semiconductor structure includes a semiconductor substrate. The semiconductor substrate is provided with a well region, a first doped region and two second doped regions. The first doped region is located in the well region and between the two second doped regions. Two second doped regions are located in the well region. Each of the two second doped regions has a first side adjacent to the first doped region and a second side opposite to the first doped region. The distance between the second side of one of the two second doped regions and the edge of the well region is the same as the distance between the second side of the other of the two second doped regions and the other edge of the well region.

In some embodiments, the first doped region of the semiconductor substrate contacts the two second doped regions, and the well region does not extend to a portion between each of the two second doped regions and the first doped region.

In some embodiments, the vertical projections of the first doped region and the vertical projections of the two second doped regions of the semiconductor substrate do not overlap each other.

In some embodiments, the two second doped regions of the semiconductor substrate extend to the first doped region.

In some embodiments, a distance between each of two second sides of the semiconductor substrate facing away from the first doped region and an edge of the well region is between 0.2 micrometers and 1 micrometer.

In some embodiments, the bottom surface of the first doped region of the semiconductor substrate is higher than the bottom surfaces of the two second doped regions, and the bottom surfaces of the first doped region and the two second doped regions are higher than the bottom surfaces of the well regions.

In some embodiments, the top surface of the semiconductor substrate, the top surface of the first doped region and the top surfaces of the two second doped regions are coplanar.

In some embodiments, the semiconductor structure further includes an oxide layer. The oxide layer is positioned on the semiconductor substrate and covers the top surface of the well region, the top surface of the first doped region and the top surfaces of the two second doped regions.

In some embodiments, the material of the semiconductor substrate includes silicon or silicon carbide, the well region is a P-type well, the first doped region includes P-type dopants, and the two second doped regions include N-type dopants.

Another aspect of the present disclosure is a method of manufacturing a semiconductor structure.

According to some embodiments of the present disclosure, a method for fabricating a semiconductor structure includes forming a well region in a semiconductor substrate under an opening of a hard mask structure, wherein the semiconductor substrate is covered by a first oxide layer; forming a sidewall spacer on the sidewall of the hard mask structure, wherein the sidewall spacer has a first portion and a second portion opposite to each other, and each of the first portion and the second portion overlaps the well region in a vertical direction; forming a hard mask layer on the hard mask structure, the sidewall spacer and the first oxide layer, wherein the hard mask layer has an opening exposing the first oxide layer; removing the first oxide layer in the opening of the hard mask layer to expose the well region from the opening of the hard mask layer; forming a first doped region in the well region below the opening of the hard mask layer; forming a spacer structure on the first doped region in the opening of the hard mask layer; removing the hard mask layer to expose two parts of the first oxide layer; forming two second doped regions in the well region under the two parts of the first oxide layer respectively, so that the first doped region is adjacent to each of the two second doped regions; and removing the hard mask structure, the sidewall spacers and the spacer structure.

In some embodiments, forming the spacer structure on the first doped region in the opening of the hard mask layer further includes forming a second oxide layer on the hard mask layer and the first doped region; forming a barrier layer on the second oxide layer to fill the opening of the hard mask layer with the barrier layer; and etching the barrier layer and the second oxide layer to define a spacing structure between the etched barrier layer and the etched second oxide layer.

In some embodiments, the sidewall spacers are formed on the sidewalls of the hard mask structure such that the bottom surface of the first portion of the sidewall spacers has the same width as the bottom surface of the second portion.

In some embodiments, the spacer is formed on the first doped region in the opening of the hard mask layer such that the thickness of the spacer is greater than 1.5 μm, and the width of the spacer is the same as the width of the first doped region.

In some embodiments, the removing the hard mask layer uses an etchant having a selectivity between the hard mask layer and the sidewall spacer and between the hard mask layer and the spacer structure.

In some embodiments, the forming the well region in the semiconductor substrate under the opening of the hard mask structure, the forming the first doped region in the well region under the opening of the second hard mask, and the forming the two second doped regions in the well region under the two portions of the first oxide layer respectively uses ion implantation.

In the above embodiments of the present disclosure, since the semiconductor structure has two second doped regions, and the distance between the second side of one of the two second doped regions and the edge of the well region is the same as the distance between the second side of the other of the two second doped regions and the other edge of the well region, the semiconductor structure can be used in a power metal oxide semiconductor field effect transistor (power MOSFET), and the distance is used as the channel length to obtain a symmetrical power MOSFET with the same channel length, so that the design of the circuit is easier. In addition, in the manufacturing method of the semiconductor structure, the spacer structure is formed on the first doped region in the opening of the hard mask layer, so that the spacer structure can cover the first doped region and serve as a hard mask for ion implantation of the second doped region, thereby avoiding the problem of overlapping displacement in the conventional process and further shrinking the semiconductor structure. In addition, the spacer structure is not used to define the channel length of the power MOSFET, so the thickness of the spacer structure is not affected by the channel length, the device can have a preferable channel length, and the spacer structure is thick enough to control the ion implantation energy of the process more flexibly.

Drawings

The aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. Note that the various features are not drawn to scale in accordance with standard practices in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

Fig. 2-10 are cross-sectional views of the semiconductor structure of fig. 1 at intermediate stages in a method of manufacturing the same.

Detailed Description

The following disclosure of embodiments provides many different embodiments, or examples, for implementing different features of the provided objects. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these examples are merely examples and are not intended to be limiting. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1 illustrates a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. As shown, the semiconductor structure 100 includes a semiconductor substrate 110. The semiconductor substrate 110 has a well region 112, a first doped region 114 and two second doped regions 116. The first doped region 114 is located in the well region 112 and is located between two second doped regions 116. Two second doped regions 116 are located in the well region 112, and each of the two second doped regions 116 has a first side 117 adjacent to the first doped region 114 and a second side 118 opposite to the first doped region 114. The distance D between the second side 118 of one of the two second doped regions 116 and the edge of the well region 112 is the same as the distance D between the second side 118 of the other of the two second doped regions 116 and the other edge of the well region 112. The semiconductor structure 100 can be used in a power metal oxide semiconductor field effect transistor (power MOSFET), and with the distance D as the channel length, a symmetrical power MOSFET with the same channel length can be obtained to stabilize the on-resistance (R _DSon), so that the design of the circuit is easier. In addition, since each of the two second doped regions 116 adjoins the first doped region 114, the semiconductor structure 100 can be more space-saving than conventional designs, resulting in a smaller size of the power MOSFET.

In the present embodiment, the first doped region 114 of the semiconductor substrate 110 is in contact with the two second doped regions 116, and the well region 112 does not extend to a portion between each of the two second doped regions 116 and the first doped region 114. Such a design may be used in a power MOSFET without excess space between the two doped regions (i.e., between the first doped region 114 and the second doped region 116) to reduce the device size. In addition, the vertical projections of the first doped region 114 and the vertical projections of the two second doped regions 116 do not overlap each other, and the two second doped regions 116 extend to the first doped region 114, so that the semiconductor structure 100 does not have the problem of insufficient concentration of doped regions due to overlapping displacement, and the device can be more stable.

In addition, a distance D between each of two second sides 118 of the semiconductor substrate 110 facing away from the first doped region 114 and an edge of the well region 112 is between 0.2 micrometers and 1 micrometer. In such a design, the distance D may be used as the channel length in the power MOSFET to obtain symmetrical power MOSFETs with the same channel length and stabilize the on-resistance (R _DSon) to make the design of the circuit easier. In addition, the distance D can be adjusted to fit different device designs.

In the present embodiment, the bottom surface of the first doped region 114 of the semiconductor substrate 110 may be lower or higher than the bottom surfaces of the two second doped regions 116, and the bottom surfaces of the first doped region 114 and the two second doped regions 116 are higher than the bottom surface of the well region 112. In addition, the top surface of the semiconductor substrate 110, the top surface of the first doped region 114, and the top surfaces of the two second doped regions 116 are coplanar. Such a design may be used in a power MOSFET where the first doped region 114 and the two second doped regions 116 may be used as source contact regions to avoid creating an equivalent Bipolar Junction Transistor (BJT) in the power MOSFET structure, which may make the device more stable.

In addition, the semiconductor structure 100 may further include an oxide layer 120. The oxide layer 120 is disposed on the semiconductor substrate 110 and covers the top surface of the well region 112, the top surface of the first doped region 114, and the top surfaces of the two second doped regions 116. The oxide layer 120 combined with the subsequent process may be used as a gate dielectric of the MOSFET, the semiconductor substrate 110 may be used as a base, the gate is above the oxide layer 120, and such a structure may be defined as a MOS capacitor and used in the structure of the power MOSFET.

In this embodiment, the material of the semiconductor substrate 110 may include silicon or silicon carbide (SiC). The semiconductor substrate 110 may also have an epitaxial layer to increase the breakdown voltage, and the bottom of the semiconductor substrate 110 may serve as a drain contact layer. In addition, the semiconductor substrate 110 may be an N-type substrate, the well region 112 may be a P-type well, the first doped region 114 may include a P-type dopant (e.g., aluminum or boron), and the two second doped regions 116 may include an N-type dopant (e.g., phosphorus or arsenic or nitrogen), such a design may be used in an N-type power MOSFET to avoid the generation of equivalent BJTs in the structure, thereby making the device more stable.

In the following description, a method of manufacturing the semiconductor structure 100 will be described.

Fig. 2-10 illustrate cross-sectional views of the method of manufacturing the semiconductor structure 100 of fig. 1 at intermediate stages. As shown in fig. 2, the method of fabricating the semiconductor structure 100 includes forming the well region 112 in the semiconductor substrate 110 under the opening 132 of the hard mask structure 130. The semiconductor substrate 110 is covered with a first oxide layer 120. In some embodiments, the first oxide layer 120, the spacer layer 131 and the oxide layer 133 may be sequentially formed on the semiconductor substrate 110 before the well region 112 is formed. Then, a patterned photoresist layer is formed on the oxide layer 133, and the spacer layer 131 and the oxide layer 133 not covered by the photoresist layer are etched to form the hard mask structure 130 having the opening 132. The photoresist layer may then be removed and ion implantation may be used to form well region 112 in semiconductor substrate 110 under opening 132 of hard mask structure 130. In some embodiments, the material of the semiconductor substrate 110 may be silicon carbide (SiC), the well region 112 is a P-type well formed by aluminum ion implantation, and the material of the spacer 131 may be polysilicon, but is not limited to the above materials.

Referring to fig. 3, sidewall spacers 140 may then be formed on the sidewalls of the hard mask structure 130. The sidewall spacers 140 have opposite first and second portions 142 and 144, and each of the first and second portions 142 and 144 vertically overlaps the well region 112. In addition, the bottom surface of the first portion 142 and the bottom surface of the second portion 144 of the sidewall spacer 140 have the same width W. In some implementations, the sidewall spacers 140 may be formed by etching sidewall spacers overlying the top surface and sidewalls of the hard mask structure 130, and the thickness of the sidewall spacers may determine the width W of the sidewall spacers 140. In some embodiments, the sidewall spacer 140 may have a thickness in the range of 0.2 microns to 1.2 microns and a width W in the range of 0.2 microns to 1 micron. In addition, the material of the sidewall spacer 140 may be polysilicon or silicon oxynitride, but is not limited thereto.

Next, referring to fig. 4 and 5, a hard mask layer 150 may be formed on the hard mask structure 130, the sidewall spacers 140 and the first oxide layer 120. In some embodiments, the material of the hard mask layer 150 is silicon nitride, and the thickness of the hard mask layer 150 is in the range of 0.2 microns to 1.2 microns. Then, a portion of the hard mask layer 150 may be removed, such that the hard mask layer 150 has an opening 152 and the first oxide layer 120 is exposed. In some embodiments, a patterned photoresist layer may be formed on the hard mask layer 150 such that the hard mask layer 150 not covered by the photoresist layer may be etched to form the openings 152. Then, the first oxide layer 120 in the opening 152 of the hard mask layer 150 may be etched to remove the well region 112 from the opening 152 of the hard mask layer 150. After etching the first oxide layer 120 in the opening 152, the photoresist layer may be removed. Thereafter, a first doped region 114 may be formed in the well region 112 under the opening 152 of the hard mask layer 150. In some embodiments, the first doped region 114 is formed in the well region 112 under the opening 152 of the hard mask layer 150, and the P-type doped region may be formed by aluminum or boron ion implantation, but is not limited thereto.

Referring to fig. 6 and 7, a second oxide layer 162 may be formed on the hard mask layer 150 and the first doped region 114. In this embodiment, the second oxide layer 162 and the first oxide layer 120 may be made of the same material, and therefore the interface is not shown. Then, a barrier layer 164 may be formed on the second oxide layer 162, such that the barrier layer 164 fills the opening 152 of the hard mask layer 150 and covers the top surface of the second oxide layer 162. In some embodiments, the material of the barrier layer 164 may be polysilicon, and the thickness of the barrier layer 164 is in the range of 0.3 microns to 1 micron. An Etch Back (CMP) or Chemical Mechanical Planarization (CMP) may then be used to Etch the barrier layer 164 such that the top surface of the barrier layer 164 is not higher (e.g., lower) than the top surface of the second oxide layer 162.

Referring to fig. 7 and 8, the second oxide layer 162 may be etched, such that the etched barrier layer 164 and the etched second oxide layer 162 define the spacer 160. In this way, the spacer 160 is formed on the first doped region 114 in the opening 152 of the hard mask layer 150. In some embodiments, the spacer structures 160 have a thickness greater than 1.5 microns. The hard mask layer 150 may then be removed, leaving two portions of the first oxide layer 120 exposed. In some implementations, removing the hard mask layer 150 may use an etchant having a selectivity between the hard mask layer 150 and the sidewall spacers 140, between the hard mask layer 150 and the spacer structures 160, and between the hard mask layer 150 and the hard mask structure 130. For example, the material of the hard mask layer 150 is silicon nitride, the material of the sidewall spacer 140 is polysilicon or silicon oxynitride, the material of the second oxide layer 162 of the spacer 160 is silicon dioxide, the material of the barrier layer 164 of the spacer 160 is polysilicon, and the material of the hard mask structure 130 is polysilicon and silicon dioxide, and the wet etching etchant is hot phosphoric acid, but not limited thereto.

Referring to fig. 9, two second doped regions 116 may be formed in the well region 112 under the exposed portions of the first oxide layer 120, such that the first doped region 114 is adjacent to each of the two second doped regions 116. In some embodiments, the above-described steps may use phosphorus, arsenic or nitrogen ion implantation, and the hard mask structure 130, the sidewall spacers 140 and the spacer structures 160 are used as patterned hard masks for ion implantation, and the thickness of the hard mask structure 130, the thickness of the sidewall spacers 140 and the thickness of the spacer structures 160 are greater than 1.5 μm, so that ions cannot pass through the patterned hard masks to form doped regions thereunder.

Since the bottom surface of the first portion 142 and the bottom surface of the second portion 144 of the sidewall spacer 140 have the same width W, a distance D between the second side 118 of one of the two second doped regions 116 and the edge of the well region 112 formed by ion implantation is the same as a distance D between the second side 118 of the other of the two second doped regions 116 and the other edge of the well region 112. In such a design, the distance D may be used as the channel length in the power MOSFET to obtain a symmetrical power MOSFET with the same channel length and stabilize R _DSon, making the design of the circuit easier. Since the spacer structures 160 are not used to define channel lengths, the thickness of the spacer structures 160 may be sufficiently thick (not less than 1.5 microns) that the ion implantation energy of the process may be more flexibly controlled with the preferred channel length (defined by the sidewall spacers 140) of the device. In addition, since the spacer 160 is formed on the first doped region 114 in the opening 152 of the hard mask layer 150, and the width of the spacer 160 is the same as the width of the first doped region 114, the spacer can be used as a hard mask for ion implantation of two second doped regions 116, so that the first doped region 114 and the two second doped regions 116 are adjacent to each other and the problem of overlapping displacement in the conventional process can be avoided, so that the power MOSFET is further reduced, and the insufficient concentration of the doped regions due to the overlapping displacement is avoided, thereby improving the stability of the device.

Referring to fig. 1 and 10, the oxide layer 133 of the hard mask structure 130 and the second oxide layer 162 of the spacer structure 160 may be removed. The spacer layer 131 of the hard mask structure 130, the sidewall spacers 140, and the blocking layer 164 of the spacer structure 160 may then be removed to obtain the semiconductor structure 100 of fig. 1. Since the fabrication method of the semiconductor structure 100 does not require a space for avoiding the overlapping displacement, the well region 112 does not extend to a portion between each of the two second doped regions 116 and the first doped region 114, so that the power MOSFET having the semiconductor structure 100 can be further reduced compared to the conventional process.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[ Symbolic description ]

100 Semiconductor structure

110 Semiconductor substrate

112 Well region

114 First doped region

116 Two second doped regions

117 First side

118 Second side

120 (First) oxide layer

130 Hard mask structure

131 Spacer layer

132 Opening(s)

133 Oxide layer

140 Sidewall spacers

142 First part

144 Second part

150 Hard mask layer

152 Opening

160 Spacing structure

162 Second oxide layer

164 Barrier layer

Distance D

W is the width.

Claims (15)

1. A semiconductor structure, comprising:

A semiconductor substrate has a well region, a first doped region in the well region, and two second doped regions in the well region, wherein the first doped region is located between the two second doped regions, each of the two second doped regions has a first side adjacent to the first doped region and a second side opposite to the first doped region, and a distance between the second side of one of the two second doped regions and an edge of the well region is the same as a distance between the second side of the other of the two second doped regions and another edge of the well region.

2. The semiconductor structure of claim 1, wherein the first doped region of the semiconductor substrate is in contact with the two second doped regions and the well region does not extend to a portion between each of the two second doped regions and the first doped region.

3. The semiconductor structure of claim 1, wherein the vertical projections of the first doped region and the vertical projections of the two second doped regions of the semiconductor substrate do not overlap each other.

4. The semiconductor structure of claim 1, wherein the two second doped regions of the semiconductor substrate extend to the first doped region.

5. The semiconductor structure of claim 1, wherein a distance between each of the two second sides of the semiconductor substrate opposite the first doped region and an edge of the well region is between 0.2 microns and 1 micron.

6. The semiconductor structure of claim 1, wherein a bottom surface of the first doped region of the semiconductor substrate is higher than bottom surfaces of the two second doped regions, and wherein bottom surfaces of the first doped region and the two second doped regions are higher than bottom surfaces of the well region.

7. The semiconductor structure of claim 1, wherein a top surface of the semiconductor substrate, a top surface of the first doped region, and top surfaces of the two second doped regions are coplanar.

8. The semiconductor structure of claim 1, further comprising:

and the oxide layer is positioned on the semiconductor substrate and covers the top surface of the well region, the top surface of the first doped region and the top surfaces of the two second doped regions.

9. The semiconductor structure of claim 1, wherein the material of the semiconductor substrate comprises silicon or silicon carbide, the well region is a P-type well, the first doped region comprises a P-type dopant, and the two second doped regions comprise an N-type dopant.

10. A method of fabricating a semiconductor structure, comprising:

forming a well region in the semiconductor substrate below the opening of the hard mask structure, wherein the semiconductor substrate is covered by the first oxide layer;

forming a sidewall spacer on a sidewall of the hard mask structure, wherein the sidewall spacer has a first portion and a second portion opposite to each other, and each of the first portion and the second portion overlaps the well region in a vertical direction;

Forming a hard mask layer on the hard mask structure, the sidewall spacer and the first oxide layer, wherein the hard mask layer has an opening exposing the first oxide layer;

Removing the first oxide layer in the opening of the hard mask layer to expose the well region from the opening of the hard mask layer;

Forming a first doped region in the well region under the opening of the hard mask layer;

forming a spacer structure on the first doped region in the opening of the hard mask layer;

Removing the hard mask layer to expose two parts of the first oxide layer;

Forming two second doped regions in the well region under the two portions of the first oxide layer respectively, such that the first doped region adjoins each of the two second doped regions; and

The hard mask structure, the sidewall spacers and the spacer structure are removed.

11. The method of claim 10, wherein forming the spacer structure over the first doped region in the opening of the hard mask layer comprises:

Forming a second oxide layer on the hard mask layer and the first doped region;

forming a barrier layer on the second oxide layer to fill the opening of the hard mask layer with the barrier layer; and

Etching the barrier layer and the second oxide layer to define the spacer structure.

12. The method of claim 10, wherein the sidewall spacers are formed on sidewalls of the hard mask structure such that a bottom surface of the first portion and a bottom surface of the second portion of the sidewall spacers have a same width.

13. The method of claim 10, wherein the spacer is formed on the first doped region in the opening of the hard mask layer such that the thickness of the spacer is greater than 1.5 μm and the width of the spacer is the same as the width of the first doped region.

14. The method of claim 10, wherein removing the hard mask layer uses an etchant having a selectivity between the hard mask layer and the sidewall spacer and between the hard mask layer and the spacer structure.

15. The method of claim 10, wherein forming the well in the semiconductor substrate under the opening of the hard mask structure, forming the first doped region in the well under the opening of the hard mask layer, and forming the two second doped regions in the well under the two portions of the first oxide layer, respectively, uses ion implantation.